A bonded bridge chip and a method of making the same

Abstract

This application discloses a bonding bridging chip and its fabrication method, relating to the field of semiconductor technology. The bonding bridging chip includes a substrate, the substrate comprising electrode contact regions, and the doping concentration of the electrode contact regions being 1*10⁻⁶. 19 -5*10 19 cm ‑3 Between the two layers, an upper electrode structure connected to the electrode contact area is disposed on the upper surface of the substrate, and a lower electrode structure connected to the electrode contact area is disposed on the lower surface of the substrate. This bonding bridging chip and its fabrication method can reduce the resistance of the bonding bridging chip and improve resistance consistency.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a bonding bridging chip and its fabrication method. Background Technology

[0002] Gold wire bonding, a key technology for electrical interconnection in semiconductor packaging and precision electronic modules, plays a vital role in the manufacturing of high-end electronic devices due to its excellent conductivity, oxidation resistance, and fatigue resistance. However, gold wire bonding places high demands on the surface characteristics of the bonding pads. Conventional immersion gold pads on printed circuit boards (PCBs) suffer from thin gold layers and poor density, failing to meet the reliability requirements of bonding. To address this issue, a gold wire bonding adapter solution has been proposed in the prior art, which uses an external bridging chip to achieve proper gold wire bonding of ordinary immersion gold pads on PCBs. The external bridging chip avoids the need for expensive nickel-palladium-gold (Ni-Pd-Au) plating on the entire PCB board for bonding, thus mitigating the high cost associated with full-board Ni-Pd-Au plating to some extent.

[0003] While the aforementioned external bridging chip solutions have made some progress in cost control, existing general-purpose adapter bridging chips still have some problems in practical applications. Specifically, existing chips generally suffer from poor contact performance, insufficient conductivity consistency, and high interface barriers. These problems lead to obstructed current transmission, reduced signal integrity, and severely restrict the long-term reliability and overall electrical performance of electronic modules. Summary of the Invention

[0004] The purpose of this application is to provide a bonding bridge chip and its fabrication method, which can reduce the resistance of the bonding bridge chip and improve resistance consistency.

[0005] The embodiments of this application are implemented as follows: A first aspect of this application provides a bonding bridging chip, including a substrate, the substrate including electrode contact regions, the doping concentration of the electrode contact regions being 1*10⁻⁶. 19 -5*10 19 cm -3 Between them, the upper surface of the substrate is provided with an upper electrode structure connected to the electrode contact area, and the lower surface of the substrate is provided with a lower electrode structure connected to the electrode contact area.

[0006] As one possible implementation, both the upper electrode structure and the lower electrode structure include an adhesion layer, a barrier layer, and a conductive layer arranged sequentially along the direction away from the substrate. The upper electrode structure is used to connect with gold wires, and the lower electrode structure is used to connect with the pads of the circuit board.

[0007] As one possible implementation, the substrate is a silicon substrate, the adhesion layer is titanium, the barrier layer is nickel, and the conductive layer is gold.

[0008] As one possible implementation, the upper electrode structure also includes an aluminum layer disposed between the barrier layer and the adhesive layer.

[0009] As one possible implementation, the thicknesses of the adhesion layer, barrier layer, and conductive layer of the lower electrode structure are 20-30 nm, 40-60 nm, and 30-50 nm, respectively; the thicknesses of the adhesion layer, aluminum layer, barrier layer, and conductive layer of the upper electrode structure are 15-25 nm, 180-100 nm, 30-40 nm, and 50-80 nm, respectively.

[0010] In one possible implementation, the substrate is a semiconductor compound substrate, the adhesion layer of the upper electrode structure is titanium, the barrier layer is platinum, and the conductive layer is gold.

[0011] In one possible implementation, the substrate is a semiconductor compound substrate, the adhesion layer of the upper electrode structure is germanium, the barrier layer is nickel, and the conductive layer is gold.

[0012] In one possible implementation, the thicknesses of the adhesion layer, barrier layer, and conductive layer of the lower electrode structure are 30-50 nm, 20-40 nm, and 40-60 nm, respectively; and the thicknesses of the adhesion layer, barrier layer, and conductive layer of the upper electrode structure are 15-25 nm, 40-60 nm, and 50-90 nm, respectively.

[0013] As one possible implementation method, the electrode contact region is doped with N-type doping.

[0014] A second aspect of this application provides a method for fabricating a bonding bridge chip, comprising: providing a substrate, the substrate including an electrode contact region; doping the electrode contact region, wherein the doping concentration of the electrode contact region is 1*10⁻⁶. 19 -5*10 19 cm -3 Between; an upper electrode structure connected to the electrode contact area is formed on the upper surface of the substrate; a lower electrode structure connected to the electrode contact area is formed on the lower surface of the substrate; the substrate with the upper and lower electrode structures is annealed at a temperature between 450 and 550°C.

[0015] As one possible implementation, magnetron sputtering is used to deposit metal on the upper and lower surfaces of a substrate to form an upper electrode structure and a lower electrode structure, wherein the magnetron sputtering temperature is between 450 and 550°C.

[0016] As one possible implementation, before doping the substrate to form the electrode contact region, the method for fabricating the bonding bridging chip further includes: cleaning the substrate; and removing the oxide layer on the substrate surface.

[0017] The beneficial effects of the embodiments of this application include: The bonding bridging chip provided in this application embodiment includes a substrate, the substrate including an electrode contact region, and the doping concentration of the electrode contact region is 1*10. 19 -5*10 19 cm -3 Between the two electrodes, an upper electrode structure connected to the electrode contact area is disposed on the upper surface of the substrate, and a lower electrode structure connected to the electrode contact area is disposed on the lower surface of the substrate. When the upper and lower electrode structures contact the heavily doped electrode contact areas, the depletion layer width on the semiconductor surface is greatly compressed due to the high doping concentration of the electrode contact areas. The extremely narrow depletion layer allows charge carriers to directly pass through the potential barrier with a very high probability through quantum tunneling, eliminating the metal-semiconductor interface barrier. This transforms the original rectifying contact into an ohmic contact, achieving ultra-low contact resistance. In addition, the defined doping concentration range ensures that the resistance of each electrode contact area remains highly consistent during mass production, improving resistance consistency. In summary, the bonding bridge chip of this application embodiment can reduce the resistance of the bonding bridge chip and improve resistance consistency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is one of the structural schematic diagrams of a bonding bridging chip provided in an embodiment of this application; Figure 2 This is a second schematic diagram of a bonding bridging chip provided in an embodiment of this application; Figure 3 A schematic diagram of a bonding bridging chip mounting structure provided in an embodiment of this application; Figure 4 This is a flowchart illustrating a method for fabricating a bonding bridging chip, as provided in an embodiment of this application.

[0020] Icons: 100 - Bonded bridging chip; 110 - Substrate; 111 - Electrode contact area; 120 - Upper electrode structure; 130 - Lower electrode structure; 141 - Adhesion layer; 142 - Barrier layer; 143 - Conductive layer; 144 - Aluminum layer; 210 - Circuit board; 211 - Solder pad; 212 - Gold wire. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. Similar reference numerals and letters in the following drawings indicate similar items. Once an item is defined in one drawing, it does not need to be further defined in other drawings.

[0022] The terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and should not be construed as limiting this application. The terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0023] Unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to connections within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] Please refer to the reference. Figure 1 and Figure 2 This application provides a bonding bridging chip 100, including a substrate 110, the substrate 110 including an electrode contact region 111, the doping concentration of the electrode contact region 111 being 1*10. 19 -5*10 19 cm -3 Between them, the upper surface of the substrate 110 is provided with an upper electrode structure 120 connected to the electrode contact area 111, and the lower surface of the substrate 110 is provided with a lower electrode structure 130 connected to the electrode contact area 111.

[0025] The bonding bridging chip 100 provided in this embodiment is used to connect the circuit board 210 and the gold wire 212 to achieve bonding of the gold wire 212. Specifically, the bonding bridging chip 100 in this embodiment includes a substrate 110 having an electrode contact region 111, wherein the doping concentration of the electrode contact region 111 is limited to 1×10⁻⁶. 19 Up to 5×10 19 cm 3The area between these layers is heavily doped. The heavy doping penetrates the entire thickness of the substrate 110 and connects with the upper electrode structure 120 and lower electrode structure 130 located on both sides of the substrate 110, forming a vertical current conduction path. Specifically, the lower electrode structure 130 is connected to the pads 211 on the circuit board 210 and to the gold wires 212, allowing electrical signals on the circuit board 210 to be transmitted through the pads 211 to the lower electrode structure 130, then along the lower electrode structure 130 to the electrode contact area 111, then to the upper electrode structure 120, and finally to the gold wires 212, forming a vertical current conduction path.

[0026] It is understood that both the upper electrode structure 120 and the lower electrode structure 130 are made of metallic materials. When the upper electrode structure 120 and the lower electrode structure 130 are in contact with the heavily doped electrode contact region 111, the depletion layer width on the semiconductor surface is greatly compressed due to the high doping concentration of the electrode contact region 111. The extremely narrow depletion layer allows charge carriers to pass directly through the potential barrier with a very high probability through quantum tunneling, eliminating the metal-semiconductor interface barrier. This transforms the original rectifying contact into an ohmic contact, achieving ultra-low contact resistance. Since the upper electrode structure 120 is connected to the gold wire 212 and the lower electrode structure 130 is connected to the pad 211, both of which are metal-to-metal connections with low resistance, the bonding bridge chip 100 of this embodiment can reduce the resistance of the bonding bridge chip 100.

[0027] In this embodiment, an electrode contact region 111 is formed on the bonding bridge chip, and the doping concentration of the electrode contact region 111 is set to 1*10. 19 -5*10 19 cm -3 This fundamentally eliminates the interface barrier, significantly reducing the contact resistance between the upper electrode structure 120 and the lower electrode structure 130 and the semiconductor substrate, resulting in smoother current transmission. The defined doping concentration range ensures that the resistance of each electrode contact area 111 remains highly consistent during mass production, improving resistance uniformity. In summary, the bonding bridge chip 100 of this application embodiment can reduce the resistance of the bonding bridge chip 100 and improve resistance uniformity.

[0028] It is understood that the embodiments of this application do not limit the number or positional relationship of the upper electrode structure 120 and the lower electrode structure 130, as long as they correspond to the arrangement of the pads 211 on the circuit board 210. In addition, the upper electrode structure 120 and the lower electrode structure 130 are connected to the number of electrode contact areas 111 respectively.

[0029] Optional, such as Figure 1 , Figure 2 and Figure 3As shown, both the upper electrode structure 120 and the lower electrode structure 130 include an adhesion layer 141, a barrier layer 142 and a conductive layer 143 arranged sequentially along the direction away from the substrate 110. The upper electrode structure 120 is used to connect with the gold wire 212, and the lower electrode structure 130 is used to connect with the pad 211 of the circuit board 210.

[0030] The upper electrode structure 120 and the lower electrode structure 130 adopt a three-layer composite structure, which consists of an adhesion layer 141, a barrier layer 142 and a conductive layer 143 in sequence along the direction away from the substrate 110. The adhesion layer 141 is closest to the substrate 110 and is used to enhance the adhesion between the metal and the substrate 110. The barrier layer 142 is located in the middle and is used to prevent the mutual diffusion between different materials. The conductive layer 143 is located on the outermost layer and serves as the main current transmission channel.

[0031] The upper electrode structure 120 is used to connect with the gold wire 212. Specifically, the upper electrode structure 120 and the gold wire 212 are connected by a wire bonding process. The lower electrode structure 130 is used to connect with the pad 211 of the circuit board 210. Specifically, the lower electrode structure 130 and the pad 211 are connected by a reflow soldering or thermoforming process.

[0032] Due to lattice mismatch or differences in thermal expansion coefficients between the conductive layer 143 and the semiconductor substrate, direct contact can easily lead to detachment. The adhesion layer 141 can form a good chemical bond with the substrate 110, firmly holding the substrate 110. In subsequent packaging processes, such as high-temperature wire bonding or soldering, atoms in the conductive layer 143 can easily diffuse into the semiconductor substrate, leading to device performance degradation or even failure. The barrier layer 142 can effectively cut off the diffusion path of atoms, protecting the substrate 110. The outermost conductive layer 143 has extremely high conductivity and is responsible for efficiently conducting current to external connection media, such as gold wires 212 or pads 211.

[0033] The adhesion layer 141 and the barrier layer 142 solve the defects of single-layer electrodes being prone to detachment and having weak interfacial adhesion. Even after multiple thermal cycles or mechanical stresses, the electrode and the substrate 110 can still maintain tight contact, avoiding ohmic contact failure caused by physical peeling. The barrier layer 142 effectively prevents the interdiffusion of atoms in the conductive layer 143 under high-temperature processes, avoiding the formation of high-resistivity intermetallic compounds at the interface, ensuring that the contact resistance remains stable and consistent throughout the chip's entire lifespan, and improving resistance consistency.

[0034] As an feasible approach, such as Figure 1 As shown, the substrate 110 is a silicon substrate, the adhesion layer 141 is titanium, the barrier layer 142 is nickel, and the conductive layer 143 is gold.

[0035] When the substrate 110 is a silicon substrate, high-resistivity single-crystal silicon is selected as the chip substrate 110. The resistivity of substrate 110 is >1000Ω·cm, with excellent natural insulation, no substrate leakage current, extremely low crosstalk, low material cost, and mature cutting process. It is suitable for mass production of general-purpose modules and is the optimal solution for industrial-grade low cost.

[0036] Titanium is an extremely reactive transition metal that readily reacts with silicon at high temperatures to form titanium silicide. Titanium silicide can form strong covalent / metallic bonds with the silicon substrate, thus achieving adhesion. The titanium silicide formed by the reaction of titanium with heavily doped silicon has extremely low specific contact resistance. Combined with the heavily doped electrode contact region 111, this material combination minimizes the potential barrier at the metal-semiconductor interface, fundamentally solving the problems of poor ohmic contact performance and impeded current transport.

[0037] Nickel has a dense crystal structure that effectively prevents the diffusion of outermost gold atoms into the silicon substrate 110 at high temperatures. Simultaneously, the nickel layer also acts as a stress buffer, alleviating mechanical stress caused by the difference in thermal expansion coefficients between silicon and gold. The nickel barrier layer 142 effectively isolates the direct contact between gold and silicon, preventing the formation of high-resistivity gold-silicon compounds during high-temperature processing. This ensures that the chip's contact resistance remains highly consistent after reflow soldering or prolonged high-temperature operation, preventing electrical performance drift and degradation.

[0038] Gold is a precious metal with excellent electrical conductivity and chemical inertness. As the outermost layer, its extremely smooth surface and lack of oxide layer not only provide very low contact resistance but also ensure stability in air, preventing oxidation and thus guaranteeing a strong bond with the gold wire 212 or the circuit board pad 211. Furthermore, being of the same material as the gold wire 212, it exhibits extremely strong bonding adhesion, capable of withstanding multiple bonding cycles and high / low temperature cycling, completely eliminating the possibility of gold wire 212 desoldering or breakage.

[0039] Optional, such as Figure 1 As shown, the upper electrode structure 120 also includes an aluminum layer 144 disposed between the barrier layer 142 and the adhesion layer 141. That is, the upper electrode structure 120 is a four-layer composite structure consisting of a titanium layer, an aluminum layer 144, a nickel layer and a gold layer disposed sequentially on the surface of the substrate 110.

[0040] When the aluminum layer 144 is located between the titanium layer and the nickel layer, the aluminum layer 144 is an ultra-high conductivity metal, which significantly reduces the electrode bulk resistance, improves the transmission capability of high current and high frequency signals, and at the same time helps to fill the micro-gaps at the interface, optimizing the carrier transport channel. The nickel layer is located between the aluminum layer 144 and the gold layer, which isolates the metal interdiffusion between the aluminum layer 144 and the top gold layer, avoids electrode failure caused by alloy phase transformation, and improves high-temperature stability.

[0041] Furthermore, titanium, nickel, and gold each have different coefficients of thermal expansion. Aluminum, as a relatively soft and highly ductile metal, can act as a stress buffer when sandwiched between titanium and nickel. When the chip undergoes high-temperature bonding or operation, the aluminum layer 144 can absorb and alleviate the mechanical stress caused by the mismatch in thermal expansion between layers through its own deformation.

[0042] As an feasible approach, such as Figure 1 As shown, the thicknesses of the adhesion layer 141, the barrier layer 142, and the conductive layer 143 of the lower electrode structure 130 are 20~30nm, 40~60nm, and 30~50nm, respectively; the thicknesses of the adhesion layer 141, the aluminum layer 144, the barrier layer 142, and the conductive layer 143 of the upper electrode structure 120 are 15~25nm, 180-100nm, 30~40nm, and 50~80nm, respectively.

[0043] The upper electrode structure is a Ti (15~25nm) / Al (80~100nm) / Ni (30~40nm) / Au (50~80nm) structure, used for bonding with the gold wire 212. Therefore, the upper electrode structure 120 needs to withstand the huge mechanical impact during the bonding of the gold wire 212. The 100~180nm aluminum layer 144 occupies most of the thickness of the upper electrode, and its excellent ductility acts as a stress buffer. The 50~80nm gold layer provides sufficient volume to ensure that a strong solder ball can be formed during the bonding of the gold wire 212, preventing poor soldering or detachment.

[0044] The lower electrode structure 130 is a Ti (20~30nm) / Ni (40~60nm) / Au (30~50 nm) structure, used for soldering to the pads 211 of the circuit board 210. The 20~30nm titanium layer is sufficient to form a dense titanium silicide on the silicon surface; the 40~60nm nickel layer provides sufficient barrier power to prevent solder erosion; and the 30~50nm gold layer just meets the requirements for surface oxidation resistance and solderability. The overall thinness helps to reduce the thermal stress of the lower electrode during the soldering process.

[0045] For titanium and nickel as functional thin films, excessive thickness increases unnecessary parasitic resistance and manufacturing costs, while excessive thinness fails to provide adhesion and barrier properties. The aforementioned thickness range falls precisely within the golden range that allows for the formation of continuous, dense thin films while minimizing parasitic resistance.

[0046] Optional, such as Figure 2 As shown, the substrate 110 is a semiconductor compound substrate, the adhesion layer 141 of the upper electrode structure 120 is titanium, the barrier layer 142 is platinum, and the conductive layer 143 is gold.

[0047] When the substrate 110 is a semiconductor compound substrate, N-type semiconductor compound substrates such as GaAs, GaP, and SiC can be selected. These substrates offer significantly better electron mobility, saturation drift velocity, and high-temperature resistance than silicon-based substrates. They also exhibit extremely low high-frequency losses, higher interface lattice matching, and can achieve superior ohmic contact linearity, making them suitable for high-reliability applications in radio frequency, high-frequency, and military-grade applications. It is understood that those skilled in the art can select a suitable substrate based on the application scenario.

[0048] When titanium comes into contact with semiconductor compounds, it can effectively reduce the Schottky barrier. Through subsequent annealing processes, titanium can react with semiconductor compounds to form extremely stable and low-resistance ohmic contacts.

[0049] Platinum is a high-melting-point, highly stable precious metal. In the high-temperature annealing or packaging processes typically required for semiconductor compound devices, the platinum layer effectively prevents the diffusion of outermost gold atoms into the semiconductor compound, avoiding the formation of deep-level defects that degrade device performance. Simultaneously, platinum also prevents the underlying titanium layer from migrating to the surface and oxidizing. As a barrier layer, Pt 142 offers even higher chemical stability, making it suitable for high-frequency, high-temperature operating conditions.

[0050] The top gold layer, as the outermost layer, provides excellent conductivity and chemical inertness, ensuring that no surface oxidation occurs when bonding with the gold wire 212, guaranteeing the strength of the bond, and has excellent flatness. The gold wire 212 has higher bonding strength and stronger aging resistance.

[0051] As an feasible approach, such as Figure 2 As shown, the substrate 110 is a semiconductor compound substrate, the adhesion layer 141 of the upper electrode structure 120 is germanium, the barrier layer 142 is nickel, and the conductive layer 143 is gold.

[0052] Germanium shares highly similar lattice constants and coefficients of thermal expansion with many semiconductor compounds. Through sputtering or evaporation deposition, coupled with appropriate annealing processes, germanium can form an extremely smooth interface with low defect density with semiconductor compounds, thereby effectively reducing the interface barrier and achieving excellent ohmic contacts.

[0053] The nickel layer, acting as a dense physical barrier, effectively blocks the diffusion of the outermost gold layer into the semiconductor compound substrate during high-temperature processing, preventing deep-level defects that could lead to device leakage or performance degradation. Simultaneously, the nickel layer provides a favorable substrate for the subsequent adhesion of the gold layer.

[0054] The outermost gold layer not only provides extremely low vertical on-resistance, but also, thanks to its extremely high chemical inertness, prevents the oxidation of the underlying germanium and nickel in the air, ensuring strong bonding with the outer gold wire 212.

[0055] Optional, such as Figure 2As shown, the thicknesses of the adhesion layer 141, the barrier layer 142, and the conductive layer 143 of the lower electrode structure 130 are 30~50nm, 20~40nm, and 40~60nm, respectively; the thicknesses of the adhesion layer 141, the barrier layer 142, and the conductive layer 143 of the upper electrode structure 120 are 15~25nm, 40~60nm, and 50~90nm, respectively.

[0056] The upper electrode structure is a Ti (15~25nm) / Al (80~100nm) / Ni (30~40nm) / Au (50~80nm) stacked structure, used for bonding with the gold wire 212. Therefore, the upper electrode structure 120 needs to withstand the huge mechanical impact during the bonding of the gold wire 212. The 30~50nm adhesion layer 141 is sufficient to form a dense interface reaction layer on the surface of the semiconductor compound substrate; the 20~40nm barrier layer 142 provides sufficient barrier capability to prevent solder erosion; and the 40~60nm conductive layer 143 just meets the requirements of surface oxidation resistance and solderability. The overall thinness helps to reduce the thermal stress of the lower electrode during the welding process.

[0057] The lower electrode structure 130 is a Ni (30~50nm) / Ge (20~40nm) / Au (40~60nm) stacked structure, used for soldering to the pads 211 of the circuit board 210. The 30~50nm adhesion layer 141 is sufficient to form a dense interface reaction layer on the surface of the semiconductor compound substrate; the 20~40nm barrier layer 142 provides sufficient barrier capability to prevent solder erosion; and the 40~60nm conductive layer 143 just meets the requirements of surface oxidation resistance and solderability. The overall thinness helps to reduce the thermal stress of the lower electrode during the soldering process.

[0058] By controlling the thickness of each functional layer within a reasonable range, the proportion of high-resistivity metal in the vertical current path is significantly reduced. Combined with the outermost thicker low-resistivity conductive layer 143, the resistance of the bonding bridge chip 100 is reduced. The thicker conductive layer 143 of the electrodes provides sufficient mechanical support and heat capacity for the gold wire 212 bonding, effectively absorbing the kinetic and thermal energy during wire bonding, and significantly improving the tensile and shear strength of the wires. The reasonable thickness ratio of the lower electrode ensures wettability and adhesion during soldering to the PCB, avoiding soldering defects caused by uneven thickness.

[0059] As one feasible approach, the electrode contact region 111 is doped with an N-type doping type.

[0060] N-type doping makes the charge carriers in electrode contact region 111 free electrons, resulting in higher electron mobility, stronger barrier tunability, and optimal lattice matching with low work function transition metal (Ti), which can minimize the interfacial contact barrier.

[0061] The size of the bonding bridge chip 100 is not limited in this embodiment. Specifically, the minimum chip size can reach 100μm×100μm. The number of bonding bridge chips 100 that can be produced from one wafer can be increased by tens of times, which greatly reduces the cost per bonding bridge chip 100. At the same time, there is no need for the 211 nickel palladium gold plating of the circuit board pads. Combined with the advantages of ultra-small chip consumables, the overall module cost is significantly reduced compared with traditional solutions, and the mass production cost-effectiveness is extremely high.

[0062] In a second aspect, this application also provides a method for fabricating a bonding bridging chip 100, such as... Figure 4 As shown, it includes: S10: Provide a substrate 110, the substrate 110 including an electrode contact region 111; The substrate 110 can be made of the same material as the bonding bridging chip 100 described above, such as a silicon substrate or a semiconductor compound substrate. The position of the electrode contact area 111 can be set according to the position of the pad 211.

[0063] S20: Doping is performed in the electrode contact region 111, wherein the doping concentration of the electrode contact region 111 is 1*10 19 -5*10 19 cm -3 between; Specifically, ion implantation can be used to dope the electrode contact region 111. In practical applications, the doping in the electrode contact region 111 is carried out by rapid thermal annealing at 1050℃ for 30s to repair ion implantation lattice damage, activate doped ions, achieve a carrier activation rate of ≥95%, and ensure uniform carrier concentration throughout the region.

[0064] S30: An upper electrode structure 120 connected to the electrode contact area 111 is formed on the upper surface of the substrate 110; The upper electrode structure 120 can be formed by low-temperature deposition of various material layers using magnetron sputtering, avoiding the diffusion failure of doped ions caused by high temperatures and ensuring that the metal layer is dense, pinhole-free, and of uniform thickness. The specific structure of the upper electrode structure 120 is the same as that of the bonding bridging chip 100 described above, but varies depending on the substrate material 110, and will not be elaborated here.

[0065] S40: A lower electrode structure 130 connected to the electrode contact area 111 is formed on the lower surface of the substrate 110; The lower electrode structure 130 can be formed by low-temperature deposition of various material layers using magnetron sputtering, avoiding the diffusion failure of doped ions caused by high temperatures and ensuring that the metal layer is dense, pinhole-free, and of uniform thickness. The specific structure of the lower electrode structure 130 is the same as that of the bonding bridging chip 100 described above, but varies depending on the substrate material 110, and will not be elaborated here.

[0066] S50: Annealing the substrate 110 on which the upper electrode structure 120 and the lower electrode structure 130 are formed, at an annealing temperature between 450 and 550°C.

[0067] Rapid annealing at 450~550℃ in a nitrogen atmosphere promotes the alloying reaction at the interface of titanium, nickel and silicon substrate, forming stable low-resistivity silicides, thoroughly solidifying ohmic contact characteristics, and achieving bidirectional non-rectified linear conduction.

[0068] Optionally, magnetron sputtering is used to deposit metal on the upper and lower surfaces of the substrate 110 at low temperature to form an upper electrode structure 120 and a lower electrode structure 130.

[0069] As one feasible approach, the fabrication method of the bonding bridging chip 100 further includes, prior to doping the substrate 110 to form the electrode contact region 111: S01: Clean the substrate 110; Specifically, SC1 and SC2 standard cleaning processes are used to remove surface particles and organic matter.

[0070] S02: Remove the oxide layer from the surface of substrate 110.

[0071] Specifically, the natural oxide layer on the surface can be removed using a dilute hydrofluoric acid solution, ensuring direct lattice contact between the metal and the semiconductor.

[0072] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0073] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this application will not describe the various possible combinations separately.

Claims

1. A bonding bridge chip, characterized in that, The substrate includes an electrode contact region, the doping concentration of which is 1*10⁻⁶. 19 -5*10 19 cm -3 Between them, the upper surface of the substrate is provided with an upper electrode structure connected to the electrode contact area, and the lower surface of the substrate is provided with a lower electrode structure connected to the electrode contact area.

2. The bonding bridge chip according to claim 1, characterized in that, Both the upper electrode structure and the lower electrode structure include an adhesion layer, a barrier layer, and a conductive layer arranged sequentially along the direction away from the substrate. The upper electrode structure is used to connect with gold wires, and the lower electrode structure is used to connect with the solder pads of the circuit board.

3. The bonding bridge chip according to claim 2, characterized in that, The substrate is a silicon substrate, the adhesion layer is titanium, the barrier layer is nickel, and the conductive layer is gold.

4. The bonding bridge chip according to claim 3, characterized in that, The upper electrode structure also includes an aluminum layer disposed between the barrier layer and the adhesion layer.

5. The bonding bridge chip according to claim 4, characterized in that, The thicknesses of the adhesion layer, barrier layer, and conductive layer of the lower electrode structure are 20-30 nm, 40-60 nm, and 30-50 nm, respectively; the thicknesses of the adhesion layer, aluminum layer, barrier layer, and conductive layer of the upper electrode structure are 15-25 nm, 180-100 nm, 30-40 nm, and 50-80 nm, respectively.

6. The bonding bridge chip according to claim 2, characterized in that, The substrate is a semiconductor compound substrate, the adhesion layer of the upper electrode structure is titanium, the barrier layer is platinum, and the conductive layer is gold.

7. The bonding bridge chip according to claim 6, characterized in that, The substrate is a semiconductor compound substrate, the adhesion layer of the upper electrode structure is germanium, the barrier layer is nickel, and the conductive layer is gold.

8. The bonding bridge chip according to claim 7, characterized in that, The thicknesses of the adhesion layer, barrier layer, and conductive layer of the lower electrode structure are 30-50 nm, 20-40 nm, and 40-60 nm, respectively; the thicknesses of the adhesion layer, barrier layer, and conductive layer of the upper electrode structure are 15-25 nm, 40-60 nm, and 50-90 nm, respectively.

9. The bonding bridge chip according to claim 1, characterized in that, The electrode contact region is doped with N-type doping.

10. A method for fabricating a bonding bridging chip, characterized in that, include: A substrate is provided, the substrate including an electrode contact region; The electrode contact region is doped, wherein the doping concentration in the electrode contact region is 1*10⁻⁶. 19 -5*10 19 cm -3 between; An upper electrode structure connected to the electrode contact area is formed on the upper surface of the substrate; A lower electrode structure connected to the electrode contact area is formed on the lower surface of the substrate; The substrate having the upper electrode structure and the lower electrode structure is annealed at a temperature between 450 and 550°C.

11. The method for fabricating a bonding bridge chip according to claim 10, characterized in that, Metal is deposited on the upper and lower surfaces of the substrate by magnetron sputtering to form an upper electrode structure and a lower electrode structure, wherein the magnetron sputtering temperature is between 450 and 550°C.

12. The method for fabricating a bonding bridge chip according to claim 10, characterized in that, Before doping to form the electrode contact region on the substrate, the method further includes: The substrate is cleaned; Remove the oxide layer from the substrate surface.

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