Semiconductor structure, semiconductor package and method of forming a semiconductor structure

Abstract

The embodiments of the present disclosure provide a semiconductor structure, a semiconductor package and a forming method of the semiconductor structure. The semiconductor structure provided by the embodiments of the present disclosure comprises a first surface provided with a first conductive pad and a first isolation layer, the first isolation layer at least exposing a surface of the first conductive pad; a first connecting layer arranged on the surface of the first conductive pad exposed to the first isolation layer and on the first isolation layer; a first conductive bump arranged on the first connecting layer and corresponding to the first conductive pad; and in a cross section perpendicular to the first surface, the absolute value of the difference between the width of the first conductive pad and the width of the first connecting layer is greater than the absolute value of the difference between the width of the first conductive pad and the width of the first conductive bump. The semiconductor structure provided by the embodiments of the present disclosure has a relatively large gap between the first connecting layer and the first conductive bump, which is convenient for subsequent filling and sealing.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure, a semiconductor package, and a method for forming a semiconductor structure. Background Technology

[0002] As chip integration increases, the density of devices within chips grows ever higher. To realize the chip's functions, these devices need to be interconnected internally, as well as interconnected with the outside of the chip. Internal interconnections mainly refer to the metal wiring layers located inside the chip, while external interconnections mainly refer to conductive bumps that connect to the internal wiring layers. These conductive bumps are exposed on the top of the chip, and solder can be applied to their exposed surfaces. The conductive bumps are then connected to other chips or circuit boards via the solder.

[0003] Structurally, the conductive bumps that enable interconnection between the chip and the outside world consist of the bump itself and the UBM layer (Under Bump Metallurgy) located between the bump and the internal metal wiring of the chip. During the formation of the UBM layer, it is often undercut due to its isotropic etching characteristics. This results in a gap between the bump and the chip, which affects the reliability of subsequent processes and may even prevent the establishment of an effective electrical connection between the bump and the internal metal wiring of the chip. Summary of the Invention

[0004] This disclosure provides semiconductor structures with higher yields and methods for forming them.

[0005] The technical spirit of this disclosure aims to solve problems not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] Some embodiments of this disclosure provide a semiconductor structure, including: a first surface having a first conductive pad and a first isolation layer, the first isolation layer exposing at least a portion of the surface of the first conductive pad; a first connection layer disposed on the surface of the first conductive pad exposed on the first isolation layer and on the first isolation layer; a first conductive bump disposed on the first connection layer, corresponding to the first conductive pad; in a cross-section perpendicular to the first surface, the first conductive pad has a first width, the first connection layer has a second width, and the first conductive bump has a third width, the second width being the sum of the width of the first connection layer on the first isolation layer and the width of the first connection layer on the first conductive pad, wherein the absolute value of the difference between the first width and the second width is greater than the absolute value of the difference between the first width and the third width.

[0007] In embodiments of this disclosure, the absolute value of the difference between the first width and the third width is less than the absolute value of the difference between the second width and the third width.

[0008] In embodiments of this disclosure, in cross-section, the first conductive pad exposed by the first insulating layer has a fourth width, which is greater than 1 / 2 of the first width.

[0009] In embodiments of this disclosure, the semiconductor structure further includes a first solder layer, which is formed at least on the first isolation layer and adjacent to the first interconnect layer.

[0010] In embodiments of this disclosure, a first solder layer covers the surface of a first conductive bump.

[0011] In embodiments of this disclosure, the semiconductor structure further includes a second surface opposite to the first surface, the second surface having a second conductive pad and a second isolation layer surrounding the second conductive pad; a second connection layer disposed on the second conductive pad and the second isolation layer; a second conductive bump disposed on the second connection layer, corresponding to the second conductive pad, wherein in a cross-section perpendicular to the second surface, the width of the second connection layer is smaller than the width of the second conductive bump; and a second solder layer formed at least on the second isolation layer and adjacent to the second connection layer.

[0012] This disclosure also provides a semiconductor package, comprising: a plurality of interconnected semiconductor structures, each semiconductor structure including: a first surface having a first conductive pad and a first isolation layer disposed thereon, the first isolation layer exposing at least a portion of the surface of the first conductive pad; a first connection layer disposed on the surface of the first conductive pad exposed on the first isolation layer, the first connection layer also disposed on the first isolation layer; and a first conductive bump disposed on the first connection layer, corresponding to the first conductive pad; in a cross-section perpendicular to the first surface, the first conductive pad has a first width, the first connection layer has a second width, and the first conductive bump has a third width, the second width being the sum of the width of the first connection layer on the first isolation layer and the width of the first connection layer on the first conductive pad, wherein the absolute value of the difference between the first width and the second width is greater than the absolute value of the difference between the first width and the third width; the first surfaces of at least two adjacent semiconductor structures face each other and are electrically connected through their respective first conductive bumps.

[0013] In embodiments of this disclosure, the absolute value of the difference between the first width and the third width of each semiconductor structure is less than the absolute value of the difference between the second width and the third width.

[0014] In embodiments of this disclosure, the package further includes: a first solder layer disposed between first conductive bumps of each semiconductor structure facing each other on a first surface, the first solder layer also being formed on a first isolation layer of each semiconductor structure and adjacent to a first interconnect layer.

[0015] In embodiments of this disclosure, each semiconductor structure further has a second surface opposite to the first surface, and the package further includes at least two adjacent semiconductor structures whose second surfaces face each other, wherein each semiconductor structure whose first surfaces face each other has a first spacing, and each semiconductor structure whose second surfaces face each other has a second spacing, and in the direction in which the semiconductor structures are connected to each other, the first spacing is greater than the second spacing.

[0016] In embodiments of this disclosure, each semiconductor structure has a second conductive pad and a second isolation layer surrounding the second conductive pad on its second surface; a second connection layer is disposed on the second conductive pad and the second isolation layer; a second conductive bump is disposed on the second connection layer and corresponding to the second conductive pad, wherein the width of the second connection layer is smaller than the width of the second conductive bump in a cross-section perpendicular to the second surface; the package further includes a second solder layer disposed between each semiconductor structure facing each other on its second surface, the second solder layer also being formed on the second isolation layer of each semiconductor structure and adjacent to the second connection layer.

[0017] In the embodiments of this disclosure, the first surface is the front side of the semiconductor structure, and the second surface is the back side of the semiconductor structure.

[0018] This disclosure also provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate; forming a first surface by disposing a first conductive pad and a first isolation layer covering a portion of the first conductive pad on the substrate; forming an initial first connection layer on the first surface, the initial first connection layer covering the surfaces of the first conductive pad and the first isolation layer; forming a first conductive bump on the initial first connection layer, the first conductive bump being disposed corresponding to the first conductive pad; removing a portion of the initial first connection layer, retaining a portion of the initial first connection layer located between the first conductive bump and the first conductive pad, forming a first connection layer; wherein, in a cross-section perpendicular to the first surface, the first conductive pad has a first width, the first connection layer has a second width, and the first conductive bump has a third width, the second width being the sum of the width of the first connection layer on the first isolation layer and the width of the first connection layer on the first conductive pad, and the absolute value of the difference between the first width and the second width being greater than the absolute value of the difference between the first width and the third width.

[0019] In embodiments of this disclosure, before or after removing a portion of the initial first connection layer, the method further includes: treating the sidewalls of the first conductive bump and the exposed surface of the first isolation layer with plasma, wherein the sidewalls of the first conductive bump are treated with microwave plasma and the exposed surface of the first isolation layer is treated with radio frequency plasma.

[0020] In embodiments of this disclosure, a first solder layer is formed on a first conductive bump, and the first solder layer is reflowed such that the first solder layer is formed at least on a first insulating layer and adjacent to a first interconnect layer.

[0021] The semiconductor structure provided in this embodiment controls the width range between the first conductive pad, the first connecting layer, and the first conductive bump, so that there is a relatively large gap between the first connecting layer and the first conductive bump. The width range of the gap is controlled between 1.5 micrometers and 2.5 micrometers. The larger gap allows the subsequent sealing layer to be completely filled, avoiding incomplete sealing and the formation of holes. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0023] Figures 1 to 9 This is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0024] Figures 10 to 11 This is a cross-sectional schematic diagram of a semiconductor package provided in an embodiment of this disclosure.

[0025] Figure 12 This is a schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0026] Figures 13 to 17 This is a schematic diagram of the cross-section of the semiconductor structure during the formation of the semiconductor structure.

[0027] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0028] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely illustrative of the relevant disclosure and not intended to limit it. Furthermore, it should be noted that only relevant parts are shown in the accompanying drawings for ease of description. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first," "second," and "third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects.

[0029] The semiconductor structure provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0030] First see Figure 1 and Figure 2 , Figure 1 and Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure provided in some embodiments of the present disclosure. The semiconductor structure 10 includes a semiconductor substrate 100, on which a first conductive pad 101 and a first isolation layer 102 are disposed. The first isolation layer 102 covers a portion of the surface of the first conductive pad 101, and a portion of the surface of the first conductive pad 101 is not covered by the first isolation layer 102; that is, the first isolation layer 102 exposes at least a portion of the surface of the first conductive pad 101. The first isolation layer 102 and the exposed surfaces of the first conductive pad 101 form a first surface 10A of the semiconductor structure 10.

[0031] The semiconductor structure 10 further includes a first interconnect layer 200 disposed on the first surface 10A. The first interconnect layer 200 includes a portion of the first conductive pad 101 exposed on the surface of the first isolation layer 102 and a portion disposed on the surface of the first isolation layer 101. The semiconductor structure 10 also includes a first conductive bump 201 disposed on the first interconnect layer 200 and correspondingly disposed with respect to the first conductive pad 101. The first conductive bump 201 and the first conductive pad 101 are electrically connected through the first interconnect layer 200.

[0032] In the above embodiment, in a cross-section perpendicular to the first surface 10A, the first conductive pad 101 has a first width W1, the first connecting layer 200 has a second width W2, and the first conductive bump 201 has a third width W3. The width W2 of the first connecting layer 200 is the sum of the width W20 of the portion located on the first insulating layer 102 and the width W21 of the portion located on the exposed surface of the first conductive pad 101. The absolute value of the difference between the first width W1 and the second width W2 is greater than the absolute value of the difference between the first width W1 and the third width W3.

[0033] In some of the above embodiments, a cross-section perpendicular to the first surface 10A is a cross-section formed by cutting along the center point of the first conductive pad 101 or the first conductive bump 201. In this case, the first width W1 is the maximum width of the first conductive pad 101 in the cross-section perpendicular to the first surface 10A, the second width W2 is the maximum width of the first connecting layer 200 in the cross-section perpendicular to the first surface 10A, and the third width W3 is the maximum width of the first conductive bump 201 in the cross-section perpendicular to the first surface 10A.

[0034] In some of the above embodiments, the first width W1 is greater than the second width W2, the first width W1 can be greater than or less than the third width W3, and the second width W2 is less than the third width W3. For example... Figure 1 As shown, the first width W1 is greater than the second width W2 and the third width W3, and the second width W2 is less than the third width W3. In this case, the difference between the first width W1 and the second width W2 is greater than the difference between the first width W1 and the third width W3. In some other embodiments described above, such as... Figure 2 As shown, the first width W1 is greater than the second width W2 and less than the third width W3. The second width W2 is less than the third width W3. At this time, the difference between the first width W1 and the second width W2 is greater than the absolute value of the difference between the first width W1 and the third width W3.

[0035] In the above embodiments, the absolute value of the difference between the first width W1 and the second width W2 is in the range of 3 micrometers to 5 micrometers, for example, it can be in the range of 3 micrometers to 3.5 micrometers, 3.5 micrometers to 4 micrometers, 4 micrometers to 4.5 micrometers, 4.5 micrometers to 5 micrometers, etc. The absolute value of the difference between the first width W1 and the third width W3 is in the range of 1 micrometer to 3 micrometers, for example, it can be in the range of 1 micrometer to 1.5 micrometers, 1.5 micrometers to 2 micrometers, 2 micrometers to 2.5 micrometers, 2.5 micrometers to 3 micrometers, etc.

[0036] In some of the above embodiments, such as Figure 1 and Figure 2As shown, there is a height difference between the surface of the first isolation layer 102 and the exposed surface of the first conductive pad 101; that is, the surface of the first isolation layer 102 is higher than the exposed surface of the first conductive pad 101. Consequently, the first surface 10A of the semiconductor structure 10 has a stepped surface, and the first interconnect layer 200 covers this stepped surface. In some embodiments, the surface of the first interconnect layer 200 located on the surface of the first conductive pad 101 is lower than the surface of the first interconnect layer 200 located on the surface of the first isolation layer 102. That is, there is a depression in the area of ​​the first interconnect layer 200 corresponding to the first conductive pad 101, and the first conductive bump 201 fills this depression and protrudes from the surface of the first interconnect layer 200.

[0037] In the above embodiments, the semiconductor substrate 100 may be made of or may include various types of semiconductor materials, including, for example, silicon, germanium, group III to V semiconductors, or other suitable materials. A device layer 103 is further disposed between the semiconductor substrate 100 and the first conductive pad 101. The device layer 103 contains semiconductor devices and a metal interconnect layer for interconnecting the semiconductor devices. The semiconductor devices may include transistors and capacitors connected to the transistors, such as DRAM device cells. The type of semiconductor device is not limited and may also be other types. The metal interconnect layer may be a conductive path that connects the semiconductor devices to each other to form a functional circuit and connects the semiconductor devices to external units. The metal interconnect layer may include one or more layers of metal wiring.

[0038] In the above embodiments, the first conductive pad 101 may be the topmost metal wiring layer that is interconnected with the metal interconnect layer in the device layer 103, for example, it may be an aluminum wiring layer or a copper wiring layer.

[0039] In the above embodiments, the first isolation layer 102 can be a passivation layer, and its material can be silicon nitride, silicon dioxide, polyimide, or other materials.

[0040] In the above embodiments, the first connecting layer 200 may be a UBM layer, which may be a single conductive layer or a composite conductive layer composed of two or more conductive layers. The material of the first connecting layer 200 may be one or a combination of metals such as titanium, copper, nickel, cobalt, and gold. When the first connecting layer 200 is a composite layer, for example, when the first connecting layer 200 is a composite layer of titanium and copper layers, the second width W2 of the first connecting layer 200 may be the average value of the widths of each layer.

[0041] In the above embodiments, the first conductive bump 201 can be cylindrical, rectangular, trapezoidal, inverted trapezoidal, or other shapes, and its material can be conductive metals such as copper, nickel, or gold.

[0042] In some embodiments, see continue to see Figure 1 and Figure 2 The semiconductor structure 10A also includes a first solder layer 202 disposed on the first conductive bump 201. The first solder layer 202 covers the top surface of the first conductive bump 201 and is used to form solder joints on the surface of the first conductive bump 201.

[0043] In some embodiments, after the first conductive bump 201 is soldered using the first solder layer 202, the semiconductor structure 10A further includes a sealing layer. For example... Figure 3 As shown, Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure provided in some embodiments of this disclosure. A sealing layer 300 covers the exposed surfaces of the first isolation layer 102, the first interconnect layer 200, the first conductive bumps 201, and the first solder layer 202, serving to isolate adjacent first conductive bumps 201 and first solder layers 202, thereby achieving insulation and protection for each first conductive bump 201 and each first solder layer 202. The sealing layer 300 may also be formed on... Figure 2 In the semiconductor structure shown, Figure 3 exist Figure 1 The example illustrates the location of the sealing layer, but does not limit the location of the sealing layer 300. The sealing layer 300 can be a molding compound, a non-conductive film (NCF), or other types of insulating sealing materials.

[0044] See also Figure 3 In the above embodiment, due to the difference in width between the first interconnect layer 200 and the first conductive bump 201, a gap region A exists between them, exposing the surface of the first isolation layer 102. The gap A exists because, during the formation of the first interconnect layer, the different materials of the first conductive bump and the first interconnect layer result in different etching selectivity ratios, leading to the first interconnect layer being etched more than the first conductive bump. However, gap A is generally undesirable, and its width is controlled to a small range, for example, less than 1 micrometer. This is because if the width of gap A is too large, it will lead to the loss of the first interconnect layer, thereby increasing the connection resistance and reducing the adhesion between the first conductive bump and the first conductive pad. However, if gap A is too small, although the aforementioned disadvantages can be overcome, with the miniaturization of semiconductor structures, an excessively small gap A will make it difficult for the sealing layer, which provides sealing and isolation, to completely fill gap A. This will result in a gap between the first conductive bump and the first isolation layer in the final packaged semiconductor structure, which will affect the electrical performance and mechanical strength of the first conductive bump.

[0045] In the semiconductor structure provided in this embodiment, by controlling the width range between the first conductive pad, the first interconnect layer, and the first conductive bump, a relatively large gap A exists between the first interconnect layer and the first conductive bump. The width range of gap A is controlled between 1.5 micrometers and 2.5 micrometers. The larger gap allows the subsequent sealing layer 300 to completely fill the gap, avoiding incomplete sealing and the formation of voids. Furthermore, to compensate for the increased resistance caused by the loss of the first interconnect layer due to the larger gap A, and the issue of connection strength with the first conductive pad, this can be achieved by appropriately increasing the width of the first conductive bump and increasing the surface area of ​​the first conductive pad exposed on the first isolation layer. That is, by reducing the difference between the first width W1 and the third width W2, the width W21 of the portion of the first interconnect layer located on the exposed surface of the first conductive pad is increased, while the width W20 of the portion of the first interconnect layer located on the first isolation layer is decreased.

[0046] In some embodiments, such as Figures 1 to 3 As shown, the surface of the first conductive pad 101 exposed by the first insulating layer 102 has a fourth width (not shown), which is the width W21 of the portion of the first connecting layer 200 on the surface of the first conductive pad 101. The fourth width is greater than 1 / 2 of the first width W1, and in some embodiments, the fourth width is not less than 5 / 7, 3 / 4, 6 / 7, etc. of the first width W1.

[0047] Embodiments of this disclosure also provide a semiconductor structure, see details below. Figures 4 to 5 , Figure 4 and Figure 5 This is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0048] The following is a detailed description Figure 4 and Figure 5 The provided semiconductor structure. Figure 4 and Figure 5 The provided semiconductor structures 10 all include a semiconductor substrate 100, a device layer 103 disposed on the semiconductor substrate 100, a first conductive pad 101 located on the device layer 103 and electrically connected to the device layer 103, and a first isolation layer 102 partially covering the first conductive pad 101. A first connection layer 200 is disposed on a portion of the surface of the first conductive pad 101 and the first isolation layer 102. A first conductive bump 201 corresponding to the surface of the first conductive pad 101 exposed on the first isolation layer 102 is disposed on the first connection layer 200. The first conductive bump 201 is electrically connected to the first conductive pad 101 through the first connection layer 200. Figure 4In the illustrated embodiment, the first width W1 is greater than the second width W2 and the third width W3, and the second width W2 is less than the third width W3. In this case, the difference between the first width W1 and the second width W2 is greater than the difference between the first width W1 and the third width W3. Figure 5 In the embodiment shown, the first width W1 is greater than the second width W2 and less than the third width W3. The second width W2 is less than the third width W3. At this time, the difference between the first width W1 and the second width W2 is greater than the absolute value of the difference between the first width W1 and the third width W3.

[0049] Other unrepresented portions of the semiconductor substrate 100, the first conductive pad 101, the first insulating layer 102, the first interconnect layer 200, and the first conductive bump 201 are... Figure 1 as well as Figure 2 The corresponding parts in the illustrated embodiment are the same, and will not be described again here. The range of the differences between the widths is also the same. Figure 1 as well as Figure 2 The corresponding difference ranges in the illustrated embodiments are the same.

[0050] Continue to refer to Figure 4 and Figure 5 The semiconductor structure 10 further includes a first solder layer 202, which includes a portion formed on the top surface of the first conductive bump 201 and a portion formed on the surface of the first isolation layer 102 and adjacent to the first interconnect layer 200. In some embodiments, the first solder layer 202 is also formed on the sidewall of the first conductive bump 201.

[0051] Continue to refer to Figure 6 The semiconductor structure 10 also includes a sealing layer 300, which covers the surface of the first solder layer 202 and isolates adjacent first conductive bumps 201. Figure 6 In the embodiment shown, the first solder layer 202 is formed in the gap A between the first connection layer 200 and the first conductive bump 201, completely filling the gap A.

[0052] In the semiconductor structure provided in the above embodiments, the first solder layer fills the space corresponding to the first isolation layer and the first conductive bump, and is adjacent to the first connection layer, which can further fill the gap A. The resistance of the first solder layer is less than that of the sealing layer, which can further reduce the resistance between the first conductive bump and the first conductive pad. In addition, the first solder layer has better fluidity than the sealing layer, and its ability to fill the gap A is higher.

[0053] In some embodiments, the absolute value of the difference between the first width W1 and the third width W3 is less than the absolute value of the difference between the second width W2 and the third width W3. For example... Figure 1 and Figure 3In the illustrated embodiment, the first width W1 is greater than the third width W3, the second width W2 is less than the third width W3, and the difference between the first width W1 and the third width W3 is less than the difference between the third width W3 and the second width W2. Figure 2 and Figure 4 In the illustrated embodiment, the first width W1 is smaller than the third width W3, the second width W2 is smaller than the third width W3, and the difference between the first width W1 and the third width W3 is smaller than the difference between the third width W3 and the second width W2. The semiconductor device provided in the above embodiment has a relatively large gap between the first interconnect layer and the first conductive bump.

[0054] In the above embodiments, the absolute value of the difference between the first width and the third width is between 1 micrometer and 1.5 micrometers, and the absolute value of the difference between the second width and the third width is between 1.5 and 2.5 micrometers.

[0055] See also Figures 1 to 6 In some embodiments, the semiconductor structure 10 further has a second surface 10B, which is opposite to the first surface 10A. The second surface 10B is provided with a second conductive pad 104 and a second isolation layer 105 surrounding the second conductive pad 104. The second conductive pad 104 may penetrate a TSV via structure of the semiconductor substrate 100 or may be other conductive structures extending through the semiconductor substrate 100. The second isolation layer 105 covers a surface of the semiconductor substrate 100 adjacent to the second surface 10B and is used to isolate a plurality of adjacent second conductive pads 104.

[0056] In the above embodiments, the semiconductor structure 10 further includes a second connection layer 203 disposed on the second surface 10B. The second connection layer 203 is disposed on the second conductive pad 104 and the second isolation layer 105. The second connection layer 203 is disposed corresponding to the second conductive pad 104 and completely covers the surface of the second conductive pad. The second connection layer 203 also partially covers the surface of the second isolation layer 105. The semiconductor structure 10 also includes a second conductive bump 204, which is disposed corresponding to the second conductive pad 104 and is disposed on the second connection layer 203. The second conductive bump 204 and the second conductive pad 104 are electrically connected through the second connection layer 203.

[0057] In some of the above embodiments, on a cross section perpendicular to the second surface B, the second conductive bump 204 and the first conductive bump 201 have the same or different widths. The width of the second conductive pad 104 is smaller than the width of the second conductive bump 204 and the width of the second connecting layer 203. The width of the second connecting layer 203 is smaller than the width of the second conductive bump 204. That is, there is a gap between the surfaces of the second connecting layer 203 and the second conductive bump 204 facing the second isolation layer 105.

[0058] In the above embodiments, the second conductive bump 204 can be cylindrical, rectangular, trapezoidal, inverted trapezoidal, or other shapes, and its material can be conductive metals such as copper, nickel, or gold.

[0059] In some embodiments, the semiconductor structure 10 further includes a second solder layer and a sealing layer, such as Figure 7 As shown, Figure 7 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this disclosure. A second solder layer 205 is disposed on the second conductive bump 204, and a sealing layer 300 covers the second solder layer 205. The second solder layer 205 at least covers the top surface of the second conductive bump 204. In some embodiments, the second solder layer 205 also covers the sidewall surface of the second conductive bump 204. In some embodiments, the second solder layer 205 is also disposed in the gap B between the second connection layer 203, the second conductive bump 204, and the second isolation layer 105. In some embodiments, the second solder layer 205 may be formed only in the gap B. In these embodiments, by using the second solder layer to fill the gap between the second connection layer, the second conductive bump, and the second isolation layer, the inability of the subsequent sealing layer to effectively fill this gap is avoided, thus preventing a decrease in sealing reliability.

[0060] Embodiments of this disclosure also provide other types of semiconductor structures, such as Figure 8 and Figure 9 As shown. Figure 8 and Figure 9 This is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure. Figure 8 and Figure 9Corresponding embodiments provide a semiconductor structure 11 and a semiconductor structure 12, respectively. Semiconductor structure 11 includes a first surface 11A and a second surface 11B opposite to the first surface 11A, and semiconductor structure 12 includes a first surface 12A and a second surface 12B opposite to the first surface 12A. The difference between semiconductor structure 11 and semiconductor structure 10 provided in the aforementioned embodiments is that the first conductive bump 201 of the first surface 11A of semiconductor structure 11A does not have a first solder layer 202, that is, only the surface of the second conductive bump 204 has a second solder layer 205; the difference between semiconductor structure 12 and semiconductor structure 10 provided in the aforementioned embodiments is that the first conductive bump 201 of the first surface 12A of semiconductor structure 12A does not have a first solder layer 202, that is, only the surface of the second conductive bump 204 has a second solder layer 205, and the second solder layer 205 is also disposed in the gap between the second connection layer 203, the second conductive bump 204, and the second isolation layer 105. The location of the second solder layer is not limited to the locations listed above. It can also be formed only in the gap between the second connecting layer 203 and the second conductive bump 204 and the second isolation layer 105, and simultaneously formed on the side wall of the second conductive bump 204 and in the gap between the second connecting layer 203 and the second conductive bump 204 and the second isolation layer 105.

[0061] In the above embodiments, the first surface 10A of the semiconductor structure 10 can be the front side of the first semiconductor structure 10, and the second surface 10B can be the back side of the first semiconductor structure 10. Similarly, the first and second surfaces of the semiconductor structures 11 and 12 also correspond to the front and back sides of the semiconductor structures 11 and 12, respectively. Here, the front side refers to the surface of the semiconductor structure adjacent to the back-end metal wiring, which is used to realize the communication interconnection between the chip and the outside world. Here, the back side refers to the surface of the semiconductor structure adjacent to the semiconductor substrate.

[0062] Embodiments of this disclosure also provide a semiconductor package. Figure 10 and Figure 11 A schematic diagram of a semiconductor package structure provided in some embodiments of this disclosure is shown below. Figure 10 and Figure 11 A detailed description of semiconductor packages is provided.

[0063] like Figure 10As shown, the semiconductor package includes at least one semiconductor structure 10 and one semiconductor structure 11 interconnected with each other. The first surface 10A of semiconductor structure 10 and the first surface 11A of semiconductor structure 11 are disposed opposite each other, and the first conductive bumps 201 on the first surface 10A and the first conductive bumps 201 on the first surface 11A are aligned and connected one-to-one. A first solder layer 202 serves as the connection medium for the corresponding first conductive bumps 201, realizing the electrical connection between the corresponding first conductive bumps 201. The first solder layer 202 is also formed on the first isolation layer 102 of each semiconductor chip and adjacent to each first connection layer 200; that is, the first solder layer 202 is also simultaneously formed in the gaps between the first isolation layer, the first connection layer, and the first conductive bumps on the first surface of each semiconductor structure.

[0064] The semiconductor structure 10 in the semiconductor package provided in the above embodiments may be derived from... Figures 1 to 7 The semiconductor structure 10 provided in the corresponding embodiments has the same or similar structural features as the semiconductor structure 10 in these embodiments. The semiconductor structure 11 in the semiconductor package provided in the above embodiments may be derived from... Figure 8 and Figure 9 The semiconductor structure 11 provided in the corresponding embodiments has the same or similar structural features as the semiconductor structure 11 in these embodiments.

[0065] In these embodiments, the interconnection between semiconductor structure 10 and semiconductor structure 11 can be achieved by thermocompression bonding technology.

[0066] In some of the above embodiments, during the thermo-press bonding process, the first solder layer 202 may be formed only between adjacent first conductive bumps 201, that is, the first solder layer 202 is not formed in the gap between the first isolation layer, the first connection layer and the first conductive bump.

[0067] In some of the above embodiments, during the formation of the above-described package, when using Figures 1 to 3 When the semiconductor structure 10 and semiconductor structure 11 of the embodiment are connected, the first solder layer 202 can be formed in the gap between the first isolation layer, the first connection layer and the first conductive bump during the thermo-press bonding process; when using Figures 4 to 6 When the semiconductor structure 10 and the semiconductor structure 11 of the embodiment are connected, the first solder layer 202 can fill the gap between the first isolation layer, the first connection layer and the first conductive bump when the first solder layer 202 is formed before thermo-press bonding. In the subsequent thermo-press bonding process, the first solder layer 202 can only have solder flowing on the surface of the corresponding first conductive bump 201.

[0068] The semiconductor package provided in the above embodiments combines the front sides of at least two semiconductor structures together, exposing the back sides of the semiconductor structures. In some embodiments, a sealing layer 300 is further formed between the first surfaces of semiconductor structure 10 and semiconductor structure 11.

[0069] This disclosure also provides a package comprising two or more semiconductor structures. Figure 11 A package comprising four semiconductor structures is shown, including two semiconductor structures 10 and two semiconductor structures 11. In a bottom-to-top connection order, the first surface 11A of the first semiconductor structure 11 faces the first surface 10A of the first semiconductor structure 10; the second surface 10B of the first semiconductor structure 10 faces the second surface 11B of the second semiconductor structure 11; and the first surface 11A of the second semiconductor structure 11 faces the first surface 10A of the second semiconductor structure 10. A first solder layer 202 is formed between two adjacent semiconductor structures whose first surfaces face each other, and a second solder layer 205 is formed between two adjacent semiconductor structures whose second surfaces face each other.

[0070] In the above embodiments, the first surface of each semiconductor structure is either the front or the back surface, and the second surface is either the back or the front surface.

[0071] In the above embodiments, a sealing layer 300 is also formed between adjacent semiconductor structures. Each sealing layer 300 can be formed together after the semiconductor structures are connected, or it can be formed first on the first or second surface of each semiconductor structure.

[0072] In some of the above embodiments, during the thermocompression bonding process of each semiconductor structure, the first solder layer 202 and / or the second solder layer 205 may only be formed between adjacent first conductive bumps 201 and adjacent second conductive bumps 204. That is, the first solder layer 202 does not fill the gaps between the first isolation layer 102, the first connection layer 200, and the first conductive bumps 201, and the second solder layer 205 does not fill the gaps between the second isolation layer 105, the second connection layer 203, and the second conductive bumps 204. These gaps are filled by the subsequently formed sealing layer 300.

[0073] In some embodiments, see continue to see Figure 11 The semiconductor structures with opposite first surfaces have a first spacing A1, and the semiconductor structures with opposite second surfaces have a second spacing A2, where A1 is greater than A2.

[0074] In some embodiments, the semiconductor package may further include a package consisting of a greater number of semiconductor structures 10 and semiconductor structures 11, or a package consisting of only a plurality of semiconductor structures 10 connected to each other and only a plurality of semiconductor structures 11 connected to each other. This disclosure does not limit this, but packages containing semiconductor structures provided in this disclosure are protected and disclosed by this disclosure.

[0075] In the semiconductor package provided by some embodiments of this disclosure, during the packaging process, since the gaps between the first interconnect layer and the first conductive bump and between the second interconnect layer and the second conductive bump are relatively large, the sealing layer formed subsequently can relatively completely fill these gaps, avoiding the problem of reduced reliability caused by the weak bonding between the conductive bump and the sealing layer.

[0076] In some embodiments of this disclosure, the gaps between the first interconnect layer and the first conductive bump, and between the second interconnect layer and the second conductive bump, of the semiconductor package provided during or before packaging are filled and sealed by the first solder layer and the second solder layer, respectively, forming a strong bonding surface and further improving the reliability of the conductive bumps on each surface.

[0077] The semiconductor package provided in some embodiments of this disclosure adopts a front-to-front and back-to-back packaging method, so that different surfaces of adjacent semiconductor structures have different spacings. This gives the package with multiple interconnected semiconductor structures good performance in terms of warpage control and packaging stability, and allows for packaging with a greater number of semiconductor structures.

[0078] The method for forming the semiconductor structure provided in this disclosure is further explained below with reference to the accompanying drawings.

[0079] Figure 12 A schematic diagram of the process for forming a semiconductor structure. Figures 13 to 17 This is a schematic diagram of the semiconductor structure corresponding to each process step.

[0080] The method for forming a semiconductor structure includes the following steps: S11, providing a semiconductor substrate, and forming a first conductive pad and a first isolation layer covering a portion of the first conductive pad on the substrate to form a first surface.

[0081] See Figure 13A semiconductor substrate 100 is provided, and a device layer 103 is formed on the semiconductor substrate 100. After forming the device layer 103, a first isolation layer 102 covering the device layer 103 and a first conductive pad 102 interconnected with the device layer 103 are formed. The first isolation layer 102 also covers a portion of the surface of the first conductive pad 101. The surface of the first conductive pad 101 not covered by the first isolation layer 102 has a gap C1. The first conductive pad 101 has a first width W1 in a direction perpendicular to the semiconductor substrate 100. The gap C1 exposes at least more than 1 / 2 of the surface area of ​​the first conductive pad 101. The top surface of the first isolation layer 102 is higher than the exposed top surface of the first conductive pad 101. The top surface of the first isolation layer 102 and the top surface of the first conductive pad 101 form the first surface 10A of the semiconductor structure.

[0082] Step S12 is performed to form an initial first connection layer on the first surface, the initial first connection layer covering the surfaces of the first conductive pad and the first isolation layer.

[0083] See Figure 14 An initial first connection layer 200' is formed on the first surface 10A. The initial first connection layer 200' covers the surface of the first isolation layer 102 and the exposed surface of the first conductive pad 101, and fills the sidewalls and bottom surface of the gap C1. A gap C2 is formed on the first conductive pad 101. The initial first connection layer 200' located on the top surface of the first conductive pad 102 has a width W21, which is greater than 1 / 2 of the first width W1 and less than the first width W1. The initial first connection layer 200' can be formed by electroplating, deposition, or other methods.

[0084] Step S13 is executed to form a first conductive bump on the initial first connection layer, the first conductive bump being disposed corresponding to the first conductive pad.

[0085] See Figure 15 A first conductive bump 201 is formed on the initial first connection layer 200', the first conductive bump 201 including fully filled Figure 14 The first conductive bump 201 includes a portion of the gap C2 and a portion protruding from the initial first connection layer 200'. The first conductive bump 201 also includes a portion formed on the surface of the initial first connection layer 200' on the surface of the first isolation layer 102. The first conductive bump 201 is correspondingly disposed with the first conductive pad 101 and connected by the initial first connection layer 200' located between the two.

[0086] In the above embodiments, the first conductive bump 201 can be formed by first forming a mask layer on the initial first connection layer 200', then patterning the mask layer, then filling the pattern area of ​​the first conductive bump through processes such as electroplating and deposition, and then removing the mask layer.

[0087] In some embodiments, while forming the first conductive bump 201, an initial first solder layer 202' is also formed over the first conductive bump 201.

[0088] Execute step S14 to remove a portion of the initial first connection layer, retaining the portion of the initial first connection layer located between the first conductive bump and the first conductive pad, forming a first connection layer; wherein, in a cross-section perpendicular to the first surface, the first conductive pad has a first width, the first connection layer has a second width, and the first conductive bump has a third width, the second width being the sum of the width of the first connection layer on the first isolation layer and the width of the first connection layer on the first conductive pad, and the absolute value of the difference between the first width and the second width being greater than the absolute value of the difference between the first width and the third width.

[0089] See Figure 16 The excess initial first connection layer 200' on the surface of the first isolation layer 102 is removed by an etching process. This removal can be done using wet etching, dry etching, etc. During the etching process, the initial first solder layer 202' and the first conductive bump 201 are also partially etched, but the amount etched is controlled to be less than the amount of the initial first connection layer 200'. This exposes a portion of the initial first connection layer 200' on the first isolation layer 102, which has a width of W20. The remaining portion of the initial first connection layer forms the first connection layer 200, which has a second width W2, including width W20 and width W21. The retained first conductive bump 201 has a third width W3, which is smaller than the first width W1. In some embodiments, the third width W3 can also be greater than the first width W1. Furthermore, during the etching process, the absolute value of the difference between the first width W1 and the second width W2 is controlled to be greater than the absolute value of the difference between the first width W1 and the third width W3.

[0090] By controlling the etching process during the formation of the first conductive bump and the first interconnect layer, as well as the size and exposure size of the first conductive pad, a larger amount of the initial first interconnect layer is etched, thereby forming a relatively large gap between the first conductive bump, the first interconnect layer, and the first isolation layer.

[0091] See also Figure 16In some embodiments, after etching the initial first interconnect layer 200' to form the first interconnect layer 200, plasma is used to treat the exposed sidewalls between adjacent first conductive bumps 201 and the exposed surface of the first isolation layer 102. For example, microwave plasma is used to treat the exposed sidewalls of each first conductive bump 201 in a direction perpendicular to the sidewalls of the first conductive bumps 201, and radio frequency plasma is used to treat the exposed surface of the first isolation layer 102 in a direction perpendicular to the surface of the first isolation layer 102. The plasma can be plasma formed by inert gas. Microwave plasma is formed by ionizing inert gas molecules under the action of microwave energy. It has advantages such as high density and low temperature. The sidewalls of the first conductive bumps 201 treated with it will become smooth, and the surface roughness will be much lower than that of the sidewalls of the first conductive bumps 201 after the etching process. Radio frequency plasma uses radio frequency energy to excite inert gas molecules into a plasma state. Its characteristic is anisotropic treatment, which can form tiny pits on the surface of the first isolation layer 102, thereby improving the surface roughness of the first isolation layer 102.

[0092] In some embodiments, the formation of the first interconnect layer 200 further includes treating the first interconnect layer with a reactive plasma, which can further shorten the width of the first interconnect layer 200. The reactive plasma can be an etching gas such as a Cl2 / BCl3 / Ar mixed gas that can react with the material of the first interconnect layer 200.

[0093] See also Figure 17 In some embodiments, after forming the first connection layer 200, the initial first solder layer 202' is reflowed to form a first solder layer 202. The first solder layer 202 at least covers the top surface and sidewalls of the first conductive bump 201, and is formed on the first isolation layer 102 and adjacent to the first connection layer 200. That is, the first solder layer 202 also fills the gaps formed by the first connection layer 200, the first conductive bump 201, and the surface of the first isolation layer 102. This is because, before reflow, the sidewalls of the first conductive bump 201 are made smoother after microwave plasma treatment, facilitating the flow of solder along the sidewalls of the first conductive bump into the aforementioned gaps. In other embodiments, since the surface roughness of the first isolation layer exposed between adjacent first conductive bumps is increased after radio frequency plasma treatment, it can block the flow of solder between adjacent first conductive bumps during reflow, thus preventing short circuits between adjacent first conductive bumps. The surface of the first isolation layer located directly below the first conductive bump is blocked by the first conductive bump and will not be interfered with by radio frequency plasma. The surface roughness will not be increased, so the solder can enter the area below the first conductive bump and connect to the first connection layer relatively easily.

[0094] In other embodiments, the flow of solder can also be blocked by etching the surface of the first isolation layer exposed between adjacent first conductive bumps to form trenches.

[0095] After forming the first solder layer 202, the semiconductor substrate 100 is flipped, and the other surface of the semiconductor substrate 100 away from the first surface 10A is used as the surface to be processed. This surface is thinned to expose the top surface of the second conductive pad 104, and further structures such as the second isolation layer, the second interconnect layer, and the second conductive bump are formed, ultimately obtaining the desired result. Figures 1 to 6 The semiconductor structure shown in the example. The formation process of the second interconnect layer and the second conductive bump is similar to that of the first interconnect layer and the first conductive bump, and will not be described in detail here.

[0096] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, comprising: A first surface having a first conductive pad and a first insulating layer, wherein the first insulating layer exposes at least a portion of the surface of the first conductive pad; A first connecting layer is disposed on the surface of the first conductive pad exposed to the first insulating layer and on the first insulating layer; The first conductive bump is disposed on the first connecting layer and is disposed corresponding to the first conductive pad; In a cross-section perpendicular to the first surface, the first conductive pad has a first width, the first connecting layer has a second width, and the first conductive bump has a third width. The second width is the sum of the width of the first connecting layer on the first insulating layer and the width of the first connecting layer on the first conductive pad, wherein the absolute value of the difference between the first width and the second width is greater than the absolute value of the difference between the first width and the third width.

2. The semiconductor structure according to claim 1, characterized in that, The absolute value of the difference between the first width and the third width is less than the absolute value of the difference between the second width and the third width.

3. The semiconductor structure according to claim 1, characterized in that, In the cross-section, the first conductive pad exposed by the first insulating layer has a fourth width, which is greater than 1 / 2 of the first width.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a first solder layer, which is formed at least on the first isolation layer and adjacent to the first interconnect layer.

5. The semiconductor structure according to claim 4, characterized in that, The first solder layer covers the surface of the first conductive bump.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The semiconductor structure further has a second surface opposite to the first surface, and the second surface is provided with a second conductive pad and a second isolation layer surrounding the second conductive pad; A second connecting layer is disposed on the second conductive pad and the second insulating layer; The second conductive bump is disposed on the second connecting layer and is disposed corresponding to the second conductive pad. In a cross-section perpendicular to the second surface, the width of the second connecting layer is smaller than the width of the second conductive bump. A second solder layer is formed at least on the second isolation layer and adjacent to the second connection layer.

7. A semiconductor package comprising a plurality of semiconductor structures interconnected with each other, said semiconductor structure comprising: A first surface, wherein a first conductive pad and a first insulating layer are disposed on the first surface, and the first insulating layer exposes at least a portion of the surface of the first conductive pad; A first connecting layer is disposed on the surface of the first conductive pad exposed to the first insulating layer, and the first connecting layer is also disposed on the first insulating layer; The first conductive bump is disposed on the first connecting layer and is disposed corresponding to the first conductive pad. In a cross-section perpendicular to the first surface, the first conductive pad has a first width, the first connecting layer has a second width, and the first conductive bump has a third width. The second width is the sum of the width of the first connecting layer on the first insulating layer and the width of the first connecting layer on the first conductive pad, wherein the absolute value of the difference between the first width and the second width is greater than the absolute value of the difference between the first width and the third width. At least two adjacent first surfaces of the semiconductor structures face each other and are electrically connected by their first conductive bumps.

8. The package according to claim 7, characterized in that, The absolute value of the difference between the first width and the third width of each semiconductor structure is less than the absolute value of the difference between the second width and the third width.

9. The package according to claim 7, characterized in that, The package further includes: a first solder layer disposed between the first conductive bumps of each of the semiconductor structures facing each other on the first surface, the first solder layer also being formed on the first isolation layer of each of the semiconductor structures and adjacent to the first interconnect layer.

10. The package according to claim 7, characterized in that, Each of the semiconductor structures further has a second surface opposite to the first surface, and the package further includes at least two adjacent semiconductor structures whose second surfaces face each other, wherein each semiconductor structure whose first surfaces face each other has a first spacing, and each semiconductor structure whose second surfaces face each other has a second spacing, and in the direction in which the semiconductor structures are connected to each other, the first spacing is greater than the second spacing.

11. The package according to claim 10, characterized in that, The second surface of each of the semiconductor structures is provided with a second conductive pad and a second isolation layer surrounding the second conductive pad; A second connecting layer is disposed on the second conductive pad and the second insulating layer; The second conductive bump is disposed on the second connecting layer and is disposed corresponding to the second conductive pad. In a cross-section perpendicular to the second surface, the width of the second connecting layer is smaller than the width of the second conductive bump. The package further includes a second solder layer disposed between the semiconductor structures facing each other on the second surface, the second solder layer also being formed on the second isolation layer of each semiconductor structure and adjacent to the second interconnect layer.

12. The package according to claim 10, characterized in that, The first surface is the front side of the semiconductor structure, and the second surface is the back side of the semiconductor structure.

13. A method for forming a semiconductor structure, comprising: A semiconductor substrate is provided, on which a first conductive pad and a first isolation layer covering a portion of the first conductive pad are disposed to form a first surface; An initial first connection layer is formed on the first surface, the initial first connection layer covering the surfaces of the first conductive pad and the first isolation layer; A first conductive bump is formed on the initial first connection layer, and the first conductive bump is disposed corresponding to the first conductive pad; A portion of the initial first connection layer is removed, leaving the portion of the initial first connection layer located between the first conductive bump and the first conductive pad, to form a first connection layer; wherein... In a cross-section perpendicular to the first surface, the first conductive pad has a first width, the first connecting layer has a second width, and the first conductive bump has a third width. The second width is the sum of the width of the first connecting layer on the first insulating layer and the width of the first connecting layer on the first conductive pad. The absolute value of the difference between the first width and the second width is greater than the absolute value of the difference between the first width and the third width.

14. The forming method according to claim 13, characterized in that, Before or after removing part of the initial first connection layer, the method further includes: treating the sidewalls of the first conductive bump and the exposed surface of the first isolation layer with plasma, wherein the sidewalls of the first conductive bump are treated with microwave plasma and the exposed surface of the first isolation layer is treated with radio frequency plasma.

15. The forming method according to claim 14, characterized in that, A first solder layer is formed on the first conductive bump, and the first solder layer is reflowed such that the first solder layer is formed at least on the first isolation layer and adjacent to the first connection layer.

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