semiconductor element

Abstract

A unit contact structure, a semiconductor device and a method of manufacturing the same are disclosed. The unit contact structure includes a bottom contact layer disposed on a substrate and enclosed by a plurality of bit line structures and a plurality of separation layers; a liner layer disposed between the bottom contact layer and the substrate, between the bottom contact layer and the plurality of bit line structures, and between the bottom contact layer and the plurality of separation layers; and a top contact layer disposed on the bottom contact layer and the liner layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polysilicon, doped polygermanium, or doped polysilicon germanium. The bottom contact layer includes tungsten, titanium, or titanium nitride.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 19 / 081,162 (priority date March 17, 2025), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] A unit contact structure, a semiconductor element, and a method for manufacturing the same are disclosed. More specifically, the invention relates to a semiconductor element having a unit contact structure including a liner and a method for manufacturing the same. Background Technology

[0004] Semiconductor components are used in a wide range of electronic applications, including personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, the challenges brought about by this miniaturization are becoming increasingly frequent and far-reaching. Therefore, improving quality, yield, performance, and reliability while reducing complexity remains a challenge.

[0005] The prior art description above is merely to provide background information and does not acknowledge that the prior art description above discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the prior art above should be considered part of the prior art in this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device including a substrate having a plurality of doped regions; a two-bit line structure formed on the substrate, extending along a first direction and separated from each other; two separator layers disposed on the substrate, extending along a second direction perpendicular to the first direction, separated from each other along the first direction, and simultaneously contacting the two-bit line structure; and a unit contact structure disposed on the substrate. The unit contact structure includes a bottom contact layer disposed on the substrate and closed by the two-bit line structure and the two separator layers. The unit contact structure also includes a liner disposed between the substrate and the bottom contact layer, between the two-bit line structure and the bottom contact layer, and between the two separator layers and the bottom contact layer. The unit contact structure further includes a top contact layer disposed on the liner and the bottom contact layer. The two-bit line structure includes an air gap disposed therebetween.

[0007] Another embodiment of this disclosure provides a semiconductor device including a substrate; a plurality of doped regions disposed in the substrate; a two-bit line structure formed on the substrate, extending along a first direction and separated from each other; two separator layers disposed on the substrate, extending along a second direction perpendicular to the first direction, separated from each other along the first direction, and simultaneously contacting the two-bit line structure; a unit contact structure disposed on the substrate; a conductive pillar disposed on the unit contact structure; a contact pad disposed on the conductive pillar; and a dielectric layer stack disposed on the substrate and including at least one dielectric layer. The two-bit line structure includes a first air gap disposed therebetween. The unit contact structure includes a bottom contact layer disposed on the substrate and closed by the two-bit line structure and the two separator layers. The unit contact structure also includes a liner disposed between the substrate and the bottom contact layer, between the two-bit line structure and the bottom contact layer, and between the two separator layers and the bottom contact layer. The unit contact structure further includes a top contact layer disposed on the liner and the bottom contact layer. The multiple doped regions are formed of silicon phosphide, phosphorus-doped silicon-carbon, silicon carbide, silicon-germanium, silicon-germanium-tin alloy, or silicon-germanium-boron alloy. One sidewall of the conductive pillar is recessed inward from one sidewall of the contact pad. One dielectric layer in the dielectric layer stack is configured to laterally surround a thicker dielectric layer of the conductive pillar and the contact pad. Multiple second air gaps are sealed within the thicker dielectric layer and are arranged alternately with the conductive pillar.

[0008] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming two separate two-bit line structures extending along a first direction on the substrate; forming a plurality of spacer structures on the side surfaces of the two-bit line structures; forming an air gap between the two-bit line structures; forming two separating layers on the substrate extending along a second direction perpendicular to the first direction, separating from each other, and forming a contact opening together with the plurality of spacer structures; conformally forming a liner layer in and within the contact opening; forming a bottom contact layer on the liner layer and within the contact opening; and forming a top contact layer on the liner layer, the bottom contact layer, and within the contact opening. The liner layer, the bottom contact layer, and the top contact layer are configured together to form a unit contact structure.

[0009] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, including providing a substrate having a plurality of active regions; forming a plurality of doped regions in the substrate; forming two-bit line structures extending along a first direction and separated from each other on the substrate; forming a plurality of spacer structures on the side surfaces of the two-bit line structures; forming a first air gap between the two-bit line structures; forming two separating layers extending along a second direction perpendicular to the first direction and separated from each other on the substrate, and forming a contact opening together with the plurality of spacer structures; conformally forming a liner layer in and within the contact opening; forming a bottom contact layer on the liner layer and within the contact opening; and forming a top contact layer on the liner layer, the bottom contact layer, and within the contact opening. The plurality of doped regions are formed of silicon phosphide, phosphorus-doped silicon-carbon, silicon carbide, silicon-germanium, silicon-germanium-tin alloy, or silicon-germanium-boron alloy. The liner layer, the bottom contact layer, and the top contact layer are configured together to form a unit contact structure.

[0010] Due to the design of the semiconductor device disclosed herein, the interface leakage current of the cell contact structure can be reduced by employing a substrate formed of doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. Furthermore, the sheet resistance of the cell contact structure can be reduced by employing a bottom contact layer and a top contact layer formed of titanium nitride, tungsten, or titanium. Therefore, the performance of the semiconductor device is improved.

[0011] The technical features and advantages of this disclosure have been broadly summarized above, thus providing a preferred understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0012] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0013] Figure 1 The flowchart illustrates a method for manufacturing a semiconductor element according to an embodiment of the present disclosure.

[0014] Figure 2 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0015] Figure 3 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 2 Cross-sectional views obtained from lines A-A' and B-B'.

[0016] Figure 4 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0017] Figure 5 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 4 Cross-sectional views obtained from lines A-A' and B-B'.

[0018] Figure 6 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0019] Figure 7 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 6 Cross-sectional views obtained from lines A-A' and B-B'.

[0020] Figure 8 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0021] Figure 9 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 8 Cross-sectional views obtained from lines A-A' and B-B'.

[0022] Figure 10 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0023] Figure 11 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 10 Cross-sectional views obtained from lines A-A' and B-B'.

[0024] Figure 12 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0025] Figure 13 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 12 Cross-sectional views obtained from lines A-A' and B-B'.

[0026] Figure 14 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0027] Figure 15 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 14 Cross-sectional views obtained from lines A-A' and B-B'.

[0028] Figure 16 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 14 Cross-sectional views obtained from lines A-A' and B-B'.

[0029] Figure 17 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0030] Figure 18 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 17 Schematic cross-sectional views obtained from lines A-A' and B-B'.

[0031] Figure 19 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0032] Figure 20 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 19 Cross-sectional views obtained from lines A-A' and B-B'.

[0033] Figure 21 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 19 Cross-sectional views obtained from lines A-A' and B-B'.

[0034] Figure 22 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 19 Cross-sectional views obtained from lines A-A' and B-B'.

[0035] Figure 23 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 19 Cross-sectional views obtained from lines A-A' and B-B'.

[0036] Figure 24 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0037] Figure 25 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 24 Cross-sectional views obtained from lines A-A' and B-B'.

[0038] Figure 26 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 24 Cross-sectional views obtained from lines A-A' and B-B'.

[0039] Figure 27For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0040] Figure 28 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 27 Cross-sectional views obtained from lines A-A' and B-B'.

[0041] Figure 29 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 27 Cross-sectional views obtained from lines A-A' and B-B'.

[0042] Figure 30 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown.

[0043] Figure 31 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 30 Cross-sectional views obtained from lines A-A' and C-C'.

[0044] Figure 32 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 30 Cross-sectional views obtained from lines A-A' and C-C'.

[0045] Figure 33 For illustrative purposes only, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to the description of this disclosure. Figure 30 Cross-sectional views obtained from lines A-A' and C-C'.

[0046] The reference numerals in the attached figures are explained as follows:

[0047] 1A: Semiconductor components

[0048] 1B: Semiconductor components

[0049] 10: Manufacturing Method

[0050] 101: Base

[0051] 105-3: Doped region / drain region

[0052] 105-3R: Groove

[0053] 103: Isolation layer

[0054] 105-1: Doped region / Common source region

[0055] 105-1R: Groove

[0056] 107: Bottom Dielectric Layer

[0057] 109: Top Insulation Layer

[0058] 109p: Bottom section

[0059] 110: Dielectric layer stacking

[0060] 116: Conductive post

[0061] 116': Initial conductive post

[0062] 118: First conductive layer

[0063] 120: Second conductive layer

[0064] 121: Dielectric layer

[0065] 200: Word Line Structure

[0066] 201: Word line dielectric layer

[0067] 203: Word Line Barrier Layer

[0068] 205: Word Line Conductive Layer

[0069] 207: Wordline Overlay

[0070] 300: Bitline Structure

[0071] 300S: Side View

[0072] 301: Top conductive layer of bit line

[0073] 307: Bitline overlay

[0074] 307TS: Top Surface

[0075] 309: Bit line contact point

[0076] 400: Spacing structure

[0077] 401: Inner spacer layer of the bit line

[0078] 401TS: Top Surface

[0079] 403: Intermediate spacer layer for bit lines

[0080] 403TS: Top Surface

[0081] 405: Spacing layer outside the bit line

[0082] 405TS: Top surface

[0083] 500: Unit contact structure

[0084] 501: Lining

[0085] 501TS: Top Surface

[0086] 503: Bottom contact layer

[0087] 503TS: Top Surface

[0088] 505: Top contact layer

[0089] 505TS: Top Surface

[0090] 601: Separator

[0091] 601TS: Top Surface

[0092] 701: First mask layer

[0093] 801: Sacrificial Layer

[0094] 803: Segmented Materials

[0095] 805: Padding Material

[0096] 807: First conductive material

[0097] 809: Second conductive material

[0098] AA: Active Zone

[0099] A-A': line

[0100] AA1: Active Zone

[0101] AA3: Active Zone

[0102] AG: Air gap

[0103] AS: Air gap

[0104] B-B': Line

[0105] C-C': Line

[0106] CP: Contact pad

[0107] OP1: Partition Opening

[0108] OP2: Contact opening

[0109] P1: Line drawing pattern

[0110] S11: Steps

[0111] S13: Steps

[0112] S15: Steps

[0113] S17: Steps

[0114] S19: Steps

[0115] TR: Word line groove

[0116] W1: Width

[0117] W2: Width

[0118] X: Direction

[0119] Y: direction

[0120] Z: Direction Detailed Implementation

[0121] The following description of this disclosure, accompanied by the accompanying drawings which are incorporated in and form a part of this specification, illustrates embodiments of this disclosure; however, this disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0122] Terms such as "an embodiment," "an embodiment," "an exemplary embodiment," "another embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0123] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0124] In this disclosure, semiconductor element generally refers to an element that can operate using semiconductor properties, including electro-optical elements, light-emitting display elements, semiconductor circuits and electronic elements.

[0125] It should be noted that in the description of this disclosure, "above" (or "upward") corresponds to the direction of the Z-direction arrow, while "below" (or "downward") corresponds to the opposite direction of the Z-direction arrow.

[0126] Figure 1 The flowchart illustrates a method 10 for manufacturing a semiconductor element 1A according to an embodiment of the present disclosure. Figure 2 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 3 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 2 Cross-sectional views obtained from lines A-A' and B-B'. Figure 4 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 5For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 4 Cross-sectional views obtained from lines A-A' and B-B'.

[0127] Reference Figures 1 to 5 In step S11, a substrate 101 is provided. An isolation layer 103 is formed in the substrate 101 to define a plurality of active regions AA. A plurality of word line structures 200 are formed in the substrate 101 to intersect with the active regions AA, and a plurality of doped regions 105-1 and 105-3 are formed in the active regions AA.

[0128] Reference Figure 2 and Figure 3 The substrate 101 includes a bulk semiconductor substrate. The bulk semiconductor substrate is formed of, for example, an elemental semiconductor, such as silicon or germanium; formed of, for example, a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide or other group III-V compound semiconductors or group II-VI compound semiconductors; or formed of a combination thereof.

[0129] In some embodiments, substrate 101 includes a semiconductor-coated insulator structure, which, from bottom to top, comprises a supporting substrate, an insulating layer, and a top layer of semiconductor material. The supporting substrate and the top layer of semiconductor material are formed of the same material as the aforementioned main semiconductor substrate. The insulating layer is a crystalline or amorphous dielectric material, such as oxides and / or nitrides. For example, the insulating layer is a dielectric oxide, such as silicon oxide. Another example is a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer comprises a stack of dielectric oxides and dielectric nitrides, such as silicon oxide, silicon nitride, and / or boron nitride stacked in any order. The thickness of the insulating layer is between about 10 nm and about 200 nm. The insulating layer eliminates leakage current between adjacent elements in substrate 101 and reduces parasitic capacitance associated with the source and drain regions.

[0130] It should be noted that when used to modify the quantity of ingredients, components, or reactants in this disclosure, the term "about" refers to possible numerical variations, such as those caused by typical measurement and liquid handling procedures used in preparing concentrates or solutions. Furthermore, variations may arise from unintentional errors in measurement procedures, differences in the manufacture, origin, or purity of the ingredients used to make the composition or perform the method, etc. In one embodiment, the term "about" means within 10% of the reported value. In another embodiment, the term "about" means within 5% of the reported value. In yet another embodiment, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0131] Reference Figure 2 and Figure 3An isolation layer 103 is formed in a substrate 101. A series of deposition processes are performed to deposit a pad oxide layer and a pad nitride layer on the substrate 101. Photolithography and subsequent etching processes, such as anisotropic dry etching, are performed to form trenches that penetrate the pad oxide and pad nitride layers and extend into the substrate 101. An insulating material is deposited into the trenches, and a planarization process, such as chemical mechanical polishing, is then performed until the top surface of the substrate 101 is exposed to remove excess deposited material, provide a substantially planar surface for subsequent process steps, and simultaneously form the isolation layer 103. The insulating material is, for example, silicon oxide or other suitable insulating materials. The isolation layer 103 defines a plurality of active regions AA in the substrate 101.

[0132] Specifically, in the description of this disclosure, the surface of an element (or feature) at its highest vertical height along the Z-direction is referred to as the top surface of that element (or feature). The surface of an element (or feature) at its lowest vertical height along the Z-direction is referred to as the bottom surface of that element (or feature).

[0133] Specifically, each of the plurality of active regions AA includes a portion of substrate 101 and the space above that portion of substrate 101. Describing an element disposed on an active region AA means that the element is disposed on the top surface of the portion of substrate 101. Describing an element disposed within an active region AA means that the element is disposed within a portion of substrate 101; however, the top surface of the element may be flush with the top surface of the portion of substrate 101. Describing an element disposed above an active region AA means that the element is disposed above the top surface of the portion of substrate 101.

[0134] In some embodiments, portions of the active region AA are doped with dopants. In some embodiments, doping is performed using an implantation process. The dopants used in the implantation process include p-type dopants or n-type dopants. P-type dopants are added to the intrinsic semiconductor to create defects for valence electrons. Examples of p-type dopants in silicon-containing substrates include, but are not limited to, boron, aluminum, gallium, and indium. N-type dopants are added to the intrinsic semiconductor to provide free electrons to the intrinsic semiconductor. Examples of n-type dopants in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus. In some embodiments, the dopant concentration of the active region AA portions is approximately 1E19 atoms / cm³. 3 Approximately 1E21 atoms / cm 3 Between. After the implantation process, the active region AA has an electrical type, such as n-type or p-type.

[0135] Reference Figure 2 and Figure 3Multiple word line trenches TR are formed in the substrate 101 to define the positions of multiple word line structures 200. The multiple word line trenches TR are formed using a photolithography process followed by an etching process. From a top perspective view, the word line trenches TR have a linear profile, extend along the X direction, and intersect with the active regions AA. Furthermore, from a top perspective view, a pair of word line trenches TR pass through each active region AA, dividing each active region AA into a common active region AA1 and an active region AA3. The common active region AA1 is located between the pair of word line trenches TR, while the active region AA3 is located on opposite sides of the pair of word line trenches TR.

[0136] Reference Figure 2 and Figure 3 Multiple word line structures 200 (e.g., two-word line structures 200) are formed in multiple word line trenches TR (e.g., two-word line trenches TR). For simplicity, clarity, and ease of description, only one word line structure 200 is described. The word line structure 200 includes a word line dielectric layer 201, a word line barrier layer 203, a word line conductive layer 205, and a word line cover layer 207.

[0137] Reference Figure 2 and Figure 3 A word line dielectric layer 201 is uniformly formed on the inner surface of the word line trench TR. The word line dielectric layer 201 has a U-shaped profile. In other words, the word line dielectric layer 201 is formed inward in the active region AA. In some embodiments, the word line dielectric layer 201 is formed using a thermal oxidation process. For example, the word line dielectric layer 201 is formed by an oxidation process on the inner surface of the word line trench TR. In some embodiments, the word line dielectric layer 201 is formed using a deposition process such as chemical vapor deposition or atomic layer deposition. The word line dielectric layer 201 comprises a high dielectric constant material, an oxide, a nitride, an oxide oxynitride, or a combination thereof. In some embodiments, the word line dielectric layer 201 is formed by radical oxidation on the polysilicon substrate after deposition. In some embodiments, the word line dielectric layer 201 is formed by radical oxidation on the silicon nitride substrate after formation of a silicon nitride substrate.

[0138] In some embodiments, the high dielectric constant material includes a hafnium-containing material. The hafnium-containing material is, for example, hafnium oxide, hafnium silicon oxide, hafnium oxynitride silicon, or a combination thereof. In some embodiments, the high dielectric constant material is, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium oxynitride silicon, aluminum oxide, or a combination thereof.

[0139] Reference Figure 2 and Figure 3A word line barrier layer 203 is uniformly formed on the word line dielectric layer 201 and within the word line trench TR. In some embodiments, the word line barrier layer 203 is formed of, for example, titanium nitride, titanium, or a combination thereof. In some embodiments, the word line barrier layer 203 is formed of, for example, titanium nitride. In some embodiments, the word line barrier layer 203 is formed using, for example, atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes.

[0140] Reference Figure 2 and Figure 3 A word line conductive layer 205 is formed on the word line barrier layer 203 and within the word line trench TR. In some embodiments, to form the word line conductive layer 205, a conductive layer is formed to fill the word line trench TR, and then a recessing process is performed. The recessing process is performed using an etch-back process or sequentially using a planarization process and an etch-back process. The word line conductive layer 205 has a recessed shape that partially fills the word line trench TR. In other words, the top surface of the word line conductive layer 205 is lower than the top surface of the substrate 101.

[0141] In some embodiments, the word line conductive layer 205 comprises a metal, a metal nitride, or a combination thereof. For example, the word line conductive layer 205 is formed of titanium nitride, tungsten, or titanium nitride / tungsten. After uniform formation of titanium nitride, a titanium nitride / tungsten structure is formed, wherein the word line trench TR portion is filled with tungsten. Alternatively, the word line conductive layer 205 may be made entirely of titanium nitride or tungsten. In some embodiments, the word line conductive layer 205 is formed of, for example, a conductive material such as doped polycrystalline silicon, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the word line conductive layer 205 is formed of, for example, tungsten, aluminum, titanium, copper, the like, or a combination thereof.

[0142] Reference Figure 2 and Figure 3 A dielectric material is deposited using, for example, chemical vapor deposition to completely fill the word line trench TR and cover the top surface of the substrate 101. A planarization process, such as chemical mechanical polishing, is performed to provide a substantially flat surface for subsequent process steps and to form the word line capping layer 207. In some embodiments, the word line capping layer 207 is formed of, for example, silicon nitride or other suitable dielectric material.

[0143] Reference Figure 4 and Figure 5A plurality of grooves 105-1R and 105-3R are formed in the substrate 101, the positions of which are defined by the active regions AA1 and AA3, respectively. In other words, each groove 105-1R is formed in the active region AA1, and each groove 105-3R is formed in the active region AA3. It should be noted that, from a top view perspective, groove 105-1R has the same profile as the active region AA1, and groove 105-3R has the same profile as the active region AA3. In some embodiments, a photolithography process and a subsequent etching process are performed to remove portions of the substrate 101 and integrally form the plurality of grooves 105-1R and 105-3R.

[0144] Reference Figure 4 and Figure 5 An epitaxial growth process is performed to fill the plurality of grooves 105-1R and the plurality of grooves 105-3R and integrally form the plurality of doped regions 105-1 and 105-3. The epitaxial growth process is chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. In some embodiments, the process temperature of the epitaxial growth process is between about 700 degrees Celsius and about 850 degrees Celsius. The process pressure of the epitaxial growth process can be between about 5 Torr and about 50 Torr. In some embodiments, a planarization process, such as chemical mechanical polishing, is selectively performed to provide a substantially flat surface for subsequent process steps.

[0145] In some embodiments, the plurality of doped regions 105-1 and 105-3 are formed from, for example, silicon phosphide (SiP), silicon-doped silicon-carbon (SiCP), silicon carbide (SiC), silicon-germanium (SiGe), silicon-germanium-tin alloy (SiGeSn), silicon-germanium-boron alloy (SiGeB), or other suitable semiconductor materials. After forming doped regions 105-1 and 105-3, doped region 105-1 can serve as a common source region, while doped region 105-3 can serve as a drain region.

[0146] Figure 6 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 7 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 6 Cross-sectional views obtained from lines A-A' and B-B'. Figure 8 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 9 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 8 Cross-sectional views obtained from lines A-A' and B-B'. Figure 10 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 11 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 10The cross-sectional views obtained along lines A-A' and B-B'. Note that some elements have been omitted in the top view for clarity.

[0147] Reference Figure 1 and Figures 6 to 11 In step S13, a plurality of bit line structures 300 are formed on the substrate 101, and a plurality of spacing structures 400 are formed on the side surfaces 300S of the plurality of bit line structures 300.

[0148] Reference Figure 6 and Figure 7 A bottom dielectric layer 107 of a dielectric layer stack 110 is formed on a substrate 101. In some embodiments, the bottom dielectric layer 107 is formed of a material having etch selectivity for the substrate 101 and the isolation layer 103. In some embodiments, the bottom dielectric layer 107 is formed of, for example, silicon nitride, boron nitride, boron phosphorus nitride, silicon carbide boron nitride, or a combination thereof. In some embodiments, the bottom dielectric layer 107 is formed of, for example, silicon nitride. In some embodiments, the bottom dielectric layer 107 is formed using, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0149] Reference Figure 6 and Figure 7 Multiple bit line contacts 309 are formed, penetrating the bottom dielectric layer 107 and extending to multiple common source regions 105-1. In some embodiments, the multiple bit line contacts 309 are formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, and metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), and transition metal aluminum nitrides, or combinations thereof. In some embodiments, the multiple bit line contacts 309 have a square cross-sectional profile when viewed from a top view, but are not limited thereto. In some embodiments, the multiple bit line contacts 309 have a rectangular, circular, or other suitable cross-sectional profile.

[0150] Reference Figure 8 and Figure 9 The plurality of bitline structures 300 are formed on the bottom dielectric layer 107 and electrically connected to the plurality of bitline contact points 309. From a top view perspective, the plurality of bitline structures 300 extend along the Y direction and are separated from each other. In other words, from a top view perspective, the plurality of bitline structures 300 intersect with the plurality of wordline structures 200. For simplicity, clarity, and ease of description, only one bitline structure 300 is described. In some embodiments, the bitline structure 300 includes a top conductive layer 301 for the bitlines and a bitline capping layer 307.

[0151] A top conductive layer 301 of the bit line is formed on and electrically connected to the bit line contact point 309. In some embodiments, the top conductive layer 301 of the bit line is formed of, for example, titanium nitride, tungsten, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other suitable conductive materials, or combinations thereof. A bit line cover layer 307 is formed on the top conductive layer 301 of the bit line. In some embodiments, the bit line cover layer 307 is formed of, for example, silicon nitride or other suitable insulating materials.

[0152] Reference Figure 10 and Figure 11 The plurality of spacing structures 400 are formed on the side surfaces 300S of the plurality of bitline structures 300. In other words, from a top view perspective, the plurality of spacing structures 400 extend along the Y direction. For simplicity, clarity and ease of description, only one spacing structure 400 is described. In some embodiments, the spacing structure 400 includes an inner spacing layer 401, a middle spacing layer 403, and an outer spacing layer 405.

[0153] A bit-line spacer layer 401 is formed on the side 300S of the bit-line structure 300. In some embodiments, the bit-line spacer layer 401 is formed of the same material as the bit-line cover layer 307. In some embodiments, the bit-line spacer layer 401 is formed of, for example, silicon nitride or other suitable insulating material. In some embodiments, the bit-line spacer layer 401 is formed by conformally depositing an insulating material on the bottom dielectric layer 107 and then performing an anisotropic etching process.

[0154] A bit-line intermediate spacer layer 403 is conformally formed on the bit-line inner spacer layer 401. In some embodiments, the bit-line intermediate spacer layer 403 is formed of, for example, silicon oxide or other suitable insulating oxide. In some embodiments, the bit-line intermediate spacer layer 403 is formed by conformally depositing an insulating oxide layer on the bottom dielectric layer 107 and then performing an anisotropic etching process.

[0155] A bitline outer spacer layer 405 is conformally formed on the bitline intermediate spacer layer 403. In some embodiments, the bitline outer spacer layer 405 is formed of the same material as the bitline inner spacer layer 401 or the bitline cover layer 307. In some embodiments, the bitline outer spacer layer 405 is formed of, for example, silicon nitride or other suitable insulating material. In some embodiments, the bitline outer spacer layer 405 is formed by conformally depositing an insulating material on the bottom dielectric layer 107 and then performing an anisotropic etching process.

[0156] In some embodiments, the inter-bit line spacer layer 401 is optional. In other words, the inter-bit line spacer layer 403 is formed directly on the side surface 300S of the bit line structure 300.

[0157] Figure 12 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 13 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 12 Cross-sectional views obtained from lines A-A' and B-B'. Figure 14 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 15 and Figure 16 For illustrative purposes, the process portions for manufacturing semiconductor device 1A according to the description of this disclosure are illustrated respectively. Figure 14 Cross-sectional views obtained from lines A-A' and B-B'. Figure 17 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 18 For illustrative purposes only, this diagram illustrates the following aspects of the present disclosure. Figure 17 Schematic cross-sectional views obtained from lines A-A' and B-B'.

[0158] Reference Figure 1 and Figures 12 to 18 In step S15, a sacrificial layer 801 is formed to cover the plurality of bit line structures 300 and the plurality of spacer structures 400. A first mask layer 701 including a line pattern P1 is formed on the sacrificial layer 801 to partially expose the sacrificial layer 801, the plurality of bit line structures 300, and the plurality of spacer structures 400. The sacrificial layer 801 is selectively removed to form the plurality of partition openings OP1, and the plurality of separator layers 601 are formed in the plurality of partition openings OP1.

[0159] Reference Figure 12 and Figure 13 A sacrificial layer 801 is formed on the bottom dielectric layer 107 to cover the plurality of bit line structures 300 and the plurality of spacer structures 400. In some embodiments, the sacrificial layer 801 is formed of a material, for example, having etch selectivity for the spacer layer 405 or the bit line cover layer 307. In some embodiments, the sacrificial layer 801 is formed of, for example, silicon oxynitride, silicon oxynitride, or other suitable materials. In some embodiments, the sacrificial layer 801 is formed using, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. In some embodiments, a planarization process, such as chemical mechanical polishing, is performed until the top surface 307TS of the plurality of bit line structures 300 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps.

[0160] It should be noted that, in the description of this disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than that of nitrogen. Silicon oxynitride refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than that of oxygen.

[0161] Reference Figure 12 and Figure 13A first mask layer 701 is formed on the sacrificial layer 801. In some embodiments, the first mask layer 701 is a photoresist layer. From a top view perspective, the line pattern P1 of the first mask layer 701 includes a plurality of rectangular spaces extending along the X direction and alternately arranged along the Y direction. Through these spaces, the sacrificial layer 801, the plurality of bit line structures 300, and the plurality of spacing structures 400 are partially exposed.

[0162] Reference Figure 14 and Figure 15 The sacrificial layer 801 exposed by the line pattern P1 of the first mask layer 701 is selectively removed. In some embodiments, the sacrificial layer 801 is removed by an anisotropic etching process, such as anisotropic dry etching. After the sacrificial layer 801 is removed, the plurality of partition openings OP1 are formed at the locations where the sacrificial layer 801 is exposed by the line pattern P1 of the first mask layer 701. After these partition openings OP1 are formed, the first mask layer 701 is removed.

[0163] Reference Figure 16 A layer of partition material 803 is formed on the sacrificial layer 801 to completely fill the plurality of partition openings OP1. In some embodiments, the partition material 803 is a material having etch selectivity for the sacrificial layer 801. In some embodiments, the partition material 803 has the same material as the bit line cover layer 307 or the bit line outer spacer layer 405. In some embodiments, the partition material 803 is, for example, silicon nitride or other suitable insulating material. In some embodiments, a layer of partition material 803 is formed by, for example, chemical vapor deposition or other suitable deposition processes.

[0164] In some embodiments, viewed in cross-section, the plurality of air gaps AG are sealed within a segmented material 803 layer, alternating with the bit line structure 300. Specifically, air gaps AG are formed at the bottom of the segmented material 803 layer. During the deposition of the segmented material 803 layer, air gaps AG are generated by varying the deposition rate during the deposition process. For example, a slower deposition rate is used at the beginning of the deposition process, followed by a faster deposition rate. This method causes the upper part of the partition opening OP1 to fill earlier than the lower part of the partition opening OP1. Thus, air gaps AG are formed in the segmented material 803 layer. With variations in deposition conditions and other parameters, air gaps AG can be formed in different shapes.

[0165] Reference Figure 17 and Figure 18A planarization process, such as chemical mechanical polishing, is performed to remove excess material, providing a substantially flat surface for subsequent process steps and transforming the partition material 803 layer into the plurality of partition layers 601. The partition layers 601 are formed or stacked on the bottom dielectric layer 107 and on a layer of the dielectric layer stack 110. From a top view perspective, each of the plurality of partition layers 601 has a linear (or rectangular) cross-section extending along the X direction. The plurality of partition layers 601 are arranged alternately along the X direction, with each corresponding bit line structure 300 located between two adjacent partition layers 601. Along the Y direction, the plurality of partition layers 601 are arranged alternately with a sacrificial layer 801, with the sacrificial layer 801 located therebetween. From a top view perspective, the arrangement of the plurality of partition layers 601 and the plurality of bit line structures 300 divides the sacrificial layer 801 into multiple portions.

[0166] For brevity, clarity, and ease of description, only one separator layer 601 is described. In some embodiments, after the planarization process, the inner spacer layer 401, the middle spacer layer 403, and the outer spacer layer 405 may be exposed. The top surface 601TS of separator layer 601, the top surface 401TS of inner spacer layer 401, the top surface 403TS of middle spacer layer 403, the top surface 405TS of outer spacer layer 405, and the top surface 307TS of bitline cover layer 307 are substantially coplanar.

[0167] In some embodiments, after the planarization process, the inner spacer layer 401 and the middle spacer layer 403 of the bit line may be covered by the outer spacer layer 405 of the bit line. In these embodiments, the top surface 405TS of the outer spacer layer 405 and the top surface 307TS of the bit line cover layer 307 are substantially coplanar.

[0168] Figure 19 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figures 20 to 23 For illustrative purposes, the process portions for manufacturing semiconductor device 1A according to the description of this disclosure are illustrated respectively. Figure 19 Cross-sectional views obtained from lines A-A' and B-B'. Figure 24 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 25 and Figure 26 For illustrative purposes, the process portions for manufacturing semiconductor device 1A according to the description of this disclosure are illustrated respectively. Figure 24 Cross-sectional views obtained from lines A-A' and B-B'. Figure 27 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 28 and Figure 29 For illustrative purposes, the process portions for manufacturing semiconductor device 1A according to the description of this disclosure are illustrated respectively. Figure 27 Cross-sectional views obtained from lines A-A' and B-B'.

[0169] Reference Figure 1 and Figures 19 to 29 In step S17, the sacrificial layer 801 is selectively removed to form a plurality of contact openings OP2, a plurality of unit contact structures 500 are formed in the plurality of contact openings OP2, and a top insulating layer 109 is formed to cover a plurality of bit line structures 300, a plurality of spacer structures 400 and a plurality of unit contact structures 500.

[0170] Reference Figure 19 and Figure 20 The sacrificial layer 801 is selectively removed by an etching process. For example, the sacrificial layer 801 is removed by an anisotropic etching process. After the sacrificial layer 801 is removed, multiple contact openings OP2 are formed in multiple portions at the locations where the sacrificial layer 801 previously existed. For simplicity, clarity, and ease of description, only one contact opening OP2 is described. From the cross-sectional perspective view, the contact opening OP2 is disposed on the bottom dielectric layer 107. From the top view, along the Y direction, two adjacent separator layers 601 surround the contact opening OP2, and along the X direction, two adjacent bit line structures 300 (or spacer structures 400 disposed on the sides 300S of the two adjacent bit line structures 300) surround the two adjacent separator layers 601.

[0171] Reference Figure 21 A through-etch process is performed to remove portions of the bottom dielectric layer 107 exposed through multiple contact openings OP2. In some embodiments, the through-etch process is an anisotropic dry etching process. The through-etch process extends the multiple contact openings OP2 downwards to the substrate 101. After the through-etch process, multiple drain regions 105-3 are exposed through the multiple contact openings OP2.

[0172] Reference Figure 22 A conformally formed pad material 805 is used to cover the substrate 101, the plurality of bit line structures 300, the plurality of spacer structures 400, and the plurality of separator layers 601. In some embodiments, the pad material 805 is, for example, doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. In some embodiments, the pad material 805 includes p-type dopants or n-type dopants. In some embodiments, the pad material 805 layer is formed by, for example, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0173] Reference Figure 23A first conductive material 807 is formed on the pad material 805 layer, and this first conductive material 807 completely fills the plurality of contact openings OP2. In some embodiments, the first conductive material 807 is a material with good electrical conductivity (or a material with better electrical conductivity than polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon germanium). In some embodiments, the first conductive material 807 is, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof. In some embodiments, the first conductive material 807 is, for example, titanium nitride, titanium, tungsten, or combinations thereof.

[0174] Reference Figure 24 and Figure 25 An etch-back process is performed to remove portions of the pad material 805 and the first conductive material 807. After the etch-back process, the remaining portion of the pad material 805 is transformed into multiple layers 501 in the multiple contact openings OP2. The remaining portion of the first conductive material 807 is transformed into multiple bottom contact layers 503 in the multiple contact openings OP2.

[0175] For brevity, clarity, and ease of description, only one liner 501 and one bottom contact layer 503 are described. In some embodiments, viewed from a cross-sectional perspective, the top surface 503TS of the bottom contact layer 503 and the top surface 501TS of the liner 501 are substantially coplanar. The top surface 503TS of the bottom contact layer 503 and the top surface 501TS of the liner 501 are lower than the top surface 307TS of the bitline overlay layer 307 (i.e., the top surface of the bitline structure 300). In some embodiments, viewed from a top perspective, the liner 501 has a square or rectangular annular cross-sectional profile. The bottom contact layer 503 has a square or rectangular cross-sectional profile.

[0176] Reference Figure 26A second conductive material 809 is formed on the substrate 101, and this second conductive material 809 completely fills the plurality of contact openings OP2 and covers the plurality of separator layers 601, the plurality of bit line structures 300, and the plurality of spacer structures 400. In some embodiments, the second conductive material 809 is, for example, a material with good electrical conductivity (or a material with better electrical conductivity than polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon germanium). In some embodiments, the second conductive material 809 has the same material as the bottom contact layer 503. In some embodiments, the second conductive material 809 is, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, the second conductive material 809 is, for example, titanium nitride, titanium, tungsten, or combinations thereof.

[0177] Reference Figure 27 and Figure 28 An etch-back process is performed to remove a portion of the second conductive material 809. After the etch-back process, the remaining portion of the second conductive material 809 is transformed into multiple top contact layers 505 in the multiple contact openings OP2. For brevity, clarity, and ease of description, only one top contact layer 505 is described. In some embodiments, from a cross-sectional perspective view, the top surface 505TS of the top contact layer 505 is lower than the top surface 307TS of the bit line overlay layer 307. In some embodiments, the width W1 of the top contact layer 505 is greater than the width W2 of the bottom contact layer 503. In some embodiments, from a top perspective view, the top contact layer 505 has a square or rectangular cross-sectional profile. The liner 501, the bottom contact layer 503, and the top contact layer 505 are configured together as a unit contact structure 500. The unit contact structure 500 is electrically connected to the corresponding drain regions 105-3.

[0178] Reference Figure 29 A top insulating layer 109 is formed on a substrate 101, covering a plurality of separator layers 601, a plurality of cell contact structures 500, a plurality of spacer structures 400, and a plurality of bit line structures 300. In some embodiments, the top insulating layer 109 is formed of the same material as the bit line cover layer 307. In some embodiments, the top insulating layer 109 is formed of, for example, silicon nitride or other suitable insulating material. After forming the top insulating layer 109, the bottom portion 109p of the top insulating layer 109 on the contact opening OP2 and the cell contact structure 500 is removed. The removal of the bottom portion 109p is performed using an anisotropic etching process, such as a dry etching process.

[0179] Using a substrate 501 formed of doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium can reduce junction leakage current in the cell contact structure 500. Furthermore, using a bottom contact layer 503 and a top contact layer 505 made of materials such as titanium nitride, tungsten, or titanium effectively reduces the sheet resistance of the cell contact structure 500. These improvements collectively enhance the performance of the semiconductor device 1A.

[0180] Figure 30 For illustrative purposes, a top view of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 31 and Figure 32 For illustrative purposes, the process portions for manufacturing semiconductor device 1A according to the description of this disclosure are illustrated respectively. Figure 30 Cross-sectional views obtained from lines A-A' and C-C'.

[0181] Reference Figure 1 and Figures 30 to 32 In step S19, a plurality of conductive pillars 116 are formed on the unit contact structure 500, and a plurality of contact pads CP are formed on the conductive pillars 116 respectively.

[0182] Reference Figure 30 and Figure 31 A first conductive layer 118 and a second conductive layer 120 are formed on the top insulating layer 109. The second conductive layer 120 is stacked on the first conductive layer 118. It should be noted that the contact opening OP2 is simultaneously filled by the first conductive layer 118. Conductive pillars 116 and contact pads CP will be formed in subsequent steps by patterning the first conductive layer 118 and the second conductive layer 120. In some embodiments, the first conductive layer 118 has a thickness greater than that of the second conductive layer 120. Furthermore, in some embodiments, the conductive material forming the second conductive layer 120 has a lower resistivity than the first conductive layer 118, and the conductive material forming the first conductive layer 118 has sufficient etch selectivity relative to the material of the second conductive layer 120. The formation of the first conductive layer 118 and the second conductive layer 120 includes deposition processes (e.g., PVD processes), electroplating processes, or combinations thereof.

[0183] Reference Figure 32The first conductive layer 118 and the second conductive layer 120 are patterned to form initial conductive pillars 116' and contact pads CP. During patterning, portions of the first conductive layer 118 and the second conductive layer 120 are removed, potentially exposing portions of the topmost dielectric layer (e.g., top insulating layer 109). The sidewalls of the formed initial conductive pillars 116' may be substantially coplanar with the sidewalls of the formed contact pads CP. In other words, the footprint of each initial conductive pillar 116' may be substantially the same as the footprint of the contact pad CP above it. In subsequent steps, the initial conductive pillars 116' are laterally recessed to form conductive pillars 116. In some embodiments, the formation of the initial conductive pillars 116' and contact pads CP includes a photolithography process and a single etching process (e.g., a single anisotropic etching process). In these embodiments, the first conductive layer 118 and the second conductive layer 120 are partially removed in the same etching process. In alternative embodiments, the formation of the initial conductive pillars 116' and contact pads CP uses two etching processes (e.g., two anisotropic etching processes). First, a first etching process is performed to form the contact pad CP, followed by a second etching process to form the initial conductive pillar 116'.

[0184] Subsequently, the initial conductive post 116' is laterally recessed to form the conductive post 116. In some embodiments, the method of laterally recessing the initial conductive post 116' includes an isotropic etching process (e.g., a wet etching process). In embodiments where the conductive material forming the contact pad CP has sufficient etch selectivity relative to the conductive material forming the initial conductive post 116', the contact pad CP is avoided from being damaged (or possibly slightly consumed) in these isotropic etching processes. Therefore, the formed conductive post 116 is laterally recessed relative to the contact pad CP. It should be noted that, as Figure 30 As shown, the plurality of conductive posts 116 and contact pads CP have a square cross-sectional profile, but are not limited thereto. In some embodiments, the plurality of conductive posts 116 and contact pads CP have a rectangular, circular or other suitable cross-sectional profile.

[0185] On the unit contact structure 500, conductive pillars 116 and contact pads CP form a T-shaped stacked structure, defining a recess therebetween. Dielectric layer 121 in dielectric layer stack 110 fills the recess defined by the T-shaped stacked structure. In some embodiments, the thickness of dielectric layer 121 is greater than the thickness of other dielectric layers in dielectric layer stack 110 (e.g., bottom dielectric layer 107 and separator layer 601). In some embodiments, the formation of dielectric layer 121 includes a deposition process (e.g., a CVD process) and a planarization process for removing excess material above the contact pads CP. After dielectric layer 121 is formed around the T-shaped stacked structure, semiconductor device 1A is completed.

[0186] Figure 33For illustrative purposes, this diagram illustrates a portion of the process for manufacturing semiconductor device 1B according to the description of this disclosure. Figure 30 Cross-sectional views obtained from lines A-A' and C-C'. Figure 33 Zhongyu Figure 32 Elements that are identical or similar are marked with similar reference numbers, and duplicate descriptions will be omitted.

[0187] Reference Figure 33 In some embodiments, the dielectric layer 121 may not completely fill the grooves between the T-shaped stacked structures. Because the conductive posts 116 are laterally recessed relative to the contact pads CP, the space between adjacent contact pads CP is shorter than the space between adjacent conductive posts 116. In other words, the grooves defined between the T-shaped stacked structures each have a relatively narrow top portion and a relatively wide bottom portion. When the dielectric layer 121 fills these narrow grooves, the relatively narrow top portions of these grooves may be sealed before the relatively wide bottom portions are fully filled. Therefore, air gaps AS may be formed in these relatively wide bottom portions. In other words, air gaps AS that may be formed are located between the conductive posts 116. As the groove size, deposition conditions, and other parameters vary, the air gaps AS may be formed in different shapes, and the tops of the air gaps AS may or may not extend beyond the tops of the conductive posts 116. In some embodiments, the air gaps AS may not expose the sidewalls of the conductive posts 116.

[0188] One embodiment of this disclosure provides a semiconductor device including a substrate having a plurality of doped regions; a two-bit line structure formed on the substrate, extending along a first direction and separated from each other; two separator layers disposed on the substrate, extending along a second direction perpendicular to the first direction, separated from each other along the first direction, and simultaneously contacting the two-bit line structure; and a unit contact structure disposed on the substrate. The unit contact structure includes a bottom contact layer disposed on the substrate and closed by the two-bit line structure and the two separator layers. The unit contact structure also includes a liner disposed between the substrate and the bottom contact layer, between the two-bit line structure and the bottom contact layer, and between the two separator layers and the bottom contact layer. The unit contact structure further includes a top contact layer disposed on the liner and the bottom contact layer. The two-bit line structure includes an air gap disposed therebetween.

[0189] Another embodiment of this disclosure provides a semiconductor device including a substrate; a plurality of doped regions disposed in the substrate; a two-bit line structure formed on the substrate, extending along a first direction and separated from each other; two separator layers disposed on the substrate, extending along a second direction perpendicular to the first direction, separated from each other along the first direction, and simultaneously contacting the two-bit line structure; a unit contact structure disposed on the substrate; a conductive pillar disposed on the unit contact structure; a contact pad disposed on the conductive pillar; and a dielectric layer stack disposed on the substrate and including at least one dielectric layer. The two-bit line structure includes a first air gap disposed therebetween. The unit contact structure includes a bottom contact layer disposed on the substrate and closed by the two-bit line structure and the two separator layers. The unit contact structure also includes a liner disposed between the substrate and the bottom contact layer, between the two-bit line structure and the bottom contact layer, and between the two separator layers and the bottom contact layer. The unit contact structure further includes a top contact layer disposed on the liner and the bottom contact layer. The multiple doped regions are formed of silicon phosphide, phosphorus-doped silicon-carbon, silicon carbide, silicon-germanium, silicon-germanium-tin alloy, or silicon-germanium-boron alloy. One sidewall of the conductive pillar is recessed inward from one sidewall of the contact pad. One dielectric layer in the dielectric layer stack is configured to laterally surround a thicker dielectric layer of the conductive pillar and the contact pad. Multiple second air gaps are sealed within the thicker dielectric layer and are arranged alternately with the conductive pillar.

[0190] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming two separate two-bit line structures extending along a first direction on the substrate; forming a plurality of spacer structures on the side surfaces of the two-bit line structures; forming an air gap between the two-bit line structures; forming two separating layers on the substrate extending along a second direction perpendicular to the first direction, separating from each other, and forming a contact opening together with the plurality of spacer structures; conformally forming a liner layer in and within the contact opening; forming a bottom contact layer on the liner layer and within the contact opening; and forming a top contact layer on the liner layer, the bottom contact layer, and within the contact opening. The liner layer, the bottom contact layer, and the top contact layer are configured together to form a unit contact structure.

[0191] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, including providing a substrate having a plurality of active regions; forming a plurality of doped regions in the substrate; forming two-bit line structures extending along a first direction and separated from each other on the substrate; forming a plurality of spacer structures on the side surfaces of the two-bit line structures; forming a first air gap between the two-bit line structures; forming two separating layers extending along a second direction perpendicular to the first direction and separated from each other on the substrate, and forming a contact opening together with the plurality of spacer structures; conformally forming a liner layer in and within the contact opening; forming a bottom contact layer on the liner layer and within the contact opening; and forming a top contact layer on the liner layer, the bottom contact layer, and within the contact opening. The plurality of doped regions are formed of silicon phosphide, phosphorus-doped silicon-carbon, silicon carbide, silicon-germanium, silicon-germanium-tin alloy, or silicon-germanium-boron alloy. The liner layer, the bottom contact layer, and the top contact layer are configured together to form a unit contact structure.

[0192] Due to the design of the semiconductor device disclosed herein, by employing a substrate 501 formed of doped polysilicon, doped polysilicon, or doped polysilicon-germanium, the interface leakage current of the cell contact structure 500 can be reduced. Furthermore, by employing a bottom contact layer 503 and a top contact layer 505 formed of titanium nitride, tungsten, or titanium, the sheet resistance of the cell contact structure 500 can be reduced. Therefore, the performance of the semiconductor device 1A can be improved.

[0193] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0194] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A substrate with multiple doped regions; Two-dimensional linear structures are formed on the substrate, extending along a first direction and separated from each other; Two separating layers are disposed on the substrate, extend along a second direction perpendicular to the first direction, are separated from each other along the first direction, and simultaneously contact the two-dimensional line structure; as well as A single-unit contact structure, disposed on the substrate, includes: A bottom contact layer is disposed on the substrate and sealed by the two-dimensional line structure and the two separation layers; A liner layer is disposed between the substrate and the bottom contact layer, between the two-dimensional linear structure and the bottom contact layer, and between the two separating layers and the bottom contact layer; and A top contact layer is disposed on the liner and the bottom contact layer. The two-dimensional line structure includes an air gap disposed therebetween.

2. The semiconductor device of claim 1, wherein the bottom contact layer comprises tungsten, titanium, or titanium nitride.

3. The semiconductor device of claim 2, wherein the top contact layer comprises a material, wherein the material of the top contact layer is the same as a material of the bottom contact layer.

4. The semiconductor device of claim 2, wherein a top surface of the top contact layer is lower than the top surface of the two-bit line structure.

5. The semiconductor device of claim 4, wherein the substrate comprises an n-type dopant or a p-type dopant.

6. The semiconductor device of claim 4, wherein the substrate comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium.

7. The semiconductor device of claim 4, wherein, viewed from a top perspective, the bottom contact layer comprises a rectangular cross-sectional profile or a square cross-sectional profile.

8. The semiconductor device of claim 1 further includes a plurality of spacer structures disposed between the unit contact structure and the two-bit line structure.

9. The semiconductor device of claim 8, wherein the plurality of spacer structures each include an inner spacer layer disposed between one of the bit line structures and the cell contact structure, an intermediate spacer layer disposed between the inner spacer layer and the cell contact structure, and an outer spacer layer disposed between the intermediate spacer layer and the cell contact structure.

10. The semiconductor device of claim 1, wherein the plurality of doped regions are formed of silicon phosphide, phosphorus-doped silicon-carbon, silicon carbide, silicon-germanium, silicon-germanium-tin alloy or silicon-germanium-boron alloy.

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