Semiconductor device

Abstract

A semiconductor device having improved heat dissipation characteristics is provided. The semiconductor device of one embodiment includes a substrate, a first transistor and a second transistor provided in an inner portion of the substrate, a first wiring provided in the inner portion of the substrate and electrically connected to a source electrode of the first transistor and a source electrode of the second transistor, and an optical coupler provided over a top surface of the substrate and controlling states of the first transistor and the second transistor.

Description

[0001] [Related Application]

[0002] This application enjoys priority based on Japanese Patent Application No. 2025-042762 (filed on March 17, 2025). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation involves a semiconductor device. Background Technology

[0004] As a semiconductor device, an opto-relay device is known, which includes two MOSFETs (metal-oxide-semiconductor field-effect transistors) and an optocoupler. The opto-relay device is a contactless relay used for transmitting AC and DC signals. Summary of the Invention

[0005] One embodiment provides a semiconductor device with improved heat dissipation characteristics.

[0006] The semiconductor device of the embodiment includes: a substrate; a first transistor and a second transistor disposed inside the substrate; a first wiring disposed inside the substrate and connected to the source electrode of the first transistor and the source electrode of the second transistor respectively; and an optocoupler disposed on the upper surface of the substrate for controlling the state of the first transistor and the second transistor. Attached Figure Description

[0007] Figure 1 This is a circuit diagram illustrating an example of the circuit structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a perspective view showing an example of the structure of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a top view showing an example of the planar layout of the surface of the semiconductor device according to the first embodiment.

[0010] Figure 4 This is a top view showing an example of the planar layout of the back side of the semiconductor device according to the first embodiment.

[0011] Figure 5 This is an example of the cross-sectional structure of the semiconductor device according to the first embodiment, along... Figure 3 and Figure 4 A cross-sectional view of the VV line.

[0012] Figure 6This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to a modified embodiment of the first embodiment.

[0013] Figure 7 This is a top view showing an example of the planar layout of the surface of the semiconductor device according to the second embodiment.

[0014] Figure 8 This is a top view showing an example of the planar layout of the back side of the semiconductor device according to the second embodiment.

[0015] Figure 9 This is an example of the cross-sectional structure of the semiconductor device according to the second embodiment, along... Figure 7 and Figure 8 A sectional view of line IX-IX.

[0016] Figure 10 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to a first variation of the second embodiment.

[0017] Figure 11 This is a top view showing an example of the planar layout of the surface of a semiconductor device in a second variation of the second embodiment.

[0018] Figure 12 This is a top view showing an example of the planar layout of the surface of a semiconductor device in a third variation of the second embodiment.

[0019] Figure 13 This is a top view showing an example of the planar layout of the surface of a semiconductor device in a fourth variation of the second embodiment. Detailed Implementation

[0020] The embodiments will now be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same function and structure will be labeled with common reference numerals in the accompanying drawings. Also, the dimensions and scale of the drawings may not be the same as in reality.

[0021] The semiconductor device described in this embodiment is, for example, a surface-mount device (SMD) electronic component. The semiconductor device described in this embodiment is, for example, an opto-relay device for transmitting high-current AC or DC signals. The semiconductor device described in this embodiment is used, for example, in industrial machinery, power conversion devices, automotive devices, home appliances, and communication devices. Furthermore, in the following description, AC and DC signals will be simply referred to as signals.

[0022] 1. First Implementation Method

[0023] The semiconductor device of the first embodiment will be described.

[0024] Figure 1This is a circuit diagram illustrating an example of the circuit structure of the semiconductor device according to the first embodiment.

[0025] Semiconductor device 1 includes electrodes 31, 32, 33, and 34. Electrodes 31 and 32 are electrode pads mounted on the outer edge of the package and are supplied with voltage from the outside for driving semiconductor device 1. During the driving of semiconductor device 1, semiconductor device 1 can transmit signals via electrodes 33 and 34.

[0026] Semiconductor device 1 includes substrate 5 and optocoupler 10. Substrate 5 is a component-integrated substrate housing MOSFETs (metal-oxide-semiconductor field-effect transistors) 20A and 20B. MOSFETs 20A and 20B are, for example, enhancement-mode N-channel MOSFETs. Optocoupler 10 is a package housing a light-emitting element 11 and a light-receiving element 12. Optocoupler 10 has terminals 13, 14, 15, and 16 as connection terminals to the outside.

[0027] The light-emitting element 11 is, for example, an LED (Light Emitting Diode). The cathode electrode of the light-emitting element 11 is connected to the electrode 31 via terminal 13. The anode electrode of the light-emitting element 11 is connected to the electrode 32 via terminal 14. The light-emitting element 11 is driven by power supplied to electrodes 31 and 32. Thus, the light-emitting state of the light-emitting element 11 is either on (lit) or off (extinguished).

[0028] The light-receiving element 12 is, for example, a PDA (Photo Diode Array). The light-receiving element 12 may comprise several to dozens of photodiodes connected in series. The light-receiving element 12 may also be a phototransistor. The cathode electrode of the light-receiving element 12 is connected to terminal 15. The anode electrode of the light-receiving element 12 is connected to terminal 16.

[0029] The source of MOSFET 20A and the source of MOSFET 20B are connected to the cathode electrode of the light-receiving element 12 via terminal 15. The gate of MOSFET 20A and the gate of MOSFET 20B are connected to the anode electrode of the light-receiving element 12 via terminal 16. The drain of MOSFET 20A is connected to electrode 33. The drain of MOSFET 20B is connected to electrode 34.

[0030] In the circuit structure of the semiconductor device 1 described above, when the light-emitting element 11 changes from an off state to an on state, light is emitted from the light-emitting element 11. The light-receiving element 12 uses the voltage generated by the photoelectromotive force effect of the light emanating from the light-emitting element 11 to turn on the MOSFETs 20A and 20B from an off state. As a result, electrodes 33 and 34 are electrically connected. Thus, the semiconductor device 1 transmits the signal supplied to one of the electrodes 33 and 34 to the other electrode 33 and 34 via the MOSFETs 20A and 20B.

[0031] Furthermore, when the light-emitting element 11 changes from the ON state to the OFF state, the illumination from the light-emitting element 11 stops. Consequently, MOSFETs 20A and 20B change from the ON state to the OFF state. Thus, the semiconductor device 1 electrically insulates the electrodes 33 and 34.

[0032] Next, use Figure 2 , Figure 3 and Figure 4 The structure of semiconductor device 1 will be described. Figure 2 This is a perspective view showing an example of the structure of the semiconductor device according to the first embodiment. Figure 3 This is a top view showing an example of the planar layout of the surface of the semiconductor device according to the first embodiment. Figure 4 This is a top view showing an example of the planar layout of the back side of the semiconductor device according to the first embodiment.

[0033] In the following description, the XY plane is a plane parallel to the mounting surface of the optocoupler 10 on the substrate 5. The X direction is the direction in which MOSFETs 20A and 20B are arranged within the XY plane. The Y direction is a direction within the XY plane orthogonal to the X direction. The Z direction is a direction orthogonal to the XY plane. The direction in the Z direction from the substrate 5 towards the optocoupler 10 is called the upward direction, and the direction from the optocoupler 10 towards the substrate 5 is called the downward direction. Furthermore, in... Figure 3 and Figure 4 For ease of explanation, a portion of the insulator is omitted from the diagram.

[0034] Semiconductor device 1 includes wirings 40, 41, 42, 43, 50, 51, 52, 53 and 54, through holes 60, 61, 62, 63, 64, 65 and 66, and sealing material 70. MOSFET 20A includes electrodes 21A, 22A and 23A. MOSFET 20B includes electrodes 21B, 22B and 23B.

[0035] Optical coupler 10 is disposed above substrate 5. Optical coupler 10 is sealed by sealing material 70 covering the substrate 5. Sealing material 70 may, for example, contain a non-transparent material.

[0036] MOSFETs 20A and 20B are arranged with optocoupler 10 in the Y direction. MOSFETs 20A and 20B are arranged within substrate 5 in the X direction. As described above, MOSFETs 20A and 20B are embedded in substrate 5. That is, MOSFETs 20A and 20B are positioned differently from optocoupler 10 in the Z direction, so they do not physically interfere with each other. Therefore, when viewed in the Y direction, MOSFETs 20A and 20B are respectively positioned overlapping with optocoupler 10. With this configuration, the X-direction spacing between MOSFETs 20A and 20B is shorter than if MOSFETs 20A and 20B were positioned in a position not overlapping with optocoupler 10 when viewed in the Y direction. That is, the X-direction spacing between MOSFETs 20A and 20B is shorter than the X-direction length of optocoupler 10.

[0037] Electrodes 21A and 22A are disposed on the upper surface of MOSFET 20A. Electrode 22A is arranged in the Y direction with electrode 21A, for example, on the side closer to optocoupler 10 than electrode 21A. Electrode 23A is disposed on the lower surface of MOSFET 20A. Electrode 21A is the source electrode. Electrode 22A is the gate electrode. Electrode 23A is the drain electrode.

[0038] Electrodes 21B and 22B are disposed on the upper surface of MOSFET 20B. Electrode 22B is arranged in the Y direction with electrode 21B, for example, on the side closer to optocoupler 10 than electrode 21B. Electrode 23B is disposed on the lower surface of MOSFET 20B. Electrode 21B is the source electrode. Electrode 22B is the gate electrode. Electrode 23B is the drain electrode.

[0039] Electrodes 31, 32, 33, and 34 are disposed separately on the lower surface of substrate 5. Electrodes 31 and 32 are arranged in the X direction. Electrodes 33 and 34 are arranged in the X direction. Electrode 33 is disposed at a position overlapping with MOSFET 20A when semiconductor device 1 is viewed from below. Electrode 34 is disposed at a position overlapping with MOSFET 20B when semiconductor device 1 is viewed from below. Electrode 31 is located closer to optocoupler 10 than electrode 33 and is arranged in the Y direction with electrode 33. Electrode 32 is located closer to optocoupler 10 than electrode 34 and is arranged in the Y direction with electrode 34.

[0040] Wirings 40, 41, 42, and 43 are conductors disposed separately on the upper surface of substrate 5. Wiring 40 is, for example, T-shaped. When viewed from below, wiring 40 has a portion overlapping with optocoupler 10 and a portion not overlapping. The portion of wiring 40 not overlapping with optocoupler 10 includes portion 401 arranged in the Y direction relative to optocoupler 10, and two portions 402 and 403 sandwiching optocoupler 10 in the X direction. The upper surface of portion 401 of wiring 40 is connected to terminal 16. Portions 402 and 403 of wiring 40 are electrically connected to terminal 16 via portion 401. Wiring 41 is, for example, rectangular. The upper surface of wiring 41 is connected to terminal 15. Wiring 42 is, for example, rectangular. The upper surface of wiring 42 is connected to terminal 13. Wiring 43 is, for example, rectangular. The upper surface of wiring 43 is connected to terminal 14.

[0041] Wiring 50, 51, 52, 53, and 54 are conductors disposed separately within the substrate 5. Wiring 50, for example, has a rectangular shape extending along the X direction. Wiring 50 is connected to the upper surface of electrode 21A of MOSFET 20A and the upper surface of electrode 21B of MOSFET 20B. Wiring 51, for example, has a rectangular shape extending along the Y direction. Wiring 51 is connected to the upper surface of electrode 22A of MOSFET 20A. Wiring 52, for example, has a rectangular shape extending along the Y direction. Wiring 52 is connected to the upper surface of electrode 22B of MOSFET 20B. Wiring 53 is connected to the lower surface of electrode 23A of MOSFET 20A. Wiring 54 is connected to the lower surface of electrode 23B of MOSFET 20B.

[0042] Vias 60, 61, 62, 63, 64, 65, and 66 are conductors that are separated from each other and extend along the Z-direction within the substrate 5. Via 60 connects the lower surface of wiring 41 to the upper surface of wiring 50. Via 61 connects the lower surface of portion 402 of wiring 40 to the upper surface of wiring 51. Via 62 connects the lower surface of portion 403 of wiring 40 to the upper surface of wiring 52. Via 63 connects the lower surface of wiring 53 to the upper surface of electrode 33. Via 64 connects the lower surface of wiring 54 to the upper surface of electrode 34. Via 65 connects the lower surface of wiring 42 to the upper surface of electrode 31. Via 66 connects the lower surface of wiring 43 to the upper surface of electrode 32. Vias 60, 61, 62, 63, 64, 65, and 66 can each be composed of multiple vias.

[0043] Next, use Figure 5 The cross-sectional structure of semiconductor device 1 will be described. Figure 5 This is an example of the cross-sectional structure of the semiconductor device according to the first embodiment, along... Figure 3 and Figure 4 A cross-sectional view of the VV line.

[0044] like Figure 5 As shown, the semiconductor device 1 further includes insulating layers 71, 72, and 73. Insulating layers 71, 72, and 73 are substrates constituting the substrate 5. Insulating layer 72 is disposed on the upper surface of insulating layer 71. Insulating layer 73 is disposed on the upper surface of insulating layer 72. Sealing material 70 is disposed on the upper surface of insulating layer 73.

[0045] The lower surface of the insulating layer 71 corresponds to the lower surface of the substrate 5. That is, electrodes 31, 32, 33, and 34 are provided on the lower surface of the insulating layer 71. Wiring circuits 53 and 54 are provided on the upper surface of the insulating layer 71. Furthermore, a portion of the vias 63, 64, 65, and 66 extend along the Z-direction within the insulating layer 71.

[0046] MOSFETs 20A and 20B are disposed on the same layer as insulating layer 72. Figure 5 In the example, the lower surfaces of MOSFET 20A and MOSFET 20B are aligned with the lower surface of insulating layer 72, and the upper surfaces of MOSFET 20A and MOSFET 20B are aligned with the upper surface of insulating layer 72. A portion of vias 65 and 66 extends along the Z direction within insulating layer 72.

[0047] The upper surface of the insulating layer 73 corresponds to the upper surface of the substrate 5. That is, wirings 40, 41, 42, and 43 are provided on the upper surface of the insulating layer 73. Wirings 59, 51, and 52 are provided on the lower surface of the insulating layer 73. Furthermore, within the insulating layer 73, a portion of through holes 60, 61, 62, 65, and a portion of 66 extend in the Z direction.

[0048] With the structure described above, the substrate 5 functions as a multilayer wiring substrate with built-in MOSFETs 20A and 20B, and has wiring on four layers: the lower surface of the insulating layer 71, the boundary between insulating layers 71 and 72, the boundary between insulating layers 72 and 73, and the upper surface of the insulating layer 73.

[0049] Furthermore, in the first embodiment, the case where vias 65 and 66 electrically connect the wiring on the lower surface of the insulating layer 71 to the wiring on the upper surface of the insulating layer 73 without wiring provided at the boundaries of insulating layers 71 and 72 and the boundaries of insulating layers 72 and 73 is described, but this is not a limitation. For example, vias 65 and 66 may also be configured to electrically connect the wiring on the lower surface of the insulating layer 71 to the wiring on the upper surface of the insulating layer 73 via wiring provided at the boundaries of insulating layers 71 and 72 and the boundaries of insulating layers 72 and 73.

[0050] According to the first embodiment, substrate 5 houses MOSFETs 20A and 20B, and wiring 50. Wiring 50 extends in the X direction within substrate 5 and is connected to the electrode 21A of MOSFET 20A and the electrode 21B of MOSFET 20B, respectively. Optocoupler 10 is disposed on the upper surface of substrate 5. Terminal 15 of optocoupler 10 is electrically connected to the electrode 21A of MOSFET 20A and the electrode 21B of MOSFET 20B via wiring 50. Terminal 16 of optocoupler 10 is electrically connected to the electrode 22A of MOSFET 20A and the electrode 22B of MOSFET 20B. Therefore, semiconductor device 1 can be configured to electrically connect the electrode 21A of MOSFET 20A and the electrode 21B of MOSFET 20B to the terminal 15 of optocoupler 10 without using wiring with relatively high resistance, such as bonding wires. Therefore, the increase in the on-resistance of MOSFETs 20A and 20B can be suppressed. Therefore, the increase in heat generation of semiconductor device 1 can be suppressed.

[0051] Furthermore, since MOSFETs 20A and 20B are positioned differently from optocoupler 10 in the Z direction, they do not physically interfere with each other. Therefore, the X-direction spacing between MOSFETs 20A and 20B can be shorter than the X-direction length of optocoupler 10. Thus, compared to the case where MOSFETs 20A and 20B are disposed on the upper surface of substrate 5, the X-direction length of semiconductor device 1 can be shortened. Therefore, semiconductor device 1 can be further miniaturized. <Modification of the First Embodiment>

[0052] Furthermore, the first embodiment described above can be adapted to various variations.

[0053] In the first embodiment described above, the wiring 40, 41, 42, and 43 provided on the upper surface of the substrate 5 and the optocoupler 10 are described as being sealed by the sealing material 70, but this is not a limitation. For example, the wiring 40, 41, 42, and 43 provided on the upper surface of the substrate 5 and the optocoupler 10 may not be sealed by the sealing material 70.

[0054] Figure 6 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to a modified embodiment of the first embodiment. Figure 6 Corresponding to the first embodiment Figure 5 .

[0055] like Figure 6 As shown, the semiconductor device 1_1 does not include the sealing material 70. That is, the upper surface of the insulating layer 73 is not sealed by the sealing material 70 and is exposed to the outside.

[0056] According to a variation of the first embodiment, the semiconductor device 1_1, like the semiconductor device 1 in the first embodiment, can be configured to electrically connect the electrodes 21A of MOSFET 20A and 21B of MOSFET 20B to the terminals 15 of the optocoupler 10 without using wiring with relatively high resistance, such as bonding wires. Therefore, the increase in the on-resistance of MOSFETs 20A and 20B can be suppressed. Therefore, the increase in heat generation of the semiconductor device 1 can be suppressed.

[0057] Furthermore, since MOSFETs 20A and 20B are positioned differently in the Z direction from optocoupler 10, they do not physically interfere with each other. Therefore, the size of the semiconductor device 1_1 can be further reduced.

[0058] 2. Second Implementation Method

[0059] Next, the semiconductor device according to the second embodiment will be described. Hereinafter, the structure that differs from that of the first embodiment will be mainly described. For structures identical to those of the first embodiment, descriptions will be omitted as appropriate.

[0060] Figure 7 This is a top view showing an example of the planar layout of the surface of the semiconductor device according to the second embodiment. Figure 8 This is a top view showing an example of the planar layout of the back side of the semiconductor device according to the second embodiment. Figure 7 and Figure 8 Corresponding to the first embodiment Figure 3 and Figure 4 .

[0061] Semiconductor device 1A also includes wirings 35, 44 and 45, through holes 67, 68 and 69, and cooling devices 81, 82 and 83.

[0062] Wiring 44 and 45 are conductors disposed separately on the upper surface of substrate 5. Wiring 44 is configured such that, when semiconductor device 1A is viewed from below, it overlaps with a portion of MOSFET 20A, except for a first region that does not interfere with wiring 41 and terminal 15. Wiring 45 is configured such that, when semiconductor device 1A is viewed from below, it overlaps with a portion of MOSFET 20B, except for a second region that does not interfere with wiring 40 and terminal 16.

[0063] Wiring 35 is a conductor disposed on the lower surface of substrate 5. Wiring 35 is disposed separately from electrodes 33 and 34 between electrodes 33 and 34.

[0064] Through-hole 67 connects the upper surface of wiring 50 to the lower surface of wiring 44. Through-hole 68 connects the upper surface of wiring 50 to the lower surface of wiring 45. Through-hole 69 connects the upper surface of wiring 35 to the lower surface of wiring 50. That is, wirings 35, 44, and 45 are at the same potential as wiring 50. Through-holes 67, 68, and 69 can also be formed by multiple through-holes.

[0065] Cooling devices 81, 82, and 83 are, for example, heat sinks. Cooling device 81 is disposed on the upper surface of wiring 44. Cooling device 82 is disposed on the upper surface of wiring 45. Cooling device 83 is disposed on the lower surface of wiring 35. Cooling devices 81 and 82 are sealed together with optocoupler 10 by sealing material 70.

[0066] Next, use Figure 9 The cross-sectional structure of semiconductor device 1A is described. Figure 9 This is an example of the cross-sectional structure of the semiconductor device according to the second embodiment. Figure 7 and Figure 8 A cross-sectional view of the IX-IX line. Figure 9 Corresponding to the first embodiment Figure 5 .

[0067] like Figure 9 As shown, wiring 35 is provided between electrodes 33 and 34 on the lower surface of insulating layer 71. Furthermore, via 69 extends along the Z direction within insulating layers 71 and 72.

[0068] Wiring 44 and 45 are provided on the upper surface of the insulating layer 73. Furthermore, vias 67 and 68 extend in the Z direction within the insulating layer 73.

[0069] With the structure described above, semiconductor device 1A can release the heat generated by MOSFETs 20A and 20B to cooling device 81 via via 67 and wiring 44, to cooling device 82 via via 68 and wiring 45, and to cooling device 83 via via 69 and wiring 35. This further improves the heat dissipation characteristics of semiconductor device 1A. <Modification of the Second Embodiment>

[0070] Furthermore, the second embodiment described above can be adapted to various variations.

[0071] In the second embodiment described above, the wiring 40, 41, 42, 43, 44 and 45, the cooling devices 81 and 82, and the optocoupler 10 provided on the upper surface of the substrate 5 are sealed with sealing material 70, but this is not a limitation. For example, the wiring 40, 41, 42, 43, 44 and 45, the cooling devices 81 and 82, and the optocoupler 10 provided on the upper surface of the substrate 5 may not be sealed with sealing material 70.

[0072] Figure 10 This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor device according to a first variation of the second embodiment. Figure 10 Corresponding to the second embodiment Figure 9 .

[0073] like Figure 10 As shown, semiconductor device 1A_1 does not include sealing material 70. That is, the upper surface of insulating layer 73 is exposed to the outside without being sealed by sealing material 70. With the above structure, semiconductor device 1A_1 can release the heat generated by MOSFETs 20A and 20B to the outside from cooling devices 81, 82 and 83 without passing through sealing material 70. As a result, the heat dissipation characteristics of semiconductor device 1A can be further improved.

[0074] According to the first variation of the second embodiment, the semiconductor device 1A_1, like the semiconductor device 1A in the second embodiment, can be configured to electrically connect the electrodes 21A of MOSFET 20A and 21B of MOSFET 20B to the terminals 15 of the optocoupler 10 without using wiring with relatively high resistance such as bonding wires. Therefore, the increase in the on-resistance of MOSFETs 20A and 20B can be suppressed. Therefore, the increase in heat generation of the semiconductor device 1 can be suppressed.

[0075] Furthermore, since MOSFETs 20A and 20B are positioned differently in the Z direction from optocoupler 10, they do not physically interfere with each other. Therefore, the semiconductor device 1A_1 can be further miniaturized.

[0076] Furthermore, in the second embodiment and the first variation thereof described above, it was explained that two cooling devices 81 and 82 were respectively provided corresponding to the two MOSFETs 20A and 20B, but this is not a limitation. Alternatively, a cooling device may be provided on the upper surface of the substrate 5 to cover the area that overlaps with both MOSFETs 20A and 20B.

[0077] Figure 11 This is a top view showing an example of the planar layout of the surface of a semiconductor device in a second variation of the second embodiment. Figure 11 Corresponding to the second embodiment Figure 7 .

[0078] like Figure 11 As shown, semiconductor device 1A_2 includes wiring 46 instead of wirings 44 and 45. Additionally, semiconductor device 1A_2 includes cooling device 83 instead of cooling devices 81 and 82.

[0079] When viewed from below, the wiring 46 covers a first region in MOSFET 20A that does not interfere with wiring 41 and terminal 15, a second region in MOSFET 20B that does not interfere with wiring 40 and terminal 16, and a third region connecting the first and second regions. Figure 11 In the example shown, the third region extends along the X direction on the upper surface of the substrate 5 opposite to the wiring 41 and the optocoupler 10, and connects the first region and the second region.

[0080] The cooling device 84 is, for example, a heat sink. The cooling device 84 is disposed on the upper surface of the wiring 46. The cooling device 84 and the optocoupler 10 are sealed together by the sealing material 70. Alternatively, as shown in the first variation of the second embodiment, the cooling device 84 may be exposed on the upper surface of the substrate 5 together with the optocoupler 10.

[0081] According to a second variation of the second embodiment, compared to the case where the cooling device is separately positioned above MOSFET 20A and MOSFET 20B, the area of ​​the cooling device can be increased. This further improves the heat dissipation effect.

[0082] Furthermore, in the second variation of the second embodiment described above, the third region of wiring 46 was arranged to bypass wiring 41, but this is not a limitation. Optocoupler 10 may also be further offset in the Y direction relative to MOSFETs 20A and 20B, so that the third region of wiring 46 is arranged without bypassing wiring 41.

[0083] Figure 12 This is a top view showing an example of the planar layout of the surface of a semiconductor device in a third variation of the second embodiment. Figure 12 In the second variation of the second embodiment Figure 11 .

[0084] like Figure 12 As shown, semiconductor device 1A_3 includes wirings 40a, 46a, 50a, and 51a in place of wirings 40, 46, 50, 51, and 52. Semiconductor device 1A_3 includes vias 60a and 61a in place of vias 60, 61, and 62. Semiconductor device 1A_3 includes a cooling device 84a in place of a cooling device 84.

[0085] When viewed from below, the semiconductor device 1A_3 is offset in the Y direction such that terminals 15 and 16 do not overlap with MOSFETs 20A and 20B.

[0086] Wiring 40a is a conductor provided on the upper surface of the substrate 5. Specifically, for example, wiring 40a corresponds to portion 401 of wiring 40 in the second variation of the second embodiment. That is, terminal 16 is connected to the upper surface of wiring 40a.

[0087] Wiring 50a and 51a are conductors disposed inside the substrate 5. Wiring 50a has, for example, a T-shape. The portion of wiring 50a extending in the X direction corresponds to wiring 50 in the second variation of the second embodiment. The portion of wiring 50a extending in the Y direction has a portion that overlaps with wiring 41 when the semiconductor device 1A_3 is viewed from below. The portion of wiring 50a extending in the Y direction is connected to wiring 41 through a via 60a. Wiring 51a includes a portion extending in the X direction, a portion connected to one end of the portion extending in the X direction and extending in the Y direction, and a portion connected to the other end of the portion extending in the X direction and extending in the Y direction. The portion of wiring 51a extending in the X direction has a portion that overlaps with wiring 40a when the semiconductor device 1A_3 is viewed from below. The portion of wiring 51a extending in the X direction is connected to wiring 40a through a via 61a. In addition, the lower surface of the portion of wiring 51a connected to one end of the portion extending in the X direction and extending in the Y direction is in contact with the upper surface of the electrode 22A of the MOSFET 20A. The lower surface of the portion of wiring 51a that is connected to the other end of the portion extending in the X direction and extends in the Y direction is connected to the upper surface of the electrode 22B of MOSFET 20B.

[0088] Wiring 46a is configured such that, when viewed from below, the semiconductor device 1A_3 covers a first region that does not interfere with MOSFET 20A, a second region that does not interfere with MOSFET 20B, and a third region connecting the first and second regions. Figure 12 In the example shown, the third region connects the portion between MOSFET 20A and MOSFET 20B on the upper surface of substrate 5.

[0089] The cooling device 84a is, for example, a radiator. The cooling device 84a is disposed on the upper surface of the wiring 46a.

[0090] According to a third variation of the second embodiment, the area of ​​the cooling device can be further increased. This further improves the heat dissipation characteristics of the heat generated by MOSFETs 20A and 20B.

[0091] Furthermore, in the third variation of the second embodiment, the case where the third region of the wiring 46 is provided between MOSFETs 20A and 20B has been described, but it is not limited to this. The third region of the wiring 46 may also be provided in all areas of the upper surface of the substrate 5 except for the area where the optocoupler 10 is provided.

[0092] Figure 13 This is a top view showing an example of the planar layout of the surface of a semiconductor device in a fourth variation of the second embodiment. Figure 13 In the third variation corresponding to the second embodiment Figure 12 .

[0093] like Figure 13 As shown, semiconductor device 1A_4 includes wiring 46b instead of wiring 46a. Semiconductor device 1A_4 includes cooling device 84b instead of cooling device 84a.

[0094] When viewing the semiconductor device 1A_4 from below, wiring 46b is arranged across the area on the upper surface of the substrate 5 that does not interfere with the optocoupler 10. Figure 13 In the example shown, wiring 46b is arranged to cover the entire area of ​​the upper surface of substrate 5 in a manner that surrounds optocoupler 10.

[0095] The cooling device 84b is, for example, a radiator. The cooling device 84b is disposed on the upper surface of the wiring 46b.

[0096] According to the fourth variation of the second embodiment, the area of ​​the cooling device can be further increased. This allows for a further increase in the area of ​​the cooling device. Consequently, the heat dissipation characteristics generated from MOSFETs 20A and 20B can be further improved.

[0097] 3. Other

[0098] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor device comprising: substrate; The first transistor and the second transistor are disposed inside the substrate; A first wiring is disposed inside the substrate and is respectively connected to the source electrode of the first transistor and the source electrode of the second transistor; and An optocoupler is disposed on the upper surface of the substrate to control the state of the first transistor and the second transistor.

2. The semiconductor device according to claim 1, wherein, The optical coupler has: The first terminal is electrically connected to the source electrode of the first transistor and the source electrode of the second transistor via the first wiring. as well as The second terminal is electrically connected to the gate electrode of the first transistor and the gate electrode of the second transistor.

3. The semiconductor device according to claim 1, wherein, The first transistor and the second transistor are arranged in a first direction. The spacing between the first transistor and the second transistor in the first direction is shorter than the length of the optocoupler in the first direction.

4. The semiconductor device according to claim 1, wherein, It also has: The second wiring is disposed on the upper surface of the substrate at a position overlapping with the first transistor; The third wiring is disposed on the upper surface of the substrate at a position overlapping with the second transistor; A first through hole is disposed inside the substrate to connect the upper surface of the first wiring and the lower surface of the second wiring. as well as A second through-hole is disposed inside the substrate, connecting the upper surface of the first wiring and the lower surface of the third wiring.

5. The semiconductor device according to claim 4, wherein, It also has: A first cooling device is disposed on the upper surface of the second wiring; and The second cooling device is disposed on the upper surface of the third wiring.

6. The semiconductor device according to claim 5, wherein, It also has: A fourth wiring is disposed continuously on the upper surface of the substrate along with the second and third wirings; as well as A third cooling device is disposed continuously on the upper surface of the fourth wiring device, along with the first and second cooling devices.

7. The semiconductor device according to claim 6, wherein, It also has: The optocoupler has a first terminal that is electrically connected to the source electrode of the first transistor and the source electrode of the second transistor via the first wiring. The semiconductor device also includes: A fifth wiring is disposed on the upper surface of the substrate and connected to the first terminal; and The third through hole connects the first wiring and the fourth wiring.

8. The semiconductor device according to claim 7, wherein, The first terminal and the fifth wiring each have portions sandwiched between the second wiring and the third wiring.

9. The semiconductor device according to claim 7, wherein: The first terminal and the fifth wiring are respectively located on the side of the optocoupler that are closer to the second wiring and the third wiring than the second wiring and the third wiring, respectively.

10. The semiconductor device according to claim 7, wherein, The fourth wiring and the third cooling device are arranged to surround the optocoupler.

11. The semiconductor device according to claim 1, wherein, It also has: A sixth wiring is disposed on the lower surface of the substrate; and A fourth through hole is disposed inside the substrate, connecting the lower surface of the first wiring to the upper surface of the sixth wiring.

12. The semiconductor device according to claim 11, wherein, It also includes a fourth cooling device, which is disposed on the lower surface of the sixth wiring.

13. The semiconductor device according to claim 1, wherein, It also includes a sealing material that covers the optical coupler.

14. The semiconductor device according to claim 1, wherein, The optocoupler is a packaged component.

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