Thermal management method for thyristor module and thyristor module

Abstract

The application discloses a thyristor module with electric-thermal-magnetic synergistic optimization and a thermal management method thereof. The module comprises a thyristor chip with an interdigital cathode structure composed of cathode fingers, a bar-shaped gate and an integrated resistor; a double-sided heat dissipation packaging structure including an upper heat dissipation substrate, a lower heat dissipation substrate, a sintered silver layer and a phase change heat conduction interface layer; an electromagnetic compatibility optimization structure including a built-in buffer network and symmetrically arranged power terminals, so that the power loop parasitic inductance is not more than 8nH. The thermal management method estimates the steady-state junction temperature by collecting the substrate temperature and calculating the conduction loss and switching loss, and detects the reverse recovery charge during the turn-off process to judge the transient junction temperature. When the temperature or charge exceeds the corresponding threshold, the hierarchical protection is executed. Through the three-level electric-thermal-magnetic synergistic optimization of the chip, packaging and system, the comprehensive performance of low on-state voltage drop, low thermal resistance, low parasitic inductance and high power cycle life is improved, and the module is suitable for medium and high power application scenarios such as medium frequency induction heating.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, specifically to a thyristor module with electrothermal-magnetic synergistic optimization, and a thermal management method based thereon. Background Technology

[0002] As the core switching device in medium- and high-power induction heating equipment, the performance of thyristors directly affects the overall efficiency, reliability, and electromagnetic compatibility of the equipment. In medium-frequency (1kHz~10kHz) applications, thyristors face prominent problems such as high conduction losses, high switching stress, voltage spikes caused by parasitic inductance, and hot spot failures caused by multi-physical field coupling.

[0003] Traditional thyristor module design typically addresses electrical, thermal, and electromagnetic issues independently, lacking cross-scale collaborative optimization from chip to package to system. For example, chip pattern design only focuses on current capacity, neglecting current sharing and thermal distribution coupling; package layout only focuses on structural strength, without electromagnetic optimization of power loop area; and thermal management strategies rely on a single temperature sensor, failing to simultaneously protect against steady-state temperature rise and transient thermal shock.

[0004] The consequences of the above discrete design are: high on-state voltage drop of the module, parasitic inductance exceeding 15nH, concentrated hotspots leading to excessive local junction temperature, and power cycle life of less than 5×10⁻⁶. 4 This approach fails to meet the demands of modern induction heating equipment for high reliability, low electromagnetic interference, and long lifespan. Therefore, it is necessary to provide a thyristor module and its thermal management method that achieves synchronous optimization of electrical, thermal, and magnetic properties from three levels: chip doping and patterning, packaging structure and materials, and system control strategy. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a thyristor module with electrothermal-magnetic synergistic optimization and its thermal management method, thereby solving the technical problems of high module loss, poor heat dissipation, strong electromagnetic interference, and lack of multi-parameter synergistic protection in the prior art.

[0006] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention is as follows:

[0007] This invention discloses a thyristor module with electrothermal-magnetic synergistic optimization, comprising:

[0008] The thyristor chip has an interdigitated cathode structure, which includes multiple parallel cathode fingers and strip gates arranged alternately between adjacent cathode fingers (the strip gates are parallel and alternate with the cathode fingers, and the center of the gate is aligned with the center of the gap between the cathode fingers). An integrated resistor is connected in series at the end of each strip gate.

[0009] A double-sided heat dissipation packaging structure includes: a lower heat dissipation substrate, wherein the lower surface of a thyristor chip is fixed to the lower heat dissipation substrate by a sintered silver layer; an upper heat dissipation substrate, disposed above the thyristor chip, and having a phase change thermal interface layer between the upper heat dissipation substrate and the upper surface of the thyristor chip; and a housing, which covers the outside of the upper heat dissipation substrate and is fixed to the lower heat dissipation substrate, wherein a pre-tightening force component is provided between the housing and the upper heat dissipation substrate for applying a set pressure to the upper heat dissipation substrate to control the contact thermal resistance of the phase change thermal interface layer.

[0010] The electromagnetic compatibility optimization structure includes: series resistors and capacitors directly soldered to the lower heat sink substrate to form a built-in buffer network (RC series branch, connected in parallel between the thyristor anode and cathode); symmetrically arranged anode power terminals and cathode power terminals are respectively connected to the lower heat sink substrate, so that the parasitic inductance of the power loop does not exceed 8nH.

[0011] Furthermore, the thyristor chip has a PNPN four-layer structure, including a P1 anode layer from bottom to top, with a surface doping concentration of 1×10⁻⁶. 19 cm -3 A 150 μm thick N1 base layer with a doping concentration of 4 × 10⁻⁶. 14 cm -3 A 800 μm thick P2 gate layer with a surface doping concentration of 2 × 10⁻⁶. 17 cm -3 The cathode layer is 100 μm thick and has an N2 cathode layer with a surface doping concentration of 1 × 10⁻⁶. 19 cm -3 Thickness 50μm.

[0012] Furthermore, the width of the cathode fingers is 0.3 mm, the spacing between adjacent cathode fingers is 0.45 mm, and the total number of interdigitated finger pairs is 120 pairs; the width of the strip gate is 0.2 mm, and the resistance of the integrated resistor is 10 Ω; the interdigitated cathode structure also includes multiple cathode short-circuit points, with a short-circuit point density of 40 points / cm². 2 Each short-circuit point has a diameter of 0.1 mm.

[0013] Furthermore, the lower heat dissipation substrate is a double-sided copper-clad AlN ceramic substrate, and the upper heat dissipation substrate is a single-sided copper-clad AlN ceramic substrate. The copper-clad layer is seamlessly brazed to the AlN ceramic using the AMB process. The phase change thermal interface layer is a 0.2mm thick phase change thermal pad. The preload assembly consists of multiple disc springs, with an applied set pressure of 200N±20N.

[0014] Furthermore, in the built-in buffer network, the capacitor is an NPO material X2Y structure capacitor with a capacitance of 0.1μF, and the resistor is a metal film resistor with a resistance of 10Ω and a power of 2W. The capacitor and resistor are welded to the anode power terminal and the cathode power terminal in close proximity.

[0015] Furthermore, the outer shell is made of oxygen-free copper, forming a fully enclosed electromagnetic shield, with a shielding effectiveness of no less than 45dB in the frequency range of 30MHz to 1GHz.

[0016] Furthermore, it also includes an NTC temperature sensor, which is fixed to the lower heat dissipation substrate near the thyristor chip by thermally conductive adhesive.

[0017] The present invention also provides a thermal management method based on any of the above-mentioned thyristor modules, wherein the thyristor module is executed by an external controller in the following steps:

[0018] Step S1: Real-time acquisition of the resistance value of the NTC temperature sensor, and calculation of the real-time temperature of the lower heat sink. Based on the current conduction current With on-state pressure drop Calculate conduction loss Based on the current off-state voltage , turn off current Shutdown time and operating frequency Calculate switching losses:

[0019]

[0020] Among them, the coefficient 0.5 is the integral coefficient of the triangular waveform of the linear overlap of voltage and current during the turn-off transient process of the thyristor. It is used to accurately characterize the transient loss energy in the switching transition range and is an industry-standard correction coefficient for modeling the switching loss of medium frequency thyristors.

[0021] Calculate total power consumption: Based on the known thermal resistance from the chip to the substrate. Real-time estimation of junction temperature ;

[0022] Step S2, Transient Junction Temperature Detection: During each turn-off process, the reverse recovery charge is obtained by integrating the cathode current. ; to the currently measured With pre-calibrated - Compare the junction temperature relationship to determine whether the current transient junction temperature exceeds the temperature corresponding to the preset charge threshold;

[0023] Step S3, Hierarchical Collaborative Protection: When When the first temperature threshold is exceeded, the thyristor conduction angle is gradually reduced to limit the output power; when Exceeding the second temperature threshold, or When the preset charge threshold is exceeded, the next trigger pulse is immediately blocked, and the control module enters a soft-start recovery process; wherein, the preset charge threshold corresponds to the third temperature threshold. The calibration value, and the third temperature threshold is higher than the second temperature threshold.

[0024] Further, the first temperature threshold is 85°C, the second temperature threshold is 110°C, and the third temperature threshold is 120°C; in step S3, when When the temperature exceeds 85°C, the conduction angle is gradually reduced from the rated value to 90°, resulting in a reduction of approximately 30% in output power; when Above 100°C or When the temperature exceeds 125°C, the module will be forcibly shut down and a fault signal will be output.

[0025] Furthermore, the present invention also provides a method for manufacturing the above-mentioned thyristor module, comprising: connecting the lower surface of the thyristor chip to a lower heat dissipation substrate using a sintering process with sintered silver; directly soldering the resistors and capacitors of the buffer network onto preset copper pads on the lower heat dissipation substrate; attaching a phase change thermal interface layer to the lower surface of an upper heat dissipation substrate, and then covering the upper surface of the thyristor chip with the upper heat dissipation substrate; placing the assembly into a housing, and applying uniform pressure to the upper heat dissipation substrate by adjusting a preload assembly, so that the phase change thermal interface layer is compressed to a target thickness; the magnitude of the preload is determined according to the pressure-thermal resistance characteristic curve of the phase change thermal interface material, so as to simultaneously meet the requirements of thermal resistance and chip stress.

[0026] Beneficial effects:

[0027] The interdigitated cathode and distributed gate structure achieve uniform current distribution across the entire circuit, eliminating localized hotspots and significantly reducing conduction losses. Double-sided AMB ceramic heatsinks, sintered silver low-temperature bonding, and a pressure-controlled phase-change thermal layer enable ultra-low thermal resistance heat dissipation and significantly improved junction temperature control accuracy, making it suitable for high-frequency variable load conditions. Integrated gate damping resistors suppress switching noise, while onboard proximity RC buffer networks and symmetrical power terminal layout keep parasitic inductance below 8nH. A fully enclosed oxygen-free copper shell provides wideband electromagnetic shielding, significantly improving interference suppression capabilities and meeting industrial Class A EMI standards.

[0028] Breaking through the limitations of traditional single temperature measurement, it integrates three criteria: measured substrate temperature, junction temperature estimated by thermal resistance model, and reverse recovery charge degradation detection. It can simultaneously identify steady-state overheating, transient high temperature, and chip aging failure. The graded protection logic takes into account both continuous equipment operation and device safety, and prevents thermal breakdown and sudden failure.

[0029] By precisely controlling the thickness and thermal resistance of the thermal interface with pre-tightening force, the chip doping, structural dimensions, and device parameters are fixed, completely solving the problem of large performance dispersion in batch production of traditional modules, and significantly improving yield and service life.

[0030] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0032] Figure 1 This is a schematic cross-sectional view of the overall structure of the thyristor module of the present invention.

[0033] Figure 2 This is a schematic diagram of the PNPN four-layer vertical structure of the thyristor chip of the present invention.

[0034] Figure 3 This is a top view schematic diagram of the interdigitated cathode structure of the thyristor chip of the present invention.

[0035] Figure 4 This is a partially enlarged view of the double-sided heat dissipation packaging structure and pre-tightening force component of the present invention.

[0036] Figure 5 This is a wiring diagram of the symmetrical layout of the power terminals and the built-in buffer network of the present invention.

[0037] Figure 6 This is a flowchart illustrating the three-level hierarchical collaborative protection in the thermal management method of the present invention.

[0038] In the diagram: 10-thyristor chip; 11-P1 anode layer; 12-N1 base layer; 13-P2 gate layer; 14-N2 cathode layer; 15-cathode finger; 16-bar gate electrode; 17-integrated resistor; 18-cathode short circuit point; 20-lower heat dissipation substrate; 21-sintered silver layer; 30-upper heat dissipation substrate; 31-phase change thermal interface layer; 40-casing; 41-preload assembly (disc spring); 50-built-in buffer network; 51-capacitor; 52-resistor; 61-anode power terminal; 62-cathode power terminal; 70-NTC temperature sensor; A-anode electrode; G-gate electrode; K-cathode electrode. Detailed Implementation

[0039] The following will describe in detail the implementation of the present invention with reference to the accompanying drawings and embodiments, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0040] See Figures 1 to 6This embodiment provides a thyristor module with electrothermal-magnetic synergistic optimization, with a rated current of 600A (RMS) and a forward blocking voltage of 1200V, suitable for 1kHz~10kHz medium-frequency induction heating equipment. The module consists of three main parts: a thyristor chip 10, a double-sided heat dissipation package structure, and an electromagnetic compatibility optimization structure, and achieves synergistic protection of the electric, thermal, and magnetic fields through system-level thermal management methods.

[0041] like Figure 1 and Figure 2 As shown, the thyristor chip 10 has a PNPN four-layer vertical structure, consisting of a P1 anode layer 11, an N1 base layer 12, a P2 gate layer 13, and an N2 cathode layer 14 from bottom to top. The upper part contains the gate electrode G and the cathode electrode K, while the lower part contains the anode electrode A. The P1 anode layer 11 is boron-doped with a surface concentration of 1×10⁻⁶. 19 cm -3 The base layer, 150 μm thick, is used to withstand high electric fields and reduce leakage current during reverse blocking. The N1 base layer 12 is phosphorus-doped at a concentration of 4 × 10⁻⁶. 14 cm -3 The thickness is 800 μm, which is a commonly used parameter determined through electrothermal coupling simulation iterations. This effectively reduces the on-state voltage drop while ensuring a 1200V blocking capability. The P2 gate layer 13 is boron-doped with a surface concentration of 2 × 10⁻⁶. 17 cm -3 The 100 μm thick N2 cathode layer is responsible for establishing the conduction channel under the action of the gate trigger signal. The N2 cathode layer 14 is phosphorus-doped with a surface concentration of 1 × 10⁻⁶. 19 cm -3 With a thickness of 50 μm, its high concentration of doping helps to reduce the contact resistance with the cathode metal and reduce the on-state voltage drop.

[0042] The chip's lateral pattern adopts an interdigitated cathode structure, such as... Figure 3 As shown, the cathode fingers 15 consist of multiple parallel, elongated strip-shaped regions, each 0.3 mm wide, with a spacing of 0.45 mm between adjacent cathode fingers. The entire chip comprises 120 pairs of interdigitated fingers, which shortens the current path by approximately 40% compared to traditional circular structures, reduces on-resistance by approximately 25%, and allows for control of the local current density to 80 A / cm². 2The following effectively avoids localized hot spots caused by current concentration. Between adjacent cathode fingers, strip gates 16, each 0.2 mm wide, are arranged alternately. Each strip gate 16 has an integrated resistor 17 connected in series at its end, with a resistance of 10 Ω. This integrated resistor 17 suppresses current spikes during gate turn-on and, in conjunction with the positive temperature coefficient of silicon in the conductivity modulation region, achieves self-current equalization within the chip: when the resistance of a certain area increases due to temperature rise, the current automatically shifts to the adjacent, lower-temperature interdigitated fingers, thus preventing hot spot formation. Furthermore, multiple cathode short-circuit points 18 are distributed between the cathode fingers 15, with a short-circuit point density of 40 / cm². 2 Each short-circuit point has a diameter of 0.1 mm. These short-circuit points provide extraction channels for excess carriers in the P2 gate layer 13 during the turn-off process, which can effectively suppress dynamic uneven current phenomena and improve the chip's dv / dt tolerance.

[0043] In chip manufacturing processes, high thermal conductivity N-type chips are selected. <100> The single-crystal silicon wafer is 4 inches (approximately 100 mm) in diameter and 1.1 mm thick, with a thermal conductivity of 160 W / m·K. The P1 anode layer 11, P2 gate layer 13, and N2 cathode layer 14 are all formed through ion implantation and high-temperature propulsion diffusion. The back side of the anode uses a Ti / Ni / Au multilayer metal system with a total thickness of 500 nm, while the front side of the cathode and gate uses an Al-Si(1%)-Cu(0.5%) alloy with a thickness of 2 μm. A 1 μm thick Si3N4 / SiO2 composite passivation layer covers the surface to provide good voltage resistance and resistance to damp heat. These material and process choices ensure the long-term reliability of the chip under electrical and thermal stress.

[0044] This embodiment employs a dual-sided cooling architecture, combining sintered silver and phase change thermally conductive materials to achieve highly efficient heat transfer from the chip to the environment. For example... Figure 1 and Figure 4 As shown, the lower heat dissipation substrate 20 is a double-sided copper-clad AlN ceramic substrate, measuring 80mm × 60mm. The AlN ceramic layer is 1mm thick, and the copper layers on both sides are each 0.3mm thick. A gapless connection is achieved between the copper layer and the AlN ceramic layer using an AMB (Active Metal Brazing) process, resulting in a contact thermal resistance of less than 0.05K / W, far superior to traditional welding structures. The lower surface of the thyristor chip 10 is fixed to the central mounting area of ​​the lower heat dissipation substrate 20 via a sintered silver layer 21. The sintered silver layer 21 is approximately 0.05mm thick, has a thermal conductivity as high as 200W / m·K, and a shear strength greater than 30MPa. Formed at a sintering temperature of 250℃, it ensures both low thermal resistance and reliable high-temperature mechanical connection.

[0045] The upper heat dissipation substrate 30 is a single-sided copper-clad AlN ceramic substrate, measuring 70mm × 50mm, with an AlN ceramic thickness of 1mm and a copper cladding layer thickness of 0.3mm. A phase change thermal interface layer 31 is provided between the upper surface of the thyristor chip 10 and the upper heat dissipation substrate 30. This phase change thermal interface layer 31 uses a 0.2mm thick phase change thermal pad (PCM) with a thermal conductivity of 8W / m·K. This material undergoes a phase change at the chip's operating temperature (above approximately 50°C), softening and fully filling the microscopic uneven gaps between the chip and the upper substrate, significantly reducing contact thermal resistance.

[0046] The outer shell 40 is made of oxygen-free copper and nickel-plated, forming a fully enclosed structure. A pre-tightening assembly 41, specifically four disc springs, is provided between the outer shell 40 and the upper heat dissipation substrate 30. The outer shell 40 is fixed to the flange of the lower heat dissipation substrate 20 using M3 stainless steel screws, and the disc springs are uniformly compressed to a compression of 0.5 mm, thereby applying a uniform pressure of 200 N ± 20 N to the upper heat dissipation substrate 30. This pressure is precisely set according to the pressure-thermal resistance characteristic curve of the phase change thermal interface material, enabling the phase change thermal pad to operate within the range of minimum thermal resistance, while controlling the mechanical stress on the chip within a safe range. Through thermo-mechanical coupling simulation verification, the first principal stress of the chip does not exceed 120 MPa, and the maximum equivalent stress at the corner of the sintered silver layer is 82 MPa, both below the material fatigue limit, ensuring no structural damage under more than 500 temperature cycles from -40℃ to 125℃.

[0047] The symmetrical structure of the double-sided heat dissipation allows the heat generated by the chip to be conducted in both the upward and downward directions simultaneously. The total thermal resistance (junction to environment) of the module can be as low as 1.2K / W when matched with a forced air cooling heatsink, which is about 40% lower than that of traditional single-sided cooling modules.

[0048] To achieve the goal of low electromagnetic interference, a coordinated design was implemented from three levels: parasitic inductance suppression, built-in buffer network, and shielding. For example... Figure 5 As shown, anode power terminals 61 and cathode power terminals 62 are symmetrically arranged on the lower heat dissipation substrate 20. Both are M8 bolt-type copper terminals, leading out from the left and right sides of the substrate, respectively. Current enters from the anode power terminal 61, flows through the chip 10, and exits from the cathode power terminal 62. The geometric area of ​​the entire power loop is compressed to 1 cm². 2 Within 8 nH. Through finite element electromagnetic simulation optimization, this symmetrical layout can reduce the parasitic inductance of the power loop to below 8 nH (the measured typical value is 7.8 nH), which significantly reduces turn-off voltage spikes and electromagnetic radiation.

[0049] The built-in buffer network 50 consists of a capacitor 51 and a resistor 52 connected in series, directly soldered onto the copper layer of the lower heat sink 20, and arranged adjacent to the anode and cathode terminals. The capacitor 51 is a 0.1μF NPO material X2Y structure capacitor, which inherently has extremely low equivalent series inductance; the resistor 52 is a 10Ω, 2W metal film resistor. The wiring length of the buffer branch is controlled within 2mm, minimizing the stray inductance of the entire absorption circuit. When the thyristor is turned off, the energy stored in the parasitic inductance can be quickly absorbed by this RC network, effectively suppressing overvoltage oscillations between the anode and cathode.

[0050] The outer casing 40 is a fully enclosed structure made of oxygen-free copper and reliably connected to the circuit ground, providing electromagnetic shielding effectiveness of no less than 45dB in the frequency range of 30MHz to 1GHz, ensuring that the radiated emissions of the module meet the EN 55014 Class A standard. In addition, the gate and control terminals use independent shielded wiring, with a distance of more than 8mm from the power circuit, further avoiding interference from the high-voltage circuit to the low-voltage control signal.

[0051] To monitor the temperature in real time, an NTC temperature sensor 70 (nominal resistance 10kΩ@25℃, B value 3435) is also integrated on the lower heat sink substrate 20 near the chip. It is attached with thermally conductive epoxy resin, and its output signal is provided to an external controller for thermal management.

[0052] The thermal management method in this embodiment is executed by an external controller (such as a DSP or MCU), combining steady-state temperature monitoring and transient junction temperature detection to form a hierarchical collaborative protection strategy. Its logic flow is as follows: Figure 6 As shown.

[0053] Step S1: Steady-state temperature monitoring and junction temperature estimation. The controller acquires the resistance value of the NTC temperature sensor 70 in real time, and obtains the real-time temperature of the lower heat sink through a voltage divider circuit and A / D conversion. At the same time, the controller acquires the current conduction current. With on-state pressure drop (It can be measured online via the sampling circuit or retrieved from pre-stored memory) - - Data table), according to formula Calculate the conduction loss. Based on the current off-state voltage. Turn-off peak current Shutdown time and operating frequency According to the formula

[0054]

[0055] Calculate the switching losses, including the turn-off time. It can be extracted from the gate control signal or the measured current waveform. Total power consumption. Thermal resistance of the chip junction to the substrate The junction temperature is estimated in real time based on a known value (0.38 K / W in this embodiment). .

[0056] Step S2: Transient junction temperature detection. During each shutdown process, the controller uses a current sensor to collect the cathode current and calculates the reverse recovery charge using an integrating circuit or digital integration algorithm. . There is a monotonically increasing relationship between the junction temperature and the temperature; this relationship was obtained through offline calibration and fabricated. - The junction temperature calibration curve is stored in the controller. The controller will store the currently measured... By comparing with the calibration curve, it can be quickly determined whether the transient junction temperature exceeds the preset charge threshold. In this embodiment, the charge threshold corresponds to the calibration value of a junction temperature of 120°C. The response time of this detection method can reach the microsecond level, which is much faster than the thermal time constant of NTC. Specifically, a Hall current sensor is used to sample the cathode current, and the controller digitally integrates at a sampling rate of 1MHz.

[0057] Step S3: Hierarchical Cooperative Protection. The controller, according to... , and Three parameters implement three levels of protection:

[0058] when When the temperature exceeds the first temperature threshold of 85°C, it indicates that the overall temperature rise of the module is too high. The controller will gradually reduce the thyristor conduction angle from the rated value to 90°, so that the output power decreases by about 30%, thereby suppressing the temperature from continuing to rise. This is the first-level protection.

[0059] when When the temperature exceeds the second temperature threshold of 110°C, or When the preset charge threshold is exceeded (corresponding to a transient junction temperature of approximately 120°C), regardless of the NTC temperature, the controller immediately blocks the next trigger pulse, prohibiting the thyristor from conducting, and simultaneously initiates soft-start recovery logic: after a settable cooling waiting time, power output is gradually restored at a lower conduction angle until the temperature drops back to a safe range; this is secondary protection. Preferably, the soft-start process involves a 10-second cooling wait, with the conduction angle increasing from 60° in 5° increments, each increment spaced 1 second apart, until the rated conduction angle is restored.

[0060] when Further rise to above 100°C, or When the estimated value exceeds 125℃ (close to the absolute maximum junction temperature), the controller forcibly shuts down the module and sends a fault signal to the system. Manual intervention or system reset is required before it can be restarted. This is a three-level protection.

[0061] In this embodiment, the priority is: Level 3 forced shutdown > Level 2 blocking pulse > Level 1 power reduction.

[0062] Through the dual protection mechanism combining steady-state temperature monitoring and transient charge detection, the module can cope with the slow temperature rise caused by long-term overload and respond quickly to the instantaneous junction temperature spikes caused by sudden load changes, effectively preventing chip thermal breakdown and increasing the power cycle life to 10. 5 More than once.

[0063] The manufacturing method of the thyristor module in this embodiment includes the following key steps:

[0064] Nano-silver paste was uniformly coated onto the chip mounting area of ​​the lower heat dissipation substrate 20 using screen printing. A thyristor chip 10 was then attached, and the substrate was sintered in a nitrogen-protected sintering furnace at 250°C for 60 minutes to form a sintered silver layer 21. The nitrogen purity was ≥99.999%, the furnace pressure was 0.1 MPa, the heating rate was 5°C / min, the temperature was held at 250°C for 60 minutes, and the substrate was allowed to cool naturally to 80°C before being removed from the furnace.

[0065] Using Sn96Ag4 solder, the capacitor 51 and resistor 52 of the buffer network are soldered onto the preset copper pads of the lower heat sink substrate 20 at 220°C for no more than 5 seconds. Specifically, nitrogen-protected reflow soldering can be used with a peak temperature of 220°C and a soldering time of 3 seconds. The flux used should be halogen-free and no-clean.

[0066] The NTC temperature sensor 70 is attached to the designated position on the lower heat sink substrate 20 using thermally conductive epoxy resin adhesive, and then cured in an 80°C oven for 30 minutes.

[0067] The anode power terminal 61, cathode power terminal 62, and control terminals (gate G and cathode trigger terminal K') are welded to their respective pads using ultrasonic welding.

[0068] The phase change thermal interface layer 31 is attached to the lower surface of the upper heat dissipation substrate 30, and then the upper heat dissipation substrate 30 is placed over the upper surface of the thyristor chip 10 to ensure that the position is aligned.

[0069] Place the above assembly into the outer shell 40, install four disc springs 41, and tighten them evenly with M3 stainless steel screws. Control the compression of the disc springs to 0.5mm through the limiting structure or torque wrench, thereby applying a uniform pressure of 200N±20N to the upper heat dissipation substrate 30.

[0070] Perform module-level electrical characteristic tests (blocking voltage, on-state voltage drop, gate parameters, switching time, etc.) and sampled thermal resistance tests, and ship out after passing the tests.

[0071] In summary, this invention achieves a cross-scale synergistic improvement in the electrical, thermal, and magnetic properties of thyristor modules through chip-level interdigital patterning and doping optimization, package-level double-sided heat dissipation and low-inductance layout, and system-level multi-parameter thermal management. Compared with existing technologies, its on-state voltage drop is reduced to below 1.8V, parasitic inductance does not exceed 8nH, junction temperature is controlled below 123℃, and power cycle life reaches 10... 5 This technology can meet the stringent requirements of medium-frequency induction heating equipment for high reliability and low electromagnetic interference.

[0072] The foregoing description illustrates and describes several preferred embodiments of the present invention. However, as previously stated, it should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the inventive concept described herein through the foregoing teachings or techniques or knowledge in related fields. Any modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A thyristor module with electrothermal-magnetic synergistic optimization, characterized in that, include: A thyristor chip has an interdigitated cathode structure, wherein the interdigitated cathode structure includes a plurality of parallel cathode fingers and strip gates located between adjacent cathode fingers and arranged alternately, and an integrated resistor is connected in series at the end of each strip gate. The double-sided heat dissipation packaging structure includes: The lower heat dissipation substrate is provided, and the lower surface of the thyristor chip is fixed to the lower heat dissipation substrate by a sintered silver layer. An upper heat dissipation substrate is disposed above the thyristor chip, and a phase change thermal interface layer is provided between the substrate and the upper surface of the thyristor chip. The outer shell is covered on the outside of the upper heat dissipation substrate and fixed to the lower heat dissipation substrate. A pre-tightening force component is provided between the outer shell and the upper heat dissipation substrate to apply a set pressure to the upper heat dissipation substrate to control the contact thermal resistance of the phase change thermal interface layer. Electromagnetic compatibility optimized structure, including: The series resistors and capacitors directly soldered onto the lower heat dissipation substrate form a built-in buffer network; The symmetrically arranged anode power terminals and cathode power terminals are respectively connected to the lower heat dissipation substrate, so that the parasitic inductance of the power loop does not exceed 8nH.

2. The thyristor module according to claim 1, characterized in that, The thyristor chip has a PNPN four-layer structure, including, from bottom to top, a P1 anode layer with a surface doping concentration of 1×10⁻⁶. 19 cm -3 A 150 μm thick N1 base layer with a doping concentration of 4 × 10⁻⁶. 14 cm -3 A 800 μm thick P2 gate layer with a surface doping concentration of 2 × 10⁻⁶. 17 cm -3 The cathode layer is 100 μm thick and has an N2 cathode layer with a surface doping concentration of 1 × 10⁻⁶. 19 cm -3 Thickness 50μm.

3. The thyristor module according to claim 1, characterized in that, The width of the cathode fingers is 0.3 mm, the spacing between adjacent cathode fingers is 0.45 mm, and the total number of interdigitated finger pairs is 120 pairs; the width of the strip gate is 0.2 mm, and the resistance of the integrated resistor is 10 Ω; the interdigitated cathode structure also includes multiple cathode short-circuit points, with a short-circuit point density of 40 points / cm². 2 Each short-circuit point has a diameter of 0.1 mm.

4. The thyristor module according to claim 1, characterized in that, The lower heat dissipation substrate is a double-sided copper-clad AlN ceramic substrate, and the upper heat dissipation substrate is a single-sided copper-clad AlN ceramic substrate. The copper-clad layer is seamlessly brazed to the AlN ceramic using the AMB process. The phase change thermal interface layer is a 0.2mm thick phase change thermal pad. The preload assembly consists of multiple disc springs, with an applied set pressure of 200N±20N.

5. The thyristor module according to claim 1, characterized in that, The built-in buffer network is an RC series branch, wherein the capacitor is an NPO material X2Y structure capacitor with a capacitance of 0.1μF, and the resistor is a metal film resistor with a resistance of 10Ω and a power of 2W. The capacitor and resistor are welded adjacent to the anode power terminal and the cathode power terminal.

6. The thyristor module according to claim 1, characterized in that, The outer shell is made of oxygen-free copper, forming a fully enclosed electromagnetic shield, with a shielding effectiveness of no less than 45dB in the frequency range of 30MHz to 1GHz.

7. The thyristor module according to claim 1, characterized in that, It also includes an NTC temperature sensor, which is fixed to the lower heat dissipation substrate near the thyristor chip by thermally conductive adhesive.

8. A thermal management method based on the thyristor module according to any one of claims 1 to 7, characterized in that, include: Step S1: Steady-state temperature monitoring and junction temperature estimation: The resistance value of the NTC temperature sensor is collected in real time, and the real-time temperature of the lower heat sink is calculated. ; Based on the current conduction current With on-state pressure drop Calculate conduction loss ; Based on the current off-state voltage , turn off current Shutdown time and operating frequency Calculate switching losses: Calculate total power consumption ; Based on the known thermal resistance from the chip to the substrate Real-time estimation of junction temperature ; Step S2, Transient junction temperature detection: During each turn-off process, the reverse recovery charge is obtained by integrating the cathode current. ; The current measurement With pre-calibrated - Compare the junction temperature relationship to determine whether the current transient junction temperature exceeds the temperature corresponding to the preset charge threshold; Step S3, Hierarchical Collaborative Protection: when When the first temperature threshold is exceeded, the thyristor conduction angle is gradually reduced to limit the output power; when Exceeding the second temperature threshold, or When the preset charge threshold is exceeded, the next trigger pulse is immediately blocked, and the control module enters the soft-start recovery process. Wherein, the preset charge threshold is the third temperature threshold. The calibration value, and the third temperature threshold is higher than the second temperature threshold.

9. The thermal management method according to claim 8, characterized in that, The first temperature threshold is 85°C, the second temperature threshold is 110°C, and the third temperature threshold is 120°C; In step S3, when When the temperature exceeds 85°C, the conduction angle will be gradually reduced from the rated value to 90°, resulting in a reduction of output power of approximately 30%. when Above 100°C or When the temperature exceeds 125°C, the module will be forcibly shut down and a fault signal will be output.

Images