Semiconductor device

Abstract

The present application relates to a semiconductor device, comprising: a substrate including a chip region; a passivation layer on the substrate; a redistribution insulating layer on the passivation layer; redistribution trenches in the chip region extending through the redistribution insulating layer into the passivation layer and arranged spaced apart from each other along a first direction of an upper surface of the substrate; and a redistribution conductive layer arranged on side surfaces of the redistribution trenches, comprising an upper surface between an upper surface of the redistribution insulating layer and a lower surface of the redistribution trenches.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0035082, filed on March 19, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure generally relate to semiconductor devices, and more specifically to semiconductor devices having alignment keys. Background Technology

[0004] Semiconductor chips have attracted much attention as a crucial component of the electronics industry due to their miniaturization, multifunctionality, and / or low manufacturing cost. With the development of the electronics industry, the integration level of semiconductor chips is also increasing. As integration level increases, chip size gradually decreases, while the number of chips formed on a single wafer continues to increase.

[0005] Semiconductor chips are manufactured on a single wafer and then diced into individual chips using processes such as sawing or dicing. As the integration density of semiconductor chips increases, the difficulty of semiconductor chip dicing also increases. Therefore, new solutions are needed. Summary of the Invention

[0006] Embodiments of this disclosure are intended to provide a semiconductor device in which dicing defects occurring during the dicing process can be minimized.

[0007] The embodiments disclosed herein are not limited to those described herein, and other unmentioned embodiments will be apparent to those skilled in the art from the following description.

[0008] In one embodiment of this disclosure, the semiconductor device may include: a substrate including a chip region; a passivation layer on the substrate; a redistribution insulating layer on the passivation layer; redistribution trenches located in the chip region, extending through the redistribution insulating layer into the passivation layer and spaced apart from each other along a first direction on the upper surface of the substrate; and a redistribution conductive layer disposed on a side surface of the redistribution trenches, and including an upper surface located between the upper surface of the redistribution insulating layer and the lower surface of the redistribution trenches.

[0009] In one embodiment of this disclosure, the semiconductor device may include: a substrate including a chip region; a conductive layer located on the substrate; a passivation layer located on the conductive layer; a redistribution insulating layer located on the passivation layer; a redistribution trench located in the chip region, penetrating the redistribution insulating layer and the passivation layer and overlapping the conductive layer; and a redistribution conductive layer disposed on a side surface of the redistribution trench, the redistribution conductive layer including an upper surface located between an upper surface of the redistribution insulating layer and a lower surface of the redistribution trench.

[0010] In one embodiment of this disclosure, the semiconductor device may include: a conductive layer on a substrate; a passivation layer on the conductive layer; a redistribution insulating layer on the passivation layer; a redistribution trench located in a chip region of the substrate, passing through the redistribution insulating layer and the passivation layer and overlapping with the conductive layer; a redistribution conductive layer disposed on a side surface of the redistribution trench, the redistribution conductive layer including an upper surface located between an upper surface of the redistribution insulating layer and a lower surface of the redistribution trench; and a protective ring disposed in a protective ring region of the substrate, wherein the redistribution trench overlaps with the protective ring, and wherein the protective ring includes a protective conductive layer disposed below the redistribution trench, and at least a portion of the redistribution conductive layer contacts the upper surface of the protective conductive layer.

[0011] According to embodiments of this disclosure, a semiconductor device can be provided in which cutting defects occurring during the cutting process can be minimized.

[0012] The advantages of the embodiments disclosed herein are not limited to those described above, and other advantages will become apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0013] The embodiments of this disclosure will be more fully understood through the following detailed description and accompanying drawings, but these descriptions and drawings are for illustrative purposes only and are not intended to limit the embodiments.

[0014] Figure 1 This is a simplified schematic diagram illustrating the planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 2 yes Figure 1 A magnified view of the alignment key area AR.

[0016] Figure 3 It is shown Figure 2 A simplified schematic diagram of an example of the cross-sectional structure shown by line I-I'.

[0017] Figure 4 It is shown Figure 2 A simplified schematic diagram of the cross-sectional structure of the section shown by line II-II'.

[0018] Figure 5 yes Figure 2 A simplified schematic diagram of another cross-sectional structure of the section shown by line I-I'.

[0019] Figure 6 It is shown Figure 2 A simplified schematic diagram of another cross-sectional structure of the section shown by line II-II'.

[0020] Figure 7 It is shown Figure 2A simplified schematic diagram of another cross-sectional structure of the section shown by line I-I'.

[0021] Figure 8 It is shown Figure 2 A simplified schematic diagram of another cross-sectional structure of the section shown by line II-II'.

[0022] Figure 9 It is shown Figure 2 A simplified schematic diagram of another cross-sectional structure of the section shown by line I-I'.

[0023] Figure 10 It is shown Figure 2 A simplified schematic diagram of another cross-sectional structure of the section shown by line II-II'.

[0024] Figure 11 This is a simplified schematic diagram illustrating the planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0025] Figure 12 yes Figure 11 A magnified view of the alignment key area AR.

[0026] Figure 13 It is shown Figure 12 A simplified schematic diagram of the cross-sectional structure of the section shown by line III-III'.

[0027] Figure 14 It is shown Figure 12 A simplified schematic diagram of the cross-sectional structure of the section shown by line IV-IV'.

[0028] Figure 15 It is shown Figure 12 A simplified schematic diagram of the cross-sectional structure of the section shown by line III-III'.

[0029] Figure 16 It is shown Figure 12 A simplified schematic diagram of the cross-sectional structure of the section shown by line IV-IV'. Detailed Implementation

[0030] The embodiments of this disclosure will be described in detail with reference to the accompanying drawings. The specific structural or functional descriptions provided in the embodiments are merely examples to illustrate the technical concepts disclosed in this disclosure. Examples or embodiments that conform to the technical concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0031] All the crosshairs in the figure represent corresponding or similar areas between the figures, rather than representing the material related to these areas.

[0032] When one element is labeled "connected" or "coupled" to another element, the two elements can be directly connected or coupled, or they can be connected or coupled through an intermediate element between them. When two elements are labeled "directly connected" or "directly coupled," one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.

[0033] When one element is identified as being "above", "below", or "under" another element, these elements may be in direct contact with each other, or an intermediate element may be placed between these elements.

[0034] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “under,” “below,” “upper,” “above,” “side surface,” “above,” “uppermost,” “below,” “lowest,” “front,” “back,” “left,” “right,” “column,” “row,” “layer,” and other terms that suggest relative spatial relationships or directions are used for ease of description or reference to the accompanying drawings and are not intended to be limiting. Within the scope of this disclosure, other spatial relationships or directions not shown in the accompanying drawings or described in the specification may exist.

[0035] Terms such as “first” and “second” are used to distinguish individual elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one embodiment, a first element may be referred to as a second element, while in another embodiment, a second element may be referred to as a first element.

[0036] In the specification, when an element included in an embodiment is described in the singular, the element may be interpreted as including multiple elements that perform the same or similar functions.

[0037] Figure 1 This is a simplified schematic diagram illustrating the planar structure of a semiconductor device according to an embodiment of the present disclosure.

[0038] refer to Figure 1 The semiconductor device according to embodiments of this disclosure may include a chip region CHR and a scribe region SR. The chip region CHR may refer to the region including memory cells and peripheral circuitry constituting a semiconductor chip. The scribe region SR may refer to the region diced when semiconductor chips are fabricated together on a wafer and then diced into individual chips. The scribe region SR may surround the chip region CHR.

[0039] The chip region CHR may include a cell region CR, a peripheral region PR, and a guard ring region GR. The cell region CR may refer to the area where memory cells are located. Memory cells may include, for example, dynamic random access memory (DRAM) cells, static random access memory (SRAM) cells, flash memory cells, magnetoresistive random access memory (MRAM) cells, phase-change random access memory (PRAM) cells, ferroelectric random access memory (FRAM) cells, resistive random access memory (RRAM) cells, or combinations thereof. In one embodiment, the memory cell may include a DRAM cell.

[0040] The peripheral region PR refers to the area where peripheral circuitry is installed to provide various signals and voltages to the memory cells. The peripheral region PR is located around the cell region CR. The peripheral region PR may surround the cell region CR.

[0041] The protection ring region GR refers to the area where a protection ring is disposed. In one embodiment, the protection ring can be used to protect the memory cells included in the cell region CR and the peripheral circuitry included in the peripheral region PR. The protection ring region GR is disposed around the peripheral region PR. The protection ring region GR may surround the peripheral region PR.

[0042] In one embodiment, at least one alignment key region AR may be provided in the peripheral region PR. The alignment key region AR may refer to an area where one or more alignment keys are provided. Alignment keys may refer to patterns used for aligning semiconductor devices during the formation of the semiconductor device.

[0043] Figure 2 yes Figure 1 A magnified view of the alignment key area AR.

[0044] refer to Figure 2 The alignment key region AR can include four redistribution trenches. However, despite Figure 2 The embodiment shows four redistribution trenches, but the number of redistribution trenches is not limited to this. Typically, at least one redistribution trench 200 may be provided in the alignment bond region AR. In one embodiment, the redistribution trench 200 may serve as a feature in the etched redistribution conductive layer 333 (refer to later). Figure 3 The key used to align the etching mask in the process described.

[0045] The redistribution trenches 200 may be spaced apart from each other along the first direction FD. In one embodiment, the width W2 of the redistribution trenches 200 in the first direction FD may be smaller than the width W1 of the redistribution trenches 200 in the second direction SD.

[0046] Figure 3 for Figure 2 A simplified schematic diagram of the cross-sectional structure of the portion shown by line I-I' in the diagram. Figure 4 for Figure 2 A simplified schematic diagram of the cross-sectional structure of the section shown by line II-II' in the diagram.

[0047] refer to Figure 3 and Figure 4 A semiconductor device according to one embodiment of the present disclosure may include a substrate 300, a first insulating layer 301, a first interlayer insulating layer 302, a second insulating layer 303, a second interlayer insulating layer 304, a third insulating layer 305, a third interlayer insulating layer 306, a fourth insulating layer 307, a passivation layer 310, a redistribution insulating layer 320, and a redistribution conductive layer 333. The passivation layer 310 may include a first passivation layer 311 and a second passivation layer 312. The redistribution conductive layer 333 may include a first redistribution conductive layer 331 and a second redistribution conductive layer 332.

[0048] Substrate 300 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Substrate 300 may include a III-V group semiconductor substrate, such as a compound semiconductor substrate like gallium arsenide (GaAs). Substrate 300 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or combinations thereof.

[0049] A first insulating layer 301 is disposed on the substrate 300. The first insulating layer 301 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0050] The first interlayer insulating layer 302 is disposed on the first insulating layer 301. The first interlayer insulating layer 302 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0051] The second insulating layer 303, the second interlayer insulating layer 304, the third insulating layer 305, the third interlayer insulating layer 306, and the fourth insulating layer 307 are sequentially disposed on the first interlayer insulating layer 302. In one embodiment, the second insulating layer 303, the third insulating layer 305, and the fourth insulating layer 307 may comprise the same material as the first insulating layer 301. The second interlayer insulating layer 304 and the third interlayer insulating layer 306 may comprise the same material as the first interlayer insulating layer 302.

[0052] A passivation layer 310 is disposed on the fourth insulating layer 307. A first passivation layer 311 is disposed on the fourth insulating layer 307. In one embodiment, the first passivation layer 311 may comprise high-density plasma (HDP) oxide. A second passivation layer 312 is disposed on the first passivation layer 311. In one embodiment, the second passivation layer 312 may comprise silicon nitride.

[0053] A redistributed insulating layer 320 is disposed on the passivation layer 310. The redistributed insulating layer 320 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0054] The redistribution trench 200 may extend through the redistribution insulating layer 320 into the passivation layer 310. For example, the redistribution trench 200 may extend through the redistribution insulating layer 320 and the second passivation layer 312 into the first passivation layer 311. In one embodiment, the redistribution trench 200 may expose the side and top surfaces of the first passivation layer 311, the side surfaces of the second passivation layer 312, and the side surfaces of the redistribution insulating layer 320. The lower surface 200LS of the redistribution trench 200 may be spaced apart from the lower surface of the first passivation layer 311. In one embodiment, the lower surface 200LS of the redistribution trench 200 may be located between the upper and lower surfaces of the first passivation layer 311. In one embodiment, at least a portion of the first side surfaces 200SS1 of the redistribution trench 200 that face each other in the first direction FD may be exposed.

[0055] A first redistributed conductive layer 331 may be disposed on a first side surface 200SS1 of a redistribution trench 200 that faces each other in a first direction FD. The first redistributed conductive layer 331 may cover the first side surface 200SS1 and the lower surface 200LS of the redistribution trench 200. The side surface of the first redistributed conductive layer 331 may contact the side surface of the redistributed insulating layer 320, the side surface of the second passivation layer 312, and the side surface of the first passivation layer 311. The lower surface of the first redistributed conductive layer 331 may contact the first passivation layer 311. In one embodiment, portions of the first redistributed conductive layer 331 may be spaced apart from each other in a redistribution trench 200. In one embodiment, at least a portion of the upper surface of the first passivation layer 311 may be exposed.

[0056] The upper surface 331US of the first redistributed conductive layer 331 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface 200LS of the redistributed trench 200. In one embodiment, the upper surface 331US of the first redistributed conductive layer 331 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface of the redistributed insulating layer 320. The lower surface of the first redistributed conductive layer 331 may be in direct contact with the lower surface 200LS of the redistributed trench 200.

[0057] The first redistributed conductive layer 331 may include a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polycrystalline silicon, conductive carbon, or a combination thereof. In one embodiment, the first redistributed conductive layer 331 may include aluminum (Al).

[0058] refer to Figure 4A second redistributed conductive layer 332 may be disposed on the second side surfaces 200SS2 of the redistribution trench 200, which face each other in the second direction SD. The second redistributed conductive layer 332 may cover the second side surface 200SS2 and the lower surface 200LS of the redistribution trench 200. The side surfaces of the second redistributed conductive layer 332 may contact the side surfaces of the redistributed insulating layer 320, the second passivation layer 312, and the first passivation layer 311. The lower surface of the second redistributed conductive layer 332 may contact the first passivation layer 311. The upper surface 332US of the second redistributed conductive layer 332 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface 200LS of the redistribution trench 200. In one embodiment, the upper surface 332US of the second redistributed conductive layer 332 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface of the redistributed insulating layer 320. The lower surface of the second redistributed conductive layer 332 can be in direct contact with the lower surface 200LS of the redistribution trench 200.

[0059] In one embodiment, portions of the second redistributed conductive layer 332 may be spaced apart from each other in a redistribution trench 200. In one embodiment, at least a portion of the upper surface of the first passivation layer 311 may be exposed. The second redistributed conductive layer 332 may comprise the same material as the first redistributed conductive layer 331.

[0060] In one embodiment, the process of forming the redistributed conductive layer 333 may include: depositing a conductive material on the upper surface 320US of the redistributed insulating layer 320, the side surfaces 200SS1 and 200SS2 of the redistributed trench 200, and the lower surface 200LS of the redistributed trench 200; depositing an insulating material on the conductive material; and then etching at least a portion of the conductive material and the insulating material. In one embodiment, the insulating material may include an oxide with an etch rate higher than that of the redistributed insulating layer 320. Because of the higher etch rate of the insulating material, at least a portion of the conductive material disposed on the side surfaces 200SS1 and 200SS2 of the redistributed trench 200 can be removed together during the removal of the conductive material and the insulating material located on the upper surface 320US of the redistributed insulating layer 320. Therefore, as Figure 3 and Figure 4 As shown, the upper surface of the redistributed conductive layer 333 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface 200LS of the redistributed trench 200.

[0061] Figure 5 for Figure 2 A simplified schematic diagram of another cross-sectional structure of the portion shown by line I-I' in the diagram. Figure 6 for Figure 2 A simplified schematic diagram of another cross-sectional structure of the portion shown by line II-II' in the diagram.

[0062] refer to Figure 5 and Figure 6 A semiconductor device according to one embodiment of the present disclosure may include a substrate 300, a first insulating layer 301, a first interlayer insulating layer 302, a second insulating layer 303, a second interlayer insulating layer 304, a third insulating layer 305, a third interlayer insulating layer 306, a fourth insulating layer 307, a passivation layer 310, a redistribution insulating layer 320, and a redistribution conductive layer 533. The passivation layer 310 may include a first passivation layer 311 located on the fourth insulating layer 307 and a second passivation layer 312 located on the first passivation layer 311. The redistribution conductive layer 533 may include a first redistribution conductive layer 531 and a second redistribution conductive layer 532.

[0063] Below, omissions and references will be used. Figure 3 and Figure 4 Any description of components that are substantially the same as those included in the semiconductor device.

[0064] refer to Figure 5 A first redistribution conductive layer 531 may be disposed on a first side surface 200SS1 of the redistribution trench 200 facing each other in a first direction FD. The first redistribution conductive layer 531 may cover the first side surface 200SS1 and the lower surface 200LS of the redistribution trench 200. In one embodiment, the first redistribution conductive layer 531 may completely cover the lower surface 200LS of the redistribution trench 200. The side surface of the first redistribution conductive layer 531 may contact the side surface of the redistribution insulating layer 320, the side surface of the second passivation layer 312, and the side surface of the first passivation layer 311. The lower surface of the first redistribution conductive layer 531 may contact the first passivation layer 311. In one embodiment, the first redistribution conductive layer 531 may completely cover the upper surface of the first passivation layer 311 that overlaps with the redistribution trench 200. In one embodiment, the side and upper surfaces of the first passivation layer 311 may not be exposed.

[0065] The upper surface 531US of the first redistributed conductive layer 531 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface 200LS of the redistributed trench 200. In one embodiment, the upper surface 531US of the first redistributed conductive layer 531 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface of the redistributed insulating layer 320. The lower surface of the first redistributed conductive layer 531 may directly contact the lower surface 200LS of the redistributed trench 200.

[0066] refer to Figure 6A second redistribution conductive layer 532 may be disposed on the second side surfaces 200SS2 of the redistribution trench 200 facing each other in the second direction SD. The second redistribution conductive layer 532 may cover the second side surface 200SS2 and the lower surface 200LS of the redistribution trench 200. In one embodiment, the second redistribution conductive layer 532 may completely cover the lower surface 200LS of the redistribution trench 200. The side surfaces of the second redistribution conductive layer 532 may contact the side surfaces of the redistribution insulating layer 320, the second passivation layer 312, and the first passivation layer 311. The lower surface of the second redistribution conductive layer 532 may contact the first passivation layer 311. The upper surface 532US of the second redistribution conductive layer 532 may be located between the upper surface 320US and the lower surface of the redistribution insulating layer 320. In one embodiment, the upper surface 532US of the second redistributed conductive layer 532 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface of the redistributed insulating layer 320. The lower surface of the second redistributed conductive layer 532 may directly contact the lower surface of the redistributed insulating layer 320.

[0067] In one embodiment, the second redistributed conductive layer 532 may completely cover the upper surface of the first passivation layer 311 that overlaps with the redistribution trench 200. In one embodiment, the side and upper surfaces of the first passivation layer 311 may not be exposed. The second redistributed conductive layer 532 may comprise the same material as the first redistributed conductive layer 531.

[0068] Figure 7 for Figure 2 A simplified schematic diagram of another cross-sectional structure of the portion shown by line I-I' in the diagram. Figure 8 for Figure 2 A simplified schematic diagram of another cross-sectional structure of the portion shown by line II-II' in the diagram.

[0069] refer to Figure 7 and Figure 8 A semiconductor device according to one embodiment of this disclosure may include a substrate 300, a first insulating layer 301, a first contact 701, a first conductive layer 702, a first interlayer insulating layer 302, a second insulating layer 303, a second contact 703, a second conductive layer 704, a second interlayer insulating layer 304, a third insulating layer 305, a third contact 705, a third conductive layer 706, a third interlayer insulating layer 306, a fourth insulating layer 307, a fourth contact 707, a fourth conductive layer 708, a passivation layer 310, a redistributed insulating layer 320, and a redistributed conductive layer 333. The passivation layer 310 may include a first passivation layer 311 and a second passivation layer 312. The redistributed conductive layer 333 may include a first redistributed conductive layer 331 and a second redistributed conductive layer 332.

[0070] refer to Figure 7 The first contact 701 can penetrate the first insulating layer 301 and be connected to the substrate 300. The first conductive layer 702 can be connected to the first contact 701. The upper surface of the first conductive layer 702 can form the same or substantially the same plane as the upper surface of the first insulating layer 301.

[0071] The second contact 703 can penetrate the second insulating layer 303 and the first interlayer insulating layer 302 to connect to the first conductive layer 702. The second conductive layer 704 can be connected to the second contact 703; specifically, the lower surface of the second conductive layer 704 can be connected to the upper surface of the second contact 703. The upper surface of the second conductive layer 704 can be coplanar with the upper surface of the second insulating layer 303. That is, the upper surface of the second conductive layer 704 can form the same or substantially the same plane as the upper surface of the second insulating layer 303.

[0072] The third contact 705 can penetrate the third insulating layer 305 and the second interlayer insulating layer 304 to connect to the second conductive layer 704. Specifically, the lower surface of the third contact 705 can be connected to the upper surface of the second conductive layer 704. The third conductive layer 706 can be connected to the third contact 705. Specifically, the lower surface of the third conductive layer 706 can be connected to the upper surface of the third contact 705. The upper surface of the third conductive layer 706 can be coplanar with the upper surface of the third insulating layer 305, that is, the upper surface of the third conductive layer 706 can form the same or substantially the same plane as the upper surface of the third insulating layer 305.

[0073] The fourth contact 707 can penetrate the fourth insulating layer 307 and the third interlayer insulating layer 306 to connect to the third conductive layer 706. Specifically, the lower surface of the fourth contact 707 can connect to the upper surface of the third conductive layer 706. The fourth conductive layer 708 can be connected to the fourth contact 707. Specifically, the lower surface of the fourth conductive layer 708 can connect to the upper surface of the fourth contact 707. The lower surface of the fourth conductive layer 708 can be coplanar with the lower surface of the first passivation layer 311, that is, the lower surface of the fourth conductive layer 708 can form the same or substantially the same plane as the lower surface of the first passivation layer 311.

[0074] The first contact 701, the first conductive layer 702, the second contact 703, the second conductive layer 704, the third contact 705, the third conductive layer 706, the fourth contact 707, and the fourth conductive layer 708 may include conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polycrystalline silicon, conductive carbon, or combinations thereof.

[0075] The first redistributed conductive layer 331 may be connected to the fourth conductive layer 708. The lower surface of the first redistributed conductive layer 331 may contact the upper surface 708US of the fourth conductive layer 708. In one embodiment, portions of the first redistributed conductive layer 331 may be spaced apart from each other in a redistribution trench 200. In one embodiment, at least a portion of the upper surface 708US of the fourth conductive layer 708 may be exposed.

[0076] The upper surface 331US of the first redistributed conductive layer 331 may be located between the upper surface 320US of the redistributed insulating layer 320 and the upper surface 708US of the fourth conductive layer 708. In one embodiment, the upper surface 331US of the first redistributed conductive layer 331 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface of the redistributed insulating layer 320.

[0077] refer to Figure 8 In one embodiment, the second redistributed conductive layer 332 may not be connected to the fourth conductive layer 708. The lower surface of the second redistributed conductive layer 332 may contact the first passivation layer 311. However, embodiments of this disclosure are not limited thereto; in some embodiments, the lower surface of the second redistributed conductive layer 332 may contact the upper surface 708US of the fourth conductive layer 708. In one embodiment, portions of the second redistributed conductive layer 332 may be spaced apart from each other in a redistribution trench 200. Figure 8 In the illustrated embodiment, the entire upper surface 708US of the fourth conductive layer 708 is exposed by the redistribution trench 200. However, the embodiment is not limited thereto; in another embodiment or a variation thereof, at least a portion of the upper surface 708US of the fourth conductive layer 708 may be exposed.

[0078] The upper surface 332US of the second redistributed conductive layer 332 may be closer to the upper surface 708US of the fourth conductive layer 708 than the upper surface 320US of the redistributed insulating layer 320. The upper surface 332US of the second redistributed conductive layer 332 may be located between the upper surface 320US of the redistributed insulating layer 320 and the upper surface 708US of the fourth conductive layer 708. In one embodiment, the upper surface 332US of the second redistributed conductive layer 332 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface of the redistributed insulating layer 320.

[0079] Figure 9 It is shown Figure 2 A simplified schematic diagram of another cross-sectional structure of the section shown by line I-I'.

[0080] Figure 10 It is shown Figure 2 A simplified schematic diagram of another cross-sectional structure of the section shown by line II-II'.

[0081] refer to Figure 9 and Figure 10 A semiconductor device according to one embodiment of the present disclosure may include a substrate 300, a first insulating layer 301, a first contact 701, a first conductive layer 702, a first interlayer insulating layer 302, a second insulating layer 303, a second contact 703, a second conductive layer 704, a second interlayer insulating layer 304, a third insulating layer 305, a third contact 705, a third conductive layer 706, a third interlayer insulating layer 306, a fourth insulating layer 307, a fourth contact 707, a fourth conductive layer 708, a passivation layer 310, a redistribution insulating layer 320, and a redistribution conductive layer 533. The passivation layer 310 may include a first passivation layer 311 located on the fourth insulating layer 307 and a second passivation layer 312 located on the first passivation layer. The redistribution conductive layer 533 may include a first redistribution conductive layer 531 and a second redistribution conductive layer 532.

[0082] Below, omissions and references will be used. Figure 7 and Figure 8 Any description of components that are substantially the same as those included in the semiconductor device.

[0083] refer to Figure 9 In one embodiment, the first redistributed conductive layer 531 may completely cover the lower surface of the redistribution trench 200. The side surfaces of the first redistributed conductive layer 531 may contact the side surfaces of the redistributed insulating layer 320, the second passivation layer 312, and the first passivation layer 311. The lower surface of the first redistributed conductive layer 531 may contact the fourth conductive layer 708, specifically, the upper surface 708US of the fourth conductive layer 708. In one embodiment, the upper surface 708US of the fourth conductive layer 708 may not be exposed.

[0084] The upper surface 531US of the first redistributed conductive layer 531 may be located between the upper surface 320US of the redistributed insulating layer 320 and the upper surface 708US of the fourth conductive layer 708. In one embodiment, the upper surface 531US of the first redistributed conductive layer 531 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface of the redistributed insulating layer 320.

[0085] refer to Figure 10 In one embodiment, the second redistributed conductive layer 532 may completely cover the lower surface of the redistribution trench 200. The side surfaces of the second redistributed conductive layer 532 may contact the side surfaces of the redistributed insulating layer 320, the second passivation layer 312, and the first passivation layer 311. The lower surface of the second redistributed conductive layer 532 may contact the fourth conductive layer 708.

[0086] The upper surface 532US of the second redistributed conductive layer 532 may be located between the upper surface 320US of the redistributed insulating layer 320 and the upper surface 708US of the fourth conductive layer 708. In one embodiment, the upper surface 532US of the second redistributed conductive layer 532 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface of the redistributed insulating layer 320.

[0087] Figure 11 This is a simplified schematic diagram illustrating the planar structure of a semiconductor device according to an embodiment of the present disclosure. Figure 12 for Figure 11 A magnified view of the alignment key area AR in the image.

[0088] refer to Figure 11 and Figure 12 The alignment key region AR can be set within the guard ring region GR. However, the location of the alignment key region AR is not limited to this. For example, the alignment key region AR can be set to overlap with the outer region PR and the guard ring region GR. Alternatively, the alignment key region AR can be set to overlap with the guard ring region GR and the scribing region SR.

[0089] refer to Figure 12 The redistribution trench 200 may overlap with the guard ring GDR. The guard ring GDR may extend along the first direction FD. In one embodiment, the redistribution trench 200 may be configured to intersect with the guard ring GDR.

[0090] Figure 13 To show Figure 12 A simplified schematic diagram of the cross-sectional structure of the section shown by line III-III'. Figure 14 To show Figure 12 A simplified schematic diagram of the cross-sectional structure of the section shown by line IV-IV'.

[0091] refer to Figure 13 and Figure 14 A semiconductor device according to one embodiment of the present disclosure may include a substrate 300, a first insulating layer 301, a first interlayer insulating layer 302, a second insulating layer 303, a second interlayer insulating layer 304, a third insulating layer 305, a third interlayer insulating layer 306, a fourth insulating layer 307, a passivation layer 310, a redistribution insulating layer 320, and a redistribution conductive layer 333. The passivation layer 310 may include a first passivation layer 311 and a second passivation layer 312. The redistribution conductive layer 333 may include a first redistribution conductive layer 331, a second redistribution conductive layer 332, and a guard ring GDR.

[0092] The protective ring GDR may include a first protective contact 1301, a first protective conductive layer 1302, a second protective contact 1303, a second protective conductive layer 1304, a third protective contact 1305, a third protective conductive layer 1306, a fourth protective contact 1307, and a fourth protective conductive layer 1308.

[0093] The first protective contact 1301 can penetrate the first insulating layer 301 and connect to the substrate 300. The first protective conductive layer 1302 can be connected to the first protective contact 1301. The upper surface of the first protective conductive layer 1302 can form the same or substantially the same plane as the upper surface of the first insulating layer 301. The first protective contact 1301 and the first protective conductive layer 1302 can respectively connect to the above-mentioned reference... Figure 7 The first contact 701 and the first conductive layer 702 described are disposed on the same layer.

[0094] The second protective contact 1303 can penetrate the second insulating layer 303 and the first interlayer insulating layer 302 to connect to the first protective conductive layer 1302. The second protective conductive layer 1304 can be connected to the second protective contact 1303. The upper surface of the second protective conductive layer 1304 can form the same or substantially the same plane as the upper surface of the second insulating layer 303. The second protective contact 1303 and the second protective conductive layer 1304 can respectively connect to the aforementioned reference... Figure 7 The second contact 703 and the second conductive layer 704 described herein are disposed on the same layer.

[0095] The third protective contact 1305 can penetrate the third insulating layer 305 and the second interlayer insulating layer 304 to connect to the second protective conductive layer 1304. The third protective conductive layer 1306 can be connected to the third protective contact 1305. The upper surface of the third protective conductive layer 1306 can form the same or substantially the same plane as the upper surface of the third insulating layer 305. The third protective contact 1305 and the third protective conductive layer 1306 can be respectively connected to the above-mentioned reference. Figure 7 The third contact 705 and the third conductive layer 706 are disposed on the same layer.

[0096] The fourth protective contact 1307 can penetrate the fourth insulating layer 307 and the third interlayer insulating layer 306 to connect to the third protective conductive layer 1306. The fourth protective conductive layer 1308 can be connected to the third protective contact 1307. The lower surface of the fourth protective conductive layer 1308 can form the same or substantially the same plane as the lower surface of the first passivation layer 311.

[0097] The first protective contact 1301, the first protective conductive layer 1302, the second protective contact 1303, the second protective conductive layer 1304, the third protective contact 1305, the third protective conductive layer 1306, the fourth protective contact 1307, and the fourth protective conductive layer 1308 may include conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polycrystalline silicon, conductive carbon, or combinations thereof.

[0098] refer to Figure 13 The first redistributed conductive layer 331 may be connected to the fourth protective conductive layer 1308. The lower surface of the first redistributed conductive layer 331 may contact the upper surface 1308US of the fourth protective conductive layer 1308. In one embodiment, portions of the first redistributed conductive layer 331 may be spaced apart from each other in a redistribution trench 200. In one embodiment, at least a portion of the upper surface 1308US of the fourth protective conductive layer 1308 may be exposed.

[0099] The upper surface 331US of the first redistributed conductive layer 331 may be located between the upper surface 320US of the redistributed insulating layer 320 and the upper surface 1308US of the fourth protective conductive layer 1308.

[0100] refer to Figure 14 In one embodiment, the second redistributed conductive layer 332 may not be connected to the fourth protective conductive layer 1308. The lower surface of the second redistributed conductive layer 332 may contact the first passivation layer 311. However, embodiments of this disclosure are not limited thereto; in some embodiments, the lower surface of the second redistributed conductive layer 332 may contact the upper surface 1308US of the fourth protective conductive layer 1308. In one embodiment, portions of the second redistributed conductive layer 332 may be spaced apart from each other in a redistribution trench 200. In one embodiment, at least a portion of the upper surface 1308US of the fourth protective conductive layer 1308 may be exposed.

[0101] The upper surface 332US of the second redistributed conductive layer 332 may be located between the upper surface 320US of the redistributed insulating layer 320 and the upper surface 1308US of the fourth protective conductive layer 1308.

[0102] Figure 15 for Figure 12 A simplified schematic diagram of another cross-sectional structure of the portion shown by line III-III' in the diagram. Figure 16 for Figure 12 A simplified schematic diagram of another cross-sectional structure of the section shown by line IV-IV' in the diagram.

[0103] refer to Figure 15 and Figure 16A semiconductor device according to one embodiment of the present disclosure may include a substrate 300, a first insulating layer 301, a first interlayer insulating layer 302, a second insulating layer 303, a second interlayer insulating layer 304, a third insulating layer 305, a third interlayer insulating layer 306, a fourth insulating layer 307, a passivation layer 310, a redistribution insulating layer 320, and a redistribution conductive layer 533. The passivation layer 310 may include a first passivation layer 311 and a second passivation layer 312. The redistribution conductive layer 533 may include a first redistribution conductive layer 531, a second redistribution conductive layer 532, and a guard ring GDR.

[0104] The protective ring GDR may include a first protective contact 1301, a first protective conductive layer 1302, a second protective contact 1303, a second protective conductive layer 1304, a third protective contact 1305, a third protective conductive layer 1306, a fourth protective contact 1307, and a fourth protective conductive layer 1308.

[0105] refer to Figure 15 In one embodiment, the first redistributed conductive layer 531 may completely cover the lower surface of the redistribution trench 200. The side surfaces of the first redistributed conductive layer 531 may contact the side surfaces of the redistribution insulating layer 320, the second passivation layer 312, and the first passivation layer 311. The lower surface of the first redistributed conductive layer 531 may contact the fourth protective conductive layer 1308. In one embodiment, the upper surface 1308US of the fourth protective conductive layer 1308 may not be exposed.

[0106] The upper surface 531US of the first redistributed conductive layer 531 may be located between the upper surface 320US of the redistributed insulating layer 320 and the upper surface 1308US of the fourth protective conductive layer 1308. In one embodiment, the upper surface 531US of the first redistributed conductive layer 531 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface of the redistributed insulating layer 320.

[0107] refer to Figure 16 In one embodiment, the second redistributed conductive layer 532 may completely cover the lower surface of the redistribution trench 200. The side surfaces of the second redistributed conductive layer 532 may contact the side surfaces of the redistributed insulating layer 320, the second passivation layer 312, and the first passivation layer 311. The lower surface of the second redistributed conductive layer 532 may contact the fourth protective conductive layer 1308.

[0108] The upper surface 532US of the second redistributed conductive layer 532 may be located between the upper surface 320US of the redistributed insulating layer 320 and the upper surface 1308US of the fourth protective conductive layer 1308. In one embodiment, the upper surface 532US of the second redistributed conductive layer 532 may be located between the upper surface 320US of the redistributed insulating layer 320 and the lower surface of the redistributed insulating layer 320.

[0109] Refer again Figure 1 and Figure 11 The redistribution trench 200 may be located in the chip region CHR. The redistribution trench 200 may be located in the peripheral region PR or the guard ring region GR. The redistribution trench 200 may serve as a bond for aligning the etch mask during the etching of the redistribution conductive layer 333.

[0110] According to embodiments of this disclosure, since the redistribution trench 200 is not provided in the scribe region SR, dicing defects that occur due to the dicing lines passing through the redistribution trench 200 can be minimized when performing a process of dicing a wafer to divide a semiconductor chip.

[0111] While this disclosure has described detailed embodiments, those skilled in the art will understand that various modifications, additions, and substitutions can be made to these embodiments without departing from the scope and technical concept of this disclosure. Therefore, the scope of this disclosure should not be limited to the foregoing embodiments. All variations within the equivalent meaning and scope of the claims are included within its scope. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: Substrate, which includes the chip region; A passivation layer is located on the substrate; A redistributed insulating layer is disposed on the passivation layer; Redistribution trenches are located in the chip region, extend through the redistribution insulating layer into the passivation layer, and are spaced apart from each other in a first direction on the upper surface of the substrate; as well as A redistributable conductive layer is disposed on the side surface of the redistribution trench and includes an upper surface located between the upper surface of the redistribution insulating layer and the lower surface of the redistribution trench.

2. The semiconductor device according to claim 1, wherein: The chip region includes a cell region and a peripheral region surrounding the cell region, and The redistribution trench is located in the peripheral area.

3. The semiconductor device according to claim 1, wherein, The width of the redistribution trench in the first direction is less than the width of the redistribution trench in the second direction intersecting the first direction.

4. The semiconductor device according to claim 1, wherein, The redistributed conductive layers are spaced apart from each other.

5. The semiconductor device according to claim 1, wherein, The redistributed conductive layer completely covers the lower surface of the redistributed trench.

6. The semiconductor device according to claim 1, further comprising: A conductive layer is disposed beneath the redistribution trench. The redistributed conductive layer is in contact with the upper surface of the conductive layer.

7. The semiconductor device according to claim 1, in, The chip region includes a cell region, a peripheral region surrounding the cell region, and a protective ring region surrounding the peripheral region. The semiconductor device further includes a protective ring disposed in the protective ring region, and The redistribution trench overlaps with the protective ring.

8. The semiconductor device according to claim 7, wherein, The protective ring includes a protective conductive layer disposed below the redistribution trench, and at least a portion of the redistribution conductive layer is in contact with the upper surface of the protective conductive layer.

9. The semiconductor device according to claim 8, wherein: The redistributed conductive layer includes: a first redistributed conductive layer and a second redistributed conductive layer, wherein the first redistributed conductive layer is located on a first side surface of the redistribution trench facing each other in the first direction, and the second redistributed conductive layer is located on a second side surface of the redistribution trench facing each other in a second direction intersecting the first direction; and The first redistributed conductive layer is in contact with the upper surface of the protective conductive layer.

10. The semiconductor device according to claim 8, wherein: The redistributed conductive layer includes: a first redistributed conductive layer and a second redistributed conductive layer, wherein the first redistributed conductive layer is located on a first side surface of the redistribution trench facing each other in the first direction, and the second redistributed conductive layer is located on a second side surface of the redistribution trench facing each other in a second direction intersecting the first direction; and The second redistributed conductive layer is spaced apart from the protective conductive layer.

11. A semiconductor device, comprising: Substrate, which includes the chip region; A conductive layer on the substrate; A passivation layer is disposed on the conductive layer; A redistributed insulating layer is disposed on the passivation layer; A redistribution trench located in the chip region, penetrating the redistribution insulating layer and the passivation layer and overlapping the conductive layer; A redistributable conductive layer is disposed on the side surface of the redistribution trench and includes an upper surface located between the upper surface of the redistribution insulating layer and the lower surface of the redistribution trench.

12. The semiconductor device according to claim 11, wherein, The width of the redistribution trench in a first direction on the upper surface of the substrate is smaller than the width of the redistribution trench in a second direction intersecting the first direction.

13. The semiconductor device according to claim 11, wherein, The redistributed conductive layers are spaced apart from each other.

14. The semiconductor device according to claim 11, wherein, The redistributed conductive layer contacts the upper surface of the conductive layer.

15. The semiconductor device according to claim 11, in, The chip region includes a cell region, a peripheral region surrounding the cell region, and a protective ring region surrounding the peripheral region. The semiconductor device further includes a protective ring disposed in the protective ring region, and The redistribution trench overlaps with the protective ring.

16. The semiconductor device according to claim 15, wherein, The protective ring includes a protective conductive layer disposed below the redistribution trench, and at least a portion of the redistribution conductive layer is in contact with the upper surface of the protective conductive layer.

17. The semiconductor device according to claim 16, wherein, The protective conductive layer and the conductive layer are disposed on the same layer.

18. The semiconductor device according to claim 16, wherein: The redistributed conductive layer includes: a first redistributed conductive layer and a second redistributed conductive layer, wherein the first redistributed conductive layer is located on a first side surface of the redistribution trench facing each other in a first direction on the upper surface of the substrate, and the second redistributed conductive layer is located on a second side surface of the redistribution trench facing each other in a second direction intersecting the first direction. The first redistributed conductive layer is in contact with the upper surface of the protective conductive layer.

19. The semiconductor device according to claim 16, wherein: The redistributed conductive layer includes: a first redistributed conductive layer and a second redistributed conductive layer, wherein the first redistributed conductive layer is located on a first side surface of the redistribution trench facing each other in a first direction on the upper surface of the substrate, and the second redistributed conductive layer is located on a second side surface of the redistribution trench facing each other in a second direction intersecting the first direction. The second redistributed conductive layer is spaced apart from the protective conductive layer.

20. A semiconductor device, comprising: A conductive layer, which is on the substrate; A passivation layer is disposed on the conductive layer; A redistributed insulating layer is disposed on the passivation layer; A redistribution trench located in the chip region of the substrate, passing through the redistribution insulating layer and the passivation layer and overlapping the conductive layer; A redistributed conductive layer is disposed on the side surface of the redistribution trench, the redistributed conductive layer including an upper surface located between the upper surface of the redistribution insulating layer and the lower surface of the redistribution trench, and A protective ring is disposed in the protective ring region of the substrate. Wherein, the redistribution trench overlaps with the protective ring, and The protective ring includes a protective conductive layer disposed below the redistribution trench, and at least a portion of the redistribution conductive layer contacts the upper surface of the protective conductive layer.

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