Metrology mark structure

Abstract

This application relates to a measurement mark structure. The measurement mark structure is placed directly within the functional area, making the actual environment around the mark consistent with the internal circuit environment of the chip, thereby eliminating measurement deviations caused by differences in pattern density, film stress, etc. Since the pattern densities of the first sub-marker and the second sub-marker are different, by setting sub-markers of different densities in the same mark structure, the pattern density environment of different regions inside the chip can be simulated, making the measurement results more reflective of the actual circuit overlay situation. At the same time, at least one first sub-marker includes at least two of overlay patterns, isolated patterns, and dense patterns, and at least one second sub-marker includes at least two of overlay patterns, isolated patterns, and dense patterns. In this way, a single measurement mark structure can simultaneously realize overlay measurement and critical dimension measurement without the need to set different types of measurement patterns, saving chip area.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a measurement mark structure. Background Technology

[0002] In semiconductor manufacturing processes, overlay accuracy is measured to determine the positional deviation of the current layer pattern relative to the previous layer pattern. Overlay accuracy is a key parameter affecting chip yield and performance. As the feature size of integrated circuits continues to shrink, the requirements for overlay accuracy are becoming increasingly stringent.

[0003] Currently, overlay marks used to measure overlay deviations are typically placed within the dicing channels of the wafer. However, the pattern density, film layer stacking, and stress environment of the dicing channel region differ significantly from those of the functional areas inside the chip. Therefore, the overlay error measured from the dicing channels cannot accurately reflect the actual overlay deviations between transistor layers inside the chip. Summary of the Invention

[0004] Therefore, it is necessary to provide a measurement mark structure to address the problems in the existing technology.

[0005] To achieve the above objectives, this application provides a measurement mark structure, comprising:

[0006] The substrate includes functional areas and diced areas;

[0007] At least one first sub-marker is located in the functional area;

[0008] At least one second sub-marker is located in the functional area, the second sub-marker is located above or below the first sub-marker, and the projection of at least one second sub-marker on the substrate at least partially overlaps with the projection of at least one first sub-marker on the substrate;

[0009] The first sub-marker and the second sub-marker have different pattern densities; the first sub-marker includes at least two of the following: overprinted pattern, isolated pattern, and dense pattern; the second sub-marker includes at least two of the following: overprinted pattern, isolated pattern, and dense pattern.

[0010] In one embodiment, the first sub-marker is located on a first conductive layer, and the second sub-marker is located on a second conductive layer. The first conductive layer is a first metal layer, and the second conductive layer is a second metal layer or a via layer.

[0011] In one embodiment, it further includes:

[0012] At least one third sub-marker is located in the functional area, above the second sub-marker; the projections of at least one first sub-marker, at least one second sub-marker, and at least one third sub-marker on the substrate at least partially overlap.

[0013] The third sub-marker includes at least two of the following: overprinted patterns, isolated patterns, and dense patterns.

[0014] In one embodiment, the first sub-marker is located in a first metal layer, the second sub-marker is located in a second metal layer, and the third sub-marker is located in a via layer.

[0015] In one embodiment, a plurality of the measurement mark structures are distributed in a plurality of the functional areas corresponding to the photolithography exposure unit.

[0016] In one embodiment, the measurement mark structure includes at least one of the following marks: dense overprint marks, isolated marks of the first metal layer, isolated marks of the second metal layer, isolated marks of the first via layer, overprint marks of the first via layer and the first metal layer, overprint marks of the first via layer and the second metal layer, and positioning marks.

[0017] In one embodiment, at least one first sub-marker includes a plurality of first bar patterns and a plurality of first block patterns; at least one second sub-marker includes a plurality of second bar patterns and a plurality of second block patterns; and the third sub-marker includes a plurality of third block patterns.

[0018] In the central region of the measurement mark structure, a plurality of first strip patterns extend along a first direction and are spaced apart along a second direction, and a plurality of second strip patterns extend along the second direction and are spaced apart along the first direction. The projections of the first strip patterns and the second strip patterns on the substrate at least partially overlap, and the third block pattern is disposed in the overlapping area of ​​the first strip patterns and the second strip patterns, constituting the dense overlay mark.

[0019] In one embodiment, among the plurality of first strip patterns, at least one first strip pattern has a length greater than the length of the other first strip patterns, and the extended portion of at least one first strip pattern serves as an isolated marker of the first metal layer;

[0020] In the plurality of second strip patterns, at least one second strip pattern has a length greater than the length of the other second strip patterns, and the extended portion of at least one second strip pattern serves as an isolated marker of the second metal layer;

[0021] At least one of the third block-shaped patterns is distributed around the periphery of the central region, forming isolated markers of the first through-hole layer.

[0022] In one embodiment, the overlay marks between the first via layer and the first metal layer, and the overlay marks between the first via layer and the second metal layer, are located around the central region;

[0023] The overlay markings between the first through-hole layer and the first metal layer include the first block pattern and the third block pattern superimposed on the first block pattern;

[0024] The overlay markings of the first through-hole layer and the second metal layer include the second block pattern and the third block pattern superimposed on the second block pattern.

[0025] In one embodiment, the positioning marker is located around the central region;

[0026] At least one first block pattern, at least one second block pattern, and at least one third block pattern are stacked in a direction perpendicular to the substrate to form an L-shaped positioning mark.

[0027] The measurement mark structure of this application has the following unexpected effects: the measurement mark structure is placed directly within the functional area, making the actual environment around the mark consistent with the internal circuit environment of the chip, thereby eliminating measurement deviations caused by differences in pattern density, film stress, etc.; since the pattern densities of the first sub-mark and the second sub-mark are different, by setting sub-marks of different densities in the same mark structure, the pattern density environment of different areas inside the chip can be simulated, making the measurement results more reflective of the actual circuit overlay situation; at the same time, at least one first sub-mark includes at least two of overlay patterns, isolated patterns, and dense patterns, and at least one second sub-mark includes at least two of overlay patterns, isolated patterns, and dense patterns. In this way, a measurement mark structure can simultaneously realize overlay measurement and critical dimension measurement without setting different types of measurement patterns, saving chip area. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a planar schematic diagram of the measurement mark structure provided in one embodiment;

[0030] Figure 2 This is a schematic diagram illustrating the overlay error of the overlay marks between the first via layer and the first metal layer in one embodiment.

[0031] Figure 3 This is a schematic diagram illustrating the overlay error of the overlay marks between the first via layer and the second metal layer in one embodiment.

[0032] Figure 4 This is a schematic diagram illustrating the overlay error of a densely overlaid mark in one embodiment.

[0033] Explanation of reference numerals in the attached figures:

[0034] 10. First sub-marker; 10a. First bar pattern; 10b. First block pattern; 10c. First isolated bar pattern; 20. Second sub-marker; 20a. Second bar pattern; 20b. Second block pattern; 20c. Second isolated bar pattern; 30. Third sub-marker; 30a. Third block pattern; A1. Central area; A2. Peripheral area; OVL dense 1. Dense overlay markings; ISO1: Isolated markings of the first metal layer; ISO2: Isolated markings of the second metal layer; ISO3: Isolated markings of the first via layer; OVL 1V1U Overlay marks between the first via layer and the first metal layer; OVL 1V2U 1. Overlap marks between the first through-hole layer and the second metal layer; ad, positioning mark; X, first direction; Y, second direction. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] Currently, overlay marks used to measure overlay misalignment are typically placed within the dicing channels of the wafer. However, the pattern density, film layer stacking, and stress environment of the dicing channel region differ significantly from those of the functional areas inside the chip. Factors such as the micro-load effect of chemical mechanical polishing, the etching load effect, and thermal stress can cause inconsistencies between the pattern displacement within the dicing channel and the chip's interior. Therefore, overlay readings obtained from the dicing channels cannot accurately reflect the actual overlay misalignment between transistor layers within the chip.

[0038] For overlay markings between via layers and metal layers, traditional designs lack corresponding metal trenches below the via pattern as a front-layer target, resulting in incorrect pattern transfer to the wafer after photolithography. After photoresist removal, overlay readings cannot be obtained using optical metrology equipment. Furthermore, because the front-layer and current-layer patterns do not overlap spatially, physical slices cannot simultaneously capture both patterns on the same cross-section, making it impossible to confirm the true overlay deviation through destructive methods or establish a correlation between optical readings and physical true values.

[0039] Furthermore, the dicing marks are only distributed around the perimeter of the chip, making it impossible to achieve a uniform distribution within the lithography exposure unit. The high-order inter-field and intra-field compensation models of the lithography machine require sufficient and uniformly distributed sampling points for accurate fitting. The sparse distribution of the dicing mark markers leads to insufficient sampling density, especially in the field edge regions, resulting in poor high-order compensation and affecting overall overlay accuracy.

[0040] In traditional designs, measurement patterns used to monitor critical dimensions of via layers can only be placed within the dicing channel. This limited channel space results in a small number of measurement patterns and insufficient sample representativeness. This affects the accuracy of optical proximity correction modeling and mask calibration during mask manufacturing, ultimately impacting the uniformity of critical dimensions on the wafer.

[0041] According to an exemplary embodiment, this embodiment provides a measurement mark structure, referring to... Figure 1 The measurement marker structure includes a substrate, at least one first sub-marker 10, and at least one second sub-marker 20.

[0042] The substrate includes functional regions and scribe lines; the functional regions are the areas inside the chip used to form integrated circuit devices, and the scribe lines are the scribing areas between chips. At least one first sub-marker 10 and at least one second sub-marker 20 are both located in the functional regions, and the second sub-marker 20 is located above or below the first sub-marker 10, that is, the first sub-marker 10 and the second sub-marker 20 are located in different conductive layers.

[0043] Viewed from a direction perpendicular to the substrate, the projection of at least one second sub-marker 20 onto the substrate at least partially overlaps with the projection of at least one first sub-marker 10 onto the substrate. During physical slicing analysis, the patterns of the first sub-marker 10 and the second sub-marker 20 can be simultaneously captured within the same cross-section, allowing direct observation and measurement of the actual physical offset between the two layers. The pattern densities of the first sub-marker 10 and the second sub-marker 20 are different. At least one first sub-marker 10 includes at least two of the following: overlay patterns, isolated patterns, and dense patterns. At least one second sub-marker 20 includes at least two of the following: overlay patterns, isolated patterns, and dense patterns. Overlay patterns are used to measure the relative positional deviation between upper and lower layers; isolated patterns and dense patterns are used to simulate the patterning environment of sparse and dense regions within the chip, respectively, and can also be used simultaneously for critical dimension measurement.

[0044] The aforementioned measurement mark structure is placed directly within the functional area, ensuring that the actual environment around the mark is consistent with the internal circuit environment of the chip, thereby eliminating measurement deviations caused by differences in pattern density, film stress, etc. Since the pattern densities of the first sub-marker 10 and the second sub-marker 20 are different, by setting sub-markers of different densities in the same mark structure, the pattern density environment of different regions inside the chip can be simulated, making the measurement results more reflective of the actual circuit overlay situation. At the same time, at least one first sub-marker 10 includes at least two of overlay patterns, isolated patterns, and dense patterns, and at least one second sub-marker 20 includes at least two of overlay patterns, isolated patterns, and dense patterns. Thus, a single measurement mark structure can simultaneously achieve overlay measurement and critical dimension measurement without the need to set different types of measurement patterns, saving chip area.

[0045] In some embodiments, refer to Figure 1 The first sub-marker 10 is located in the first conductive layer, and the second sub-marker 20 is located in the second conductive layer. The first conductive layer is a first metal layer, and the second conductive layer is a second metal layer or a via layer.

[0046] When the second conductive layer is a second metal layer, the first sub-marker 10 and the second sub-marker 20 together form an overlay mark between the first and second metal layers, used to measure the overlay deviation between the two metal layers. When the second conductive layer is a via layer, the first sub-marker 10 and the second sub-marker 20 together form an overlay mark between the first metal layer and the via layer, used to measure the overlay deviation of the via layer relative to the underlying first metal layer. Because the measurement mark structure is located in the functional area, regardless of whether the second conductive layer is a metal layer or a via layer, the optical measurement device can clearly identify the relative position of the upper and lower patterns and accurately obtain the overlay reading. At the same time, because the upper and lower patterns overlap in the projection direction, the physical slice can simultaneously capture the two patterns on the same cross-section, thereby establishing a correlation between the optical reading and the physical true value.

[0047] In some embodiments, refer to Figure 1 The second conductive layer is a second metal layer. The first sub-marker 10 and the second sub-marker 20 together form an overlay mark between the first metal layer and the second metal layer, which is used to measure the overlay deviation between the two metal layers. At least one of the first sub-marker 10 or the second sub-marker 20 also includes at least one of an isolated pattern or a dense pattern. The isolated pattern is used to simulate the graphic environment of the sparse area inside the chip, and the dense pattern is used to simulate the graphic environment of the high-density wiring area inside the chip, so that the measurement mark structure can also be used for the measurement and monitoring of critical dimensions.

[0048] In some embodiments, refer to Figure 1 The second conductive layer is a via layer. The first sub-marker 10 and the second sub-marker 20 together form the overlay markings between the first metal layer and the via layer. At least one of the first sub-marker 10 or the second sub-marker 20 further includes at least one of isolated markings or dense markings. Isolated markings are used to simulate the pattern environment of sparse areas inside the chip, while dense markings are used to simulate the pattern environment of high-density wiring areas inside the chip. Below the second sub-marker 20 of the via layer is a corresponding first sub-marker 10 of the first metal layer, ensuring that the pattern can be correctly transferred to the wafer surface after photolithography. After removing the photoresist, the relative position between the via pattern and the underlying metal pattern can be identified using optical measurement equipment, accurately obtaining the overlay readings.

[0049] Similarly, at least one of the first sub-marker 10 or the second sub-marker 20 also includes isolated marks and dense marks to enable critical dimension measurements.

[0050] In some embodiments, refer to Figure 1 The measurement mark structure also includes at least one third sub-marker 30, which is located in the functional area and above or below the second sub-marker 20; along the direction perpendicular to the substrate, the projections of at least one first sub-marker 10, at least one second sub-marker 20 and at least one third sub-marker 30 on the substrate at least partially overlap, so that the physical slice can simultaneously capture the three-layer pattern of the first sub-marker 10, the second sub-marker 20 and the third sub-marker 30 on the same cross-section.

[0051] In some embodiments, refer to Figure 1 The first sub-marker 10 is located in the first metal layer, the second sub-marker 20 is located in the second metal layer, and the third sub-marker 30 is located in the via layer. The first sub-marker 10, the second sub-marker 20, and the third sub-marker 30 together form the overlay markings for the first metal layer, the second metal layer, and the via layer. This allows the via layer to simultaneously establish an overlay relationship with both the first and second metal layers, meeting the complex overlay measurement requirements of connecting multiple metal layers in advanced processes.

[0052] In some embodiments, the first sub-marker 10 further includes at least one of a first dense pattern, a first isolated pattern, or a first positioning pattern; the second sub-marker 20 further includes at least one of a second dense pattern, a second isolated pattern, or a second positioning pattern; and the third sub-marker 30 includes at least one of a third dense pattern, a third isolated pattern, or a third positioning pattern.

[0053] Further, the first sub-marker 10 includes at least two of a first dense pattern, a first isolated pattern, and a first positioning pattern. The second sub-marker 20 includes at least two of a second dense pattern, a second isolated pattern, and a second positioning pattern. The third sub-marker 30 includes at least two of a third dense pattern, a third isolated pattern, and a third positioning pattern.

[0054] Furthermore, the first sub-marker 10 simultaneously includes a first dense pattern, a first isolated pattern, and a first positioning pattern. The second sub-marker 20 simultaneously includes a second dense pattern, a second isolated pattern, and a second positioning pattern. The third sub-marker 30 simultaneously includes a third dense pattern, a third isolated pattern, and a third positioning pattern.

[0055] In some embodiments, overlay patterns are used to measure the relative positional deviation between upper and lower layers, dense patterns are used to simulate high-density wiring areas inside the chip, isolated patterns are used to simulate sparse areas, and positioning patterns are used to provide positional references for measurement equipment. Overlay patterns, isolated patterns, and dense patterns can be implemented using strip patterns and / or block patterns and / or combinations of strip patterns and block patterns.

[0056] In some embodiments, refer to Figure 1 The measurement marking structure includes at least one of the following markings: dense overlay markings (OVL). dense The isolated markings for the first metal layer (ISO1), the second metal layer (ISO2), the first via layer (ISO3), and the overlay markings between the first via layer and the first metal layer (OVL) are also present. 1V1U OVL markings between the first via layer and the second metal layer 1V2U Positioning markers (ad). By integrating the above-mentioned multiple markers into the same measurement marker structure, multi-layer overlay measurement, critical dimension measurement and positioning in multi-density environments can be realized simultaneously, without the need to set different types of measurement patterns in the functional area, effectively saving chip area.

[0057] In some embodiments, refer to Figure 1At least one first sub-marker 10 includes multiple first strip patterns 10a and multiple first block patterns 10b; at least one second sub-marker 20 includes multiple second strip patterns 20a and multiple second block patterns 20b; and a third sub-marker 30 includes multiple third block patterns 30a. The strip patterns are elongated strip-shaped graphics extending in one direction, used to form overlay gratings or positioning reference lines; the block patterns are rectangular or square island-shaped graphics, used to simulate the graphic environment of through-holes or isolated metal blocks. The graphic dimensions of both the strip patterns and the block patterns are formed according to the minimum design rules of the photolithography process, making the entire mark structure compact and occupying a small area.

[0058] Reference Figure 1 In the central region A1 of the measurement mark structure, multiple first strip patterns 10a extend along a first direction X and are spaced apart along a second direction Y, and multiple second strip patterns 20a extend along the second direction Y and are spaced apart along the first direction X. The extension directions of the first strip patterns 10a and the second strip patterns 20a are different, for example, they are perpendicular to each other, so that overlay deviation information along the first direction X and the second direction Y can be obtained respectively during measurement. The projections of the first strip patterns 10a and the second strip patterns 20a onto the substrate at least partially overlap, and a third block pattern 30a is disposed in the overlapping area of ​​the first strip patterns 10a and the second strip patterns 20a, forming a dense overlay mark OVL. dense .

[0059] In this way, the via pattern can establish an overlay relationship with the underlying first and second metal layers in the dense pattern area. The central region A1 is used to test the overlay accuracy under the dense lithography pattern environment. Because dense patterns are prone to distortion caused by optical proximity effect and process scaling effect in the lithography process, this dense overlay mark OVL... dense It can detect alignment deviations between layers under these conditions.

[0060] In some embodiments, refer to Figure 1 Among the plurality of first stripe patterns 10a, at least one first stripe pattern 10a has a length greater than the lengths of the other first stripe patterns 10a, and the extended portion of the at least one first stripe pattern 10a serves as an isolated mark ISO1 for the first metal layer. Among the plurality of second stripe patterns 20a, at least one second stripe pattern 20a has a length greater than the lengths of the other second stripe patterns 20a, and the extended portion of the at least one second stripe pattern 20a serves as an isolated mark ISO2 for the second metal layer. This results in the same stripe pattern forming a dense overlay mark OVL in the central region A1. dense The extended portion also serves as an isolated marker, further saving marker area.

[0061] Reference Figure 1At least one third block pattern 30a is distributed around the central region A1, forming an isolated marker ISO3 for the first via layer. This is used to simulate the patterning environment of the first via layer in a sparse region inside the chip and can be used for measuring the critical dimensions of the first via layer. Below the isolated marker ISO3 of the first via layer, there is also an isolated first block pattern 10b or a second block pattern 20b, providing physical support for at least one third block pattern 30a. This ensures that the pattern can be completely transferred to the wafer surface during photolithography and etching processes. The support pattern does not participate in measurement and is only used as a structural substrate.

[0062] In some embodiments, refer to Figure 1 OVL markings for the first via layer and the first metal layer 1V1U OVL markings between the first via layer and the second metal layer 1V2U Located around the central region A1; the overlay mark OVL between the first via layer and the first metal layer. 1V1U Includes a first block pattern 10b and a third block pattern 30a stacked on the first block pattern 10b; and an overlay mark OVL between the first via layer and the second metal layer. 1V2U It includes a second block pattern 20b and a third block pattern 30a superimposed on the second block pattern 20b.

[0063] In this embodiment, the overlay mark OVL is used between the first via layer and the first metal layer. 1V1U Below, an isolated second strip pattern 20c is also provided as a measurement substrate. The second isolated strip pattern 20c extends along the second direction Y, providing physical support for the upper first block pattern 10b and third block pattern 30a, ensuring that the pattern can be completely transferred to the wafer surface during photolithography and etching processes. The second isolated strip pattern 20c does not participate in the optical measurement of overlay deviations, but is only used as a substrate.

[0064] Reference Figure 1 OVL markings for the first via layer and the second metal layer 1V2U Below, an isolated first isolated strip pattern 10c is also provided as a measurement substrate. The first isolated strip pattern 10c extends along the first direction X and does not participate in the optical measurement of overlay deviation; it is only used as a substrate.

[0065] Thus, the overlay mark OVL between the first via layer and the first metal layer is formed. 1V1U OVL markings between the first via layer and the second metal layer 1V2U Set around the central region A1, and working in conjunction with the dense overlay markers OVLdense in the central region A1 and the isolated markers around it, it can simultaneously acquire multi-layer overlay data under different pattern density environments in a single measurement.

[0066] In some embodiments, refer to Figure 1 The positioning mark ad is located around the central region A1; at least one first block pattern 10b, at least one second block pattern 20b and at least one third block pattern 30a are stacked in a direction perpendicular to the substrate to form an L-shaped positioning mark ad.

[0067] The lithography machine uses positioning markers (ADs) to identify the position on the wafer, providing a coordinate reference for measurement equipment. Integrating the positioning markers (ADs) into the same measurement marker structure eliminates the need for separate positioning markers within the functional area, further saving chip area.

[0068] In some embodiments, refer to Figure 1 In the central region A1 of the measurement mark structure, the length of the middle first bar pattern 10a of the plurality of first bar patterns 10a is greater than the length of the other first bar patterns 10a, and along the first direction X, both ends of the middle first bar pattern 10a extend outward relative to the other first bar patterns 10a. Similarly, the length of the middle second bar pattern 20a of the plurality of second bar patterns 20a is greater than the length of the other second bar patterns 20a, and along the second direction Y, both ends of the middle second bar pattern 20a extend outward relative to the other second bar patterns 20a. The middle first bar pattern 10a and the middle second bar pattern 20a intersect in a cross shape, dividing the measurement mark structure into four peripheral regions A2 located around the central region.

[0069] Among them, one end of the extended end of the first strip pattern 10a in the middle serves as the isolated mark ISO1 of the first metal layer, and one end of the extended end of the second strip pattern 20a in the middle serves as the isolated mark ISO2 of the second metal layer.

[0070] The isolated marker ISO3 for the first via layer, and the overlay marker OVL for the first via layer and the first metal layer. 1V1U OVL markings between the first via layer and the second metal layer 1V2U And the positioning marker ad, which are set in the four peripheral areas A2 respectively.

[0071] Furthermore, referring to Figure 1 On the extended end of the second strip pattern 20a in the middle, a plurality of first block patterns 10b are arranged side by side along the first direction X. Each first block pattern 10b is stacked with a third block pattern 30a, forming multiple overlay marks OVL between the first through-hole layer and the first metal layer. 1V1U On the extended end of the first strip pattern 10a in the middle, a plurality of second block patterns 20b are arranged side by side along the second direction Y. Each second block pattern 20b is stacked with a third block pattern 30a, forming multiple overlay marks OVL between the first through-hole layer and the second metal layer. 1V2UThe side-by-side arrangement of multiple overlay marks increases the number of sampling points for overlay measurement, which can improve the reliability of measurement results and reduce the impact of random errors of a single mark on the accuracy of overlay compensation.

[0072] In this embodiment, the measurement mark structure is divided into a central region A1 and four peripheral regions A2 by extending the central first strip pattern 10a and the central second strip pattern 20a through a cross intersection. The central region A1 contains densely packed overlay marks OVL. dense Different types of isolated markers, interlayer overlay markers, and positioning markers ad are placed in the four peripheral areas A2, which facilitates the measurement equipment to quickly locate and identify different types of markers, thus improving measurement efficiency.

[0073] In some embodiments, multiple measurement marker structures are distributed in multiple functional areas corresponding to the photolithography exposure unit.

[0074] A photolithography exposure unit refers to the entire area covered by a single exposure of a photolithography machine. It typically includes functional areas of multiple chips and dicing zones between them. In this embodiment, the measurement marker structure is not located solely within the functional area of ​​a single chip, but rather distributed across the functional areas of multiple different chips within the exposure unit.

[0075] In this embodiment, the graphic size of the measurement marker structure is formed according to the minimum design rules of the photolithography process. Each measurement marker structure occupies a small area, thus allowing multiple measurement marker structures to be evenly placed in multiple functional areas within the photolithography exposure unit. Multiple measurement marker structures cover both the central region A1 and the edge regions of the entire exposure field, avoiding the problem of sparse and unevenly distributed sampling points caused by placing measurement marker structures only in the dicing path.

[0076] In this embodiment, the measurement mark structures placed in each functional area include at least two of the following: overlay marks, isolated marks, and dense marks. This allows the mark structures distributed in various locations to be used for both overlay measurement and critical dimension measurement, thereby simultaneously acquiring overlay deviation distribution and critical dimension distribution data across the entire exposure field in a single measurement process. Since multiple measurement mark structures can be set within the exposure unit, the number of sampling points for critical dimension measurement is increased, which is beneficial for improving the accuracy of optical proximity effect correction and mask calibration during mask manufacturing, ultimately improving the uniformity of critical dimensions on the wafer.

[0077] In some embodiments, the measurement marker structure can be generated and placed in the chip layout using an automated generation script. The automated generation script follows a preset rule file, which includes the spacing, number, and distribution position of sub-markers. The parameters in the rule file can be adjusted according to the needs of different products, and the script can automatically generate a marker array that meets the requirements, significantly shortening the layout design cycle and ensuring the consistency and accuracy of the marker layout.

[0078] According to an exemplary embodiment, this embodiment provides a measurement method, which performs measurements based on the measurement mark structure of the above embodiment. Multiple measurement mark structures are uniformly distributed in the functional area of ​​the substrate. The measurement method includes steps S101-S102.

[0079] Step S101: Obtain the relative positional deviation between at least one first sub-marker 10 and at least one second sub-marker 20, and / or obtain the relative positional deviation between at least one third sub-marker 30 and at least one first sub-marker 10 and at least one second sub-marker 20.

[0080] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, the first sub-marker 10, the second sub-marker 20, and the third sub-marker 30 in the measurement mark structure are located in different conductive layers. The relative positional deviation between each sub-marker reflects the overlay accuracy of the current layer process relative to the previous layer process.

[0081] Step S102: Perform overlay compensation on the lithography machine based on the relative position deviation.

[0082] After obtaining the relative positional deviation, the deviation data is fed back to the lithography machine's control system. The control system then uses the deviation data, combined with a preset compensation model, to calculate the compensation amount for each area within the exposure unit and adjust the exposure position of subsequent batches accordingly to correct overlay deviations and improve the overlay accuracy of subsequent products.

[0083] Since the measurement mark structure in this embodiment is evenly distributed in multiple functional areas within the lithography exposure unit, the lithography machine control system can obtain sufficient and evenly distributed sampling data throughout the exposure field, making the compensation calculation more accurate.

[0084] In some embodiments, the measurement method further includes: measuring the critical dimensions of at least one first sub-marker 10 and / or at least one second sub-marker 20 and / or at least one third sub-marker 30 using isolated or dense patterns in the measurement mark structure, and compensating for the mask fabrication process or photolithography process based on the deviation of the critical dimensions. Thus, overlay deviation data and critical dimension deviation data can be obtained simultaneously in a single measurement process, optimizing the process and improving yield.

[0085] In some embodiments, refer to Figure 2 Step S101: Obtain the overlay mark OVL between the first via layer and the first metal layer. 1V1U The relative position deviation includes: measuring a first distance *a* between the third block pattern 30a and the same side edge of the first block pattern 10b along the first side edge along the first direction *X*, measuring a second distance *b* between the third block pattern 30a and the same side edge of the first block pattern 10b along the second side edge, and using half the difference between the first distance *a* and the second distance *b* as the first offset *x* along the first direction *X*. In this embodiment, the formula for calculating the first offset *x* is expressed as: *x* = (ab) / 2.

[0086] Along the second direction Y, the third distance c between the third block pattern 30a and the same-side edge of the first block pattern 10b along the third side edge is measured, and the fourth distance d between the first block pattern 10b and the same-side edge of the first block pattern 10b along the fourth side edge is measured. Half of the difference between the third distance c and the fourth distance d is taken as the second offset y along the second direction Y. In this embodiment, the formula for calculating the second offset y is expressed as: y = (cd) / 2.

[0087] In some embodiments, refer to Figure 3 Step S101: Obtain the overlay mark OVL between the first via layer and the second metal layer. 1V2U When the relative position deviation is such that the first block pattern 10b in the above formula is replaced with the second sub-marker 20, the offset calculation method is similar to that in the above embodiment, and will not be repeated here.

[0088] In some embodiments, refer to Figure 4 Step S101: Obtain the dense overlay mark OVL dense The relative positional deviation includes: along the first direction X, the measurement of the densely overlaid markings OVL dense The first distance a between the third block pattern 30a and the same side edge of the second strip pattern 20a along the first side edge is measured, and the second distance b between the third block pattern 30a and the same side edge of the second strip pattern 20a along the second side edge is measured. Half of the difference between the first distance a and the second distance b is taken as the first offset x along the first direction X.

[0089] Along the first direction X, measure the dense overlay mark OVL dense The third distance c between the third block pattern 30a and the same side edge of the first strip pattern 10a along its third side edge is measured. The fourth distance d between the third block pattern 30a and the same side edge of the first strip pattern 10a along its fourth side edge is measured. Half of the difference between the third distance c and the fourth distance d is taken as the second offset y along the second direction Y. The offset calculation method is similar to that in the above embodiment and will not be repeated.

[0090] The measurement mark structure of this application has the following unexpected effects: the measurement mark structure is placed directly within the functional area, making the actual environment around the mark consistent with the internal circuit environment of the chip, thereby eliminating measurement deviations caused by differences in pattern density, film stress, etc.; since the pattern densities of the first sub-marker 10 and the second sub-marker 20 are different, by setting sub-markers of different densities in the same mark structure, the pattern density environment of different areas inside the chip can be simulated, making the measurement results more reflective of the actual circuit overlay situation; at the same time, at least one first sub-marker 10 includes at least two of overlay patterns, isolated patterns, and dense patterns, and at least one second sub-marker 20 includes at least two of overlay patterns, isolated patterns, and dense patterns. In this way, a measurement mark structure can simultaneously realize overlay measurement and critical dimension measurement without setting different types of measurement patterns, saving chip area.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A measurement mark structure, characterized in that, include: The substrate includes functional areas and diced areas; At least one first sub-marker is located in the functional area; At least one second sub-marker is located in the functional area, the second sub-marker is located above or below the first sub-marker, and the projection of at least one second sub-marker on the substrate at least partially overlaps with the projection of at least one first sub-marker on the substrate; The first sub-marker and the second sub-marker have different pattern densities; the first sub-marker includes at least two of the following: overprinted pattern, isolated pattern, and dense pattern; the second sub-marker includes at least two of the following: overprinted pattern, isolated pattern, and dense pattern.

2. The measurement mark structure according to claim 1, characterized in that, The first sub-marker is located on the first conductive layer, and the second sub-marker is located on the second conductive layer. The first conductive layer is a first metal layer, and the second conductive layer is a second metal layer or a via layer.

3. The measurement mark structure according to claim 1 or 2, characterized in that, Also includes: At least one third sub-marker is located in the functional area, above the second sub-marker; At least one first sub-marker, at least one second sub-marker, and at least one third sub-marker have projections on the substrate that at least partially overlap. The third sub-marker includes at least two of the following: overprinted patterns, isolated patterns, and dense patterns.

4. The measurement mark structure according to claim 3, characterized in that, The first sub-marker is located in the first metal layer, the second sub-marker is located in the second metal layer, and the third sub-marker is located in the via layer.

5. The measurement mark structure according to claim 1, characterized in that, Multiple measurement mark structures are distributed in multiple functional areas corresponding to the photolithography exposure unit.

6. The measurement mark structure according to claim 4, characterized in that, The measurement mark structure includes at least one of the following marks: dense overprint mark, isolated mark of the first metal layer, isolated mark of the second metal layer, isolated mark of the first through-hole layer, overprint mark of the first through-hole layer and the first metal layer, overprint mark of the first through-hole layer and the second metal layer, and positioning mark.

7. The measurement mark structure according to claim 6, characterized in that, At least one first sub-marker includes a plurality of first bar patterns and a plurality of first block patterns; at least one second sub-marker includes a plurality of second bar patterns and a plurality of second block patterns; the third sub-marker includes a plurality of third block patterns; In the central region of the measurement mark structure, a plurality of first strip patterns extend along a first direction and are spaced apart along a second direction, and a plurality of second strip patterns extend along the second direction and are spaced apart along the first direction. The projections of the first strip patterns and the second strip patterns on the substrate at least partially overlap, and the third block pattern is disposed in the overlapping area of ​​the first strip patterns and the second strip patterns, constituting the dense overlay mark.

8. The measurement mark structure according to claim 7, characterized in that, In the plurality of the first strip patterns, at least one of the first strip patterns has a length greater than the length of the other first strip patterns, and the extended portion of at least one of the first strip patterns serves as an isolated marker of the first metal layer; In the plurality of second strip patterns, at least one second strip pattern has a length greater than the length of the other second strip patterns, and the extended portion of at least one second strip pattern serves as an isolated marker of the second metal layer; At least one of the third block-shaped patterns is distributed around the periphery of the central region, forming isolated markers of the first through-hole layer.

9. The measurement mark structure according to claim 7, characterized in that, The overlay marks between the first through-hole layer and the first metal layer, and the overlay marks between the first through-hole layer and the second metal layer are located around the central region; The overlay markings between the first through-hole layer and the first metal layer include the first block pattern and the third block pattern superimposed on the first block pattern; The overlay markings of the first through-hole layer and the second metal layer include the second block pattern and the third block pattern superimposed on the second block pattern.

10. The measurement mark structure according to claim 7, characterized in that, The positioning markers are located around the central area; At least one first block pattern, at least one second block pattern, and at least one third block pattern are stacked in a direction perpendicular to the substrate to form an L-shaped positioning mark.

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