Packaging structure and packaging method

Abstract

This application provides a packaging structure and packaging method, relating to the field of semiconductor packaging technology. The packaging structure includes: a substrate, a first chip, and a second chip. The substrate has a first side and a second side facing each other, with a recessed portion on the first side. A circuit is disposed inside the substrate, with a first connection port located on the first side and a second connection port located on the second side, for connection to an external module. The first chip is disposed on the first side and electrically connected to the first connection port. The second chip is disposed in the recessed portion and stacked with the first chip via a hybrid bonding layer. This application solves the problems of high signal delay, low process yield, and high manufacturing cost caused by using TSV technology for three-dimensional stacked interconnection in related technologies, achieving a TSV-free, low interconnect delay, high signal integrity, and low-cost three-dimensional stacked packaging structure and method.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging structure and packaging method. Background Technology

[0002] System-in-package (SiP) integrates multiple chips in a three-dimensional stack, which can increase computing power density and shorten inter-chip interconnect latency without relying on process miniaturization, thus meeting the needs of consumer electronics and automotive electronics for miniaturization, high bandwidth and low power consumption.

[0003] In related technologies, three-dimensional stacked packaging typically uses TSV (Through-Silicon Via) combined with microbumps to achieve vertical interconnection between chips. That is, through holes are made on the silicon substrate and filled with metal, and then combined with bump bonding to form an electrical path.

[0004] However, the TSV process has systemic defects: its fabrication process involves multiple complex steps such as deep hole etching, insulating / barrier layer deposition and electroplating filling, with a narrow process window, which easily leads to filling voids, stress concentration and interface delamination, resulting in low yield; at the same time, the parasitic capacitance and resistance introduced by TSV will increase signal delay and power consumption, affecting the integrity of high-frequency signals. Summary of the Invention

[0005] This application provides a packaging structure and packaging method to solve the problems of high signal delay, low process yield and high manufacturing cost caused by the use of TSV process for three-dimensional stacked interconnection in related technologies, and realize a three-dimensional stacked packaging structure and method with no TSV, low interconnect delay, high signal integrity and low cost.

[0006] In a first aspect, embodiments of this application provide a packaging structure, including: a substrate, a first chip, and a second chip. The substrate has a first side and a second side opposite to each other, and a recess is provided on the first side. A circuit is provided inside the substrate, with a first connection port of the circuit located on the first side and a second connection port of the circuit located on the second side. The two connection ports are used to connect to an external module. The first chip is disposed on the first side and electrically connected to the first connection port. The second chip is disposed in the recess and is stacked with the first chip through a hybrid bonding layer.

[0007] In one possible implementation, the first chip is inverted on the first side; the central region of the first chip is electrically connected to the second chip, and the edge region of the first chip is electrically connected to the substrate.

[0008] In one possible implementation, the first chip is electrically connected to the first connection port via a controllable collapse chip connection bump.

[0009] In one possible implementation, the recess is a fitting groove, and the inner wall of the fitting groove is provided with a heat-conducting layer and / or an electromagnetic shielding layer; when the inner wall of the fitting groove is provided with a heat-conducting layer and an electromagnetic shielding layer, the heat-conducting layer and the electromagnetic shielding layer are arranged sequentially from the inside to the outside.

[0010] In one possible implementation, the interlocking groove includes a groove opening and a groove bottom, with the groove opening located on a first side; the thermally conductive layer includes a graphene layer, a boron nitride layer, and a silicon-based thermally conductive adhesive layer sequentially disposed along the direction from the groove opening to the groove bottom.

[0011] In one possible implementation, the second chip is bonded to the recess, and a buffer layer is provided between the second chip and the recess.

[0012] In one possible implementation, a heat sink cover is provided on the first side, a heat sink cavity is provided inside the heat sink cover, and an opening communicating with the heat sink cavity is provided on one side of the heat sink cover; the heat sink cover is disposed outside the first chip and the second chip through the opening cover, and the heat sink cover is bonded to the substrate.

[0013] In one possible implementation, a first chip, a second chip, and a recessed portion are provided in multiples corresponding to each other.

[0014] In one possible implementation, the thickness of the hybrid bonding layer is 1 μm-10 μm.

[0015] Secondly, embodiments of this application provide a packaging method based on the packaging structure in any of the above embodiments, comprising: S1, connecting multiple second chips to a first chip by hybrid bonding; S2, cutting the bonded first chip to form multiple chip units, such that each chip unit contains a second chip; S3, preparing a substrate and providing a recess on a first side of the substrate, the recess corresponding to a second chip; S4, inverting the chip unit on the first side of the substrate, such that the second chip is located in the recess; S5, electrically connecting the first chip to the substrate by controlled collapse chip connection solder bump bonding, and bonding the first chip and the second chip to the substrate respectively; S6, providing a heat sink on the first side of the substrate, such that the heat sink covers the outside of the first chip, and providing solder balls on the second side of the substrate, such that the solder balls are electrically connected to the substrate.

[0016] The packaging structure and method provided in this application, by placing the second chip within a recess in the substrate, occupies the thickness space of the substrate rather than the space above the substrate, thus not increasing the overall thickness of the packaging structure. A hybrid bonding layer is disposed between the first and second chips, with the active surfaces of the first and second chips directly bonded to each other via the hybrid bonding layer. Electrical signals are transmitted from the central region of the first chip to the second chip through the hybrid bonding layer. This transmission path is directly perpendicular to the active surfaces of the first and second chips, and only includes the dielectric layer and metal bonding structure of the hybrid bonding layer, without including through-silicon via (TSV) structures. Therefore, there are no parasitic capacitance and inductance effects introduced by TSVs, and signal delay is reduced. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] Figure 1 A cross-sectional view of a packaging structure provided in an embodiment of this application;

[0019] Figure 2 An assembly diagram of the first chip and the second chip of the packaging structure provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of the substrate structure of the packaging structure provided in one embodiment of this application;

[0021] Figure 4 An assembly diagram of the first chip, the second chip, and the substrate of a packaging structure provided in an embodiment of this application;

[0022] Figure 5 A top view of a first chip and a second chip in a packaging structure provided in an embodiment of this application;

[0023] Figure 6 A flowchart of an embodiment of the encapsulation method provided in this application.

[0024] Figure label:

[0025] 100: Substrate; 200: First chip; 300: Second chip; 400: Hybrid bonding layer; 500: Controllable collapse chip connection bump; 600: Heat sink; 700: Solder ball;

[0026] 110: Recessed area; 111: Groove opening; 112: Groove bottom;

[0027] 610: Heat dissipation cavity; 620: Opening. Detailed Implementation

[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0029] Three-dimensional chip interconnect packaging technology belongs to the field of advanced semiconductor packaging. It is mainly used to achieve three-dimensional integration and high-speed interconnection of multiple chips within a limited packaging area. It is suitable for systems with high requirements for size, bandwidth, power consumption and reliability, such as smart terminals, automotive electronics and edge computing.

[0030] In such applications, the packaging structure typically needs to establish stable electrical connection paths between the substrate, chip, and external modules, and achieve data interaction between chips through stacking or embedding to meet the development needs of system-level integration.

[0031] Existing 3D chip interconnect packaging solutions typically employ microbumps, TSVs, or hybrid bonding to achieve vertical connections between chips. Microbump solutions primarily rely on bump structures to achieve electrical conduction between upper and lower chips; TSV solutions establish vertical electrical connections by forming through-channels within the chip; and hybrid bonding solutions achieve chip stack interconnection through bonding interfaces, and further integrate with the substrate and external modules to complete system packaging.

[0032] However, in high-density packaging scenarios, microbumps are limited by interconnect spacing, which can easily lead to significant parasitic effects, making it difficult to balance high bandwidth and miniaturization requirements. Although TSV can achieve vertical conduction, it has a long process chain, high manufacturing cost, and is prone to stress concentration and increased transmission path, which in turn affect device performance and packaging yield.

[0033] Traditional hybrid bonding schemes often rely on additional adapter structures or complex assembly relationships in actual packaging, which not only increases the overall thickness but also increases the pressure on heat dissipation and assembly control, leading to increased mass production complexity. When the above-mentioned defects occur simultaneously, the packaging structure often struggles to meet the comprehensive requirements of low latency, low cost, high reliability, and high integration.

[0034] In view of this, how to balance interconnect density, transmission performance, structural compactness and packaging reliability in three-dimensional chip interconnect packaging has become an urgent technical problem to be solved.

[0035] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0036] Reference Figure 1 The present application provides a packaging structure including: a substrate 100, a first chip 200 and a second chip 300. The substrate 100 has a first side and a second side opposite to each other. The first side is provided with a recess 110. A circuit is provided inside the substrate 100. The first connection port of the circuit is located on the first side and the second connection port of the circuit is located on the second side. The two connection ports are used to connect to an external module. The first chip 200 is disposed on the first side and electrically connected to the first connection port. The second chip 300 is disposed in the recess 110 and is stacked with the first chip 200 through a hybrid bonding layer 400.

[0037] Specifically, the substrate 100 can be an organic packaging substrate or a ceramic packaging substrate. Organic packaging substrates, for example, are BT (Bismaleimide Triazine) resin substrates or ABF (Ajinomoto Build-up Film) laminated substrates. Ceramic packaging substrates, for example, are alumina substrates or aluminum nitride substrates. The circuitry inside the substrate 100 is a multilayer metal wiring structure. This multilayer metal wiring structure is isolated by interlayer insulating dielectric layers, and the metal layers are electrically connected through vias. The first connection port of the circuit is located on the first side of the substrate 100. The first connection port is a metal pad array used for electrical interconnection with the first chip 200. The second connection port of the circuit is located on the second side of the substrate 100. The second connection port is also a metal pad array used for connection with external modules. The recess 110 is a groove structure formed on the first side of the substrate 100. The bottom surface of this groove structure is flat, and the angle between the side surface and the bottom surface can be a right angle or a rounded corner.

[0038] Furthermore, the depth of the recess 110 provided on the first side of the substrate 100 can be set according to the thickness of the second chip 300, so that the second chip 300 is partially or completely embedded in the recess 110. The first chip 200 is disposed on the first side of the substrate 100, with its active surface facing the first side of the substrate 100. The active surface of the first chip 200 has a first pad area and a second pad area. The first pad area is located in the center region of the first chip 200, and the second pad area is located in the edge region of the first chip 200. The first pad area is used for electrical connection with the second chip 300, and the second pad area is used for electrical connection with the first connection port of the substrate 100. The second chip 300 is disposed within the recess 110, with its active surface facing the first chip 200. The active surface of the second chip 300 has a third pad area, which corresponds in position to the first pad area of ​​the first chip 200.

[0039] During use, the second chip 300 is first vertically interconnected with the first chip 200 through a hybrid bonding layer 400, forming an assembly of the first chip 200 and the second chip 300. This assembly is then placed on the first side of the substrate 100, aligning the second chip 300 and embedding it into the recess 110, while simultaneously aligning the second pad area of ​​the edge region of the first chip 200 with the first connection port on the first side of the substrate 100. Next, the second pad area of ​​the first chip 200 is soldered to the first connection port of the substrate 100, achieving electrical connection between the first chip 200 and the substrate 100. Finally, electrical connection is achieved with an external module through the second connection port on the second side of the substrate 100, completing the signal transmission between the entire package structure and the external system.

[0040] In this embodiment, the second chip 300 is disposed within the recess 110 of the substrate 100. The second chip 300 occupies the thickness space of the substrate 100 rather than the space above the substrate 100, therefore the second chip 300 does not increase the overall thickness of the package structure. A hybrid bonding layer 400 is disposed between the first chip 200 and the second chip 300. The active surfaces of the first chip 200 and the second chip 300 are directly bonded to each other through the hybrid bonding layer 400. Electrical signals are transmitted from the central region of the first chip 200 to the second chip 300 through the hybrid bonding layer 400. This transmission path is directly perpendicular to the active surfaces of the first chip 200 and the second chip 300. The path only includes the dielectric layer and metal bonding structure of the hybrid bonding layer 400, and does not include through-silicon via (TSV) structures. Therefore, there are no parasitic capacitance and parasitic inductance effects introduced by TSVs, and signal delay is reduced.

[0041] Reference Figure 1 and Figure 4 In some embodiments of this application, the first chip 200 is inverted on the first side; the central region of the first chip 200 is electrically connected to the second chip 300, and the edge region of the first chip 200 is electrically connected to the substrate 100.

[0042] Specifically, the first chip 200 is inverted on the first side of the substrate 100, meaning that the active surface of the first chip 200 faces the first side of the substrate 100, while the back side of the first chip 200 faces away from the first side of the substrate 100. The central region of the first chip 200 refers to the central portion of the active surface of the first chip 200, where a first pad array is arranged for electrical interconnection with the second chip 300. The edge region of the first chip 200 refers to the peripheral portion of the active surface of the first chip 200, where a second pad array is arranged for electrical interconnection with the substrate 100.

[0043] Furthermore, the central region of the first chip 200 is electrically connected to the second chip 300 by direct bonding through a hybrid bonding layer 400. The hybrid bonding layer 400 is located between the central region of the first chip 200 and the active surface of the second chip 300. The hybrid bonding layer 400 includes a dielectric bonding portion and a metal bonding portion. The dielectric bonding portion is formed by molten bonding of the dielectric layer of the central region of the first chip 200 and the dielectric layer of the active surface of the second chip 300. The metal bonding portion is formed by direct metal bonding of the copper pads of the central region of the first chip 200 and the copper pads of the active surface of the second chip 300.

[0044] In the process of use, the second chip 300 is first bonded to the central region of the first chip 200 through the hybrid bonding layer 400 to form a chip stack unit. Then, the entire chip stack unit is flipped so that the active surface of the first chip 200 faces the first side of the substrate 100, while the second chip 300 is aligned with the recess 110 of the substrate 100. Next, the chip stack unit is placed on the substrate 100, so that the second chip 300 is embedded in the recess 110, and the second pad array on the edge region of the first chip 200 is aligned with the first connection port on the first side of the substrate 100. Finally, the electrical and mechanical connections between the first chip 200 and the substrate 100 are completed.

[0045] In this embodiment, the first chip 200 is inverted and placed on the first side of the substrate 100, with the active surface of the first chip 200 facing both the second chip 300 and the substrate 100. The first pad array in the central region of the first chip 200 is directly bonded to the third pad array on the active surface of the second chip 300 via a hybrid bonding layer 400. Electrical signals are transmitted from the central region of the first chip 200 to the second chip 300 via the metal bonding portion of the hybrid bonding layer 400; this path is a solid metal path perpendicular to the active surface of the first chip 200. The second pad array in the edge region of the first chip 200 is connected to the first connection port of the substrate 100, and electrical signals are transmitted from the edge region of the first chip 200 to the substrate 100; this path is also a vertical solid metal and solder path. Neither signal transmission path passes through a through-silicon via (TSV) structure, thus eliminating the parasitic effects and signal delays associated with TSVs.

[0046] Reference Figure 2 In some embodiments of this application, the first chip 200 is electrically connected to the first connection port via a controllable collapse chip connection bump 500.

[0047] Specifically, the controllable collapse chip connection bump 500 is an interconnect structure for flip chip packaging, located between the second pad array on the edge region of the first chip 200 and the first connection port on the first side of the substrate 100. During reflow soldering, the controllable collapse chip connection bump 500 melts under heat, forming a controllable collapse height under surface tension, thus maintaining a consistent spacing between the first chip 200 and the substrate 100.

[0048] Furthermore, the controllable collapse chip connection bump 500 can be a high-lead solder bump or a eutectic solder bump, and the material of the eutectic solder bump can be a tin-lead eutectic alloy or a tin-silver eutectic alloy. The controllable collapse chip connection bump 500 is disposed on a second pad in the edge region of the first chip 200. The second pad is a metal pad disposed in the edge region of the active surface of the first chip 200, and the material of the metal pad can be aluminum or copper. The controllable collapse chip connection bump 500 is connected to the first connection port on the first side of the substrate 100 through a reflow soldering process. The first connection port is a metal pad disposed on the first side of the substrate 100, and the material of the metal pad can be copper, and its surface can be provided with a nickel-gold plating layer or a nickel-palladium-gold plating layer.

[0049] During use, the first chip 200, equipped with controllable collapse chip connection bumps 500, is aligned with the first side of the substrate 100, making contact between the controllable collapse chip connection bumps 500 and the first connection port on the first side of the substrate 100. The entire structure is then placed in a reflow oven for heating. The heating temperature is determined based on the solder composition of the controllable collapse chip connection bumps 500; for example, the reflow peak temperature of tin-silver-copper solder can be between 240 and 250 degrees Celsius. During heating, the controllable collapse chip connection bumps 500 melt and form a stable bump shape under surface tension, simultaneously achieving electrical and mechanical connections between the second pad of the first chip 200 and the first connection port of the substrate 100. After cooling, the controllable collapse chip connection bumps 500 solidify, fixing the first chip 200 onto the substrate 100.

[0050] In this embodiment, a second pad array on the edge region of the first chip 200 is electrically connected to the first connection port of the substrate 100 via a controllable collapse chip connection bump 500. The controllable collapse chip connection bump 500 melts during reflow soldering, and its liquid solder adaptively adjusts its collapse height under surface tension. When there is a difference in the local spacing between the first chip 200 and the substrate 100, the collapse height of each controllable collapse chip connection bump 500 is adjusted accordingly, compensating for the coplanarity deviation between the first chip 200 and the substrate 100. After cooling and solidification, each controllable collapse chip connection bump 500 forms a continuous intermetallic compound connection with its corresponding first connection port. This connection is a solid metallurgical bonding structure, ensuring low resistance characteristics for each electrical connection channel.

[0051] Reference Figure 3 In some embodiments of this application, the recess 110 is a fitting groove, and the inner wall of the fitting groove is provided with a heat-conducting layer and / or an electromagnetic shielding layer; when the inner wall of the fitting groove is provided with a heat-conducting layer and an electromagnetic shielding layer, the heat-conducting layer and the electromagnetic shielding layer are arranged sequentially from the inside to the outside.

[0052] Specifically, the recess 110 is a fitting groove formed on the first side of the substrate 100. The contour of the fitting groove matches the contour of the second chip 300, allowing the second chip 300 to be embedded in the fitting groove. The inner wall of the fitting groove includes a bottom surface and a side surface. The bottom surface is the surface opposite to the back surface of the second chip 300, and the side surface is the surface surrounding the second chip 300. A thermally conductive layer is disposed on the inner wall of the fitting groove to conduct the heat generated by the second chip 300 to the substrate 100. An electromagnetic shielding layer is disposed on the inner wall of the fitting groove to block external electromagnetic signals from interfering with the second chip 300, and to block the electromagnetic signals generated by the second chip 300 from interfering with external circuits.

[0053] Furthermore, the inner wall of the fitting groove may only have a heat-conducting layer without an electromagnetic shielding layer, and the heat-conducting layer covers the bottom and sides of the fitting groove. Alternatively, the inner wall of the fitting groove may only have an electromagnetic shielding layer without a heat-conducting layer, and the electromagnetic shielding layer covers the bottom and sides of the fitting groove. When both a heat-conducting layer and an electromagnetic shielding layer are provided on the inner wall of the fitting groove, the heat-conducting layer and the electromagnetic shielding layer are arranged sequentially from the inside out, that is, the heat-conducting layer is close to the second chip 300, and the electromagnetic shielding layer is close to the substrate 100, or the electromagnetic shielding layer is close to the second chip 300, and the heat-conducting layer is close to the substrate 100. The material of the heat-conducting layer can be thermal grease, thermal adhesive, or a metal heat-conducting layer, and the material of the metal heat-conducting layer can be copper or aluminum. The material of the electromagnetic shielding layer can be metal foil or a conductive coating, and the material of the metal foil can be copper foil or aluminum foil, and the material of the conductive coating can be silver paste or copper paste.

[0054] During use, after the second chip 300 is embedded in the fitting slot, its back surface contacts the thermally conductive layer on the bottom of the fitting slot, and its side surface contacts the thermally conductive layer or electromagnetic shielding layer on the side of the fitting slot. The heat generated by the second chip 300 during operation is conducted through its back and side surfaces to the thermally conductive layer, and then through the thermally conductive layer to the substrate 100, from which the substrate 100 dissipates the heat to the external environment. When electromagnetic interference signals are present in the external environment, the electromagnetic shielding layer can reflect or absorb these signals, preventing them from entering the fitting slot and affecting the normal operation of the second chip 300. Simultaneously, the electromagnetic signals generated by the second chip 300 itself are also confined within the fitting slot by the electromagnetic shielding layer, preventing them from interfering with external circuits.

[0055] In this embodiment, a heat-conducting layer is provided on the inner wall of the mating groove. The back side of the second chip 300 is in direct contact with the heat-conducting layer on the bottom surface of the mating groove, and the side side of the second chip 300 is in direct contact with the heat-conducting layer on the side of the mating groove. The heat of the second chip 300 is conducted to the heat-conducting layer through both its back side and side side. The heat transfer area includes the area of ​​the back side and the area of ​​the side side of the second chip 300. The heat conduction path is a solid heat conduction path from the second chip 300 through the heat-conducting layer to the substrate 100, without passing through an air gap. Therefore, heat can be efficiently conducted from the second chip 300 to the substrate 100. The junction temperature of the second chip 300 during operation is reduced. By providing an electromagnetic shielding layer on the inner wall of the mating groove, the electromagnetic shielding layer has a continuous metal layer structure. When external electromagnetic interference signals reach the surface of the electromagnetic shielding layer, the electromagnetic shielding layer reflects and absorbs them, blocking the spatial path of external electromagnetic interference signals entering the interior of the mating groove. At the same time, the electromagnetic signals generated by the second chip 300 itself are blocked by the electromagnetic shielding layer and constrained inside the mating groove when radiating outward, blocking its spatial radiation path to the external circuit.

[0056] In some other possible embodiments, a thermally conductive via can be provided at the bottom of the fitting groove, penetrating the substrate 100. The thermally conductive via is filled with a thermally conductive material, which can be copper or thermally conductive adhesive. One end of the thermally conductive via is connected to the thermally conductive layer on the bottom surface of the fitting groove, and the other end is connected to the second side of the substrate 100, so that the heat of the second chip 300 is directly conducted to the second side of the substrate 100 and then dissipated through the heat dissipation structure provided on the second side of the substrate 100. A metallization layer can be provided on the sidewall of the fitting groove. This metallization layer is connected to the ground layer of the substrate 100 through the metal wiring inside the substrate 100, thereby forming a grounding shielding structure.

[0057] In some embodiments of this application, the interlocking groove includes a groove opening 111 and a groove bottom 112, with the groove opening 111 located on a first side; the thermally conductive layer includes a graphene layer, a boron nitride layer, and a silicon-based thermally conductive adhesive layer sequentially disposed along the direction from the groove opening 111 to the groove bottom 112.

[0058] Specifically, the interlocking groove includes a groove opening 111 and a groove bottom 112. The groove opening 111 is located on the first side of the substrate 100, that is, the groove opening 111 is the opening of the interlocking groove on the first side of the substrate 100. The groove bottom 112 is the bottom surface of the interlocking groove, that is, the deepest position of the interlocking groove inside the substrate 100. The direction from the groove opening 111 to the groove bottom 112 is the depth direction of the interlocking groove, that is, the entry direction when the second chip 300 is inserted into the interlocking groove. A graphene layer, a boron nitride layer and a silicon-based thermally conductive adhesive layer are sequentially disposed along the direction from the groove opening 111 to the groove bottom 112, that is, from the position near the groove opening 111 to the position near the groove bottom 112, the graphene layer, the boron nitride layer and the silicon-based thermally conductive adhesive layer are sequentially disposed.

[0059] Furthermore, the graphene layer is disposed on the outermost layer of the inner wall of the interlocking groove, meaning the graphene layer is in direct contact with the second chip 300. The graphene layer is a single-layer or multi-layer graphene film with high in-plane thermal conductivity, enabling rapid diffusion of heat generated by the second chip 300 along the wall of the interlocking groove. A boron nitride layer is disposed between the graphene layer and the silicon-based thermally conductive adhesive layer. The boron nitride layer is a hexagonal boron nitride film with high thermal conductivity and good electrical insulation, enabling further transfer of heat conducted from the graphene layer to the silicon-based thermally conductive adhesive layer while providing electrical insulation. The silicon-based thermally conductive adhesive layer is disposed between the boron nitride layer and the substrate 100. The silicon-based thermally conductive adhesive layer is an adhesive layer filled with silicon-based thermally conductive filler, exhibiting good material compatibility with the substrate 100 and enabling heat conduction from the boron nitride layer to the substrate 100.

[0060] In this embodiment, a graphene layer, a boron nitride layer, and a silicon-based thermally conductive adhesive layer are sequentially disposed along the groove opening 111 to the groove bottom 112. The graphene layer is in direct contact with the second chip 300. The heat from the second chip 300 first enters the graphene layer. The in-plane thermal conductivity of the graphene layer is higher than its normal thermal conductivity. After entering the graphene layer, the heat spreads rapidly along the in-plane direction of the interlocking groove wall, making the temperature of the back and side areas of the second chip 300 more uniform and preventing heat accumulation in local areas of the second chip 300. The boron nitride layer is an electrically insulating material with high volume resistivity. Located between the graphene layer and the silicon-based thermally conductive adhesive layer, it blocks the electrical leakage path from the second chip 300 through the thermally conductive layer to the substrate 100. A silicon-based thermally conductive adhesive layer is filled between the boron nitride layer and the substrate 100. Both the boron nitride layer and the substrate 100 are made of silicon-containing materials. The interface between the two is tightly bonded and has low interfacial thermal resistance. The path of heat conduction from the boron nitride layer to the substrate 100 through the silicon-based thermally conductive adhesive layer is a continuous solid thermal conduction path.

[0061] In some embodiments of this application, the second chip 300 is bonded to the recessed portion 110, and a buffer layer is provided between the second chip 300 and the recessed portion 110.

[0062] Specifically, the bonding between the second chip 300 and the recess 110 refers to the fixed connection between the back and side surfaces of the second chip 300 and the inner wall of the recess 110 using an adhesive material. A buffer layer is disposed between the second chip 300 and the recess 110, that is, the buffer layer is located between the outer surface of the second chip 300 and the inner wall of the recess 110, and the buffer layer separates the second chip 300 from the inner wall of the recess 110.

[0063] Furthermore, the bonding between the second chip 300 and the recess 110 can be achieved using a thermally conductive adhesive. This adhesive fills the space between the back surface of the second chip 300 and the bottom surface of the recess 110, as well as between the side surface of the second chip 300 and the side surface of the recess 110. A buffer layer can be disposed between the back surface of the second chip 300 and the bottom surface of the recess 110, or between the side surface of the second chip 300 and the side surface of the recess 110, or simultaneously between the back surface of the second chip 300 and the bottom surface of the recess 110, and between the side surface of the second chip 300 and the side surface of the recess 110. The buffer layer can be made of an elastomer, such as silicone rubber or polyurethane rubber, and its thickness can be adjusted according to the gap between the second chip 300 and the recess 110.

[0064] During use, a buffer layer material is first applied to the inner wall surface of the recess 110 or the outer surface of the second chip 300, and then the second chip 300 is embedded in the recess 110. The buffer layer material is compressed during the embedding process, filling the gap between the second chip 300 and the inner wall of the recess 110. The buffer layer material is then cured by heating or ultraviolet light irradiation, fixing the second chip 300 within the recess 110. In subsequent use, when the package structure is subjected to mechanical impact or temperature changes, relative displacement or stress occurs between the substrate 100 and the second chip 300 due to the difference in their thermal expansion coefficients. The buffer layer absorbs and buffers this displacement and stress through its own elastic deformation, reducing the mechanical and thermal stress transmitted to the second chip 300.

[0065] In this embodiment, the second chip 300 is bonded to the recessed portion 110. An adhesive material is filled between the back and sides of the second chip 300 and the inner wall of the recessed portion 110. After curing, the adhesive material forms a continuous solid interface between the second chip 300 and the recessed portion 110. This interface can withstand shear and tensile forces, constraining the second chip 300 to a fixed position within the recessed portion 110. A buffer layer is disposed between the second chip 300 and the recessed portion 110. The buffer layer is an elastomer material layer with an elastic modulus lower than that of the substrate 100 and the second chip 300. When the substrate 100 expands or contracts due to temperature changes, the relative displacement between the substrate 100 and the second chip 300 is first absorbed by the elastic deformation of the buffer layer. The molecular chain segments inside the buffer layer stretch and contract, converting mechanical energy into heat energy and dissipating it. The stress value transmitted to the second chip 300 is reduced to below the second chip 300's withstand threshold.

[0066] Reference Figure 1In some embodiments of this application, a heat dissipation cover 600 is provided on the first side, a heat dissipation cavity 610 is provided inside the heat dissipation cover 600, and an opening 620 communicating with the heat dissipation cavity 610 is provided on one side of the heat dissipation cover 600; the heat dissipation cover 600 covers the outside of the first chip 200 and the second chip 300 through the opening 620, and the heat dissipation cover 600 is bonded to the substrate 100.

[0067] Specifically, a heat sink 600 is disposed on the first side of the substrate 100. The heat sink 600 has a heat dissipation cavity 610 inside, which is a hollow structure inside the heat sink 600 used to accommodate the first chip 200 and the second chip 300. One side of the heat sink 600 has an opening 620 communicating with the heat dissipation cavity 610. The opening 620 is located on the side of the heat sink 600 facing the substrate 100, allowing the heat dissipation cavity 610 to communicate with the outside. The heat sink 600 covers the first chip 200 and the second chip 300 through the opening 620; that is, the first chip 200 and the second chip 300 are located inside the heat dissipation cavity 610, and the heat sink 600 covers and tops the first chip 200 and the second chip 300.

[0068] Furthermore, the heat sink 600 is bonded to the substrate 100 by using a thermally conductive adhesive to bond the edge of the opening 620 of the heat sink 600 to the first side surface of the substrate 100. The thermally conductive adhesive can be thermally conductive epoxy resin or thermally conductive silicone grease. The material of the heat sink 600 can be a metal, such as copper or aluminum, or a composite material, such as graphite-copper composite or aluminum-silicon carbide composite. The outer surface of the heat sink 600 can be provided with heat dissipation fins, which are thin sheet structures extending outward from the outer surface of the heat sink 600 to increase the heat dissipation area of ​​the heat sink 600.

[0069] During operation, the heat generated by the first chip 200 and the second chip 300 is first conducted to the air within the heat dissipation cavity 610, and then transferred to the inner wall of the heat sink 600 through thermal radiation and convection. After absorbing heat, the inner wall of the heat sink 600 conducts the heat through its walls to the outer surface. The heat dissipation fins on the outer surface of the heat sink 600 increase the contact area with the external air, allowing heat to dissipate from the outer surface and fins into the external environment. Simultaneously, the heat sink 600, with its rigid structure, covers the first chip 200 and the second chip 300, providing physical protection and preventing external mechanical forces from directly acting on the chip surfaces.

[0070] In this embodiment, a heat sink 600 with a heat dissipation cavity 610 is provided and placed over the first chip 200 and the second chip 300. The wall of the heat sink 600 is made of a thermally conductive material. The air inside the heat dissipation cavity 610 absorbs heat from the first chip 200 and the second chip 300 and its temperature rises. When the hot air comes into contact with the inner wall of the heat sink 600, it transfers heat to the wall of the heat sink 600. The wall of the heat sink 600 absorbs heat and its temperature rises. The heat is conducted from the inner wall to the outer wall along the solid structure of the wall of the heat sink 600, and then dissipated through convection and radiation between the outer surface of the heat sink 600 and the external environment.

[0071] The heat sink 600 is bonded to the first side of the substrate 100. The wall of the heat sink 600 is a continuous rigid structure, surrounding the first chip 200 and the second chip 300 around and above. When external mechanical force is applied to the heat sink 600, the wall of the heat sink 600 bears the force and disperses it to the bonding interface with the substrate 100, preventing the external mechanical force from directly acting on the surfaces of the first chip 200 and the second chip 300. After the heat sink 600 is bonded to the substrate 100, the rigid wall of the heat sink 600 generates a restraining torque on the edge region of the substrate 100. The direction of this restraining torque is opposite to the direction of the warping deformation of the substrate 100 caused by temperature changes, thereby suppressing the amount of warping deformation of the substrate 100.

[0072] Reference Figure 5 In some embodiments of this application, the first chip 200, the second chip 300, and the recessed portion 110 are provided in multiple ways.

[0073] Specifically, the first chip 200, the second chip 300, and the recessed portion 110 are provided in a one-to-one correspondence, meaning that the package structure can include multiple first chips 200, multiple second chips 300, and multiple recessed portions 110. Each first chip 200 corresponds to one second chip 300 and one recessed portion 110, forming multiple independent chip stack structures. Each chip stack structure can operate independently of each other, or they can be electrically interconnected through the circuitry inside the substrate 100.

[0074] Furthermore, multiple first chips 200 can be arranged side-by-side on the first side of the substrate 100, and the edge region of each first chip 200 is electrically connected to the first connection port of the substrate 100 through a controllable collapsed chip connection bump 500. Multiple recesses 110 are respectively formed on the first side of the substrate 100, and the position of each recess 110 corresponds to the position of the central region of the corresponding first chip 200. Multiple second chips 300 are respectively disposed within the corresponding recesses 110, and each second chip 300 is stacked with the central region of the corresponding first chip 200 through a hybrid bonding layer 400. The functions of the multiple first chips 200 can be the same or different; for example, some first chips 200 are computing chips, and some are storage control chips. The functions of the multiple second chips 300 can be the same or different; for example, some second chips 300 are storage chips, and some are interface chips.

[0075] During use, multiple first chips 200 are electrically connected to the substrate 100 via controllable collapse chip connection bumps 500, and multiple second chips 300 are vertically interconnected with their corresponding first chips 200 via hybrid bonding layers 400. The circuitry within the substrate 100 interconnects the multiple first chips 200, the multiple second chips 300, and the first chips 200 and second chips 300 according to a preset circuit topology, enabling collaborative operation of the multi-chip system. The signal transmission path between each first chip 200 and its corresponding second chip 300 is a vertical direct bonding path, resulting in a short path and low latency. Signal transmission between different groups of chips is achieved through metal wiring within the substrate 100.

[0076] This embodiment employs a one-to-one correspondence between multiple first chips 200, multiple second chips 300, and multiple recesses 110. The vertical interconnection between each first chip 200 and its corresponding second chip 300 is achieved through a hybrid bonding layer 400. Electrical signals within each group are transmitted from the first chip 200 to the second chip 300 via the metal bonding structure of the hybrid bonding layer 400. This path is a solid metal path perpendicular to the active surface of the first chip 200 and does not include through-silicon vias (TSVs). Electrical signals between the chip groups are transmitted through multilayer metal wiring within the substrate 100, which consists of solid metal paths in both horizontal and vertical directions.

[0077] In some embodiments of this application, the thickness of the hybrid bonding layer 400 is 1 μm-10 μm.

[0078] Specifically, the thickness of the hybrid bonding layer 400 is the vertical spacing between the first chip 200 and the second chip 300, that is, the dimension of the hybrid bonding layer 400 in the stacking direction of the first chip 200 and the second chip 300. The thickness of the hybrid bonding layer 400 ranges from 1 μm to 10 μm, including the endpoint values ​​of 1 μm and 10 μm.

[0079] Furthermore, the hybrid bonding layer 400 is composed of a dielectric bonding portion and a metal bonding portion. The dielectric bonding portion is the dielectric interface formed after the dielectric layers of the first chip 200 and the second chip 300 are bonded together. The metal bonding portion is the metal bonding interface formed after the copper pads of the first chip 200 and the copper pads of the second chip 300 are bonded together. The thickness of the dielectric bonding portion and the thickness of the metal bonding portion can be the same or different. When the thickness of the hybrid bonding layer 400 is 1 μm, it is suitable for high-density interconnect scenarios, providing more interconnect channels per unit area. When the thickness of the hybrid bonding layer 400 is 10 μm, it is suitable for scenarios requiring higher bonding strength, as a thicker hybrid bonding layer 400 can provide a larger bonding area and higher bonding strength.

[0080] During use, the first chip 200 and the second chip 300 are bonded face-to-face through a hybrid bonding layer 400. During bonding, the active surfaces of the first chip 200 and the second chip 300 are placed opposite each other. The dielectric layers of the first chip 200 and the second chip 300 are pre-bonded at room temperature via van der Waals forces. The copper pads of the first chip 200 and the second chip 300 are then metal-bonded via atomic diffusion during subsequent heat treatment. After bonding, the thickness of the hybrid bonding layer 400 is determined to be between 1 μm and 10 μm. This thickness of the hybrid bonding layer 400 results in a very small vertical distance between the first chip 200 and the second chip 300. Signals are directly transmitted from the copper pads of the first chip 200 through the metal bonding portion of the hybrid bonding layer 400 to the copper pads of the second chip 300, following a vertical path formed by the solid metal structure.

[0081] In this embodiment, the thickness of the hybrid bonding layer 400 is set to 1μm to 10μm, and the vertical spacing between the first chip 200 and the second chip 300 is this thickness value. After the electrical signal is output from the copper pads of the first chip 200, it directly enters the copper pads of the second chip 300 via the metal bonding portion of the hybrid bonding layer 400. The length of this transmission path is equal to the thickness of the hybrid bonding layer 400, i.e., not exceeding 10μm. The medium in the transmission path is the dielectric bonding portion of the hybrid bonding layer 400, but the signal is mainly transmitted via the copper-copper direct bonding interface of the metal bonding portion. This interface has a continuous metallic crystal structure, and the interatomic bonding force at the interface is a metallic bond. Electrons experience minimal scattering during transmission, resulting in low path resistance.

[0082] In other possible embodiments, the thickness of the hybrid bonding layer 400 can be set according to the pad size and pad spacing of the first chip 200 and the second chip 300, specifically from 3μm to 7μm. The smaller the pad size and the smaller the pad spacing, the thinner the hybrid bonding layer 400 can be, thereby achieving a higher interconnect density. The material of the dielectric bonding portion of the hybrid bonding layer 400 can be silicon dioxide or silicon carbide, and the material of the metal bonding portion can be pure copper or a copper alloy. The bonding process of the hybrid bonding layer 400 can be completed at the wafer level, i.e., multiple second chips 300 are first bonded to corresponding positions on the wafer of the first chip 200, and then the bonded wafer is diced into individual chip units.

[0083] Reference Figure 6 This application also provides a packaging method based on the packaging structure in any of the above embodiments, including: S1, connecting multiple second chips 300 to a first chip 200 by hybrid bonding; S2, cutting the bonded first chip 200 to form multiple chip units, such that each chip unit contains a second chip 300; S3, preparing a substrate 100, and providing a recess 110 on a first side of the substrate 100, wherein the recess 110 corresponds one-to-one with the second chip 300; S4, packaging the chip units... S5. The first chip 200 is electrically connected to the substrate 100 by means of controllable collapse chip connection solder bump bonding, and the first chip 200 and the second chip 300 are respectively bonded to the substrate 100; S6. A heat dissipation cover 600 is provided on the first side of the substrate 100 so that the heat dissipation cover 600 covers the outside of the first chip 200, and a solder ball 700 is provided on the second side of the substrate 100 so that the solder ball 700 is electrically connected to the substrate 100.

[0084] Specifically, connecting multiple second chips 300 to the first chip 200 via hybrid bonding means bonding the multiple second chips 300 to corresponding bonding positions on the first chip 200. Dividing the bonded first chip 200 into multiple chip units, with each chip unit containing a second chip 300, means cutting the first chip 200 with the bonded second chips 300 along a dicing line to divide it into individual chip units. Each chip unit includes a first chip 200 and at least one second chip 300 bonded thereto.

[0085] Furthermore, the substrate 100 is fabricated, and a recess 110 is formed on the first side of the substrate 100, with each recess 110 corresponding to a second chip 300. This means that the substrate 100 can be fabricated using conventional packaging substrate manufacturing processes, including insulating layer lamination, metal wiring fabrication, and via fabrication. The recess 110 can be formed on the first side of the substrate 100 by laser ablation or mechanical milling, and the position and size of each recess 110 match the position and size of the corresponding second chip 300. Inverting the chip unit on the first side of the substrate 100, with the second chip 300 located in the recess 110, means flipping the cut chip unit so that the active surface of the first chip 200 faces the first side of the substrate 100, while simultaneously aligning the second chip 300 with the corresponding recess 110 and embedding it therein.

[0086] In the process of use, firstly, multiple second chips 300 are bonded to corresponding positions on the first chip 200 using a hybrid bonding process to form a bonding structure. Then, the bonded structure is cut into multiple independent chip units, each chip unit including the first chip 200 and the second chips 300 bonded thereto. Simultaneously, a recess 110 is fabricated on the substrate 100 using laser ablation or mechanical milling, and metal wiring circuitry is fabricated inside the substrate 100. Next, the cut chip units are inverted so that the second chips 300 are aligned with the recess 110 of the substrate 100, and the chip units are placed on the substrate 100, embedding the second chips 300 into the recess 110. At the same time, the pads on the edge region of the first chip 200 are aligned with the first connection port on the first side of the substrate 100. The first chip 200 is electrically connected to the substrate 100 via controlled collapse chip bonding with solder bumps. This involves melting and solidifying the controlled collapse chip bonding bumps using a reflow soldering process, achieving both electrical and mechanical connections between the first chip 200 and the substrate 100. Then, the first chip 200 and the second chip 300 are bonded to the substrate 100 respectively. This is achieved by injecting and curing underfill adhesive between the first chip 200 and the substrate 100, and between the second chip 300 and the recess 110. Finally, a heat sink 600 is provided on the first side of the substrate 100, covering the first chip 200 and bonded to it. Solder balls 700 are provided on the second side of the substrate 100, electrically connecting to the second connection port of the substrate 100.

[0087] In this embodiment, the second chip 300 and the first chip 200 are first hybrid-bonded, and then the bonded structure is cut. During the hybrid bonding process, all bonding positions on the first chip 200 are simultaneously bonded to the corresponding second chip 300. This results in high capacity utilization of the bonding equipment and short bonding time per chip. The first chip 200 and the second chip 300 in the cut chip unit are vertically interconnected via the hybrid bonding layer 400. When the chip unit is inverted and mounted on the substrate 100, the second chip 300 is embedded in the recess 110 of the substrate 100, while the first chip 200 is located above the first side surface of the substrate 100. The second chip 300 occupies the thickness space of the recess 110 within the substrate 100, not the space above the first side surface of the substrate 100. Therefore, the height of the entire package structure is determined by the thickness of the substrate 100 and the thickness of the first chip 200, without adding the thickness of the second chip 300. When the first chip 200 is electrically connected to the substrate 100 by the controlled collapse chip connection solder bump bonding method, the controlled collapse chip connection solder bump melts and forms a metallurgical bonding interface with the first connection port of the substrate 100. This interface is a continuous intermetallic compound structure, which realizes a low-resistance electrical connection.

[0088] Finally, it should be noted that other embodiments of this application will readily conceive of by those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope.

Claims

1. A packaging structure, characterized in that, include: A substrate (100) has a first side and a second side opposite to each other. The first side is provided with a recess (110). A circuit is provided inside the substrate (100). The first connection port of the circuit is located on the first side, and the second connection port of the circuit is located on the second side. The two connection ports are used to connect to an external module. The first chip (200) is disposed on the first side and electrically connected to the first connection port; The second chip (300) is disposed in the recess (110) and is stacked with the first chip (200) through a hybrid bonding layer (400).

2. The packaging structure according to claim 1, characterized in that, The first chip (200) is placed upside down on the first side; The central region of the first chip (200) is electrically connected to the second chip (300), and the edge region of the first chip (200) is electrically connected to the substrate (100).

3. The packaging structure according to claim 1, characterized in that, The first chip (200) is electrically connected to the first connection port via a controllable collapse chip connection bump (500).

4. The packaging structure according to claim 1, characterized in that, The recess (110) is a fitting groove, and the inner wall of the fitting groove is provided with a heat-conducting layer and / or an electromagnetic shielding layer; When the heat-conducting layer and the electromagnetic shielding layer are provided on the inner wall of the fitting groove, the heat-conducting layer and the electromagnetic shielding layer are arranged sequentially from the inside to the outside.

5. The packaging structure according to claim 4, characterized in that, The fitting groove includes a groove opening (111) and a groove bottom (112), and the groove opening (111) is located on the first side; The thermally conductive layer includes a graphene layer, a boron nitride layer and a silicon-based thermally conductive adhesive layer arranged sequentially along the direction from the groove opening (111) to the groove bottom (112).

6. The packaging structure according to claim 1, characterized in that, The second chip (300) is bonded to the recess (110), and a buffer layer is provided between the second chip (300) and the recess (110).

7. The packaging structure according to any one of claims 1-6, characterized in that, The first side is provided with a heat dissipation cover (600), the heat dissipation cover (600) is provided with a heat dissipation cavity (610) inside, and one side of the heat dissipation cover (600) is provided with an opening (620) communicating with the heat dissipation cavity (610). The heat sink (600) covers the outside of the first chip (200) and the second chip (300) through the opening (620), and the heat sink (600) is bonded to the substrate (100).

8. The packaging structure according to any one of claims 1-6, characterized in that, The first chip (200), the second chip (300), and the recessed portion (110) are provided in multiple corresponding positions.

9. The packaging structure according to any one of claims 1-6, characterized in that, The thickness of the hybrid bonding layer (400) is 1μm-10μm.

10. A packaging method, characterized in that, Based on the packaging structure according to any one of claims 1-9, it includes: Multiple second chips (300) are connected to the first chip (200) by a hybrid bonding method. The first chip (200) after bonding is cut to form multiple chip units, and each chip unit contains the second chip (300). A substrate (100) is prepared, and a recess (110) is provided on a first side of the substrate (100), the recess (110) corresponding one-to-one with the second chip (300); The chip unit is placed upside down on the first side of the substrate (100), and the second chip (300) is located in the recess (110). The first chip (200) is electrically connected to the substrate (100) by means of controlled collapse chip connection solder bump bonding, and the first chip (200) and the second chip (300) are respectively bonded to the substrate (100); A heat dissipation cover (600) is provided on the first side of the substrate (100) so that the heat dissipation cover (600) covers the outside of the first chip (200), and a solder ball (700) is provided on the second side of the substrate (100) so that the solder ball (700) is electrically connected to the substrate (100).

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