Embedded bridge chip organic ceramic package substrate structure and manufacturing method

Abstract

The application belongs to the technical field of semiconductor chip packaging, and particularly relates to an embedded bridge chip organic ceramic packaging substrate structure and a manufacturing method. A high-thermal-conductivity ceramic core plate is used as a rigid support, through-hole metallization is used to realize up-down electrical interconnection, an ABF / PP / PI composite layer is double-sidedly stacked, a bridge chip or an active chip is embedded in a slot on the upper side, high-bandwidth memory and computing power chips are attached to the surface layer, and a power supply structure is arranged on the back of the substrate. The ceramic core plate has high thermal conductivity and low thermal expansion coefficient, and in combination with the dielectric layer structure, warping is inhibited; the embedded chip shortens the interconnection path and improves signal integrity; and bidirectional heat dissipation reduces thermal resistance. The application has the advantages of high thermal conductivity, low warping, high wiring density and multifunctional integration, the process is mature and controllable, and the application is suitable for high-reliability high-power-consumption scenes such as vehicle regulations, military use, spaceflight, servers and AI computing modules.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip packaging technology, and in particular to an organic ceramic packaging substrate structure and manufacturing method for embedded bridging chips. Background Technology

[0002] With the rapid upgrading of industries such as artificial intelligence, high-performance computing, and 5G communication, high-performance chips and high-bandwidth memory are constantly evolving towards higher integration, higher power consumption, higher frequency and higher speed. The heat dissipation capacity, dimensional stability, high-speed interconnect performance and mass production cost of packaging substrates are facing multiple stringent requirements.

[0003] Current mainstream packaging substrate solutions all have significant shortcomings: First, the thermal expansion coefficients of the substrate and copper layer of traditional organic multilayer substrates differ greatly, making large-size substrates prone to irreversible warping deformation, leading to reliability issues such as solder joint cracking and signal transmission degradation. Second, organic substrates generally have low thermal conductivity, which cannot meet the heat dissipation requirements of high-power chips, easily causing chip heat accumulation, frequency reduction, and shortened lifespan. Third, existing 2.5D bridging packaging mostly relies on silicon interposer solutions, which require high processing precision, have complex processes, and have high mass production costs, making it difficult to meet the comprehensive requirements of high wiring density, efficient heat dissipation, and low warping. Fourth, conventional packaging solutions embed a single type of functional chip, making it difficult to simultaneously meet the diverse needs of high-speed interconnection and active function integration, resulting in insufficient system integration. Fifth, it is difficult to balance performance improvement and cost control in high-end computing power packaging, which restricts large-scale application.

[0004] In summary, existing technologies cannot simultaneously meet the core requirements of high thermal conductivity, low warpage, high trace density, multi-functional integration, and low-cost mass production, which has become a technological bottleneck restricting the large-scale application of high-end computing power packaging. Summary of the Invention

[0005] This invention proposes an organic ceramic packaging substrate structure and manufacturing method for embedded bridging chips, aiming to solve the technical problem that high thermal conductivity, low warpage, high wiring density and low cost mass production cannot be achieved simultaneously in existing packaging substrate solutions.

[0006] In a first aspect, the present invention provides an organic ceramic packaging substrate for embedded bridging chips, comprising: A ceramic core board includes a ceramic substrate, a ceramic core board filler filling the through holes of the ceramic substrate, and an electroplated copper coating layer covering the upper and lower surfaces of the ceramic substrate and interconnected with the copper layer of the through hole wall. The upper and lower surfaces of the ceramic substrate are electrically interconnected through the through holes and the ceramic core board filler inside them. The electroplated copper coating layer has a semi-covered structure and has interconnected pads on its surface. An ABF / PP / PI composite layer is stacked on the upper and lower surfaces of the ceramic core board. It is composed of multiple layers of ABF / PP / PI dielectric layers. Each ABF / PP / PI dielectric layer has a metal trace layer on its outer side. Adjacent metal trace layers are electrically interconnected through solid copper pillars in blind vias. A solder mask layer covers the outermost ABF / PP / PI dielectric layer; The surface pads are located outside the solder mask layer and are electrically interconnected with the metal trace layer through solid copper pillars inside the blind vias. A slot is provided in the upper ABF / PP / PI composite layer, the bottom of the slot exposes the metal trace layer, a metal layer boss is provided at the bottom of the slot, and a bridging chip is embedded in the slot; High-bandwidth memory and computing chip are flip-chip mounted on the surface pads, and the back of the high-bandwidth memory and computing chip are connected to the heat sink via TIM adhesive. The back of the substrate is provided with a power supply structure, on which IPD passive devices, SiC chips or GaN chips are provided.

[0007] Furthermore, the ceramic core board filler is a solid structure with full copper plating. The solid structure with full copper plating is formed by directly plating the through hole with an electroplating process. The copper layer on the hole wall of the through hole, the ceramic core board filler, and the electroplated copper coating layer are an integral electroplated structure.

[0008] Furthermore, the ceramic core board filler includes a copper layer on the hole wall and a filler body. The hole wall of the through hole is formed with a copper layer, and the space inside the through hole located inside the copper layer is filled with an insulating filler or a conductive filler.

[0009] Furthermore, the bridging chip is a silicon bridging chip or a glass bridging chip. The silicon bridging chip or the glass bridging chip is mounted in the slot through a DAF film. The back side of the silicon bridging chip or the glass bridging chip is attached to the metal layer boss. The interconnect surface of the silicon bridging chip or the glass bridging chip is provided with chip pads. The chip pads are electrically interconnected with the metal trace layer through the blind via.

[0010] Furthermore, the bridging chip is a silicon 3D bridging chip or a glass 3D bridging chip. The silicon 3D bridging chip or the glass 3D bridging chip has through-silicon vias or through-glass vias inside. The silicon 3D bridging chip or the glass 3D bridging chip is bonded and interconnected with the metal layer bosses by conductive adhesive. The interconnection surface of the silicon 3D bridging chip or the glass 3D bridging chip has chip pads. The chip pads are electrically interconnected with the metal trace layer through the blind vias.

[0011] Furthermore, the bridging chip is an active chip, which is mounted in the slot using a DAF film or conductive adhesive. The back side of the active chip is attached to the metal layer boss, and the interconnect surface of the active chip is provided with chip pads. The chip pads are electrically interconnected with the metal trace layer through the blind via.

[0012] Furthermore, the ABF / PP / PI composite layer on the upper side has one or more slots, and any one or more of the following are embedded in the slots: silicon bridging chip or glass bridging chip, silicon three-dimensional bridging chip or glass three-dimensional bridging chip, and active chip. The silicon bridging chip or glass bridging chip is mounted in the corresponding slot by a DAF film, the silicon three-dimensional bridging chip or glass three-dimensional bridging chip is mounted in the corresponding slot by conductive adhesive, and the active chip is mounted in the corresponding slot by a DAF film or conductive adhesive.

[0013] Furthermore, the ceramic substrate is made of any one of alumina, aluminum nitride, silicon nitride, silicon carbide, or diamond.

[0014] Secondly, the present invention provides a method for fabricating an organic ceramic packaging substrate for an embedded bridge chip, the method being used to fabricate the organic ceramic packaging substrate for the embedded bridge chip, comprising: A ceramic substrate is provided, and the ceramic substrate is ground, cleaned, and dried. A plurality of through holes are processed on the ceramic substrate, and a copper layer is formed on the hole wall and both sides of the ceramic substrate. The copper layer on both sides is patterned by a subtractive process to form a semi-covered electroplated copper film layer. Ceramic core board filler is filled into the through holes to obtain a ceramic core board. Multiple ABF / PP / PI dielectric layers are symmetrically laminated on the upper and lower surfaces of the ceramic core board. Metal trace layers are prepared on the outside of each ABF / PP / PI dielectric layer. Blind vias are processed and solid copper pillars are formed in the blind vias to achieve electrical interconnection between the metal trace layers. Slots are processed at preset positions and metal layer bosses are prepared at the bottom of the slots. The bridging chip is mounted in the slots and the top ABF / PP / PI dielectric layer is laminated. A solder resist layer is formed on the outermost ABF / PP / PI dielectric layer surface, and surface pads are prepared on the outside of the solder resist layer; a high-bandwidth memory and a computing chip are flip-chip mounted on the surface pads, and IPD passive devices, SiC chips or GaN chips are mounted on the back power supply structure on the back of the substrate. A thermal interface material is coated on the back of the high-bandwidth memory and the computing chip and a heat sink is attached.

[0015] The technical effects of this invention are: (1) Using high thermal conductivity ceramic material as the ceramic substrate, through holes are processed on the ceramic substrate in a regular pattern, and a copper layer is formed on the hole wall. Ceramic core board filler is filled into the through holes, and a semi-covering electroplated copper film layer is formed on the upper and lower surfaces of the ceramic substrate. The copper layer on the hole wall of the through hole is interconnected with the electroplated copper film layer to realize the electrical interconnection of the upper and lower surfaces of the ceramic core board. High thermal conductivity ceramic itself has high thermal conductivity and low coefficient of thermal expansion. Using it as the core board can provide an efficient heat conduction path and anti-warping structure for the composite substrate. The metallization of the through holes enables the ceramic core board to undertake the functions of heat conduction and support while also having the ability to vertically transmit electrical signals, avoiding the increase in cost and process complexity caused by setting an additional silicon interposer. (2) An ABF / PP / PI composite layer consisting of multiple ABF / PP / PI dielectric layers is symmetrically stacked on the upper and lower surfaces of the ceramic core board. Metal trace layers are set on the outside of each ABF / PP / PI dielectric layer. The adjacent metal trace layers are electrically interconnected through solid copper pillars in blind vias. The ABF / PP / PI dielectric layer has excellent film-forming properties and planarization capabilities, and is suitable for fabricating fine-width / spacing metal trace layers and micro-blind via interconnection structures on its surface and inside, thereby achieving high-density wiring. The symmetrical stacking on the upper and lower surfaces causes the ABF / PP / PI composite layers on both sides to generate symmetrical thermal stress distribution during thermal cycling. This works in conjunction with the central rigid ceramic core board to effectively offset interlayer thermal stress and significantly suppress the warping deformation of the overall substrate. (3) A slot is set in the upper ABF / PP / PI composite layer, exposing the metal trace layer at the bottom of the slot. A metal layer bump is set on the metal trace layer at the bottom of the slot. The bridging chip is placed in the slot, so that the back of the bridging chip is tightly attached to the metal layer bump. The chip pads on the interconnect surface of the bridging chip are electrically interconnected with the metal trace layer through blind holes inside the ABF / PP / PI composite layer. The heat of the bridging chip is conducted to the ceramic core board through the metal layer bump and the metal trace layer, forming a dedicated downward heat conduction path to achieve in-situ heat dissipation of the bridging chip. High-speed signals can be transmitted between the bridging chip and the surface flip chip through short-distance wiring in the ABF / PP / PI composite layer, effectively reducing signal transmission loss and delay. (4) The high-bandwidth memory and computing chip on the surface are mounted on the surface pads using a flip-chip process. The back of the high-bandwidth memory and computing chip are connected to the heat sink via a thermal interface material. Heat is dissipated upwards through the thermal interface material and the heat sink, which together with the aforementioned downward heat conduction path to the ceramic core board constitutes a bidirectional heat dissipation architecture, reducing the overall thermal resistance of the package and alleviating the heat accumulation problem of high-power chips. Attached Figure Description

[0016] Figure 1 A schematic diagram of the cross-section of a solid, fully copper-plated ceramic core plate. Figure 2A schematic diagram of a cross-section of a ceramic core plate with copper-plated hole walls and internal filler structure; Figure 3 A schematic diagram of the cross-section of an organic ceramic packaging substrate for silicon-bridged chips or glass-bridged chips embedded bridged chips; Figure 4 A schematic diagram of the cross-section of an organic ceramic packaging substrate for a silicon 3D bridging chip or a glass 3D bridging chip type embedded bridging chip; Figure 5 A schematic diagram of the cross-section of the organic ceramic packaging substrate for an active chip-type embedded bridge chip; Figure 6 A schematic diagram of a cross-section of a multi-bridged chip-type organic ceramic packaging substrate; Figure 7 Top view of a multi-bridged chip-type organic ceramic packaging substrate embedded; Figure 8 This is a top view of a multi-bridge chip-type organic ceramic packaging substrate.

[0017] The meanings of the labels in the figures are as follows: 001 - Organic ceramic packaging substrate; 100 - Ceramic core board; 104 - Ceramic substrate; 210 - Electroplated copper coating layer; 230 - Blind via; 240 - Metal trace layer; 241 - Metal layer boss; 250 - Surface pad; 300 - ABF / PP / PI composite layer; 310 - Ceramic core board filler; 320 - ABF / PP / PI dielectric layer; 330 - Solder resist layer; 401 - Thermal interface material (TIM adhesive); 42 0 - DAF film (chip mounting film); 430 - Conductive adhesive; 510 - Silicon bridging chip or glass bridging chip; 520 - Silicon 3D bridging chip or glass 3D bridging chip; 530 - IPD passive device / SiC chip or GaN chip; 540 - Active chip; 550 - High bandwidth memory (HBM); 560 - Computing chip; 601 - Through silicon via / Through glass via (TSV / TGV); 602 - Chip pad. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This invention addresses the technical challenge mentioned in the background section regarding the inability to simultaneously achieve high thermal conductivity, low warpage, high wiring density, and low-cost mass production in existing packaging substrate solutions. It provides an organic ceramic packaging substrate for embedded bridge chips, as referenced in the background section. Figures 1 to 8As shown in the accompanying drawings, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Example 1

[0020] This embodiment uses an embedded bridge chip organic ceramic package substrate 001 that integrates a silicon or glass bridge chip 510 with an active chip 540, corresponding to... Figure 3 , Figure 5 The structure shown uses a ceramic substrate 104 as the core to prepare a ceramic core board 100. A silicon bridging chip or glass bridging chip 510 and an active chip 540 are simultaneously embedded in the upper ABF / PP / PI composite layer 300. This structure is suitable for high-end computing power packaging scenarios that require 2.5D high-speed interconnection and active function integration.

[0021] In this embodiment, the ceramic substrate 104 is made of aluminum nitride 95 ceramic with a thickness of 0.5 mm and a thermal conductivity of 180 W / m·K. After grinding, cleaning, and drying pretreatment of the ceramic substrate 104, through holes with a diameter of 100 μm are machined using laser drilling technology. After drilling and cleaning, a full-hole copper plating process is performed, directly electroplating to completely fill the holes, forming the ceramic core board filler 310. At the same time, an integrated copper layer is formed on the upper and lower surfaces of the ceramic substrate 104. The copper layers on both sides are patterned using an etching subtraction process to form a semi-covered electroplated copper coating layer 210. Simultaneously, connecting pads are prepared to jointly constitute the conductive structure of the ceramic core board 100. In this embodiment, the ceramic core board filler 310 is a solid structure with full copper plating, corresponding to the integrated electroplated structure of the hole wall copper layer and the electroplated copper coating layer 210. Figure 1 The structure shown.

[0022] Four ABF / PP / PI composite layers 300 are symmetrically stacked on the upper and lower surfaces of the ceramic core board 100, with a trace spacing of 30μm for each ABF / PP / PI dielectric layer 320. The metal trace layers 240 are interconnected through blind vias 230 with a diameter of 50μm. A 20μm thick solid copper pillar is electroplated inside the blind via 230 to achieve low impedance electrical interconnection between layers.

[0023] During the fabrication of the upper ABF / PP / PI composite layer 300, three ABF / PP / PI dielectric layers 320 are first laminated and corresponding metal wiring layers 240 are fabricated. Grooves of suitable depth are machined at preset positions for both types of chips, with each groove reaching the surface of the second metal wiring layer 240. Metal layer bosses 241 are fabricated on the metal wiring layer 240 at the bottom of each groove using pattern electroplating. Embedded silicon bridging chips or glass bridging chips 510 and active chips 540 are then mounted in the corresponding grooves using a DAF film 420, ensuring a tight fit between the back of the chip and the metal layer bosses 241 to form a downward heat conduction path. Chip pads 602 are provided on the interconnect surfaces of both types of chips, and they are electrically interconnected with the metal wiring layer 240 through blind vias 230 inside the subsequent composite layer. After mounting, the uppermost ABF / PP / PI dielectric layer 320 is laminated, and top-level wiring and blind via fabrication are completed, achieving full embedded integration of the two types of chips.

[0024] The substrate has an overall size of 100mm and a warpage of 0.08% / mm. A solder resist layer 330 is applied to the outermost dielectric layer. Surface pads 250 are fabricated outside the solder resist layer 330, and these surface pads 250 are electrically interconnected with the inner metal trace layer 240 through solid copper pillars within blind vias 230. On the backside of the substrate, an IPD passive device, a SiC chip, or a GaN chip 530 is integrated into the backside power supply structure. The surface pads 250 are adapted for flip-chip mounting of the computing chip 560 and the high-bandwidth memory 550. The backsides of the high-bandwidth memory 550 and the computing chip 560 are coated with a thermal interface material 401, which, when bonded to the heat sink, forms a top heat dissipation path and, together with the downward heat dissipation path of the ceramic core board 100, forms a bidirectional heat dissipation architecture. The thermal interface material 401 is a TIM adhesive.

[0025] Based on the same inventive concept, this embodiment also provides a method for fabricating an organic ceramic packaging substrate for an embedded bridging chip, the fabrication steps of which are as follows: S1: Select aluminum nitride 95 ceramic substrate, and perform grinding, ultrasonic cleaning and drying treatment in sequence to ensure that the surface is flat and free of impurities; S2: Laser drilling technology is used to process through holes with a diameter of 100μm that are regularly distributed throughout the ceramic substrate 104, and the inside of the holes and the surface of the substrate are cleaned. S3: Perform full-hole copper plating process, directly fill the small holes completely by electroplating to form ceramic core board filler 310, and at the same time form continuous copper layer on the upper and lower surfaces of ceramic substrate 104. S4: The double-sided surface copper layer is patterned using an etching subtraction process to form a semi-covered electroplated copper film layer 210 and a connecting pad, thus producing a ceramic core board 100. S5: The first ABF / PP / PI dielectric layer 320 is symmetrically laminated on the upper and lower surfaces of the ceramic core board 100, and the corresponding metal trace layer 240 is prepared; blind holes 230 with a diameter of 50μm are processed, and 20μm thick solid copper pillars are formed by electroplating to realize the electrical interconnection between the surface traces and the ceramic core board 100. S6: Repeatedly press the dielectric layer, prepare the metal trace layer, process blind holes and electroplated copper pillars to complete the stacking of a total of 300 ABF / PP / PI composite layers, with patterned routing completed simultaneously for each layer; S7: Grooves are processed at preset positions of the bridging chip and the active chip respectively. The groove depth reaches the surface of the second metal trace layer 240. After cleaning the groove, the corresponding metal layer boss 241 is prepared on the metal trace layer 240 at the bottom of the groove by pattern electroplating. S8: The silicon bridging chip or glass bridging chip 510 and the active chip 540 are respectively mounted in the corresponding slots through the DAF film 420, so that the back of the chip is tightly attached to the metal layer protrusion 241, and the curing is completed. S9: Press the top ABF / PP / PI dielectric layer 320, process the corresponding blind vias and prepare the top metal trace layer 240 to achieve electrical interconnection between the two types of chip pads 602 and the inner layer traces; S10: A solder mask layer 330 is coated on the outermost dielectric layer surface, a surface pad 250 is prepared on the outside of the solder mask layer 330, and corresponding blind holes are processed to realize the electrical interconnection between the surface pad 250 and the inner metal trace layer 240. S11: IPD passive devices, SiC chips or GaN chips 530 are mounted on the power supply structure on the back of the substrate; high-bandwidth memory 550 and computing chip 560 are mounted on surface pad 250 using MCM flip-chip packaging process. S12: Coat the back of the high-bandwidth memory 550 and the computing chip 560 with thermal interface material 401, attach the heat sink and cure it to complete the overall packaging. Example 2

[0026] This embodiment uses an embedded bridge chip organic ceramic packaging substrate 001 with an embedded silicon three-dimensional bridge chip or a glass three-dimensional bridge chip 520, corresponding to... Figure 4 The structure shown embeds a silicon 3D bridge chip or a glass 3D bridge chip 520 within the upper ABF / PP / PI composite layer 300, making it suitable for high-end computing power packaging scenarios with ultra-high density 3D interconnects.

[0027] The core difference between this embodiment and Embodiment 1 is: The slot contains a silicon 3D bridging chip or a glass 3D bridging chip 520, with through-silicon vias or glass vias 601 inside the chip to achieve 3D signal interconnection. The chip is bonded and interconnected to the metal layer bosses 241 via conductive adhesive 430, achieving both mechanical fixation and electrical conduction. The chip pads 602 are electrically interconnected to the metal trace layer 240 via blind vias 230, working in conjunction with the internal through-silicon vias or glass vias 601 to achieve higher density 3D signal transmission and interconnection expansion.

[0028] The remaining structural components include a ceramic core board 100, a ceramic substrate 104, an electroplated copper coating layer 210, blind vias 230, a metal trace layer 240, metal layer bosses 241, surface pads 250, an ABF / PP / PI composite layer 300, ceramic core board filler 310, an ABF / PP / PI dielectric layer 320, a solder resist layer 330, a thermal interface material 401, IPD passive devices / SiC chips or GaN chips 530 on the back power supply structure, a high-bandwidth memory 550, a computing chip 560, etc. The material parameters, interconnect logic, and basic fabrication process are the same as in Example 1. Only the slot size, boss layout, and blind via alignment process parameters need to be adjusted according to the size of the three-dimensional bridging chip, the pad position, and the parameters of the through-silicon vias / glass vias. Example 3

[0029] This embodiment uses an embedded bridge chip organic ceramic package substrate 001 with an embedded active chip 540, corresponding to... Figure 5 The structure shown embeds only the active chip 540 within the upper ABF / PP / PI composite layer 300, making it suitable for packaging scenarios where active function integration is the core requirement and no bridging interconnection is needed.

[0030] The difference between this embodiment and Embodiment 1 is that only a single slot is provided within the upper ABF / PP / PI composite layer 300, and only the active chip 540 is mounted within the slot. The active chip 540 can be mounted within the slot using DAF film 420 or conductive adhesive 430. The mounting method is selected based on whether electrical connection is required on the back of the chip: if only heat conduction and mechanical fixation are required, DAF film 420 is used; if back-side electrical grounding or power supply is required, conductive adhesive 430 is used. The back of the chip is tightly bonded to the metal layer protrusion 241 to form a heat conduction path, and the chip pad 602 is electrically interconnected with the metal trace layer 240 through blind via 230 to achieve signal extraction.

[0031] The remaining structural components include a ceramic core board 100, a ceramic substrate 104, an electroplated copper coating layer 210, blind vias 230, a metal trace layer 240, metal layer bosses 241, surface pads 250, an ABF / PP / PI composite layer 300, a ceramic core board filler 310, an ABF / PP / PI dielectric layer 320, a solder resist layer 330, a thermal interface material 401, an IPD passive device / SiC chip or GaN chip 530 on the back power supply structure, a high-bandwidth memory 550, a computing chip 560, etc. The material parameters and manufacturing process are the same as in Example 1. Example 4

[0032] This embodiment uses a structure where the ceramic core board filler is made of copper-plated hole walls plus filler. Figure 2 The structure shown at the same time Figure 1 This example serves as a comparative reference for a fully copper-plated solid structure. The difference between this embodiment and Example 1 lies in the different methods of metallizing the small holes in the ceramic core plate 100.

[0033] In this embodiment, after laser drilling is completed, a copper layer is first electroplated on the hole wall and both sides of the ceramic substrate 104. Then, a subtractive process is used to pattern the copper layer on both sides to form a semi-covering electroplated copper film layer 210. Finally, the remaining space inside the hole is filled with an insulating filler such as resin or a conductive filler such as conductive paste to form the ceramic core board filler 310. This solution is suitable for applications where the cost of filling the hole is sensitive or where the dielectric properties inside the hole need to be adjusted.

[0034] The remaining structural components include a ceramic substrate 104, an electroplated copper coating layer 210, blind vias 230, a metal trace layer 240, metal layer bosses 241, surface pads 250, an ABF / PP / PI composite layer 300, an ABF / PP / PI dielectric layer 320, a solder resist layer 330, a thermal interface material 401, a DAF film 420, conductive adhesive 430, a silicon bridging chip or a glass bridging chip 510, an IPD passive device / SiC chip or GaN chip 530, an active chip 540, a high-bandwidth memory 550, a computing chip 560, and chip pads 602, etc. The material parameters and manufacturing process are the same as in Example 1.

[0035] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. An organic ceramic packaging substrate for embedded bridging chips, characterized in that, include: A ceramic core board (100) includes a ceramic substrate (104), a ceramic core board filler (310) filling the through holes of the ceramic substrate (104), and an electroplated copper coating layer (210) covering the upper and lower surfaces of the ceramic substrate (104) and interconnected with the copper layer of the through hole wall. The upper and lower surfaces of the ceramic substrate (104) are electrically interconnected through the through holes and the ceramic core board filler (310) inside them. The electroplated copper coating layer (210) has a semi-covered structure and has interconnected pads on its surface. An ABF / PP / PI composite layer (300) is stacked on the upper and lower surfaces of the ceramic core board (100), and is composed of multiple layers of ABF / PP / PI dielectric layers (320). Each layer of the ABF / PP / PI dielectric layer (320) has a metal trace layer (240) on its outer side, and adjacent metal trace layers (240) are electrically interconnected through solid copper pillars in blind vias (230). A solder mask layer (330) covers the outermost ABF / PP / PI dielectric layer (320); The surface pad (250) is located outside the solder mask layer (330) and is electrically interconnected with the metal trace layer (240) through the solid copper pillar in the blind hole (230); A slot is provided in the upper ABF / PP / PI composite layer (300), the bottom of the slot exposes the metal trace layer (240), a metal layer boss (241) is provided at the bottom of the slot, and a bridging chip is embedded in the slot; The high-bandwidth memory (550) and the computing chip (560) are flip-chip mounted on the surface pad (250), and the back sides of the high-bandwidth memory (550) and the computing chip (560) are connected to the heat sink via TIM adhesive (401). The back of the substrate is provided with a power supply structure, on which IPD passive devices, SiC chips or GaN chips (530) are provided.

2. The embedded bridging chip organic ceramic packaging substrate according to claim 1, characterized in that, The ceramic core board filler (310) is a solid structure with full copper plating. The solid structure with full copper plating is formed by electroplating the through hole directly. The copper layer of the hole wall, the ceramic core board filler (310) and the electroplated copper coating layer (210) are an integral electroplated structure.

3. The organic ceramic packaging substrate for embedded bridging chips according to claim 1, characterized in that, The ceramic core board filler (310) includes a copper layer on the hole wall and a filler body. The hole wall of the through hole is formed with a copper layer, and the space inside the through hole located inside the copper layer is filled with an insulating filler or a conductive filler.

4. The organic ceramic packaging substrate for embedded bridging chips according to claim 1, characterized in that, The bridging chip is a silicon bridging chip or a glass bridging chip (510). The silicon bridging chip or the glass bridging chip (510) is mounted in the slot through a DAF film (420). The back side of the silicon bridging chip or the glass bridging chip (510) is attached to the metal layer boss (241). The interconnect surface of the silicon bridging chip or the glass bridging chip (510) is provided with chip pads (602). The chip pads (602) are electrically interconnected with the metal trace layer (240) through the blind via (230).

5. The organic ceramic packaging substrate for embedded bridging chips according to claim 1, characterized in that, The bridging chip is a silicon 3D bridging chip or a glass 3D bridging chip (520). The silicon 3D bridging chip or the glass 3D bridging chip (520) has silicon vias or glass vias (601) inside. The silicon 3D bridging chip or the glass 3D bridging chip (520) is bonded and interconnected with the metal layer boss (241) through conductive adhesive (430). The interconnection surface of the silicon 3D bridging chip or the glass 3D bridging chip (520) has chip pads (602). The chip pads (602) are electrically interconnected with the metal trace layer (240) through the blind vias (230).

6. The organic ceramic packaging substrate for embedded bridging chips according to claim 1, characterized in that, The bridging chip is an active chip (540). The active chip (540) is mounted in the slot using a DAF film (420) or conductive adhesive (430). The back side of the active chip (540) is attached to the metal layer boss (241). The interconnect surface of the active chip (540) is provided with chip pads (602). The chip pads (602) are electrically interconnected with the metal trace layer (240) through the blind via (230).

7. The organic ceramic packaging substrate for embedded bridging chips according to claim 1, characterized in that, The ABF / PP / PI composite layer (300) on the upper side has one or more slots. The slots are embedded with any one or more of the following: silicon bridging chip or glass bridging chip (510), silicon three-dimensional bridging chip or glass three-dimensional bridging chip (520), and active chip (540). The silicon bridging chip or glass bridging chip (510) is attached to the corresponding slot through DAF film (420). The silicon three-dimensional bridging chip or glass three-dimensional bridging chip (520) is attached to the corresponding slot through conductive adhesive (430). The active chip (540) is attached to the corresponding slot through DAF film (420) or conductive adhesive (430).

8. The organic ceramic packaging substrate for embedded bridging chips according to claim 1, characterized in that, The ceramic substrate (104) is made of any one of alumina, aluminum nitride, silicon nitride, silicon carbide, or diamond.

9. A method for fabricating an organic ceramic packaging substrate for embedded bridging chips, characterized in that, The manufacturing method is used to manufacture the organic ceramic packaging substrate for the embedded bridge chip according to any one of claims 1-8, comprising: A ceramic substrate (104) is provided, and the ceramic substrate (104) is ground, cleaned and dried. A plurality of through holes are processed on the ceramic substrate (104), and a copper layer is formed on the hole wall of the through holes and on both sides of the ceramic substrate (104). The copper layer on both sides is patterned by a subtractive process to form a semi-covering electroplated copper film layer (210). The through holes are filled with ceramic core board filler (310) to obtain a ceramic core board (100). Multilayer ABF / PP / PI dielectric layers (320) are symmetrically laminated on the upper and lower surfaces of the ceramic core board (100). Metal trace layers (240) are prepared on the outside of each ABF / PP / PI dielectric layer (320). Blind vias (230) are processed and solid copper pillars are formed in the blind vias (230) to achieve electrical interconnection between the metal trace layers (240). A slot is processed at a preset position and a metal layer boss (241) is prepared at the bottom of the slot. The bridging chip is mounted in the slot and the top ABF / PP / PI dielectric layer (320) is laminated. A solder resist layer (330) is formed on the outermost ABF / PP / PI dielectric layer (320), and a surface pad (250) is prepared on the outside of the solder resist layer (330). A high-bandwidth memory (550) and a computing chip (560) are flip-chip mounted on the surface pad (250). An IPD passive device, a SiC chip, or a GaN chip (530) is mounted on the back power supply structure on the back of the substrate. A thermal interface material (401) is coated on the back of the high-bandwidth memory (550) and the computing chip (560), and a heat sink is attached.

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