Power module and manufacturing method thereof, electronic device

Abstract

The embodiment of the application provides a kind of power module and its manufacturing method, electronic equipment, it is related to power semiconductor technical field.Power module first sets up power chip on the composite substrate with conductive, insulating and heat conducting layer, and forms chip external connection by lead-out structure, then utilizes chip package piece to complete local encapsulation;Subsequently, the obtained chip packaging assembly is embedded in the through slot of the core plate, and a power packaging layer that integrates the power lead-out structure is formed on the outside.The scheme can shorten the electrical circuit, reduce the parasitic parameter, improve the heat conduction capacity, and improve the packaging structure strength, manufacturing adaptability and long-term operation reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a power module and its manufacturing method, and an electronic device. Background Technology

[0002] In high-power-density applications such as electric drive systems for new energy vehicles, photovoltaic inverters, and data center power supplies, power semiconductor modules need to achieve high efficiency, high reliability, and high integration under high-frequency switching conditions.

[0003] In related technologies, power module packaging typically employs PCB embedded technology, which involves directly placing bare chips or thin plastic-encapsulated chips into pre-processed cavities or semi-cured layers within the inner layers of a multilayer printed circuit board (PCB). Subsequently, a high-temperature and high-pressure lamination process is used to cure the resin and encapsulate the chip. Laser-formed blind holes or micro-holes with copper plating are then used to achieve electrical interconnection between the chip and the traces on the inner layers of the PCB.

[0004] However, because the embedded power chips are extremely sensitive to foreign objects and surface cleanliness, this process places extremely high demands on the cleanliness level of PCB manufacturing workshops, forcing traditional production lines to undergo large-scale modifications, resulting in poor compatibility with existing production lines and seriously hindering large-scale production. Summary of the Invention

[0005] This application provides a power module and its manufacturing method, as well as an electronic device, to reduce the requirements of the factory environment during chip packaging and improve the compatibility of power module manufacturing with existing production lines.

[0006] In a first aspect, embodiments of this application provide a power module, including:

[0007] A chip packaging assembly includes a substrate, a chip, a chip lead-out structure, and a chip package. The chip is disposed on one side of the substrate. The chip lead-out structure is connected to both the chip and the substrate. The chip package covers the chip, a portion of the substrate, and a portion of the chip lead-out structure. The external terminals of the chip lead-out structure are exposed in the chip package.

[0008] A core board, wherein the core board has a groove extending through the core board along the thickness direction, and the chip packaging assembly is disposed in the groove;

[0009] A power package that encapsulates the chip and the chip packaging assembly, wherein the power package has a power lead-out structure and the external terminals of the power lead-out structure are exposed outside the power package.

[0010] In one possible implementation, the substrate includes a conductive layer, an insulating layer, and a thermally conductive layer stacked sequentially, the chip has at least two external terminals, at least one of the external terminals is located on the side of the chip close to the substrate and is connected to the conductive layer, and at least a portion of the thermally conductive layer is exposed outside the chip package.

[0011] In one possible implementation, the multiple external terminals of the chip lead structure exposed outside the chip package are arranged in a U-shape with inner and outer sleeves or in a crisscross pattern with intervals.

[0012] In one possible implementation, the chip includes a first external terminal and a second external terminal, the first external terminal being located on the side of the chip close to the conductive layer and connected to the conductive layer, and the second external terminal being located on the side of the chip away from the substrate.

[0013] The chip lead-out structure includes a first chip lead-out component and a second chip lead-out component. The first chip lead-out component is connected to the conductive layer, and the second chip lead-out component is connected to the second external terminal.

[0014] The external terminals of the first chip lead and the second chip lead are exposed outside the chip package.

[0015] In one possible implementation, the core plate has opposing first and second surfaces along the thickness direction;

[0016] The external terminal of the chip lead-out structure is flush with the first surface; and / or, the surface of the thermal conductive layer on the side opposite to the chip is flush with the second surface.

[0017] In one possible implementation, the chip includes a power terminal, a reference terminal, and a control terminal;

[0018] The power terminal is located on the side of the chip close to the conductive layer and is connected to the conductive layer, forming the first external terminal of the chip; the reference terminal and the control terminal are both spaced apart on the side of the chip away from the substrate, forming different second external terminals;

[0019] The chip lead-out structure includes a power chip lead-out component, which is connected to the conductive layer to form the first chip lead-out component;

[0020] The chip lead-out structure includes a reference chip lead-out and a control chip lead-out. The reference chip lead-out is connected to the reference terminal, and the control chip lead-out is connected to the control terminal. The reference chip lead-out and the control chip lead-out respectively form different second chip lead-outs.

[0021] In one possible implementation, the chip packaging assembly contains a plurality of chips, which are arranged in an array at intervals along the surface direction of the substrate.

[0022] Multiple chips are connected in parallel through the chip lead-out structure;

[0023] The power terminals of the plurality of chips are all connected to the conductive layer, and the conductive layer is connected to at least one of the first chip leads;

[0024] The reference terminals of the multiple chips are connected in parallel through different reference chip leads; the control terminals of the multiple chips are connected in parallel through different control chip leads.

[0025] In one possible implementation, there are multiple chip packaging components, and the core board has multiple slots, which are spaced apart along the surface direction of the core board.

[0026] Multiple chip packaging components are disposed one-to-one in multiple slots;

[0027] The chips in the multiple chip packaging assemblies are connected in series.

[0028] In one possible implementation, the power lead-out structure includes a power lead-out, a reference lead-out, a control lead-out, a first intermediate lead-out, and a second intermediate lead-out;

[0029] The two chip packaging assemblies connected in series include a first chip packaging assembly and a second chip packaging assembly, wherein the power terminal of the chip in the first chip packaging assembly is connected to the power lead-out component;

[0030] The reference terminal of the chip in the first chip package assembly is connected to the power terminal of the chip in the second chip package assembly via the first intermediate lead-out, and the reference terminal of the chip in the second chip package assembly is connected to the reference lead-out.

[0031] The control terminal of the chip in the first chip package assembly and the control terminal of the chip in the second chip package assembly are connected through the second intermediate lead-out and connected to the control lead-out.

[0032] In one possible implementation, the power package includes a first power packaging layer and a first conductive layer. The first power packaging layer is disposed on a first surface of the core board, and the first conductive layer is disposed on the side of the first power packaging layer opposite to the core board. The first conductive layer is connected to the chip lead-out structure to form the power lead-out structure.

[0033] In one possible implementation, the power package further includes a second power package layer and a heat dissipation layer, the second power package layer being disposed on a second surface of the core board, the heat dissipation layer being disposed on the side of the second power package layer facing away from the core board, and the heat dissipation layer being thermally connected to the thermally conductive layer.

[0034] In one possible implementation, the power package further includes a third power package layer and a third conductive layer, the third power package layer being disposed on the first conductive layer to seal the first conductive layer, the third conductive layer being disposed on the side of the third power package layer opposite to the core board, and the third conductive layer being connected to the first conductive layer to form the control lead-out.

[0035] In one possible implementation, the core board includes a core board substrate and a fourth conductive layer and a fifth conductive layer disposed on both sides of the core board substrate in the thickness direction.

[0036] The reference chip lead-out, the control chip lead-out, and the power chip lead-out are formed in the fourth conductive layer;

[0037] The thermally conductive layer is formed in the fifth conductive layer.

[0038] In one possible implementation, the thickness of the heat dissipation layer is greater than the thickness of the first conductive layer.

[0039] In one possible implementation, the thickness of the second power packaging layer is greater than the thickness of the first power packaging layer.

[0040] In one possible implementation, a heat sink is provided on the side of the heat dissipation layer opposite to the core plate.

[0041] Secondly, embodiments of this application provide a method for manufacturing a power module, used to prepare the aforementioned power module, the preparation method comprising:

[0042] A core board is provided, and a groove is formed in the core board, the groove penetrating the core board along the thickness direction;

[0043] A chip packaging assembly is provided, and the chip packaging assembly is installed in the tray. The chip packaging assembly includes a substrate, a chip, a chip lead-out structure, and a chip package. The substrate includes a conductive layer, an insulating layer, and a thermally conductive layer stacked sequentially. The chip is disposed on one side of the conductive layer of the substrate. The chip lead-out structure is connected to the chip and the conductive layer respectively. The chip package covers the chip, part of the substrate, and part of the chip lead-out structure. The external terminals of the chip lead-out structure are exposed in the chip package.

[0044] A power package is formed, which encapsulates the chip and the chip packaging assembly. The power package contains a power lead-out structure, and the external terminals of the power lead-out structure are exposed outside the power package.

[0045] Thirdly, embodiments of this application also provide an electronic device, including the power module described above.

[0046] The power module provided in this application embodiment, by setting a chip packaging assembly including a substrate, a chip, a chip lead-out structure, and a chip package, and placing the chip packaging assembly in a through slot of a core board, and externally encapsulating the chip and chip packaging assembly with a power package and setting a power lead-out structure, can form a module packaging structure with clear layers and high integration. This shortens the chip-related interconnection paths and optimizes the electrical connection and heat conduction relationship inside the module, thereby helping to reduce parasitic parameters, improve heat dissipation capacity, and improve the structural stability and manufacturing assembly reliability of the module. Furthermore, by first pre-packaging the chip, substrate, and chip lead-out structure with the chip package to form a package, the requirements for the engineering environment in subsequent operations are reduced, and the compatibility of the power module manufacturing with existing production lines is improved. Attached Figure Description

[0047] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0048] Figure 1 This is a structural cross-sectional view of the chip packaging assembly in the power module provided in this application;

[0049] Figure 2 A schematic diagram of a chip packaging component in a power module provided in this application;

[0050] Figure 3 A schematic diagram of another chip packaging component in the power module provided in this application;

[0051] Figure 4 A schematic diagram of the structure in which the chip packaging components are disposed within the core board in the power module provided in this application;

[0052] Figure 5 This is a cross-sectional view of the power module after its first lamination, as provided in this application.

[0053] Figure 6 A complete structural cross-sectional view of the power module provided in this application;

[0054] Figure 7 A flowchart illustrating the manufacturing method of the power module provided in this application.

[0055] Explanation of reference numerals in the attached figures:

[0056] 10. Chip packaging assembly; 100. Substrate; 110. Conductive layer; 120. Insulating layer; 130. Thermally conductive layer; 200. Chip; 300. Chip lead-out structure; 360. Power chip lead-out component; 370. Reference chip lead-out component; 380. Control chip lead-out component; 400. Chip package assembly; 410. First blind via;

[0057] 20. Core board; 201. Scouring groove; 202. First surface; 203. Second surface; 204. Fourth conductive layer; 205. Fifth conductive layer; 206. Core board substrate;

[0058] 30. Power package; 302. First power package layer; 303. First conductive layer; 304. Second power package layer; 305. Heat dissipation layer; 306. Third power package layer; 307. Third conductive layer; 308. Second blind via; 309. Third blind via; 310. Fourth blind via;

[0059] 40. Radiator.

[0060] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0061] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0062] Power semiconductor packaging technology is widely used in high-power-density devices such as electric drive systems for new energy vehicles, photovoltaic inverters, and data center power supplies to achieve electrical connections, insulation support, and heat dissipation for power chips. Existing power modules typically employ discrete or embedded packaging solutions, placing the power chip on a substrate or circuit board. Connections between the chip and external circuits are achieved through leads, metal layers, or interlayer conductive structures, while the package provides insulation protection and mechanical fixation, simultaneously transferring heat to the heat dissipation path. This type of solution can meet general power conversion requirements, but in high-frequency, high-power-density scenarios, the connection path between the chip and external circuits is often long, and maintaining a symmetrical circuit layout is difficult.

[0063] Due to the long interconnect paths and complex spatial distribution, parasitic inductance is prone to increase, leading to overvoltage, oscillation, and additional losses during switching. When multiple chips are connected in parallel, inconsistent drive response and deteriorated dynamic current sharing may also occur. At the same time, the heat dissipation path in the existing structure usually passes through many intermediate layers, resulting in high thermal resistance and difficulty in timely heat dissipation. In addition, the board-level stack-up and packaging structure are prone to warping or insufficient reliability during manufacturing, which ultimately affects the module assembly accuracy, yield, and long-term operational stability.

[0064] In view of this, in order to solve the above problems, this application provides a power module, which sets up a chip packaging assembly including a substrate, a chip, a chip lead-out structure and a chip package, and sets the chip packaging assembly in the slot of the core board, and then combines it with a power package that covers the chip and the chip packaging assembly and has a power lead-out structure, thereby realizing the synergistic integration of chip-level packaging and module-level packaging, thus providing a basis for reducing parasitic parameters, optimizing thermal management and improving manufacturing adaptability.

[0065] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0066] This application provides a power module, referring to... Figure 1 , Figure 5 and Figure 6 The power module includes a chip packaging assembly 10, a core board 20, and a power package 30.

[0067] The chip packaging assembly 10 includes a substrate 100, a chip 200, a chip lead-out structure 300, and a chip package 400. The chip 200 is disposed on one side of the substrate 100. The chip lead-out structure 300 is connected to both the chip 200 and the substrate 100. The chip package 400 covers the chip 200, a portion of the substrate 100, and a portion of the chip lead-out structure 300. The external terminals of the chip lead-out structure 300 are exposed in the chip package 400. The core board 20 has a slot 201 extending through the core board 20 along its thickness direction. The chip packaging assembly 10 is disposed within the slot 201. The power package 30 covers the chip 200 and the chip packaging assembly 10. The power package 30 contains a power lead-out structure, and the external terminals of the power lead-out structure are exposed in the power package 30.

[0068] Reference Figure 1The chip packaging assembly 10 is a packaging unit that integrates the power chip 200, substrate 100, chip lead-out structure 300, and local packaging layer into one unit. It serves as the electrical connection, insulation support, and local heat dissipation path for the chip 200, and acts as the basic unit for subsequent module-level packaging. The chip 200, substrate 100, and chip lead-out structure 300 are initially packaged by the chip packaging component 400 to form a package, thereby reducing the environmental requirements for subsequent operations and improving the compatibility of power module manufacturing with existing production lines. It also allows the chip packaging assembly 10 to undergo separate electrical performance and insulation withstand voltage tests before being embedded in the core board 20, screening out defective products and improving the final module yield.

[0069] For example, chip 200 can be an IGBT (Insulated Gate Bipolar Transistor) chip 200, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) chip 200, or a diode chip 200. Specifically, it can be a SiC MOSFET chip 200 or a GaN HEMT chip 200.

[0070] The substrate 100 includes a conductive layer 110, an insulating layer 120, and a thermally conductive layer 130 stacked sequentially. The chip 200 has at least two external terminals, at least one of which is located on the side of the chip 200 closest to the substrate 100 and connected to the conductive layer 110. At least a portion of the thermally conductive layer 130 is exposed outside the chip package 400. Multiple external terminals of the chip lead-out structure 300 exposed outside the chip package 400 are arranged in a U-shape with inner and outer sleeves or in a crisscross pattern with intervals.

[0071] For example, the substrate 100 is used to electrically support the chip 200 and transfer the heat generated by the chip 200 to the underlying structure. The substrate 100 includes a conductive layer 110, an insulating layer 120 and a thermally conductive layer 130 stacked in sequence. The conductive layer 110 is disposed facing the chip 200 and connected to the chip lead-out structure 300. The insulating layer 120 is located between the conductive layer 110 and the thermally conductive layer 130 to achieve electrical isolation. The thermally conductive layer 130 is arranged facing the external heat dissipation direction to form a heat conduction channel.

[0072] In one possible embodiment, the conductive layer 110 can be a copper layer, an aluminum layer, or a silver-plated copper layer; the insulating layer 120 can be a ceramic layer, a resin layer, or a polymer insulating layer; and the thermally conductive layer 130 can be a metal heat dissipation layer 305, a ceramic thermally conductive layer 130, or a composite thermally conductive layer 130. The thicknesses of the conductive layer 110, the insulating layer 120, and the thermally conductive layer 130 can be matched according to current carrying capacity, insulation distance, and thermal resistance requirements. The thickness of the insulating layer 120 must meet electrical isolation requirements, while the thickness of the thermally conductive layer 130 is coordinated with the length of the heat dissipation path and mechanical strength. In this application, the base layer is an aluminum nitride (AMB) structure, whose high bending strength and high thermal conductivity balance mechanical reliability and heat dissipation performance, and can withstand the high-pressure and high-temperature environment of subsequent lamination processes.

[0073] For example, the power package 30 can be formed by single-layer molding, double-layer molding, or partial encapsulation, and the material can be epoxy molding compound, silicone, or high-temperature resistant composite potting material.

[0074] For example, the chip package 400 can be formed using epoxy molding compound, silicone, potting compound, or thermosetting composite encapsulation material, and its encapsulation method can be integral molding, partial dispensing encapsulation, or partitioned potting. The chip package 400 is used to provide insulation protection, mechanical fixation, and define local electrical interfaces for the chip 200. The chip package 400 covers the upper surface and sides of the chip 200, while also covering a portion of the substrate 100 and partially encapsulating the chip lead structure 300, but leaving the external terminals of the chip lead structure 300 exposed to form connection windows for subsequent module-level packaging.

[0075] In one possible implementation, the chip 200 includes a first external terminal and a second external terminal. The first external terminal is located on the side of the chip 200 close to the conductive layer 110 and is connected to the conductive layer 110. The second external terminal is located on the side of the chip 200 away from the substrate 100.

[0076] The chip lead-out structure 300 includes a first chip lead-out and a second chip lead-out. The first chip lead-out is connected to the conductive layer 110, and the second chip lead-out is connected to a second external terminal. The external terminals of the first chip lead-out and the second chip lead-out are exposed in the chip package 400.

[0077] The first external terminal and the second external terminal of the chip 200 are respectively disposed on both sides of the chip 200 along its thickness direction. The first external terminal is the power input port of the chip 200. The second external terminal can be configured as multiple, and the multiple second external terminals are arranged at intervals. The second external terminal can be the output and / or control port of the chip 200.

[0078] Correspondingly, the chip lead-out structure 300 and the first and second external terminals of the chip 200 are respectively configured as a first chip lead-out and a second chip lead-out. The first external terminal of the chip 200 is soldered to the conductive layer 110 of the substrate 100, and the first chip lead-out is soldered to the conductive layer 110 to realize the lead-out of the first external terminal of the chip 200, and at least part of the first chip lead-out is exposed outside the chip package 400. The second chip lead-out is directly connected to the second external terminal of the chip 200, and at least part of the second chip lead-out is exposed outside the chip package 400 to realize the lead-out of the second external terminal of the chip 200.

[0079] Both the first chip lead-out and the second chip lead-out can be solder pads, and the solder pads can be copper layer structures.

[0080] In one possible implementation, refer to Figure 5 The core board 20 has a first surface 202 and a second surface 203 opposite to each other along the thickness direction. The external terminal of the chip lead-out structure 300 is flush with the first surface 202; and / or, the surface of the thermal conductive layer 130 on the side opposite to the chip 200 is flush with the second surface 203.

[0081] The core board 20 has a through groove 201 extending along the thickness direction, which allows the chip packaging assembly 10 to be embedded in the groove 201 and form a mating positioning relationship with the core board 20. The external end of the chip lead-out structure 300 is flush with the first surface 202, and / or the surface of the thermal conductive layer 130 facing away from the chip 200 is flush with the second surface 203, so that the core board 20 can provide a flat mating reference when assembled with external circuit boards, heat sinks 40 or other power devices. The flush arrangement of the external terminals of the chip lead-out structure 300 with the first surface 202 allows external pads, crimp terminals, or interconnecting metal parts to be directly exposed on the upper surface of the core board 20 at the same height, thereby reducing the step difference after packaging and facilitating stable connection with external circuits via soldering, reflow soldering, conductive adhesive bonding, or bonding. The flush arrangement of the surface of the thermally conductive layer 130 facing away from the chip 200 with the second surface 203 ensures that the back of the core board 20 is on the same plane as the thermal interface, which is beneficial for forming a fully fitted heat transfer contact surface between the power module and the heat sink, cooling plate, or thermal pad, reducing interface thermal resistance and improving the heat flow output path. Furthermore, the chip packaging assembly 10 is completely integrated into the core board 20, achieving full utilization of the space in the thickness direction of the core board 20. The flush arrangement of the thermally conductive layer 130 of the substrate 100 with the second surface 203 of the core board 20 provides a flat contact interface for subsequent back-side heat dissipation paths.

[0082] In one possible implementation, chip 200 includes a power terminal, a reference terminal, and a control terminal. The power terminal is located on the side of chip 200 close to the conductive layer 110 and is connected to the conductive layer 110, forming a first external terminal of chip 200; the reference terminal and the control terminal are both spaced apart on the side of chip 200 away from the substrate 100, forming different second external terminals.

[0083] Reference Figure 1 The chip lead-out structure 300 includes a power chip lead-out 360, which is connected to the conductive layer 110 to form a first chip lead-out. The chip lead-out structure 300 also includes a reference chip lead-out 370 and a control chip lead-out 380. The reference chip lead-out 370 is connected to a reference terminal, and the control chip lead-out 380 is connected to a control terminal. The reference chip lead-out 370 and the control chip lead-out 380 respectively form different second chip lead-outs.

[0084] The power terminal, reference terminal, and control terminal constitute three types of external electrodes with different functions. The power terminal carries the main power circuit current, the reference terminal provides a potential reference or sampling reference, and the control terminal receives drive signals or feedback signals, thereby spatially separating the high-current path and low-current signal path of the chip 200. The power terminal is located on the side of the chip 200 closest to the conductive layer 110 and is electrically connected to the conductive layer 110 by welding, sintering, conductive adhesive connection, or metal interconnection. The main current is directly led out to the substrate 100 through the conductive layer 110, thereby reducing the current transmission path length. The reference terminal and control terminal are located on the side of the chip 200 away from the substrate 100. They are arranged alternately to avoid unnecessary crosstalk between the control signal and the reference signal, and they each constitute different second external terminals for docking with external drive circuits, detection circuits, or protection circuits.

[0085] The chip 200 can be a power MOSFET, a SiC (Silicon Carbide) MOSFET, an IGBT, or a composite power device with drive and detection terminals. In the example of this application, the chip 200 is a MOSFET, with the power terminal of the chip 200 being the drain, the reference terminal of the chip 200 being the source, and the control terminal of the chip 200 being the gate.

[0086] For example, the chip lead-out structure 300 can be a pad or a metal clip structure. In the example of this application, the power chip lead-out 360 is a drain pad or a drain metal clip, the reference chip lead-out 370 is a source pad or a source metal clip, and the control chip lead-out 380 is a gate pad or a gate metal clip.

[0087] In one possible implementation, the chip packaging assembly 10 contains a plurality of chips 200, which are arranged in an array at intervals along the surface of the substrate 100; the plurality of chips 200 are connected in parallel through chip lead-out structures 300; the power terminals of the plurality of chips 200 are all connected to the conductive layer 110, and the conductive layer 110 is connected to at least one first chip lead-out; the reference terminals of the plurality of chips 200 are connected in parallel through different reference chip lead-outs 370; and the control terminals of the plurality of chips 200 are connected in parallel through different control chip lead-outs 380.

[0088] Multiple chips 200 are integrated in an array-spaced manner within the chip packaging assembly 10. Their array arrangement along the surface of the substrate 100 creates a regular or semi-regular spatial distribution of the chips 200 within the plane, facilitating current sharing, heat dissipation, and symmetrical drive paths. When multiple chips 200 are connected in parallel via chip lead-out structures 300, these structures establish electrical connection channels between each chip 200 and external circuits, enabling the chips 200 to work collaboratively under identical or nearly identical drive conditions. The power terminals of multiple chips 200 are all connected to the conductive layer 110. The conductive layer 110 serves as a common bus layer, undertaking the main current transmission and reception function, and is connected to at least one first chip lead-out component, thereby leading the power-side signals of the multiple chips 200 out of the chip package 400. The reference terminals of the multiple chips 200 are connected in parallel through different reference chip leads 370 to form a common reference or reference circuit. The control terminals of the multiple chips 200 are connected in parallel through different control chip leads 380 to achieve unified driving or synchronous control of the control terminals of each chip 200. Through the above parallel connection, the multiple chips 200 can form an electrically cooperative working unit and reduce the stress concentration caused by a single chip 200 carrying excessive current.

[0089] In one possible embodiment, the plurality of chips 200 may be configured as two, four, six or more, arranged in a matrix array, linear array or staggered array on one side of the conductive layer 110 of the substrate 100.

[0090] For example, refer to Figure 2 When multiple chips 200 are arranged in an array or ring, the power chip lead-out 360, the reference chip lead-out 370 and the control chip lead-out 380 are arranged in a U-shape nested configuration. That is, in the example of this application, the drain pad, source pad and gate pad are arranged in a U-shape.

[0091] In other examples, refer to Figure 3, when a plurality of chips 200 are arranged in a single linear row, the power chip lead-out member 360, the reference chip lead-out member 370 and the control chip lead-out member 380 are nested in a "川" shape, that is, in the example of the present application, the drain pad, the source pad and the gate pad are arranged in a "川" shape.

[0092] For example, when the chip lead-out structure 300 is a pad, the chip 200 needs to be welded to the conductive layer 110 of the substrate 100 first, and the chip 200 and the substrate 100 are encapsulated and coated by the chip package 400. A plurality of first blind holes 410 are opened on a side surface of the chip package 400 close to the chip 200, the plurality of first blind holes 410 respectively communicate the source and the gate of the chip 200, and also communicate with the conductive layer 110, so that the drain pad passes through the first blind hole 410 to connect to the conductive layer 110, and the source pad and the gate pad pass through the first blind hole 410 to connect to the source and the gate of the core board 20 respectively.

[0093] In the process of manufacturing the chip packaging assembly 10 according to the present application, the drains of a plurality of chips 200 are welded to the conductive layer 110 of the substrate 100, so as to realize parallel connection of the drains of each chip 200. A plastic packaging material is used to encapsulate the welded structure, the plastic packaging material wraps the upper surface and four side surfaces of the AMB substrate 100 to form the chip package 400, then first blind holes 410 are formed on the chip package 400 at positions corresponding to the gates, sources and drains of each chip 200 by laser drilling, the gates of each chip 200 are collectively led out to the same gate pad on the surface of the chip package 400, the source and the drain are respectively led out to corresponding pads on the upper surface, so as to form the chip packaging assembly 10. True parallel driving and single-point grounding are achieved, and the gate paths of each chip 200 are highly symmetrical, which is beneficial to dynamic current sharing.

[0094] For example, a browned layer is arranged on the surface of the chip package 400, and the browned layer is formed by a browning treatment to increase the surface roughness and improve the friction between the chip packaging assembly 10 and the groove 201.

[0095] In a possible embodiment, with reference to Figure 4 , there are a plurality of chip packaging assemblies 10, a plurality of grooves 201 are arranged on the core board 20, and the plurality of grooves 201 are arranged at intervals along the board surface direction of the core board 20; the plurality of chip packaging assemblies 10 are arranged in the plurality of grooves 201 in a one-to-one correspondence; the chips 200 in the plurality of chip packaging assemblies 10 are connected in series with each other.

[0096] Multiple chip packaging components 10 are correspondingly disposed within multiple slots 201 of the same core board 20, forming a series packaging unit array extending along the board surface. Each chip packaging component 10 is a sub-unit that can be independently manufactured and tested, and is then assembled by being embedded into a separate slot 201 on the core board 20. When multiple slots 201 are spaced apart along the board surface of the core board 20, gaps are typically maintained between the slots 201 for insulation, heat dissipation, and processing compensation. The shape of the slots 201 can be rectangular, elongated, or stepped, and can also be locally chamfered or positioned according to the outline of the chip packaging component 10 to improve the embedding positioning accuracy.

[0097] In one possible implementation, the power lead-out structure includes a power lead-out, a reference lead-out, a control lead-out, a first intermediate lead-out, and a second intermediate lead-out.

[0098] The two chip packaging components 10 connected in series include a first chip packaging component and a second chip packaging component. The power terminal of the chip 200 of the first chip packaging component is connected to a power lead.

[0099] The reference terminal of the chip 200 of the first chip package assembly is connected to the power terminal of the chip 200 of the second chip package assembly through a first intermediate lead, and the reference terminal of the chip 200 of the second chip package assembly is connected to the reference lead.

[0100] The control terminal of chip 200 in the first chip package assembly and the control terminal of chip 200 in the second chip package assembly are connected through a second intermediate lead-out and connected to a control lead-out.

[0101] The power lead, reference lead, and control lead are used to connect to the external bus, reference potential terminal, and control drive terminal, respectively. The first intermediate lead and the second intermediate lead are used to establish a cascaded potential transfer channel between the two chip package assemblies 10. The power lead typically corresponds to the main current input terminal of the series system. One end of the power lead is connected to the power terminal of the chip 200 of the first chip package assembly, and the other end is exposed on the surface of the power package 30 for external circuit access. The reference lead is used to output the reference potential of the second chip package assembly and serve as the potential reference interface of the series system. The control lead is used to lead the control signal to the two chip package assemblies 10 to ensure that they maintain synchronous control when operating in series. The first intermediate lead is disposed between the reference terminal of the first chip package assembly and the power terminal of the second chip package assembly. Its function is to transfer the output potential of the front-end chip package assembly 10 to the input potential of the rear-end chip package assembly 10. The second intermediate lead is disposed between the control terminal of the first chip package assembly and the control terminal of the second chip package assembly, and is connected to the control lead to realize parallel or synchronous driving of the control terminals of the two-stage chips 200. This enables the power series connection and control docking of the series-connected chips 200 to be completed within a limited package space, thereby shortening the external connection path and reducing loop stray parameters.

[0102] In one possible embodiment, the power lead, reference lead, control lead, first intermediate lead, and second intermediate lead can be defined as metal conductors in different functional areas. The power lead is used to carry a large operating current, the reference lead is used to carry a relatively stable reference current or potential connection, and the control lead is used to transmit gate or drive control signals. The first intermediate lead and the second intermediate lead are respectively used to form a relay-type cascade connection between the two chip package assemblies 10.

[0103] Because the power circuit has high requirements for conductivity and thermal stability, the power leads are generally located near the edge of the power package 30 or its external port, forming a low-impedance connection with the power terminal of the first chip package assembly. The reference lead is typically located on the other side or corresponding to the second chip package assembly to form a relatively independent reference path. The control lead can be located between the power leads and the reference lead, or at different locations on different layers, to balance signal integrity and package compactness. The first intermediate lead connects the reference terminal of the first chip package assembly and the power terminal of the second chip package assembly, and the second intermediate lead connects the control terminals of the two chip package assemblies 10 and further leads to the control lead, thus forming an integrated series power supply and control interface. This allows series current and control signals to be transmitted across components within a shorter path, reducing the need for cross-wiring.

[0104] In one possible embodiment, the power leads, reference leads, control leads, and first and second intermediate leads can be one or more combinations of copper busbars, metal sheets, pad bridges, copper-plated vias, or flexible conductor structures, or can be made of copper, aluminum, nickel / tin surface-treated parts, or composite conductor materials. The power leads preferably have a large cross-sectional area and low resistance, for example, they can be formed into wide plate-like, stepped, or thickened busbar-like structures to accommodate higher series currents. The reference and control leads can be made into narrow sheet-like, lead-like, or thin-film conductor shapes to meet the needs of potential sampling and control signal transmission. The first and second intermediate leads can be further made into narrow bridge-like, short-circuited strip structures, interlayer conductive pillar structures, or flexible bridging structures, wherein the first intermediate lead emphasizes low inductance and low resistance, and the second intermediate lead emphasizes the synchronization and anti-interference capability of the control signal.

[0105] In this example, the external power supply first enters the power terminal of the chip 200 of the first chip package assembly via the power lead-out component. Then, after the current completes the switching control inside the first chip package assembly, it is transmitted to the power terminal of the chip 200 of the second chip package assembly via the first intermediate lead-out component. Then, it flows back to its reference terminal inside the second chip package assembly and forms an external reference loop through the reference lead-out component, thereby forming a series power channel between the two chip package assemblies 10.

[0106] In one possible implementation, refer to Figure 5 and Figure 6 The power package 30 includes a first power package layer 302 and a first conductive layer 303. The first power package layer 302 is disposed on the first surface 202 of the core board 20. The first conductive layer 303 is disposed on the side of the first power package layer 302 away from the core board 20. The first conductive layer 303 is connected to the chip lead-out structure 300 to form a power lead-out structure.

[0107] The first power packaging layer 302 is a packaging medium layer disposed on the upper side of the core board 20 and used to cover and protect the chip lead-out structure 300 and its local area. It provides electrical insulation, mechanical fixation and environmental protection for the upper structure of the power module, and provides a stable bearing foundation for the subsequent deployment of the first conductive layer 303.

[0108] For example, the first power encapsulation layer 302 can be a molding compound, epoxy resin, silicone, polyimide layer, modified polymer potting compound, or multilayer composite encapsulation material. In the example of this application, the first power encapsulation layer 302 can be a prepreg, which is hot-pressed onto the first surface 202 of the core board 20.

[0109] For example, a first conductive layer 303 is disposed on the side of the first power packaging layer 302 opposite to the core board 20, and the first conductive layer 303 is used to form a power lead-out structure. In the example of this application, the first conductive layer 303 is a copper foil layer. After the first conductive layer 303 is disposed on the first power packaging layer 302, it is patterned to form a power lead-out structure.

[0110] For example, a plurality of second blind vias 308 are provided on the first power packaging layer 302, penetrating the first power packaging layer 302. The second blind vias 308 are disposed along the thickness direction of the first power packaging layer 302. Power lead-out structures pass through the second blind vias 308 and connect to the corresponding chip lead-out structures 300, thereby realizing the lead-out of each electrode of the chip 200. Furthermore, vertical interconnect paths are formed on the first power packaging layer 302 by laser drilling, further reducing parasitic inductance.

[0111] In the example of this application, after the core board 20 and the chip packaging assembly 10 are encapsulated by the first power packaging layer 302, a second blind hole 308 is formed by laser drilling. Then, the second blind hole 308 is filled by electroplating to connect the chip lead-out structure 300 and the first conductive layer 303. The first conductive layer 303 is then patterned to form the power lead-out structure.

[0112] In one possible implementation, the power package 30 further includes a second power package layer 304 and a heat dissipation layer 305. The second power package layer 304 is disposed on the second surface 203 of the core board 20, and the heat dissipation layer 305 is disposed on the side of the second power package layer 304 away from the core board 20. The heat dissipation layer 305 is thermally connected to the thermally conductive layer 130.

[0113] For example, the second power packaging layer 304 is disposed on the second surface 203 of the core board 20, and cooperates with the first power packaging layer 302 to seal and fix the core board 20 and the chip packaging assembly on the core board 20, forming an insulating seal. The heat dissipation layer 305 is disposed on the side of the second power packaging layer 304 away from the core board 20 and is connected to the thermally conductive layer 130, thereby drawing away heat from the substrate 100 and improving the heat dissipation effect of the chip packaging assembly 10.

[0114] For example, the second power packaging layer 304 can be a prepreg, which is hot-pressed onto the second surface 203 of the core board 20. The second power packaging layer 304 has a plurality of third blind vias 309 penetrating it. The third blind vias 309 are arranged along the thickness direction of the second power packaging layer 304. The heat dissipation layer 305 can be a copper foil layer, which is laminated onto the second power packaging layer 304. The heat dissipation layer 305 passes through the third blind vias 309 and connects to the thermally conductive layer 130, thereby enabling heat dissipation from the chip packaging assembly 10.

[0115] For example, the thickness of the first power packaging layer 302 and the second power packaging layer 304 is 50-100 μm. The thickness of the first conductive layer 303 and the third conductive layer 307 can be 35 μm.

[0116] In the example of this application, after the core board 20 and the chip packaging assembly 10 are encapsulated by the second power packaging layer 304, a third blind hole 309 is formed by laser drilling, and then the third blind hole 309 is filled by electroplating to connect the heat dissipation layer 305 and the heat conduction layer 130.

[0117] In one possible implementation, a heat sink 40 is disposed on the side of the heat dissipation layer 305 facing away from the core board 20. The heat sink 40 is directly soldered or sintered to the outer surface of the heat dissipation layer 305. Since the substrate 100 itself provides internal electrical insulation, and the thermally conductive layer 130 is isolated from the outside through the side of the molding compound and the core board 20, and the heat dissipation layer 305 is at a safe potential (typically the drain potential), the heat sink 40 can be directly connected to the heat dissipation layer 305 without the need for an additional insulating sheet, significantly reducing thermal resistance. Heat is efficiently dissipated from the power chip 200 via the conductive layer 110, insulating layer 120, thermally conductive layer 130, heat dissipation layer 305, and heat sink 40, achieving efficient heat dissipation in the vertical direction.

[0118] In one possible implementation, the power package 30 further includes a third power package layer 306 and a third conductive layer 307. The third power package layer 306 is disposed on the first conductive layer 303 to seal the first conductive layer 303. The third conductive layer 307 is disposed on the side of the third power package layer 306 away from the core board 20. The third conductive layer 307 is connected to the first conductive layer 303 and forms a control lead-out.

[0119] For example, the third power encapsulation layer 306 is a prepreg, disposed on the side of the first conductive layer 303 away from the core board 20, insulating and sealing the first conductive layer 303. The third conductive layer 307 is disposed on the side of the third power encapsulation layer 306 away from the core board 20, and is used to form a power lead-out structure. In the example of this application, the third conductive layer 307 is a copper foil layer, and after being disposed on the third power encapsulation layer 306, it is patterned to form the power lead-out structure.

[0120] For example, a plurality of fourth blind vias 310 penetrating the third power packaging layer 306 are provided on the third power packaging layer 306. The fourth blind vias 310 are disposed along the thickness direction of the third power packaging layer 306. Power lead-out structures pass through the fourth blind vias 310 and connect to the first conductive layer 303. Furthermore, vertical interconnect paths are formed on the third power packaging layer 306 by laser drilling, further reducing parasitic inductance. In the example of this application, the first conductive layer 303 is the power layer of the chip 200, and the first conductive layer 303 forms power leads and reference leads to carry the main power circuit with high current and high voltage. The third conductive layer 307 forms control leads to form weak current signal circuits such as driving, protection, and sampling. The layered arrangement of power leads and control leads, through physical isolation and electromagnetic shielding, suppresses electromagnetic interference and noise coupling of control signals caused by transient current and rapid voltage changes during power switching. This ensures accurate timing of drive signals and reliable sampling data, thereby improving the module's dynamic response performance, anti-interference capability, and system stability under high-frequency switching. At the same time, it facilitates the separate optimization of the low-inductance design of the power circuit and the high-density integration of the control circuit, achieving a synergistic improvement in power density and reliability.

[0121] In the example of this application, after the first conductive layer 303 is encapsulated by the third power packaging layer 306, a fourth blind hole 310 is formed by laser drilling. Then, the fourth blind hole 310 is filled by electroplating to connect the third conductive layer 307 and the first conductive layer 303. The third conductive layer 307 is then patterned to form a control lead-out.

[0122] In one possible implementation, the core board 20 includes a core board substrate 206 and a fourth conductive layer 204 and a fifth conductive layer 205 disposed on both sides of the core board substrate 206 in the thickness direction; a reference chip lead-out 370, a control chip lead-out 380 and a power chip lead-out 360 are formed in the fourth conductive layer 204; and a thermally conductive layer 130 is formed in the fifth conductive layer 205.

[0123] In this application, the fourth conductive layer 204 of the core board substrate 206 is disposed on one surface along the thickness direction of the core board substrate 206, and the fifth conductive layer 205 is disposed on the other surface along the thickness direction of the core board substrate 206. These two layers respectively perform the functions of electrical lead-out and heat dissipation, thereby enabling the core board 20 to simultaneously handle signal / power transmission and heat dissipation within the same supporting structure. The power lead-out structure can be partially formed in the fourth conductive layer 204 of the core board 20, providing partial conductive paths for the electrode leads and series connections of the chip packaging assembly 10. In the example of this application, the core board 20 is a PCB board.

[0124] In one possible embodiment, the core substrate 206 may be made of FR-4 fiberglass epoxy board, high Tg epoxy fiberglass board, polyimide board, metal-based insulating board or ceramic substrate; the fourth conductive layer 204 and the fifth conductive layer 205 may be made of copper foil layer, aluminum foil layer, nickel copper composite layer or metallized deposition layer.

[0125] For example, the gap between the sidewall of the scouring groove 201 and one side of the chip packaging assembly 10 is 50 μm to 150 μm.

[0126] In one possible implementation, the thickness of the heat dissipation layer 305 is greater than the thickness of the first conductive layer 303.

[0127] Furthermore, the thickness of the heat dissipation layer 305 is greater than the thickness of the third conductive layer 307. The thickness of the first conductive layer 303 is equal to the thickness of the third conductive layer 307.

[0128] For example, the thickness of the heat dissipation layer 305 can be 1.5 to 2 times the thickness of the first conductive layer 303.

[0129] In one possible implementation, the thickness of the second power packaging layer 304 is greater than the thickness of the first power packaging layer 302.

[0130] Furthermore, the thickness of the first power packaging layer 302 is equal to the thickness of the third power packaging layer 306.

[0131] For example, the thickness of the second power encapsulation layer 304 can be twice that of the first power encapsulation layer 302. That is, the first power encapsulation layer 302 and the third power encapsulation layer 306 use a single layer of prepreg, while the second power encapsulation layer 304 is composed of two layers of prepreg stacked together.

[0132] In other examples, the thickness of the second power packaging layer 304 can also be 1.5 to 3 times the thickness of the first power packaging layer 302.

[0133] On one side of the first surface 202 of the core board 20, a first power packaging layer 302 and a first conductive layer 303, as well as a third power packaging layer 306 and a third conductive layer 307 are stacked sequentially. On one side of the second surface 203 of the core board 20, a second power packaging layer 304 and a heat dissipation layer 305 are stacked. The thickness of the heat dissipation layer 305 is greater than the thickness of the first conductive layer 303 and the third conductive layer 307, thus forming an asymmetrical layer structure. The thicker second power packaging layer 304 and heat dissipation layer 305 provide stronger support for the lamination and subsequent processing of the power module, thereby reducing the warpage of the power module. The core board 20 has a chip packaging assembly 10 and a fourth conductive layer 204 and a fifth conductive layer 205. Their combined thermal expansion characteristics are balanced with the combination of the second power packaging layer 304 and the heat dissipation layer 305 below the core board 20, effectively suppressing the warpage deformation of the overall module during high lamination temperature and subsequent thermal cycling.

[0134] This application also provides a method for manufacturing a power module, used to prepare the power module described above, referring to... Figure 7 The preparation methods include:

[0135] S1, a core board 20 is provided, and a groove 201 is formed on the core board 20, the groove 201 penetrating the core board 20 along the thickness direction.

[0136] S2, a chip packaging assembly 10 is provided and installed in the slot 201. The chip packaging assembly 10 includes a substrate 100, a chip 200, a chip lead-out structure 300, and a chip package 400. The substrate 100 includes a conductive layer 110, an insulating layer 120, and a thermally conductive layer 130 stacked sequentially. The chip 200 is disposed on one side of the conductive layer 110 of the substrate 100. The chip lead-out structure 300 is connected to the chip 200 and the conductive layer 110 respectively. The chip package 400 covers the chip 200, part of the substrate 100, and part of the chip lead-out structure 300. The external terminals of the chip lead-out structure 300 are exposed in the chip package 400.

[0137] S3, forming a power package 30, which encapsulates the chip 200 and the chip package assembly 10. The power package 30 has a power lead-out structure inside, and the external terminals of the power lead-out structure are exposed outside the power package 30.

[0138] In step S2, the conductive layer 110 of the substrate 100 is patterned to form a pre-fabricated circuit pattern, including drain pads for soldering chips 200 and transition pads for leading out the source and gate. The drains of multiple chips 200 are soldered onto the conductive layer 110 of the substrate 100, achieving parallel connection of the drains of each chip 200. The soldered structure is encapsulated using a molding compound, which covers the upper surface and four sides of the AMB substrate 100 to form a chip package 400. Blind vias are then formed on the chip package 400 corresponding to the gate, source, and drain positions of each chip 200 using laser drilling. The gates of each chip 200 are uniformly led out to the same gate pad on the surface of the chip package 400, and the source and drain are led out to their corresponding pads on the upper surface, forming a chip package assembly 10.

[0139] In step S1, the inner wall of the scouring tank 201 and the outer surface of the chip packaging assembly 10 also need to be browned and plasma cleaned. The chip packaging assembly 10 is then buried in the scouring tank 201 so that the side of the thermal conductive layer 130 of the chip packaging assembly 10 facing away from the chip 200 is flush with the second surface 203 of the core board 20.

[0140] In step S3, a first power packaging layer 302 and a first conductive layer 303 are sequentially stacked on the first surface 202 of the core board 20 and the upper surface of the chip packaging assembly 10. At least two layers of prepreg and copper foil are sequentially stacked on the second surface 203 of the core board 20 and the heat-conducting layer 130 exposed at the bottom of the chip packaging assembly 10 to form a second power packaging layer 304 and a heat dissipation layer 305. The thickness of the heat dissipation layer 305 is greater than the thickness of the first conductive layer 303. This is a single lamination process.

[0141] In the first lamination process, the aforementioned laminated structure is placed in a laminator and laminated at a temperature of 180-200℃ and a pressure of 2.0-3.5MPa for 60-90 minutes. During lamination, the resin in each prepreg melts and flows, filling the gap between the core board 20 and the chip packaging assembly 10, as well as the unevenness of the upper surface of the chip packaging assembly 10, thus achieving a strong bond between the layers.

[0142] First, the first conductive layer 303 and the heat dissipation layer 305 are patterned to form a power lead-out structure.

[0143] Then, a second blind hole 308 is formed by laser drilling at the position of the gate pad, source pad and drain pad in the chip package assembly 10 corresponding to the first power package layer, penetrating the first power package layer 302, and electroplating to fill it, so as to realize the vertical lead-out of the electrode.

[0144] Then, a third power packaging layer 306 and a third conductive layer 307 are sequentially laminated on the first conductive layer 303 for secondary lamination. The third conductive layer 307 is then patterned to form a circuit layer. The second lamination can use the same process parameters as the first lamination, or a slightly lower temperature (170-190°C) can be used to reduce thermal shock to the formed structure. After lamination, the third conductive layer 307 is patterned to form control leads. If necessary, a fourth blind via 310 can be fabricated through the third power packaging layer 306 to lead control signals from the first conductive layer 303 to the third conductive layer 307.

[0145] Finally, the heat sink 40 is directly soldered or sintered onto the outer surface of the heat dissipation layer 305. The heat sink 40 is a liquid-cooled microchannel copper block with a microchannel width of 200μm to 500μm. The soldering method uses silver sintering or high-lead solder, with a soldering temperature of 250-300℃. Since the substrate 100 itself provides insulation, the heat sink 40 can be directly at the drain potential without the need for an additional insulating sheet, thus reducing thermal resistance.

[0146] In some examples, a partial area of ​​the second power packaging layer 304 between the second surface 203 of the core board 20 and the thermally conductive layer 130 of the chip packaging assembly has an array of thermally conductive vias. These vias are filled with a conductive and thermally conductive material during the first lamination, forming a vertical thermal conduction path after lamination and curing. This directly conducts the heat from the chip packaging assembly to the heat dissipation layer 305, further reducing thermal resistance. The conductive and thermally conductive material can be copper paste or silver paste.

[0147] In the chip packaging assembly, the gate unified pad is located at the center on the side away from the substrate 100, and the source pad and drain pad are symmetrically distributed around the gate pad, which is beneficial to the symmetry of the circuit wiring of the first conductive layer 303 and the consistency of parasitic parameters.

[0148] This application also provides an electronic device including the power module described above.

[0149] This electronic device can be used as a power conversion device in new energy vehicle electric drive systems, photovoltaic inverters, or data center power supplies, with the power module integrated as a core power unit inside the device. Because the power module adopts a structure where the chip packaging component 10 and the power package 30 are co-integrated, and a compact arrangement is achieved through the slot 201 of the core board 20, the electrical interconnection path between the chip 200 and the external circuit is shortened, parasitic inductance and stray circuit parameters are reduced, and overvoltage, oscillation, and additional losses during high-frequency switching are suppressed, thereby improving the dynamic response consistency when multiple chips 200 are operating. Simultaneously, this power module optimizes the heat conduction conditions from the chip 200 to the external heat dissipation path, thus helping to reduce thermal resistance, improve heat dissipation efficiency, and reduce the risk of package warpage and interlayer bonding failure, thereby improving the assembly reliability, operational stability, and adaptability to high power density applications of the electronic device. Finally, it should be noted that other embodiments of this application will readily conceive of by those skilled in the art upon considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed in this application. It is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and alterations can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A power module, characterized in that, include: A chip packaging assembly (10) includes a substrate (100), a chip (200), a chip lead-out structure (300), and a chip package (400). The chip (200) is disposed on one side of the substrate (100). The chip lead-out structure (300) is connected to the chip (200) and the substrate (100) respectively. The chip package (400) covers the chip (200), part of the substrate (100), and part of the chip lead-out structure (300). The external terminals of the chip lead-out structure (300) are exposed in the chip package (400). A core board (20) is provided with a slot (201) extending through the core board (20) along the thickness direction, and the chip packaging assembly (10) is disposed in the slot (201); A power package (30) covers the chip (200) and the chip package assembly (10). The power package (30) has a power lead-out structure inside, and the external terminals of the power lead-out structure are exposed outside the power package (30).

2. The power module according to claim 1, characterized in that, The substrate (100) includes a conductive layer (110), an insulating layer (120), and a thermally conductive layer (130) stacked sequentially. The chip (200) has at least two external terminals, at least one of which is located on the side of the chip (200) close to the substrate (100) and connected to the conductive layer (110). At least a portion of the thermally conductive layer (130) is exposed outside the chip package (400).

3. The power module according to claim 1 or 2, characterized in that, The multiple external terminals of the chip lead structure (300) exposed outside the chip package (400) are arranged in a U-shape with inner and outer sleeves or in a crisscross shape with intervals.

4. The power module according to claim 2, characterized in that, The chip (200) includes a first external terminal and a second external terminal. The first external terminal is located on the side of the chip (200) close to the conductive layer (110) and is connected to the conductive layer (110). The second external terminal is located on the side of the chip (200) away from the substrate (100). The chip lead-out structure (300) includes a first chip lead-out and a second chip lead-out, wherein the first chip lead-out is connected to the conductive layer (110) and the second chip lead-out is connected to the second external terminal; The external terminals of the first chip lead and the second chip lead are exposed in the chip package (400).

5. The power module according to claim 2, characterized in that, The core plate (20) has a first surface (202) and a second surface (203) opposite each other along the thickness direction; The external terminal of the chip lead-out structure (300) is flush with the first surface (202); and / or, the surface of the thermal conductive layer (130) on the side opposite to the chip (200) is flush with the second surface (203).

6. The power module according to claim 4, characterized in that, The chip (200) includes a power terminal, a reference terminal, and a control terminal; The power terminal is located on the side of the chip (200) close to the conductive layer (110) and is connected to the conductive layer (110). The power terminal forms the first external terminal of the chip (200). The reference terminal and the control terminal are both spaced apart on the side of the chip (200) away from the substrate (100). The reference terminal and the control terminal form different second external terminals. The chip lead-out structure (300) includes a power chip lead-out component (360), which is connected to the conductive layer (110) to form the first chip lead-out component; The chip lead-out structure (300) includes a reference chip lead-out (370) and a control chip lead-out (380). The reference chip lead-out (370) is connected to the reference terminal, and the control chip lead-out (380) is connected to the control terminal. The reference chip lead-out (370) and the control chip lead-out (380) respectively form different second chip lead-outs.

7. The power module according to claim 6, characterized in that, The chip packaging assembly (10) contains a plurality of chips (200), which are arranged in an array at intervals along the surface direction of the substrate (100). Multiple chips (200) are connected in parallel through the chip lead-out structure (300); The power terminals of the plurality of chips (200) are all connected to the conductive layer (110), and the conductive layer (110) is connected to at least one of the first chip leads; The reference terminals of the plurality of chips (200) are connected in parallel through different reference chip leads (370); the control terminals of the plurality of chips (200) are connected in parallel through different control chip leads (380).

8. The power module according to claim 6, characterized in that, There are multiple chip packaging components (10), and there are multiple slots (201) on the core board (20). The multiple slots (201) are arranged at intervals along the board surface direction of the core board (20). Multiple chip packaging components (10) are disposed one-to-one in multiple slots (201); The chips (200) in the plurality of chip packaging assemblies (10) are connected in series.

9. The power module according to claim 8, characterized in that, The power lead-out structure includes a power lead-out component, a reference lead-out component, a control lead-out component, a first intermediate lead-out component, and a second intermediate lead-out component; The two chip packaging assemblies (10) connected in series include a first chip packaging assembly and a second chip packaging assembly, wherein the power terminal of the chip (200) of the first chip packaging assembly is connected to the power lead-out member; The reference terminal of the chip (200) of the first chip package assembly is connected to the power terminal of the chip (200) of the second chip package assembly through the first intermediate lead-out, and the reference terminal of the chip (200) of the second chip package assembly is connected to the reference lead-out. The control terminal of the chip (200) of the first chip package assembly and the control terminal of the chip (200) of the second chip package assembly are connected through the second intermediate lead-out and connected to the control lead-out.

10. The power module according to claim 9, characterized in that, The power package (30) includes a first power package layer (302) and a first conductive layer (303). The first power package layer (302) is disposed on the first surface (202) of the core board (20). The first conductive layer (303) is disposed on the side of the first power package layer (302) away from the core board (20). The first conductive layer (303) is connected to the chip lead-out structure (300) and forms the power lead-out structure.

11. The power module according to claim 10, characterized in that, The power package (30) further includes a second power package layer (304) and a heat dissipation layer (305). The second power package layer (304) is disposed on the second surface (203) of the core board (20). The heat dissipation layer (305) is disposed on the side of the second power package layer (304) away from the core board (20). The heat dissipation layer (305) is thermally connected to the thermally conductive layer (130).

12. The power module according to claim 11, characterized in that, The power package (30) further includes a third power package layer (306) and a third conductive layer (307). The third power package layer (306) is disposed on the first conductive layer (303) to seal the first conductive layer (303). The third conductive layer (307) is disposed on the side of the third power package layer (306) away from the core board (20). The third conductive layer (307) is connected to the first conductive layer (303) and forms the control lead-out.

13. The power module according to claim 6, characterized in that, The core board (20) includes a core board substrate (206) and a fourth conductive layer (204) and a fifth conductive layer (205) disposed on both sides of the core board substrate (206) in the thickness direction; The reference chip lead-out (370), the control chip lead-out (380), and the power chip lead-out (360) are formed in the fourth conductive layer (204); The thermally conductive layer (130) is formed in the fifth conductive layer (205).

14. The power module according to claim 11, characterized in that, The thickness of the heat dissipation layer (305) is greater than the thickness of the first conductive layer (303).

15. The power module according to claim 11, characterized in that, The thickness of the second power packaging layer (304) is greater than the thickness of the first power packaging layer (302).

16. The power module according to claim 11, characterized in that, A heat sink (40) is provided on the side of the heat dissipation layer (305) away from the core plate (20).

17. A method for manufacturing a power module, used to prepare a power module as described in any one of claims 1-16, characterized in that, The preparation method includes: A core board (20) is provided, and a scooping groove (201) is formed on the core board (20), the scooping groove (201) penetrating the core board (20) along the thickness direction; A chip packaging assembly (10) is provided and installed in the slot (201). The chip packaging assembly (10) includes a substrate (100), a chip (200), a chip lead-out structure (300), and a chip package (400). The substrate (100) includes a conductive layer (110), an insulating layer (120), and a thermally conductive layer (130) stacked sequentially. The chip (200) is disposed on one side of the conductive layer (110) of the substrate (100). The chip lead-out structure (300) is connected to the chip (200) and the conductive layer (110) respectively. The chip package (400) covers the chip (200), part of the substrate (100), and part of the chip lead-out structure (300). The external terminals of the chip lead-out structure (300) are exposed in the chip package (400). A power package (30) is formed, which covers the chip (200) and the chip package assembly (10). A power lead-out structure is provided inside the power package (30), and the external terminals of the power lead-out structure are exposed outside the power package (30).

18. An electronic device, characterized in that, Includes the power module as described in any one of claims 1-16.

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