Semiconductor package including redistribution substrate

Abstract

A semiconductor package according to an embodiment of the disclosure includes a package substrate, a redistribution substrate bonded to the package substrate by first bumping, and including a dielectric layer and a redistribution pattern, a first underfill layer filled in a space between the package substrate and the redistribution substrate, a semiconductor chip bonded to the redistribution substrate by second bumping, and a first molding layer disposed on the redistribution substrate and surrounding the semiconductor chip, wherein the dielectric layer includes a negative dielectric layer including polyimide at a mass ratio of 50% or more.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to semiconductor technology, and more specifically, to a semiconductor package including a redistributed substrate. Background Technology

[0002] A semiconductor chip includes an integrated circuit for storing or processing data. Additionally, a semiconductor chip includes chip pads for inputting data to the integrated circuit or outputting data from the integrated circuit to an external device. A semiconductor package is used to electrically connect the semiconductor chip to an external device.

[0003] Various methods can be applied to electrically connect chip pads to external devices. A redistribution substrate has a redistribution pattern that is electrically connected to the chip pads. In semiconductor packaging using a redistribution substrate, fan-out packaging is a technique that extends the redistribution pattern of the redistribution substrate beyond the area where the semiconductor chip is located and provides external connection terminals on the redistribution pattern. Fan-out packaging allows for high-density I / O (input / output) because the number and spacing of external connection terminals are not limited by the size of the semiconductor chip. Summary of the Invention

[0004] In one embodiment, a semiconductor package may include: a package substrate; a redistribution substrate bonded to the package substrate via a first bump and including a dielectric layer and a redistribution pattern; a first underfill layer filling the space between the package substrate and the redistribution substrate; a semiconductor chip bonded to the redistribution substrate via a second bump; and a first molding layer disposed on the redistribution substrate and surrounding the semiconductor chip, wherein the dielectric layer includes a negative tone dielectric layer comprising 50% or more polyimide by mass.

[0005] In one embodiment, a semiconductor package may include: a package substrate; a redistribution substrate bonded to the package substrate via a first bump and including a dielectric layer and a redistribution pattern; and a first semiconductor chip bonded to the redistribution substrate via a second bump, wherein the dielectric layer includes a negative dielectric layer comprising 50% or more polyimide by mass. Attached Figure Description

[0006] This disclosure will be more fully understood from the following detailed description and accompanying drawings, which are provided by way of illustration only and are not intended to limit the scope of this disclosure.

[0007] Figure 1 , Figure 2 , Figure 3 and Figure 4 This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0008] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0009] Crosshairs running through the figures indicate corresponding or similar areas between figures, rather than indicating material associated with these areas.

[0010] When a component is labeled “connected” or “linked” to another component, these components can be connected or linked directly or through an intermediate component between them. When two components are labeled “directly connected” or “directly linked”, one component is directly connected or directly linked to the other component without any intermediate component between them.

[0011] When one element is identified as being "above", "over", "below", or "below" another element, these elements may be in direct contact with each other, or an intermediate element may be placed between these elements.

[0012] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “down,” “under,” “above,” “on,” “side,” “upper,” “top,” “lowest,” “front,” “back,” “left,” “right,” “column,” “row,” and “height,” as well as other terms that suggest relative spatial relationships or orientations, are used for ease of description or reference to the accompanying drawings and are not intended to be limiting. Other spatial relationships or orientations not shown in the drawings or described in the specification are within the scope of this disclosure.

[0013] Terms such as “first” and “second” are used to distinguish between various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be referred to as the second element, and in another example, the second element may be referred to as the first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0014] In the description, when an element included in an embodiment is described in the singular, the element may be interpreted as including multiple elements that perform the same or similar functions.

[0015] Figure 1 This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure.

[0016] Reference Figure 1The semiconductor package 10 according to embodiments of the present disclosure includes a package substrate 100, a redistribution substrate 200, a first semiconductor chip 410, and a second semiconductor chip 420. The semiconductor package 10 according to embodiments of the present disclosure also includes a first molding layer 510, a second molding layer 520, a first bottom fill layer 610, and external connection terminals 700.

[0017] The packaging substrate 100 includes a substrate body 110, an upper substrate pad 120, a lower substrate pad 130, an upper insulating layer 140, and a lower insulating layer 150.

[0018] The substrate body 110 may include multiple insulating layers and multiple wirings. Although not shown, the multiple insulating layers may include a core insulating layer, a first substrate insulating layer disposed on the core insulating layer, and a second substrate insulating layer disposed below the core insulating layer. Each wiring may include a through-hole penetrating the core insulating layer, an upper conductive pattern disposed on the upper surface of the core insulating layer, and a lower conductive pattern disposed below the lower surface of the core insulating layer.

[0019] The core insulation layer may have a coefficient of thermal expansion from 2.5 ppm / °C to 19 ppm / °C (parts per million per degree Celsius). The core insulation layer may have a glass transition temperature (Tg) from 170°C to 240°C. The core insulation layer may have a Young's modulus from 10 GPa to 36 GPa (gigapascals). In embodiments, the coefficient of thermal expansion of a layer is a measure of the degree to which a material expands or contracts with temperature changes. For example, the coefficient of thermal expansion may be equal to the change in length divided by the product of the original length and the temperature change.

[0020] The first and second substrate insulating layers may include a prepreg (e.g., prepreg composite fibers). The first and second substrate insulating layers may have a coefficient of thermal expansion of 5 ppm / °C to 19 ppm / °C. The first and second substrate insulating layers may have a glass transition temperature of 160°C to 240°C. The first and second substrate insulating layers may have a Young's modulus of 12 GPa to 26 GPa.

[0021] The upper substrate pad 120 is disposed on the upper surface of the substrate body 110. The lower substrate pad 130 is disposed below the lower surface of the substrate body 110. The upper substrate pad 120 and the lower substrate pad 130 may be part of the circuit and / or wiring structure of the package substrate 100.

[0022] An upper insulating layer 140 is disposed on the upper surface of the substrate body 110 and is configured to expose the upper substrate pads 120. A lower insulating layer 150 is disposed below the lower surface of the substrate body 110 and is configured to expose the lower substrate pads 130.

[0023] The upper insulating layer 140 and the lower insulating layer 150 may include a photosensitive solder resist (PSR). The upper insulating layer 140 and the lower insulating layer 150 may have a coefficient of thermal expansion of 15 ppm / °C to 60 ppm / °C. The upper insulating layer 140 and the lower insulating layer 150 may have a glass transition temperature of 100°C to 160°C. The upper insulating layer 140 and the lower insulating layer 150 may have a Young's modulus of 3.3 GPa to 7.8 GPa.

[0024] The redistribution substrate 200 is mounted on the packaging substrate 100 via the first bump 310. The redistribution substrate 200 is electrically and physically connected to the packaging substrate 100 via the first bump 310.

[0025] The redistribution substrate 200 includes a dielectric layer 210 and a redistribution pattern 220. The redistribution substrate 200 may be a multilayer redistribution layer (RDL). The dielectric layer 210 may be composed of a negative dielectric (NTD) comprising 50% or more polyimide by mass.

[0026] The dielectric layer 210 may have a coefficient of thermal expansion of 20 ppm / °C to 50 ppm / °C. The glass transition temperature of the dielectric layer 210 may be higher than that of the first bottom filler layer 610. In one embodiment, the glass transition temperature of the dielectric layer 210 may be 200°C or higher. In other embodiments, the glass transition temperature of the dielectric layer 210 may be 200°C to 220°C. In one embodiment, the tensile strength of the dielectric layer 210 may be 500 MPa or higher. In other embodiments, the tensile strength of the dielectric layer 210 may be 500 MPa to 700 MPa (megapascals). In one embodiment, the elongation of the dielectric layer 210 may be 50% or higher. In other embodiments, the elongation of the dielectric layer 210 may be 70% or higher. In embodiments, the elongation of the dielectric layer may refer to the ability of a material to stretch or deform under tensile stress before fracture. In some embodiments, the elongation percentage is calculated as the difference between the length at fracture and the original length, divided by the original length, and then multiplied by 100. In embodiments, tensile strength refers to the maximum tensile stress a material can withstand before fracture or failure. For example, higher tensile strength means a stronger dielectric material that can resist greater forces without tearing or cracking. In embodiments, the glass transition temperature (Tg) of the dielectric layer is the temperature at which the material transitions from a rigid glassy state to a soft rubbery state. For example, below Tg, the layer is hard, rigid, and brittle. For example, above Tg, the layer becomes softer and more flexible and loses mechanical and dimensional stability. In embodiments, Tg indicates a phase transition in polymer behavior, rather than a solid-liquid change.

[0027] The redistribution pattern 220 can be a metallic wiring. The metallic wiring can include copper (Cu). Each redistribution pattern 220 includes via segments and wiring segments. The via segments can be components for vertical connections, and the wiring segments can be components for horizontal connections. The via segments vertically penetrate the corresponding dielectric layer 210. Wiring segments are disposed on the via segments and the dielectric layer 210. The width of the wiring segments can be greater than the width of the via segments. The via segments and wiring segments can be formed integrally.

[0028] The redistribution patterns 220 each include a first UBM pad 221, a second UBM pad 222, and a connection pattern 223. The first UBM pad 221 and the second UBM pad 222 may be disposed in the uppermost dielectric layer 210 and may extend to the upper surface of the uppermost dielectric layer 210. The upper surfaces of the first UBM pad 221 and the second UBM pad 222 may not be covered by the uppermost dielectric layer 210. The connection pattern 223 connects the first UBM pad 221 and the second UBM pad 222. The connection pattern 223 may not be exposed outside the uppermost dielectric layer 210. In an embodiment, the UBM pad may be an under-bump metallization pad.

[0029] The first bump 310 is disposed below the lower surface of the redistribution substrate 200. The first bump 310 is connected to the redistribution pattern 220 disposed in the lowermost dielectric layer 210 (for example, the lowermost dielectric layer may be as follows). Figure 1 The dielectric layer closest to the package substrate 100 is shown. The first bump 310 may be a solder layer or a stacked structure of a conductive pillar and a solder layer. The solder layer may include a tin-silver (Sn-Ag) alloy. The conductive pillar may include a metal different from the solder layer. The conductive pillar may include copper. The first bump 310 is bonded to the upper substrate pad 120 of the package substrate 100.

[0030] The first semiconductor chip 410 and the second semiconductor chip 420 comprise silicon as the primary component. The coefficient of thermal expansion of silicon is 2.6 ppm / °C to 3.0 ppm / °C. The first semiconductor chip 410 is bonded to the redistribution substrate 200 via a second bump 320. The first semiconductor chip 410 is electrically and physically connected to the redistribution substrate 200 via the second bump 320. The first semiconductor chip 410 includes a first silicon substrate and a first integrated circuit (not shown), and has a first chip pad 411 connected to the first integrated circuit on its lower surface facing the redistribution substrate 200. The second bump 320 is disposed below the first chip pad 411. The second bump 320 may be a solder layer or a stacked structure of conductive pillars and solder layers. The solder layer may include a tin-silver (Sn-Ag) alloy. The conductive pillars may include a metal different from the solder layer. The conductive pillars may include copper. The second bump 320 is bonded to a first UBM pad 221 of the redistribution substrate 200.

[0031] The second semiconductor chip 420 is bonded to the redistribution substrate 200 via a third bump 330. The second semiconductor chip 420 is electrically and physically connected to the redistribution substrate 200 via the third bump 330. The second semiconductor chip 420 includes a second silicon substrate and a second integrated circuit (not shown), and has a second chip pad 421 connected to the second integrated circuit on its lower surface facing the redistribution substrate 200. The third bump 330 is disposed below the second chip pad 421. The third bump 330 may be a solder layer or a stacked structure of conductive pillars and solder layers. The solder layer may include a tin-silver (Sn-Ag) alloy. The conductive pillars may include a metal different from the solder layer. The conductive pillars may include copper. The third bump 330 is bonded to a second UBM pad 222 of the redistribution substrate 200. The second chip pad 421 of the second semiconductor chip 420 can be connected to a first chip pad 411 of the first semiconductor chip 410 via the third bump 330, the second UBM pad 222, the connection pattern 223, the first UBM pad 221, and the second bump 320.

[0032] A first molding layer 510 is disposed on the redistribution substrate 200 and covers the first semiconductor chip 410 and the second semiconductor chip 420. The first molding layer 510 covers the side surfaces of the first semiconductor chip 410 and the second semiconductor chip 420. The first molding layer 510 may expose the upper surfaces of the first semiconductor chip 410 and the second semiconductor chip 420. The upper surface of the first molding layer 510 may be positioned on the same plane as the upper surfaces of the first semiconductor chip 410 and the second semiconductor chip 420.

[0033] The first molding layer 510 may extend to fill the space between the first semiconductor chip 410 and the redistribution substrate 200, and the space between the second semiconductor chip 420 and the redistribution substrate 200. The first molding layer 510 may have a molded underfill (MUF) shape that fills the space between the first semiconductor chip 410 and the redistribution substrate 200, and the space between the second semiconductor chip 420 and the redistribution substrate 200. The first molding layer 510 may surround the second bump 320 and the third bump 330.

[0034] The first molding layer 510 may have a coefficient of thermal expansion of 9 ppm / °C to 40 ppm / °C. The first molding layer 510 may have a glass transition temperature of 110°C to 150°C. The first molding layer 510 may have a Young's modulus of 9 GPa to 28 GPa.

[0035] The first molding layer 510 may include epoxy molding compound (EMC). The epoxy molding compound may include resin and filler.

[0036] The first underfill layer 610 may fill the space between the package substrate 100 and the redistribution substrate 200. The first underfill layer 610 may surround the first bump 310. The first underfill layer 610 may extend to and cover the side surface of the redistribution substrate 200. The first underfill layer 610 may extend to and cover a portion of the side surface of the first molding layer 510. The side surface and the bottom surface of the redistribution substrate 200 may be covered by the first underfill layer 610. The first underfill layer 610 may be capillary underfill (CUF).

[0037] The coefficient of thermal expansion of the first bottom filler layer 610 may be equal to or approximately equal to the coefficient of thermal expansion of the dielectric layer 210 of the redistribution substrate 200. The coefficient of thermal expansion of the first bottom filler layer 610 may be between 20 ppm / °C and 40 ppm / °C. In an embodiment, the first bottom filler layer 610 may mitigate stress caused by the mismatch in the coefficients of thermal expansion between the package substrate 100 and the redistribution substrate 200 when thermal changes are applied, and may suppress or mitigate cracking in the first bump 310 due to stress.

[0038] The glass transition temperature of the first bottom filler layer 610 may be lower than the glass transition temperature of the dielectric layer 210 of the redistribution substrate 200. The glass transition temperature of the first bottom filler layer 610 may be between 130°C and 180°C. The first bottom filler layer 610 may include an insulating resin such as epoxy resin.

[0039] A second molding layer 520 is disposed on the packaging substrate 100 and covers the first bottom fill layer 610 and the first molding layer 510. The second molding layer 520 may cover the side surfaces of the first molding layer 510 and may expose the upper surfaces of the first semiconductor chip 410, the second semiconductor chip 420, and the first molding layer 510. The upper surface of the second molding layer 520 may be positioned on the same plane as the upper surfaces of the first semiconductor chip 410, the second semiconductor chip 420, and the first molding layer 510. In this embodiment, because the upper surfaces of the first semiconductor chip 410 and the second semiconductor chip 420 are exposed, the heat generated when the first semiconductor chip 410 and the second semiconductor chip 420 are operated can be discharged to the outside through the upper surfaces of the first semiconductor chip 410 and the second semiconductor chip 420.

[0040] The second molding layer 520 may have a coefficient of thermal expansion of 9 ppm / °C to 40 ppm / °C. The second molding layer 520 may have a glass transition temperature of 110°C to 150°C. The second molding layer 520 may have a Young's modulus of 9 GPa to 28 GPa.

[0041] The second molding layer 520 may include epoxy molding compound (EMC). The epoxy molding compound may include resin and filler.

[0042] Figures 2 to 4 This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure.

[0043] Reference Figure 2 The semiconductor package 20 includes a package substrate 100, a redistribution substrate 200, a first semiconductor chip 410 and a second semiconductor chip 420, a first molding layer 510 and a second molding layer 520, a first underfill layer 610, a second underfill layer 620 and a third underfill layer 630, and external connection terminals 700. (Refer to the above...) Figure 1 Compared to the semiconductor package 10 described, the semiconductor package 20 further includes a second underfill layer 620 and a third underfill layer 630.

[0044] The second underfill layer 620 can fill the space between the redistribution substrate 200 and the first semiconductor chip 410. The second underfill layer 620 can be formed separately from the first molding layer 510. The second underfill layer 620 can be CUF (capillary underfill). The second underfill layer 620 can extend to and cover a portion of the side surface of the first semiconductor chip 410. The second underfill layer 620 can surround the second bump 320. In an embodiment, the second underfill layer 620 can alleviate stress caused by the mismatch of the coefficients of thermal expansion between the redistribution substrate 200 and the first semiconductor chip 410 when thermal changes are applied, and can suppress or mitigate cracking in the second bump 320 due to stress.

[0045] The third bottom filler layer 630 can fill the space between the redistribution substrate 200 and the second semiconductor chip 420. The third bottom filler layer 630 can be formed separately from the first molding layer 510. The third bottom filler layer 630 can be a CUF (Cumulative Core Surface). The third bottom filler layer 630 can extend to and cover a portion of the side surface of the second semiconductor chip 420. The third bottom filler layer 630 can surround the third bump 330. In an embodiment, the third bottom filler layer 630 can alleviate stress caused by the mismatch in the coefficients of thermal expansion between the redistribution substrate 200 and the second semiconductor chip 420 when thermal changes are applied, and can suppress or mitigate cracking in the third bump 330 due to stress.

[0046] The coefficients of thermal expansion of the second bottom filler layer 620 and the third bottom filler layer 630 may be equal to or approximately the coefficient of thermal expansion of the dielectric layer 210 of the redistribution substrate 200. The coefficients of thermal expansion of the second bottom filler layer 620 and the third bottom filler layer 630 may be from 20 ppm / °C to 40 ppm / °C. The glass transition temperatures of the second bottom filler layer 620 and the third bottom filler layer 630 may be lower than the glass transition temperature of the dielectric layer 210 of the redistribution substrate 200. The glass transition temperatures of the second bottom filler layer 620 and the third bottom filler layer 630 may be from 130°C to 180°C. The second bottom filler layer 620 and the third bottom filler layer 630 may comprise an insulating resin such as epoxy resin.

[0047] A first molding layer 510 is disposed on the redistribution substrate 200 and covers the first semiconductor chip 410, the second semiconductor chip 420, the second bottom fill layer 620, and the third bottom fill layer 630. The first molding layer 510 covers the side surfaces of the first semiconductor chip 410, the second semiconductor chip 420, the second bottom fill layer 620, and the third bottom fill layer 630.

[0048] Reference Figure 3 According to embodiments of the present disclosure, a semiconductor package 30 includes a package substrate 100, a redistribution substrate 200, a first semiconductor chip 410 and a second semiconductor chip 420, a first molding layer 510 and a second molding layer 520, a first bottom fill layer 610, a heat sink 810, and external connection terminals 700. Referring to the above... Figure 1 Compared to the described semiconductor package 10, the semiconductor package 30 also includes a heat sink 810. (Referring to the above...) Figure 1 Compared to the semiconductor package 10, the semiconductor package 30 also includes an adhesive member 910.

[0049] A heat sink 810 is disposed above the upper surfaces of the first semiconductor chip 410 and the second semiconductor chip 420, as well as above the upper surfaces of the first molding layer 510 and the second molding layer 520. In this embodiment, the upper surfaces of the first semiconductor chip 410 and the second semiconductor chip 420 are surfaces facing away from the packaging substrate 100. An adhesive member 910 is disposed between the first semiconductor chip 410 and the heat sink 810, and between the second semiconductor chip 420 and the heat sink 810, and the heat sink 810 is attached to the first semiconductor chip 410 and the second semiconductor chip 420 via the adhesive member 910. The heat sink 810 may include metal. The adhesive member 910 may be a thermal interface material.

[0050] The heat generated during the operation of the first semiconductor chip 410 and the second semiconductor chip 420 is transferred to the heat sink 810 through the upper surface of the first semiconductor chip 410 and the upper surface of the second semiconductor chip 420, and can be discharged to the outside through the heat sink 810.

[0051] Reference Figure 4 According to embodiments of the present disclosure, a semiconductor package 40 includes a package substrate 100, a redistribution substrate 200, a first semiconductor chip 410 and a second semiconductor chip 420, a first molding layer 510, a first bottom filler layer 610, a heat sink 820, and external connection terminals 700. Referring to the above... Figure 1 Compared to the semiconductor package 10 described, the semiconductor package 40 does not include a second molding layer 520 and also includes a heat sink 820.

[0052] The heat sink 820 surrounds the redistribution substrate 200, the first semiconductor chip 410 and the second semiconductor chip 420, the first molding layer 510 and the first bottom fill layer 610. The heat sink 820 has a cavity 821 in which the redistribution substrate 200, the first semiconductor chip 410 and the second semiconductor chip 420, the first molding layer 510 and the first bottom fill layer 610 are housed.

[0053] A first adhesive member 921 is disposed between the first semiconductor chip 410 and the heat sink 820, and between the second semiconductor chip 420 and the heat sink 820. The first adhesive member 921 can attach the heat sink 820 to the first semiconductor chip 410 and the second semiconductor chip 420. A second adhesive member 922 is disposed between the packaging substrate 100 and the heat sink 820. The second adhesive member 922 can attach the heat sink 820 to the packaging substrate 100.

[0054] The first adhesive member 921 and the second adhesive member 922 may be heat-transfer materials. The heat sink 820 may include metal. The heat generated during the operation of the first semiconductor chip 410 and the second semiconductor chip 420 is transferred to the heat sink 820 through the upper surface of the first semiconductor chip 410, the upper surface of the second semiconductor chip 420 and the first adhesive member 921, and can be discharged to the outside through the heat sink 820.

[0055] Refer to the above Figures 1 to 4 In the described embodiment, two semiconductor chips are disposed on the redistribution substrate, but this disclosure is not limited thereto. The number of semiconductor chips disposed on the redistribution substrate may be one, three, or more.

[0056] The effects of this disclosure will now be described.

[0057] Photosensitive dielectric layers can be used as dielectric layers in redistribution substrates. Photosensitive dielectric layers include positive dielectric layers (PTD) and negative dielectric layers (NTD).

[0058] The positive dielectric layer comprises a polymer (e.g., phenol and imide) at a mass ratio of 15% or less, and includes a photoacid generator (PAG). When the positive dielectric layer is exposed to light, the photoacid generator (PAG) is photodecomposed to generate acid, and the protecting groups of the polymer are removed by the generated acid, thereby modifying the positive dielectric layer to dissolve in the developer. The positive dielectric layer is patterned in such a way that the exposed portions, which are exposed to light, dissolve in the developer and are removed, while the unexposed portions, which are not exposed to light, remain.

[0059] The negative dielectric layer comprises 50% or more polyimide by mass. The negative dielectric layer is modified to be insoluble through crosslinking upon exposure to light. The negative dielectric layer is patterned in such a manner that the exposed portions remain, while the unexposed portions are removed by a developer. The negative dielectric layer does not contain substances that inhibit crosslinking (e.g., photoacid generator PAG), resulting in a highly cured, dense network structure. Because the negative dielectric layer has a dense network structure, it has a lower coefficient of thermal expansion (CTE) than the positive dielectric layer. Compared to the positive dielectric layer, the negative dielectric layer exhibits superior elongation characteristics and tensile strength because the molecular chains are effectively stretched. The dielectric layer of the redistribution substrate of the semiconductor package according to various embodiments of this disclosure is composed of a negative dielectric layer.

[0060] The redistribution substrate serves as a stress buffer between the semiconductor chip and the packaging substrate. Silicon, a major component of the semiconductor chip, has a coefficient of thermal expansion of 2.6 ppm / °C to 3.0 ppm / °C, significantly different from the coefficient of thermal expansion of the insulating layer forming the packaging substrate. Therefore, the stress buffer needs to have a coefficient of thermal expansion less than or equal to that of the packaging substrate. Furthermore, in embodiments, it is desirable for the redistribution substrate to have high elongation and tensile strength to act as a stress buffer. According to some embodiments, as elongation and tensile strength increase, it becomes more resistant to physical stress caused by thermal changes, and the likelihood of cracking due to fatigue failure is reduced.

[0061] According to embodiments of this disclosure, the redistribution substrate including a negative dielectric layer has a coefficient of thermal expansion (CTE) of 20 ppm / °C to 50 ppm / °C. Therefore, in embodiments, the redistribution substrate can serve as a buffer to mitigate mechanical stress caused by the difference in CTE between a packaging substrate including components with a maximum CTE of 15 ppm / °C to 60 ppm / °C and a semiconductor chip including components with a minimum CTE of 2.6 ppm / °C to 3.0 ppm / °C. Because, in embodiments, the redistribution substrate including a negative dielectric layer can have a tensile strength of 500 MPa to 700 MPa and an elongation of 50% or higher, the redistribution substrate can become more resistant to physical stress caused by thermal changes, and the likelihood of cracking due to fatigue failure can be reduced.

[0062] According to embodiments of this disclosure, the bottom filler layer filling the space between the encapsulation substrate and the redistribution substrate has a coefficient of thermal expansion (CTE) of 20 ppm / °C to 40 ppm / °C. Therefore, in embodiments, the bottom filler layer can act as a buffer to mitigate mechanical stress caused by the difference in CTE between the encapsulation substrate comprising components with a CTE of 15 ppm / °C to 60 ppm / °C and the redistribution substrate comprising components with a CTE of 20 ppm / °C to 50 ppm / °C. Thus, in embodiments, the bottom filler layer can become more resistant to physical stress caused by thermal changes, and the likelihood of cracking due to fatigue failure can be reduced.

[0063] Although detailed embodiments of the present disclosure have been disclosed herein, those skilled in the art will understand that various modifications, additions, and substitutions related to these embodiments are possible without departing from the scope and technical concept of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the embodiments described above. All changes within the meaning and equivalent scope of the claims are included within its scope.

[0064] Cross-references to related applications

[0065] This application claims priority to Korean Patent Application No. 10-2025-0035137, filed on March 19, 2025 with the Korean Intellectual Property Office, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor package comprising: Packaging substrate; A redistribution substrate, which is bonded to the packaging substrate via a first bump, the redistribution substrate including a dielectric layer and a redistribution pattern; A first bottom filler layer fills the space between the packaging substrate and the redistribution substrate; A semiconductor chip, which is bonded to the redistribution substrate via a second bump; as well as A first molding layer is disposed on the redistribution substrate and surrounds the semiconductor chip. The dielectric layer includes a negative dielectric layer, which comprises 50% or more polyimide by mass.

2. The semiconductor package according to claim 1, wherein, The dielectric layer has a coefficient of thermal expansion of 20 parts per million (ppm / °C) to 50 ppm / °C.

3. The semiconductor package according to claim 1, wherein, The dielectric layer has a tensile strength of 500 MPa to 700 MPa.

4. The semiconductor package according to claim 1, wherein, The dielectric layer has an elongation of 50% or higher.

5. The semiconductor package according to claim 1, in, The packaging substrate includes components having a coefficient of thermal expansion of 15 ppm / °C to 60 ppm / °C, and the semiconductor chip includes components having a coefficient of thermal expansion of 2.6 ppm / °C to 3.0 ppm / °C. The first bottom filler layer has a coefficient of thermal expansion of 20 ppm / °C to 40 ppm / °C.

6. The semiconductor package according to claim 1, wherein, The glass transition temperature of the dielectric layer is higher than that of the first bottom filler layer.

7. The semiconductor package according to claim 1, wherein, The dielectric layer has a glass transition temperature of 200°C to 220°C.

8. The semiconductor package according to claim 1, wherein, The first bottom filler layer has a glass transition temperature of 130°C to 180°C.

9. The semiconductor package according to claim 1, further comprising: A second bottom filler layer is disposed between the redistribution substrate and the semiconductor chip.

10. The semiconductor package according to claim 9, wherein, The second bottom filler layer has a coefficient of thermal expansion of 20 ppm / °C to 40 ppm / °C.

11. The semiconductor package according to claim 9, wherein, The glass transition temperature of the second bottom filling layer is lower than that of the dielectric layer.

12. The semiconductor package according to claim 9, wherein, The second bottom filler layer has a glass transition temperature of 130°C to 180°C.

13. The semiconductor package according to claim 1, wherein, The first molding layer is formed to surround the side surface of the semiconductor chip and fill the space between the semiconductor chip and the redistribution substrate.

14. The semiconductor package according to claim 1, wherein, The first bottom fill layer extends to and covers the side surface of the redistribution substrate.

15. The semiconductor package of claim 1, further comprising: A second molding layer is disposed on the packaging substrate and covers the first bottom fill layer and the first molding layer.

16. The semiconductor package of claim 15, wherein, The first molding layer and the second molding layer are formed to expose the upper surface of the semiconductor chip.

17. The semiconductor package of claim 16, further comprising: A heat sink is disposed on the upper surface of the semiconductor chip.

18. The semiconductor package of claim 1, further comprising: A heat sink with a cavity in which the semiconductor chip, the first bottom filler layer, the first molding layer and the redistribution substrate are housed.

19. A semiconductor package comprising: Packaging substrate; A redistribution substrate, which is bonded to the package substrate via a first bump, and includes a dielectric layer and a redistribution pattern; as well as A first semiconductor chip, which is bonded to the redistribution substrate via a second bump. The dielectric layer includes a negative dielectric layer, which comprises 50% or more polyimide by mass.

20. The semiconductor package of claim 19, wherein, The dielectric layer has a coefficient of thermal expansion of 20 parts per million (ppm / °C) to 50 ppm / °C.

21. The semiconductor package of claim 19, wherein, The dielectric layer has a tensile strength of 500 MPa to 700 MPa.

22. The semiconductor package of claim 19, wherein, The dielectric layer has an elongation of 50% or higher.

23. The semiconductor package of claim 19, wherein, The packaging substrate includes components having a coefficient of thermal expansion of 15 ppm / °C to 60 ppm / °C, and the first semiconductor chip includes components having a coefficient of thermal expansion of 2.6 ppm / °C to 3.0 ppm / °C.

24. The semiconductor package of claim 19, wherein, The dielectric layer has a glass transition temperature of 200°C to 220°C.

25. The semiconductor package of claim 19, further comprising: A second semiconductor chip is bonded to the redistribution substrate via a third bump.

26. The semiconductor package of claim 25, wherein, The redistribution pattern includes: The first bump is used to metallize the UBM pad, and the second bump is attached to the first UBM pad. The second UBM pad, the third bump being attached to the second UBM pad; and A connection pattern that connects the first UBM pad and the second UBM pad.

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