X.5-layer substrate

Abstract

The X.5 layer substrate without using the embedded trace substrate process during formation can produce high yield with relaxed L / S at low cost in short manufacturing time (only 4x lamination process without separation process). For example, the substrate can include mSAP, two landing pads, two escape lines, two bump pads, and a photoimageable dielectric layer on the mSAP patterned substrate.

Description

[0001] This application is a divisional application of Chinese invention patent application 202180056474.6 (PCT / US2021 / 045034) entitled "X.5 layer substrate" filed on August 6, 2021. Technical Field

[0002] This disclosure relates generally to substrates, and more particularly, but not exclusively, to fan-out substrates. Background Technology

[0003] Modern substrate electronics are becoming increasingly prevalent and are driven by the growing need for cost and size reduction. One approach is to use fan-out substrates. Fan-out packaging continues to gain prominence in the industry, based on significant technological advantages that have led to its widespread commercialization. A “fan-out” package can be defined as any package with chip-surface fan-out connections that support more external I / O. Traditional fan-out packages use epoxy molding compounds to fully embed the die, rather than placing them on a substrate or interposer. Fan-out packaging typically involves dicing a chip on a silicon wafer, then precisely positioning the known good chip on a thin “reconstruction” or carrier wafer / panel, molding it, and then forming a redistribution layer (RDL) on top of the molded area (chip and fan-out area), followed by solder balls on top. In one technology, a standard fan-out RDL contains embedded material (such as an organic laminate or silicon wafer) instead of a die in a molding compound. Fan-out is a wafer-level packaging (WLP) technology. It is essentially a true chip-level packaging (CSP) technology because the final package is approximately the same size as the die itself.

[0004] To meet the signal fan-out requirements of high-level module products with bare dies, a ten-layer embedded trace substrate (10L ETS) can be used. However, 10L ETS has several issues, including but not limited to: Long manufacturing time: 9 lamination processes + carrier separation; High warpage: The ETS layer is subjected to 9 times the stress during lamination; Low throughput: Cu patterning and SR damage caused by processing 20-layer thick panels in the rolling mill; Extremely low yield: Short-circuit and open-circuit problems caused by the fine trace / pitch (L / S) required for a 90 μm pitch (e.g., 8 μm / 10 μm), with at least two escape lines; and High cost: caused by all of the above problems.

[0005] Therefore, systems, devices, and methods are needed to overcome the shortcomings of traditional methods. Summary of the Invention

[0006] The following presents a brief summary of one or more aspects and / or examples associated with the apparatus and methods disclosed herein. Therefore, this summary should not be considered a broad overview associated with all conceived aspects and / or examples, nor should it be considered as identifying key or essential elements associated with all conceived aspects and / or examples, or depicting the scope associated with any particular aspect and / or example. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts related to one or more aspects and / or examples associated with the apparatus and methods disclosed herein, prior to the detailed embodiments presented below.

[0007] In one aspect, the substrate includes: a modified semi-additive process (mSAP) patterned substrate; a first landing pad on a first side of the mSAP patterned substrate; a second landing pad on the first side of the mSAP patterned substrate adjacent to the first landing pad; a first escape line on the first side of the mSAP patterned substrate between the first landing pad and the second landing pad; a second escape line on the first side of the mSAP patterned substrate adjacent to the first escape line between the first landing pad and the second landing pad; a photoimageable dielectric layer on the first side of the mSAP patterned substrate, the dielectric layer being configured to encapsulate the first escape line and the second escape line; a first bump pad on the dielectric layer opposite to the mSAP patterned substrate, the first bump pad extending through the dielectric layer to the first landing pad; and a second bump pad on the dielectric layer opposite to the mSAP patterned substrate, the second bump pad extending through the dielectric layer to the second landing pad.

[0008] In another aspect, the substrate includes: a support component; a first landing pad on a first side of the support component; a second landing pad on the first side of the support component adjacent to the first landing pad; a first escape line on the first side of the support component between the first landing pad and the second landing pad; a second escape line on the first side of the support component adjacent to the first escape line between the first landing pad and the second landing pad; an insulating component on the first side of the support component, the insulating component being configured to encapsulate the first escape line and the second escape line; a first bump pad on the insulating component opposite to the support component, the first bump pad extending through the insulating component to the first landing pad; and a second bump pad on the insulating component opposite to the support component, the second bump pad extending through the insulating component to the second landing pad.

[0009] In another aspect, a method for manufacturing a substrate includes: providing a modified semi-additive process (mSAP) patterned substrate; forming a first landing pad on a first side of the mSAP patterned substrate; forming a second landing pad on the first side of the mSAP patterned substrate adjacent to the first landing pad; forming a first escape line on the first side of the mSAP patterned substrate between the first landing pad and the second landing pad; forming a second escape line on the first side of the mSAP patterned substrate adjacent to the first escape line between the first landing pad and the second landing pad; forming a photoimageable dielectric layer on the first side of the mSAP patterned substrate, the dielectric layer being configured to encapsulate the first escape line and the second escape line; forming a first bump pad on the dielectric layer opposite to the mSAP patterned substrate, the first bump pad extending through the dielectric layer to the first landing pad; and forming a second bump pad on the dielectric layer opposite to the mSAP patterned substrate, the second bump pad extending through the dielectric layer to the second landing pad.

[0010] In another aspect, a non-transitory computer-readable medium including instructions, when executed by a processor, causing the processor to perform a method comprising: providing a modified semi-additive process (mSAP) patterned substrate; forming a first landing pad on a first side of the mSAP patterned substrate; forming a second landing pad on the first side of the mSAP patterned substrate adjacent to the first landing pad; forming a first escape line on the first side of the mSAP patterned substrate between the first landing pad and the second landing pad; and forming a first escape line on the first side of the mSAP patterned substrate between the first landing pad and the second landing pad; and forming a first landing pad on the first side of the mSAP patterned substrate ... on the first side of the mSAP patterned substrate on the second side of the mSAP patterned substrate on the first side of the mSAP patterned substrate on the second side of the mSAP patterned substrate on the first side of the mSAP patterned substrate on the second side of the mSAP patterned substrate on the first side of the mSAP patterned substrate on the second side of the mSAP patterned substrate on the first side of the mSAP patterned substrate on the second side of the mSAP patterned substrate on the first side of the mSAP patterned substrate on the second side A first escaping line is formed on the side near the first landing pad and the second landing pad to form a second escaping line; an imageable dielectric layer is formed on a first side of the mSAP patterned substrate, the dielectric layer being configured to encapsulate the first escaping line and the second escaping line; a first bump pad is formed on the dielectric layer opposite to the mSAP patterned substrate, the first bump pad extending through the dielectric layer to the first landing pad; and a second bump pad is formed on the dielectric layer opposite to the mSAP patterned substrate, the second bump pad extending through the dielectric layer to the second landing pad.

[0011] Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed embodiments. Attached Figure Description

[0012] A more complete understanding of various aspects of this disclosure and its many accompanying advantages will be readily obtained by referring to the following detailed description, in conjunction with the accompanying drawings, which are for illustrative purposes only and not for limiting the scope of this disclosure: Figure 1 Exemplary substrates according to some examples of this disclosure are illustrated; Figures 2 to 4The illustrations depict exemplary methods for manufacturing a substrate according to some examples of this disclosure; Figure 5 Exemplary substrates and processes according to some examples of this disclosure are illustrated; Figure 6 Exemplary methods according to some examples of this disclosure are illustrated; Figure 7 The illustrations show exemplary mobile devices according to some examples of this disclosure; and Figure 8 The illustrations depict various electronic devices that can be integrated with any of the aforementioned methods, apparatuses, semiconductor devices, integrated circuits, dies, interposers, packages, or pop-ups, according to some examples of this disclosure.

[0013] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Therefore, for clarity, the dimensions of the features shown may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all parts of a particular device or method. Furthermore, the same reference numerals denote the same features throughout the specification and drawings. Detailed Implementation

[0014] The exemplary methods, apparatuses, and systems disclosed herein mitigate the drawbacks of conventional methods, apparatuses, and systems, as well as other previously undefined needs. Embodiments herein include the production of high-yield X.5 layer substrates with a loose L / S at low cost in short manufacturing times (only 4x lamination processes without separation processes) without the use of an embedded trace substrate process during formation. Examples also include (1) substrates that do not require an ETS process; (2) high yields with a loose L / S using a modified semi-additive process (mSAP) instead of a very fine L / S ETS; (3) short manufacturing times with only 4 lamination processes and no additional separation processes; and (4) manufacturing at a lower cost.

[0015] Figure 1 Exemplary substrates according to some examples of this disclosure are illustrated. For example... Figure 1As shown, substrate 100 may include a modified semi-additive process (mSAP) patterned substrate 110; a first landing pad 120 on a first side of the mSAP patterned substrate 110; a second landing pad 130 on the first side of the mSAP patterned substrate 110 adjacent to the first landing pad 120; a first escape line 140 on the first side of the mSAP patterned substrate 110 between the first landing pad 120 and the second landing pad 130; and a second escape line 150 on the first side of the mSAP patterned substrate 110 adjacent to the first escape line 140 between the first landing pad 120 and the second landing pad 130. A photoimageable dielectric layer 160 is disposed on a first side of an mSAP patterned substrate 110, the photoimageable dielectric layer 160 being configured to encapsulate a first effluent line 140 and a second effluent line 150; a first bump pad 170 on the photoimageable dielectric layer 160 opposite to the mSAP patterned substrate 110, the first bump pad 170 extending through the photoimageable dielectric layer 160 to a first landing pad 120; and a second bump pad 180 on the photoimageable dielectric layer 160 opposite to the mSAP patterned substrate 110, the second bump pad 180 extending through the photoimageable dielectric layer 160 to a second landing pad 130.

[0016] like Figure 1 As shown, substrate 100 may also include multiple external connections 105 (e.g., solder balls configured in a ball grid array or pad-side gate array), one or more devices 115 such as active (e.g., logic dies or integrated circuits) or passive (e.g., capacitors, inductors, etc.) embedded in, on top of, or on the mSAP patterned substrate 110, metallization structures 125 (e.g., redistribution layers) in or on the mSAP patterned substrate 110, and molding compounds 135 on the mSAP patterned substrate 110, as well as other conventional aspects of electronic packaging. It should be understood that the size (or height from a side view) of the photoimageable dielectric layer 160 may be approximately half that of a standard laminate used in conventional layers (e.g., substrates constructed with mSAP). Therefore, substrate 100 can contain 10L with a 0.5L dielectric, which does not require an ETS process, uses a loose L / S (mSAP) instead of a very fine L / S (ETS), and reduces manufacturing time at a lower cost than conventional mSAP substrates by using only a 4x lamination process without a ball separation process.

[0017] Figures 2 to 4 Exemplary methods for manufacturing a substrate are illustrated according to some examples of this disclosure. For example... Figure 2As shown, a method 200 for manufacturing a substrate (e.g., substrate 100) may begin by forming an mSAP patterned substrate 210 having 10 layers of laminated prepreg blanks (which may also include embedded devices, vias, and metallization structures) and a half-layer of dielectric to form a dielectric layer 260. Method 200 may include forming a first escaping line 240 and a second escaping line 250 in the dielectric layer 260 on one side of the mSAP patterned substrate 210. Figure 3 As shown, method 200 can proceed to form: a first landing pad 220 on a first side of the mSAP patterned substrate 210; a second landing pad 230 on the first side of the mSAP patterned substrate 210 adjacent to the first landing pad 220; a first bump pad 270 on a dielectric layer 260 opposite the mSAP patterned substrate 210, the first bump pad 270 extending through the dielectric layer 260 to the first landing pad 220; and a second bump pad 280 on the dielectric layer 260 opposite the mSAP patterned substrate 210, the second bump pad 280 extending through the dielectric layer 260 to the second landing pad 230. This can be achieved through various means, including performing laser drilling or exposure of photoimageable dielectrics (PIDs) to expose specific traces / pads, via plating, and pad patterning. Figure 4 As shown, method 200 may end with forming a solder mask layer 245 and attaching one or more devices 215 (e.g., flip chips, etc.).

[0018] Figure 5 Exemplary substrates and processes 300 according to some examples of this disclosure are illustrated. For example... Figure 5As shown, the mSAP patterned substrate 310 (e.g., substrate 110, substrate 210) may include a first landing pad 320 on a first side of the mSAP patterned substrate 310; a second landing pad 330 on the first side of the mSAP patterned substrate 310 adjacent to the first landing pad 320; a first escaping line 340 on the first side of the mSAP patterned substrate 310 between the first landing pad 320 and the second landing pad 330; and a second escaping line 350 on the first side of the mSAP patterned substrate 310 adjacent to the first escaping line 340 between the first landing pad 320 and the second landing pad 330. A photoimageable dielectric layer 360 is disposed on a first side of the mSAP patterned substrate 310, the photoimageable dielectric layer 360 being configured to encapsulate a first exit line 340 and a second exit line 350; a first bump pad 370 on the photoimageable dielectric layer 360 opposite to the mSAP patterned substrate 310, the first bump pad 370 extending through the photoimageable dielectric layer 360 to a first landing pad 320; and a second bump pad 380 on the photoimageable dielectric layer 360 opposite to the mSAP patterned substrate 310, the second bump pad 380 extending through the photoimageable dielectric layer 360 to a second landing pad 330. Figure 5 As shown, the conventional ETS layer 395 configuration exhibits very fine line / space constraints (8 µm / 10 µm) required for a 90 µm pitch and two escape lines. As shown in the conventional ETS layer 395 configuration (w / 2 escape lines), the surfaces are coplanar, and each bump pad has a width of approximately 44 µm, with approximately 10 µm of spacing between the edges of the coplanar bump pads and the escape lines, as well as between adjacent escape lines, where each escape line has a width of approximately 8 µm. However, as shown in structure 385, a more relaxed L / S is achieved with the non-coplanar structure shown. This allows for greater spacing between traces with the same 90 µm pitch and wider traces within the photoimageable dielectric layer 360. For example, the first escape line 340, the second escape line 350, the first bump pad 370, and the second bump pad 380 can be coplanar. In another example, the first escape line 340 and the second escape line 350 may coplanar on a first plane, and the first landing pad 320 and the second landing pad 330 may coplanar on a second plane different from the first plane. Furthermore, the photoimageable dielectric layer 360 may separate the fine L / S region from the solder joint region in the solder layer (not shown), and alternatively, the photoimageable dielectric layer 360 does not contain any reinforcing or prepreg material, making the manufacturing process easier and less costly.

[0019] Figure 6 Exemplary methods according to some examples of this disclosure are illustrated. For example... Figure 6As shown, method 400 can begin at block 402 by providing an mSAP-patterned substrate. Method 400 can continue at block 404 by forming a first landing pad on a first side of the mSAP-patterned substrate. Method 400 can continue at block 406 by forming a second landing pad on the first side of the mSAP-patterned substrate, adjacent to the first landing pad. Method 400 can continue at block 408 by forming a first escape line on the first side of the mSAP-patterned substrate between the first and second landing pads. Method 400 can continue at block 410 by forming a second escape line on the first side of the mSAP-patterned substrate, adjacent to the first escape line between the first and second landing pads. Method 400 can continue at block 412 by forming a photoimageable dielectric layer on the first side of the mSAP-patterned substrate, the dielectric layer being configured to encapsulate the first and second escape lines. Method 400 may continue at block 414 by forming a first bump pad on a dielectric layer opposite the mSAP patterned substrate, the first bump pad extending through the dielectric layer to a first landing pad. Method 400 may end at block 416 by forming a second bump pad on a dielectric layer opposite the mSAP patterned substrate, the second bump pad extending through the dielectric layer to a second landing pad.

[0020] Alternatively, method 400 may include forming a solder resist on a dielectric layer configured to encapsulate a first bump pad and a second bump pad; wherein the first escape line, the second escape line, the first landing pad, and the second landing pad are coplanar; wherein the first escape line and the second escape line are coplanar in a first plane, and the first bump pad and the second bump pad are coplanar in a second plane different from the first plane; wherein the dielectric layer separates the fine L / S region from the solder joint region; wherein the dielectric layer does not contain any reinforcing material or prepreg material; and incorporating the substrate into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, and devices in motor vehicles.

[0021] Figure 7 The illustration shows exemplary mobile devices according to some examples of this disclosure. Reference now is made to... Figure 7A block diagram depicts a mobile device configured according to exemplary aspects and generally designated as 500. In some aspects, the mobile device 500 may be configured as a wireless communication device. As shown in the figure, the mobile device 500 includes a processor 501, which may be configured to implement the methods described herein in some aspects. The processor 501 is shown as including an instruction pipeline 512, a buffer processing unit (BPU) 508, a branch instruction queue (BIQ) 511, and a choke 510, as are well known in the art. For clarity, other well-known details of these blocks (e.g., counters, entries, confidence fields, weighted sums, comparators, etc.) are omitted from this view of the processor 501.

[0022] The processor 501 can be communicatively connected to the memory 532 via a link, which can be a die-to-die or chip-to-chip link. The mobile device 500 also includes a display 528 and a display controller 526, wherein the display controller 526 is connected to the processor 501 and the display 528.

[0023] In some respects, Figure 7 It may include an encoder / decoder (codec) 534 (e.g., an audio and / or voice codec) connected to the processor 501; a speaker 536 and a microphone 538 connected to the codec 534; and a wireless controller 540 (which may include a modem) connected to the wireless antenna 542 and the processor 501.

[0024] In certain aspects, with one or more of the aforementioned boxes present, the processor 501, display controller 526, memory 532, codec 534, and wireless controller 540 may be contained in a system-in-package or system-on-a-chip device 522. Input devices 530 (e.g., a physical or virtual keyboard), power supply 544 (e.g., a battery), display 528, speaker 536, microphone 538, wireless antenna 542, and power supply 544 may be external to the system-on-a-chip device 522 and may be coupled to components of the system-on-a-chip device 522, such as interfaces or controllers.

[0025] It should be noted that, although Figure 7 Mobile devices are described, but processor 501 and memory 532 can also be integrated into set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptop computers, tablet computers, communication devices, mobile phones or other similar devices.

[0026] Figure 8The illustrations depict various electronic devices that can be integrated with any of the aforementioned integrated devices, semiconductor devices, integrated circuits, dies, interposers, packages, or PoPs, according to some examples of this disclosure. For example, mobile phone device 602, laptop computer device 604, and fixed-location terminal device 606 may include integrated device 600 as described herein. Integrated device 600 can be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and package-on-package devices described herein. Figure 8 The devices 602, 604, and 606 shown are merely exemplary. Other electronic devices may also feature integrated device 600, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as instrument reading devices, communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (such as autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0027] It should be understood that the various aspects disclosed herein can be described as functional equivalents of structures, materials, and / or devices as described and / or understood by those skilled in the art. It should also be noted that the methods, systems, and apparatuses disclosed in the specification or claims can be implemented by devices including corresponding actuating means for performing the methods. For example, in one aspect, the substrate (e.g., substrate 100) may include: a support component (e.g., an mSAP patterned substrate); a first landing pad on a first side of the support component; a second landing pad on the first side of the support component adjacent to the first landing pad; a first escape line on the first side of the support component between the first and second landing pads; a second escape line on the first side of the support component adjacent to the first and second landing pads; an insulating component (e.g., a dielectric layer) on the first side of the support component, the insulating component being configured to encapsulate the first and second escape lines; a first bump pad on the insulating component opposite to the support component, the first bump pad extending through the insulating component to the first landing pad; and a second bump pad on the insulating component opposite to the support component, the second bump pad extending through the insulating component to the second landing pad. It should be understood that the foregoing aspects are provided by way of example only, and the aspects claimed are not limited to the specific references and / or descriptions cited as examples.

[0028] Figures 1 to 8 One or more components, processes, features, and / or functions shown may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may be added without departing from this disclosure. It should also be noted that in this disclosure… Figures 1 to 8 The corresponding descriptions are not limited to dies and / or ICs. In some implementations, Figures 1 to 8 The descriptions and corresponding information can be used to manufacture, create, provide, and / or produce integrated devices. In some implementations, a device may comprise a die, integrated device, die package, integrated circuit (IC), device package, integrated circuit (IC) package, wafer, semiconductor device, package-on-package (PoP) device, and / or interposer. The active side of the device (such as a die) is the portion of the device that contains the active components of the device (e.g., transistors, resistors, capacitors, inductors, etc.) that perform the operation or function of the device. The back side of the device is the side of the device opposite the active side. As used herein, the metallization structure may comprise metal layers, vias, pads, or traces with dielectrics therebetween, such as redistribution layers or RDLs.

[0029] As used herein, the terms “user equipment” (or “UE”), “user terminal”, “client equipment”, “communication equipment”, “wireless equipment”, “wireless communication equipment”, “handheld device”, “mobile device”, “mobile terminal”, “mobile station”, “phone”, “access terminal”, “subscriber equipment”, “subscriber terminal”, “subscriber station”, “terminal”, and variations thereof may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive equipment in motor vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device that can receive wireless communication and / or navigation signals, such as via short-range wireless, infrared, wired connections, or other connections, regardless of whether satellite signal reception, auxiliary data reception, and / or location-related processing occur on that device or the other device. Furthermore, these terms are intended to encompass all devices capable of communicating with the core network via the Radio Access Network (RAN), including both wireless and wired communication devices, and via the core network, the UE can connect to external networks such as the Internet and other UEs. Of course, other mechanisms for connecting the UE to the core network and / or the Internet are also possible, such as via a wired access network, a Wireless Local Area Network (WLAN) (e.g., based on IEEE 802.11, etc.), and so on. The UE can be implemented by any of a variety of devices, including but not limited to printed circuit (PC) cards, small flash devices, external or internal modems, wireless or wired telephones, smartphones, tablets, tracking devices, asset tags, etc. The communication link through which the UE can send signals to the RAN is referred to as an uplink channel (e.g., reverse traffic channel, reverse control channel, access channel, etc.). The communication link through which the RAN can send signals to the UE is referred to as a downlink or forward link channel (e.g., paging channel, control channel, broadcast channel, forward traffic channel, etc.). As used herein, the term Traffic Channel (TCH) can refer to an uplink / reverse or downlink / forward traffic channel.

[0030] Wireless communication between electronic devices can be based on various technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread), or other protocols that can be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network (PAN) technology designed and marketed by the Bluetooth Special Interest Group (SIG) to provide significantly reduced power consumption and cost while maintaining similar communication range. With the adoption of Bluetooth Core Specification version 4.0, BLE was incorporated into the main Bluetooth standard in 2010 and updated in Bluetooth 5 (both are explicitly incorporated herein by reference in their entirety).

[0031] The term "example" as used herein means "serving as an example, instance, or illustration." Any detail described herein as an "example" should not be construed as superior to other examples. Similarly, the term "example" does not imply that all examples encompass the features, advantages, or modes of operation discussed. Furthermore, specific features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0032] The terminology used herein is for the purpose of describing particular examples and is not intended to limit the scope of the examples disclosed herein. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” “containing,” and / or “comprising” as used herein specify the presence of the stated features, integers, actions, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, actions, operations, elements, components, and / or combinations thereof.

[0033] It should be noted that the terms “connection,” “linkage,” or any variation thereof refer to any direct or indirect connection or link between elements, and may cover the presence of an intermediate element between two elements that are “connected” or “linked” together via an intermediate element.

[0034] Any references to elements in this document using names such as "first," "second," etc., do not limit the number and / or order of these elements. Rather, these names are used as a convenient way to distinguish two or more elements and / or examples of elements. Furthermore, unless otherwise stated, a group of elements may include one or more elements.

[0035] Nothing stated or described in this application is intended to offer any component, movement, feature, benefit, advantage, or equivalent to the public, whether or not such component, movement, feature, benefit, advantage, or equivalent is stated in the claims.

[0036] Furthermore, those skilled in the art will understand that the various illustrative logic blocks, modules, circuits, and algorithmic actions described in the examples disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and actions have been generally described above in accordance with their functions. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application; however, such implementation decisions should not be construed as departing from the scope of this disclosure.

[0037] The methods, sequences, and / or algorithms described in the examples disclosed herein can be directly incorporated into hardware, into software modules executed by a processor, or a combination of both. Software modules can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art, comprising non-transitory types of memory or storage media. Exemplary storage media are coupled to the processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor.

[0038] Although some aspects have been described in conjunction with the device, it goes without saying that these aspects also constitute a description of the corresponding method, and therefore, blocks or components of the device should also be understood as corresponding method actions or features of method actions. Similarly, aspects described in conjunction with method actions or as method actions also constitute a description of the corresponding boxes, details, or features of the corresponding device. Some or all method actions can be performed by (or using) hardware devices, such as, for example, microprocessors, programmable computers, or electronic circuits. In some examples, some or more of the most important method actions can be performed by such devices.

[0039] In the specific embodiments described above, it can be seen that different features are combined together in the examples. This manner of disclosure should not be construed as an intention to claim an example with more features than expressly mentioned in the corresponding claims. Rather, this disclosure may contain fewer features than all of the single examples disclosed. Therefore, the following claims should be considered as included in the specification, where each claim can serve as a separate example on its own. Although each claim may represent a separate example on its own, it should be noted that while dependent claims may express a specific combination with one or more claims in the claims, other examples may also contain or include combinations of the subject matter of the dependent claim with any other dependent claim, or any feature combined with other dependent and independent claims. Such combinations are presented herein unless it is expressly stated that no particular combination is intended to be used. Furthermore, features of a claim may be contained in any other independent claim, even if the claim is not directly dependent on that independent claim.

[0040] Furthermore, in some examples, a single action can be subdivided into multiple sub-actions or contain multiple sub-actions. Such sub-actions can be included in the public disclosure of a single action and are part of the public disclosure of the single action.

[0041] Although the foregoing disclosure illustrates illustrative examples of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. The functions and / or actions of the method claims according to the examples of the disclosure described herein do not need to be performed in any particular order. Furthermore, well-known elements will not be described in detail or omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. Moreover, although elements of this disclosure may be described or claimed in the singular, plural forms are also contemplated unless expressly stated to be limited to the singular.

Claims

1. A substrate, comprising: Modified semi-additive process (mSAP) for patterning substrates; The first landing pad is on the first side of the mSAP patterned substrate; The second landing pad is located on the first side of the mSAP patterned substrate, close to the first landing pad. The first escape line is located on the first side of the mSAP patterned substrate between the first landing pad and the second landing pad. The second escape line is located on the first side of the mSAP patterned substrate, between the first landing pad and the second landing pad, close to the first escape line. A photoimageable dielectric layer is provided on the first side of the mSAP patterned substrate, and the photoimageable dielectric layer is configured to encapsulate the first escape line and the second escape line. A first bump pad, on the imagerable dielectric layer, opposite the mSAP patterned substrate, extends through the imagerable dielectric layer to the first landing pad; and A second bump pad is positioned opposite the mSAP patterned substrate on the photoimageable dielectric layer, extending through the photoimageable dielectric layer to the second landing pad.

2. A substrate, comprising: Components used for support; The first landing pad is on the first side of the component used for support; The second landing pad is located on the first side of the component used for support, near the first landing pad; The first escape line is located on the first side of the component used for support, between the first landing pad and the second landing pad; The second escape line is located on the first side of the component used for support, between the first landing pad and the second landing pad, close to the first escape line. An insulating component on the first side of the supporting component, the insulating component being configured to encapsulate the first escaping wire and the second escaping wire; A first bump pad, opposite the supporting component on the insulating component, extends through the insulating component to the first landing pad; and A second bump pad, on the insulating component, is opposite the supporting component, extending through the insulating component to the second landing pad.

3. A method for manufacturing a substrate, the method comprising: Provides patterned substrates using an improved semi-additive process (mSAP); A first landing pad is formed on a first side of the mSAP patterned substrate; A second landing pad is formed on the first side of the mSAP patterned substrate, close to the first landing pad; A first escape line is formed on the first side of the mSAP patterned substrate between the first landing pad and the second landing pad; A second escaping line is formed on the first side of the mSAP patterned substrate, close to the first escaping line, between the first landing pad and the second landing pad; A photoimageable dielectric layer is formed on the first side of the mSAP patterned substrate, and the photoimageable dielectric layer is configured to encapsulate the first escaping line and the second escaping line. A first bump pad is formed on the optically imageable dielectric layer opposite to the mSAP patterned substrate, the first bump pad extending through the optically imageable dielectric layer to the first landing pad; and A second bump pad is formed on the photoimageable dielectric layer opposite to the mSAP patterned substrate, the second bump pad extending through the photoimageable dielectric layer to the second landing pad.

4. A non-transitory computer-readable medium comprising instructions that, when executed by the processor, cause the processor to perform a method, the method comprising: Provides patterned substrates using an improved semi-additive process (mSAP); A first landing pad is formed on a first side of the mSAP patterned substrate; A second landing pad is formed on the first side of the mSAP patterned substrate, close to the first landing pad; A first escape line is formed on the first side of the mSAP patterned substrate between the first landing pad and the second landing pad; A second escaping line is formed on the first side of the mSAP patterned substrate, close to the first escaping line, between the first landing pad and the second landing pad; A photoimageable dielectric layer is formed on the first side of the mSAP patterned substrate, and the photoimageable dielectric layer is configured to encapsulate the first escaping line and the second escaping line. A first bump pad is formed on the optically imageable dielectric layer opposite to the mSAP patterned substrate, the first bump pad extending through the optically imageable dielectric layer to the first landing pad; and A second bump pad is formed on the photoimageable dielectric layer opposite to the mSAP patterned substrate, the second bump pad extending through the photoimageable dielectric layer to the second landing pad.

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