Semiconductor device

Abstract

A semiconductor device according to an embodiment of the disclosure can include a substrate including a chip region and a scribe lane region, an insulating structure disposed on the substrate and having one side surface located in the scribe lane region, a barrier structure including an inner barrier layer having an uppermost surface closer to the substrate than an upper surface of the insulating structure and overlapping one side surface of the insulating structure, and an outer barrier layer located on the inner barrier layer, and a redistribution pattern layer covering the barrier structure and spaced apart from the inner barrier layer.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0035714, filed on March 20, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments disclosed herein generally relate to semiconductor devices. Background Technology

[0003] Semiconductor devices have attracted much attention as an important component of the electronics industry due to their miniaturization, multifunctionality, and / or low manufacturing cost. With the development of the electronics industry, the demand for high integration in semiconductor devices is also increasing.

[0004] To meet the requirements of high integration, semiconductor devices may include redistribution layer (RDL) patterns. The redistribution layer pattern can be electrically connected to chip pads and can extend from the area where the chip pads are located to another area. Summary of the Invention

[0005] The purposes of this disclosure are not limited to those set forth herein, and other purposes not mentioned will be apparent to those skilled in the art from the following description.

[0006] The embodiments disclosed herein aim to provide a semiconductor device capable of preventing device characteristic degradation due to process defects.

[0007] In one embodiment of this disclosure, the semiconductor device may include: a substrate including a chip region and a scribe region; an insulating structure disposed on the substrate and having a side surface located in one of the scribe regions; a barrier structure including an inner barrier layer and an outer barrier layer located on the inner barrier layer, the inner barrier layer having a surface closer to the uppermost surface of the substrate than the upper surface of the insulating structure and overlapping a side surface of the insulating structure; and a redistribution patterned layer covering the barrier structure and spaced apart from the inner barrier layer.

[0008] In one embodiment of this disclosure, the semiconductor device may include: a substrate; an interlayer insulating layer disposed on the substrate and including an outer boundary; an insulating structure disposed on the interlayer insulating layer and including an inner boundary located inside the outer boundary; a barrier structure including an inner barrier layer and an outer barrier layer located on the inner barrier layer, wherein the inner barrier layer has a surface closer to the uppermost surface of the substrate than the upper surface of the insulating structure and overlaps with a side surface of the insulating structure; and a redistribution patterned layer covering the barrier structure and spaced apart from the inner barrier layer.

[0009] In embodiments of this disclosure, the semiconductor device may include: an interlayer insulating layer on a substrate; an insulating structure disposed on the interlayer insulating layer, the insulating structure including a redistribution insulating layer and a passivation layer; a guard ring extending through the interlayer insulating layer and into the passivation layer over a guard ring region of the substrate; an insulating structure disposed on the substrate and having a side surface located in a scribe region of the substrate; a dummy pattern layer having a lower surface coplanar with the lower surface of the passivation layer; a barrier structure formed on the dummy pattern layer and having a middle portion and an edge portion, the middle portion extending parallel to the dummy pattern along a first direction and the edge portion extending perpendicular to the dummy pattern layer; and a redistribution pattern layer covering the barrier structure.

[0010] According to embodiments of this disclosure, a semiconductor device capable of preventing device characteristic degradation due to process defects can be provided.

[0011] The advantages of this disclosure are not limited to those described above, and other advantages will become apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0012] The embodiments of this disclosure will be more fully understood through the following detailed description and accompanying drawings, but these descriptions and drawings are for illustrative purposes only and are not intended to limit the embodiments.

[0013] Figure 1 This is a simplified schematic diagram showing a wafer incorporating a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 2 yes Figure 1 A magnified view of region A in the middle.

[0015] Figure 3 It is shown Figure 2 A simplified schematic diagram of the cross-sectional structure of the section shown by line I-I'.

[0016] Figures 4 to 11 It is based on Figure 3 A simplified schematic diagram of the method for forming a semiconductor device according to the disclosed embodiments. Detailed Implementation

[0017] The embodiments of this disclosure will be described in detail with reference to the accompanying drawings. The specific structural or functional descriptions provided in the embodiments are merely examples to illustrate the concepts disclosed in this application. Examples or embodiments based on the technical concepts of this disclosure can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0018] All the crosshairs in the figure represent corresponding or similar areas between the figures, rather than representing the material related to these areas.

[0019] When one element is labeled "connected" or "coupled" to another element, the two elements can be directly connected or coupled, or they can be connected or coupled through an intermediate element between them. When two elements are labeled "directly connected" or "directly coupled," one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.

[0020] When one element is identified as being "above", "on top of", "below", or "under" another element, these elements may be in direct contact with each other, or an intermediate element may be placed between these elements.

[0021] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “below,” “under,” “above,” “upper,” “side surface,” “above,” “topmost,” “below,” “bottommost,” “front,” “back,” “left,” “right,” “column,” “row,” “layer,” and other terms that suggest relative spatial relationships or directions are used for ease of description or reference to the accompanying drawings and are not intended to be limiting. Within the scope of this disclosure, other spatial relationships or directions not shown in the accompanying drawings or described in the specification may exist.

[0022] Terms such as “first” and “second” are used to distinguish individual elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one embodiment, a first element may be referred to as a second element, while in another embodiment, a second element may be referred to as a first element.

[0023] In the specification, when an element included in an embodiment is described in the singular, the element may be interpreted as including multiple elements that perform the same or similar functions.

[0024] Figure 1 This is a simplified schematic diagram showing a wafer 1 in which a semiconductor device according to an embodiment of the present disclosure is integrated.

[0025] refer to Figure 1 Wafer 1 may include a chip region CHR and a scribe region SR. The scribe region SR may surround the chip region CHR.

[0026] A chip region (CHR) is the region formed by dicing a wafer 1 to create individual semiconductor chips. Each chip region (CHR) may contain one or more integrated circuits operating as individual semiconductor chips. Each chip region (CHR) may include a cell region (CR) and a guard ring region (GR). The guard ring region (GR) may be continuous with the side surface of the cell region (CR).

[0027] The scribing region SR can extend along a first direction FD and a second direction SD to surround the side surface of each chip region CHR. The first direction FD and the second direction SD can be substantially perpendicular to each other. The scribing region SR can be continuous with the chip region CHR. In the dicing process, wafer 1 can be diced along the dicing lines in the scribing region SR using dicing techniques such as lasers or blades.

[0028] The scribe area SR may include a redistribution alignment key area AR. The redistribution alignment key area AR refers to the area where redistribution alignment keys are set. Redistribution alignment keys are used for alignment during the etching of redistribution patterned layers in semiconductor device manufacturing processes.

[0029] The redistributed alignment key region (AR) can be positioned between adjacent chip regions (CHR). Although Figure 1 The diagram shows the redistribution alignment key region AR positioned between adjacent chip regions CHR on the first direction FD, but the placement of the redistribution alignment key region AR is not limited to this.

[0030] refer to Figure 1 The first semiconductor device 100 and the second semiconductor device 200 adjacent to the first semiconductor device 100 may be included in a portion of the wafer 1. The region between the first semiconductor device 100 and the second semiconductor device 200 may be defined as region A.

[0031] Figure 2 yes Figure 1 A magnified view of region A in the middle.

[0032] A portion of the first semiconductor device 100 and a portion of the second semiconductor device 200 may be included in region A.

[0033] refer to Figure 2 The first semiconductor device 100 may include a portion of a first chip region CHR1 and a first scribe region SR1 continuous with the first chip region CHR1. The first chip region CHR1 may include a first cell region CR1 and a first guard ring region GR1. The first guard ring region GR1 may be continuous with the first cell region CR1. The first guard ring region GR1 may include a first guard ring 110. The first guard ring 110 may extend to surround the edge of the first cell region CR1.

[0034] refer to Figure 2The second semiconductor device 200 may include a portion of a second chip region CHR2 and a second scribe region SR2 continuous with the second chip region CHR2. The second chip region CHR2 may include a second cell region CR2 and a second guard ring region GR2. The second guard ring region GR2 may be continuous with the second cell region CR2. The second guard ring region GR2 may include a second guard ring 210. The second guard ring 210 may extend to surround the edge of the second cell region CR2.

[0035] The redistribution alignment key region AR can be set in a portion of the first scribe region SR1 and the second scribe region SR2. The redistribution alignment key RK can be set in the redistribution alignment key region AR. The redistribution alignment key RK can be used for alignment during etching of the redistribution patterned layer in semiconductor device manufacturing processes.

[0036] Despite Figure 2 In the example shown, three redistribution alignment keys RK are depicted in the redistribution alignment key region AR, but the embodiment is not limited to this, and the redistribution alignment key region AR may have a variety of redistribution alignment keys RK.

[0037] exist Figure 2 In the illustrated embodiment, the redistribution alignment key RK can be as follows: Figure 2 As shown, the redistribution alignment key RK is set in a strip shape on the plane defined by the first direction FD and the second direction SD, but is not limited to this. The arrangement of the redistribution alignment key RK can vary in many ways. Furthermore, the shape of the redistribution alignment key RK can also be changed.

[0038] Figure 3 It is shown Figure 2 A simplified schematic diagram of the cross-sectional structure of the section shown by line I-I'.

[0039] refer to Figure 3 The first semiconductor device 100 may include a first substrate 101, a first guard ring 110, a first interlayer insulating layer 120 located on the first substrate, a first insulating structure 130 disposed on the first interlayer insulating layer 120, a first dummy pattern layer 140, a first barrier structure 150 disposed on the first dummy pattern layer 140, and a first redistribution pattern layer 160 disposed on the first barrier structure. The first guard ring 120 may pass through the first interlayer insulating layer 120.

[0040] The first semiconductor device 100 may include a first outer boundary 121. In one embodiment, the first outer boundary 121 may be the outermost boundary of the first semiconductor device 100. In one embodiment, the outer boundary of the first interlayer insulating layer 120 may be the same as the first outer boundary 121. In one embodiment, the first outer boundary 121 may be disposed in the first scribe region SR1.

[0041] The first insulating structure 130 may include a first inner boundary 131 located in the first scribe region SR1. The first inner boundary 131 may be a boundary of the first semiconductor device 100 that is closer to the first guard ring region GR1 than the first outer boundary 121. The first insulating structure 130 may have a side surface 130a in the first scribe region SR1. In one embodiment, the side surface 130a of the first insulating structure 130 may be the same as the first inner boundary 131.

[0042] The first outer boundary 121 can extend along the third direction VD, and the first inner boundary 131 can extend along the third direction VD. The third direction VD can be substantially perpendicular to the first direction FD.

[0043] A first substrate 101 is disposed in a first chip region CHR1 and a first scribe region SR1. The first chip region CHR1 includes a first cell region CR1 and a first guard ring region GR1.

[0044] The first protective ring 110 and the first interlayer insulating layer 120 may be disposed on the first substrate 101. The first substrate 101 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The first substrate 101 may include a III-V group semiconductor substrate, such as a compound semiconductor substrate like GaAs. The first substrate 101 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or a combination thereof.

[0045] A first protective ring 110 may be disposed on the first substrate 101. The first protective ring 110 may be disposed within the first protective ring region GR1. The first protective ring 110 may be disposed inside the first inner boundary 131. The first protective ring 110 may be disposed inside a side surface 130a of the first insulating structure 130. The first protective ring 110 may pass through the first interlayer insulating layer 120 and contact the first substrate 101 at one end. The other end of the first protective ring may extend into the first passivation oxide layer 133.

[0046] The first interlayer insulating layer 120 may comprise silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. The first interlayer insulating layer 120 may comprise an insulating material having excellent step coverage and gap-filling properties. In one embodiment, the first interlayer insulating layer 120 may comprise an oxide, such as tetraethyl orthosilicate (TEOS) or borosilicate glass (BPSG).

[0047] The first insulating structure 130 may be disposed on the first interlayer insulating layer 120. The first insulating structure 130 may include a first passivation layer 132 and a first redistribution insulating layer 135. The first redistribution insulating layer 135 may be disposed on the first passivation layer 132.

[0048] The first passivation layer 132 includes a high-density plasma oxide, a nitride, or a combination thereof. The first passivation layer 132 may include a first passivation oxide layer 133 and a first passivation nitride layer 134. The first passivation nitride layer 134 may be disposed on the first passivation oxide layer 133. In one embodiment, the first passivation oxide layer 133 may include a high-density plasma oxide.

[0049] The first redistributed insulating layer 135 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. The first redistributed insulating layer 135 may include a first redistributed oxide layer 136 and a first redistributed nitride layer 137. The first redistributed nitride layer 137 may be disposed on the first redistributed oxide layer 136.

[0050] The first dummy pattern layer 140 may be disposed on the first interlayer insulating layer 120. The first dummy pattern layer 140 may form a coplanar plane with the lower surface of the first insulating structure 130. The first dummy pattern layer 140 may overlap with at least a portion of the region disposed between the first outer boundary 121 and the first inner boundary 131.

[0051] One side surface 140a of the first dummy pattern layer 140 may be disposed inside the first inner boundary 131. Another side surface 140a of the first dummy pattern layer 140 may be disposed inside the first insulating structure 130. The other side surface 140b of the first dummy pattern layer 140 may be disposed outside the first inner boundary 131. The other side surface 140b of the first dummy pattern layer 140 may also be disposed outside the first insulating structure 130.

[0052] A first barrier structure 150 may be disposed on the first dummy pattern layer 140. In one embodiment, the first barrier structure 150 may overlap with the first dummy pattern layer 140. The first barrier structure 150 may be disposed on one side surface 130a of the first insulating structure 130. The first barrier structures 150 (151, 152) may be disposed between one side surface 130a of the first insulating structure 130 and the other side surface 140b of the first dummy pattern layer 140. The distance from the lower surface of the first barrier structure 150 to the first substrate 101 may be greater than the distance from the lower surface of the first insulating structure 130 to the first substrate 101.

[0053] Although Figure 3 The first blocking structure 150 is shown to include a first intermediate portion 150m extending parallel to a first direction FD and a second edge portion 150e extending parallel to a third direction VD. However, the embodiments are not limited thereto, and the extension direction of the first blocking structure 150 can be changed in various ways.

[0054] The first barrier structure 150 may include a first inner barrier layer 151 and a first outer barrier layer 152. The uppermost surface of the first inner barrier layer 151 may be disposed closer to the first substrate 101 than the upper surface of the first insulating structure 130.

[0055] The lower surface of the first passivation layer 132 may be disposed closer to the first substrate 101 than the lower surface of the first inner barrier layer 151. The lower surface of the first inner barrier layer 151 may be disposed between the upper surface of the first passivation layer 132 and the lower surface of the first passivation layer 132.

[0056] The distance from the uppermost surface of the first inner barrier layer 151 to the first substrate 101 in the vertical direction may be greater than the distance from the uppermost surface of the first protective ring 110 to the first substrate 101 in the vertical direction. In one embodiment, the vertical direction may refer to a third direction VD.

[0057] The first outer barrier layer 152 may be disposed outside the first inner barrier layer 151 from one side surface 130a of the first insulating structure 130. The first outer barrier layer 152 may be disposed on the first inner barrier layer 151. The first outer barrier layer 152 may overlap the first inner barrier layer 151.

[0058] The first outer barrier layer 152 may completely cover any side surface of the first inner barrier layer 151. In one embodiment, one side surface of the first inner barrier layer 151 may be spaced apart from one side surface 130a of the first insulating structure 130. One side surface of the first inner barrier layer 151 may be disposed between one side surface 130a of the first insulating structure 130 and a side surface of the first redistribution pattern layer 160. In one embodiment, one side surface of the first inner barrier layer 151 may be disposed between the first outer boundary 121 and the first inner boundary 131.

[0059] although Figure 3 Not shown, but in one embodiment, the first outer barrier layer 152 may extend along the third direction VD to cover the uppermost surface of the first inner barrier layer 151.

[0060] The first inner barrier layer 151 may include a conductive metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). In one embodiment, the first inner barrier layer 151 may include titanium nitride (TiN). In one embodiment, the first outer barrier layer 152 may include the same or substantially the same material as the first inner barrier layer 151.

[0061] A first redistribution pattern layer 160 may be disposed on the first barrier structure 150. The first redistribution pattern layer 160 may cover the first barrier structure 150. The first redistribution pattern layer 160 may be spaced apart from the first inner barrier layer 151.

[0062] although Figure 3 Not shown in the diagram, but in an embodiment, the first redistribution pattern layer 160 may extend along a third direction VD to cover the uppermost surface of the first barrier structure 150. Although Figure 3 The first redistribution pattern layer 160 is shown to have an intermediate portion extending in a direction parallel to a first direction and opposing edge portions or sides extending in a third direction VD, but embodiments of the present disclosure are not limited thereto, and the extension direction of the first redistribution pattern layer 160 may be changed in various ways.

[0063] The second semiconductor device 200 may include a second substrate 201, a second guard ring 210, a second interlayer insulating layer 220, a second insulating structure 230, a second dummy pattern layer 240, a second barrier structure 250, and a second redistribution pattern layer 260. The aforementioned features of the second semiconductor device 200 may be mirror images of corresponding features of the first semiconductor device 100 along an axis of symmetry extending along the first outer boundary 121.

[0064] The second semiconductor device 200 may include a second outer boundary 221. In one embodiment, the second outer boundary 221 may be the outermost boundary of the boundary of the second semiconductor device 200. In one embodiment, the outer boundary of the second interlayer insulating layer 220 may be the same as the second outer boundary 221. In one embodiment, the second outer boundary 221 may be disposed in the second scribe region SR2.

[0065] The second insulating structure 230 may include a second inner boundary 231 disposed in the second scribe region SR2. The second inner boundary 231 may be a boundary of the second semiconductor device 200 that is closer to the boundary of the second guard ring region GR2 than the second outer boundary 221. The second insulating structure 230 may have a side surface 230a in the second scribe region SR2. In the illustrated embodiment, this side surface 230a of the second insulating structure 230 may be the same as the second inner boundary 231.

[0066] The second outer boundary 221 can extend along a third party to VD, and the second inner boundary 231 can extend along a third party to VD.

[0067] The second substrate 201 is disposed in the second chip region CHR2 and the second scribe region SR2. The second chip region CHR2 may include a second cell region CR2 and a second guard ring region GR2.

[0068] The second protective ring 210 and the second interlayer insulating layer 220 may be disposed on the second substrate 201. The second substrate 201 may comprise the same or substantially the same material as the first substrate 101.

[0069] The second protective ring 210 may be disposed on the second substrate 201. The second protective ring 210 may be disposed in the second protective ring region GR2. The second protective ring 210 may be disposed inside the second inner boundary 231. The second protective ring 210 may pass through the second interlayer insulating layer 220 and contact the second substrate 201 at one end. The other end of the second protective ring 210 may extend into the second passivation oxide layer 233.

[0070] The second interlayer insulation layer 220 may include the same or substantially the same material as the first interlayer insulation layer 120.

[0071] The second insulating structure 230 may be disposed on the second interlayer insulating layer 220. The second insulating structure 230 may include a second passivation layer 232 and a second redistribution insulating layer 235. The second redistribution insulating layer 235 may be disposed on the second passivation layer 232.

[0072] The second passivation layer 232 may comprise a material substantially the same as that of the first passivation layer 132. The second passivation layer 232 may comprise a second passivation oxide layer 233 and a second passivation nitride layer 234. The second passivation nitride layer 234 may be disposed on the second passivation oxide layer 233. In one embodiment, the second passivation oxide layer 233 may comprise a material substantially the same as that of the first passivation oxide layer 133.

[0073] The second redistributed insulating layer 235 may include a second redistributed oxide layer 236 and a second redistributed nitride layer 237. The second redistributed nitride layer 237 may be disposed on the second redistributed oxide layer 236.

[0074] The second dummy pattern layer 240 may be disposed on the second interlayer insulating layer 220. The lower surface of the second dummy pattern layer 240 may form the same plane as the lower surface of the second insulating structure 230. The second dummy pattern layer 240 may overlap with at least a portion of the region disposed between the second outer boundary 221 and the second inner boundary 231.

[0075] One side surface 240a of the second dummy pattern layer 240 may be disposed inside the second inner boundary 231. Another side surface 240a of the second dummy pattern layer 240 may be disposed inside the side surface 230a of the second insulating structure 230. The other side surface 240b of the second dummy pattern layer 240 may be disposed outside the second inner boundary 231. The other side surface 240b of the second dummy pattern layer 240 may also be disposed outside the side surface 230a of the second insulating structure 230.

[0076] The second barrier structure 250 may be disposed on the second dummy pattern layer 240. In one embodiment, the second barrier structure 250 may overlap with the second dummy pattern layer 240. The second barrier structure 250 may be disposed on one side surface 230a of the second insulating structure 230. The second barrier structure 250 may be disposed between one side surface 230a of the second insulating structure 230 and the other side surface 240b of the second dummy pattern layer 240. The distance from the lower surface of the second barrier structure 250 to the second substrate 201 may be greater than the distance from the lower surface of the second insulating structure 230 to the second substrate 201.

[0077] The second barrier structure 250 may include a second inner barrier layer 251 and a second outer barrier layer 252. The uppermost surface of the second inner barrier layer 251 may be disposed closer to the second substrate 201 than the upper surface of the second insulating structure 230.

[0078] although Figure 3 The second blocking structure 250 is shown to include a second intermediate portion 250m extending parallel to the first direction FD and a second edge portion 250e extending parallel to the third direction VD. However, the embodiments are not limited to this, and the extension direction of the second blocking structure 250 can be changed in various ways.

[0079] The second outer barrier layer 252 may overlap with the second inner barrier layer 251. The lower surface of the second passivation layer 232 may be disposed closer to the second substrate 201 than the lower surface of the second inner barrier layer 251. The lower surface of the second inner barrier layer 251 may be disposed between the upper surface of the second passivation layer 232 and the lower surface of the second passivation layer 232.

[0080] The distance from the uppermost surface of the second inner barrier layer 251 to the second substrate 201 in the vertical direction can be greater than the distance from the uppermost surface of the second protective ring 210 to the second substrate 201 in the vertical direction.

[0081] The second outer barrier layer 252 may be disposed outside the second inner barrier layer 251 from one side surface 230a of the second insulating structure 230. The second outer barrier layer 252 may be disposed on the second inner barrier layer 251.

[0082] The second outer barrier layer 252 may completely cover one side surface of the second inner barrier layer 251. In one embodiment, one side surface of the second inner barrier layer 251 may be spaced apart from one side surface 230a of the second insulating structure 230. One side surface of the second inner barrier layer 251 may be disposed between one side surface 230a of the second insulating structure 230 and a side surface of the second redistribution pattern layer 260. In one embodiment, one side surface of the second inner barrier layer 251 may be disposed between the second outer boundary 221 and the second inner boundary 231.

[0083] although Figure 3 Not shown, but in one embodiment, the second outer barrier layer 252 may extend on the third-direction VD to cover the uppermost surface of the second inner barrier layer 251.

[0084] The second inner barrier layer 251 may comprise a material substantially the same as that of the first inner barrier layer 151. The second outer barrier layer 252 may comprise a material substantially the same as that of the second inner barrier layer 251.

[0085] The second redistribution pattern layer 260 may be disposed on the second barrier structure 250. The second redistribution pattern layer 260 may cover the second barrier structure 250. The second redistribution pattern layer 260 may be spaced apart from the second inner barrier layer 251.

[0086] although Figure 3 Not shown in the diagram, but in an embodiment, the second redistribution pattern layer 260 may extend along a third direction VD to cover the uppermost surface of the second barrier structure 250. Although Figure 3 The middle portion of the second redistribution pattern layer 260 is shown extending along the first direction FD, but the embodiment is not limited to this, and the extension direction of the second redistribution pattern layer 260 can be changed in various ways.

[0087] Figures 4 to 11 To show the basis Figure 3 A schematic diagram of a method for forming a semiconductor device according to the disclosed embodiments.

[0088] refer to Figure 4 Guard rings 110 and 210, as well as an interlayer insulating layer 20, can be formed on the substrate 10. The first guard ring 110 can be disposed in the first guard ring region GR1. The second guard ring 210 can be disposed in the second guard ring region GR2.

[0089] A dummy pattern layer 40 may be formed on the interlayer insulating layer 20. The dummy pattern layer 40 may be disposed in the scribe area SR. In one embodiment, the dummy pattern layer 40 may include aluminum (Al).

[0090] refer to Figure 5 A passivation layer 32 can be formed on the interlayer insulating layer 20. The passivation layer 32 can control moisture permeation and other processes in subsequent processes. The passivation layer 32 may include a passivation oxide layer 33 and a passivation nitride layer 34. The passivation nitride layer 34 may be disposed on the passivation oxide layer 33. In one embodiment, the passivation oxide layer 33 may include a high-density plasma oxide.

[0091] refer to Figure 6A redistributed insulating layer 35 may be formed on the passivation layer 32. The redistributed insulating layer 35 may include a redistributed oxide layer 36 and a redistributed nitride layer 37. The redistributed nitride layer 37 may be disposed on the redistributed oxide layer 36. An insulating structure 30 including the passivation layer 32 and the redistributed insulating layer 35 may be formed.

[0092] refer to Figure 7 A redistributed via region VR can be formed in the scribing region SR. The redistributed via region VR can be formed to penetrate the upper part of the insulating structure 30. The redistributed via region VR can be formed by anisotropic etching to expose the upper surface of the dummy pattern layer 40. In one embodiment, the redistributed via region VR can have a strip shape, but the embodiment is not limited to this. The shape of the redistributed via region VR can be changed in a variety of ways. The lower surface of the redistributed via region VR can contact a portion of the upper surface of the dummy pattern layer 40. With the formation of the redistributed via region VR, a first insulating structure 130 and a second insulating structure 230 can be formed.

[0093] refer to Figure 8 An inner barrier layer 51 may be formed on the upper and side surfaces of the first insulating structure 130, the upper and side surfaces of the second insulating structure 230, and the upper surface of the dummy pattern layer 40. The inner barrier layer 51 may be formed using a film-forming technique with excellent step coverage, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The inner barrier layer 51 may include a conductive metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). In one embodiment, the inner barrier layer 51 may include titanium nitride (TiN).

[0094] A dummy oxide layer 70 can be formed on the inner barrier layer 51. (Reference) Figure 8 The dummy oxide layer 70 can fill the interior of the redistributed via region VR.

[0095] refer to Figure 9 The dummy oxide layer 70 can be etched to expose a portion of the upper surface of the inner barrier layer 51. The redistributed nitride layers 137 and 237 can be used as etch barriers to form the inner barrier layer 51 on the sidewalls of the redistributed via region VR.

[0096] After a portion of the upper surface of the inner barrier layer 51 is exposed, an etching process can be performed on the inner barrier layer 51. The upper surfaces of the first insulating structure 130 and the second insulating structure 230 can be exposed. The upper surfaces of the first insulating structure 130, the second insulating structure 230, and the dummy oxide layer 70 can be formed in the same plane or substantially the same plane. The uppermost surface of the inner barrier layer 51 can be closer to the substrate 10 than the upper surfaces of the first insulating structure 130 and the second insulating structure 230.

[0097] refer to Figure 10 For example, the dummy oxide layer 70 can be removed by an etching process. As a result, the upper and side surfaces of the inner barrier layer 51 can be exposed. Only the inner barrier layer 51 can be disposed in the redistributed via region VR.

[0098] refer to Figure 11 An outer barrier layer 52 may be formed to cover the upper surface and partial side surfaces of the first insulating structure 130, the upper surface and partial side surfaces of the second insulating structure 230, and the upper surface and side surfaces of the inner barrier layer 51. The outer barrier layer 52 may be formed using the same method as the inner barrier layer 51. In one embodiment, the outer barrier layer 52 may be formed to conformally cover the inner barrier layer 51. In one embodiment, the outer barrier layer 52 may comprise the same material as the inner barrier layer 51.

[0099] A redistribution material 60 may be deposited on the outer barrier layer 52. During the deposition of the redistribution material 60, a droop structure 61 may be formed. The redistribution material 60 may include a conductive metallic material, such as copper (Cu) or aluminum (Al). In one embodiment, the redistribution material 60 may include aluminum (Al).

[0100] Since the outer barrier layer 52 and the redistribution material 60 are formed only after the inner barrier layer 51 is set in the redistribution via region VR, the thin deposition of the redistribution material 60 at the lower end of the redistribution via region VR can be compensated, thereby reducing the occurrence of cracks at the lower end of the redistribution via region VR.

[0101] Because the deposition thickness of the redistributed material 60 is reduced, the overhang becomes smaller, thereby reducing the width of the redistributed via region VR. This improves cutability in subsequent processes and ensures sufficient recognition space (redistributed via space) for the redistributed via region VR when identifying the redistributed alignment key RK.

[0102] Refer again Figure 3 The redistributed material 60 can be etched. The outer barrier layer 52 can be etched. Part of the redistributed material 60 can be removed. Part of the outer barrier layer 52 can be removed. Redistributed pattern layers 160 and 260 can be formed by etching the redistributed material 60.

[0103] Although not shown, a dummy insulating layer may be formed. The dummy insulating layer may cover the upper surface and part of the side surfaces of insulating structures 130 and 230, barrier structures 150 and 250, and the uppermost surface of redistribution pattern layers 160 and 260. In one embodiment, the dummy insulating layer may include polyimide isoindolequinazolinidone (PIQ).

[0104] Although detailed embodiments of this disclosure have been disclosed, those skilled in the art will understand that various modifications, additions, and substitutions can be made to these embodiments without departing from the scope and technical concept of this disclosure. Therefore, the scope of this disclosure should not be limited to the foregoing embodiments. All changes within the equivalent meaning and scope of the claims are included within its scope. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: The substrate includes the chip region and the scribe region; An insulating structure disposed on the substrate and having a side surface located in the scribe region; A barrier structure comprising an inner barrier layer and an outer barrier layer located on the inner barrier layer, the inner barrier layer having a position disposed closer to the uppermost surface of the substrate than the upper surface of the insulating structure and overlapping the one side surface of the insulating structure; as well as A redistribution pattern layer covers the barrier structure and is spaced apart from the inner barrier layer.

2. The semiconductor device according to claim 1, wherein, The outer barrier layer completely covers the side surface of the inner barrier layer that is spaced apart from the side surface of the insulating structure, and the outer barrier layer is disposed between the side surface of the insulating structure and the side surface of the redistribution pattern layer.

3. The semiconductor device according to claim 1, wherein, The outer barrier layer comprises the same material as the inner barrier layer.

4. The semiconductor device according to claim 1, further comprising: A dummy pattern layer has a lower surface that forms a plane with the lower surface of the insulating structure, a side surface disposed inside the one side surface of the insulating structure, and another side surface disposed outside the one side surface of the insulating structure.

5. The semiconductor device according to claim 4, wherein, The blocking structure overlaps with the dummy pattern layer.

6. The semiconductor device according to claim 4, wherein, The barrier structure is disposed between one side surface of the insulating structure and the other side surface of the dummy pattern layer.

7. The semiconductor device according to claim 1, wherein The insulating structure includes a passivation layer, and in, The lower surface of the passivation layer is positioned closer to the substrate than the lower surface of the inner barrier layer.

8. The semiconductor device according to claim 7, wherein, The lower surface of the inner barrier layer is disposed between the upper surface of the passivation layer and the lower surface of the passivation layer.

9. The semiconductor device according to claim 7, wherein, The passivation layer comprises high-density plasma oxides, nitrides, or combinations thereof.

10. The semiconductor device according to claim 1, further comprising: A protective ring is disposed on the inner side of one side surface of the insulation structure. Wherein, the distance from the uppermost surface of the inner barrier layer to the substrate in the vertical direction is greater than the distance from the uppermost surface of the protective ring to the substrate in the vertical direction.

11. A semiconductor device, comprising: Substrate; An interlayer insulating layer disposed on the substrate and including an outer boundary; An insulating structure disposed on the interlayer insulating layer and including an inner boundary disposed inside the outer boundary; A barrier structure comprising an inner barrier layer and an outer barrier layer located on the inner barrier layer, the inner barrier layer having a position disposed closer to the uppermost surface of the substrate than the upper surface of the insulating structure and overlapping a side surface of the insulating structure; as well as A redistribution pattern layer covers the barrier structure and is spaced apart from the inner barrier layer.

12. The semiconductor device according to claim 11, wherein, The outer barrier layer completely covers the side surface of the inner barrier layer located between the outer boundary and the inner boundary.

13. The semiconductor device according to claim 11, wherein, The outer barrier layer comprises the same material as the inner barrier layer.

14. The semiconductor device of claim 11, further comprising: A dummy pattern layer has a lower surface that forms a plane with the lower surface of the insulating structure, overlaps at least a portion of the region between the outer boundary and the inner boundary, and has a side surface disposed inside the inner boundary and another side surface disposed outside the inner boundary.

15. The semiconductor device according to claim 14, wherein, The blocking structure overlaps with the dummy pattern layer.

16. The semiconductor device according to claim 14, wherein, The blocking structure is disposed between the inner boundary and the other side surface of the dummy pattern layer.

17. The semiconductor device of claim 11, wherein... The insulating structure includes a passivation layer, and in, The lower surface of the passivation layer is positioned closer to the substrate than the lower surface of the inner barrier layer.

18. The semiconductor device according to claim 17, wherein, The lower surface of the inner barrier layer is disposed between the upper surface of the passivation layer and the lower surface of the passivation layer.

19. The semiconductor device of claim 11, further comprising: A protective ring is disposed on the inner side of the inner boundary. Wherein, the distance from the uppermost surface of the inner barrier layer to the substrate in the vertical direction is greater than the distance from the uppermost surface of the protective ring to the substrate in the vertical direction.

20. A semiconductor device, comprising: An interlayer insulating layer, which is on the substrate; An insulating structure disposed on the interlayer insulating layer, the insulating structure comprising a redistribution insulating layer and a passivation layer; A protective ring that passes through the interlayer insulating layer and extends into the passivation layer above the protective ring region of the substrate; An insulating structure disposed on the substrate and having a side surface located in a scribe region of the substrate; A dummy pattern layer has a lower surface that is coplanar with the lower surface of the passivation layer; A blocking structure is formed on the dummy pattern layer and has a central portion and an edge portion, the central portion extending parallel to the dummy pattern layer along a first direction, and the edge portion extending perpendicular to the dummy pattern layer. A redistributed pattern layer covers the blocking structure.

Images