Encapsulation carrier, co-encapsulation optical structure and method of manufacturing thereof

Abstract

The application discloses a packaging board, a co-packaging optical structure and a manufacturing method thereof. The packaging board comprises a substrate and an electronic integrated circuit. A first surface of the substrate is provided with a conductive circuit. The substrate comprises a dielectric layer and a conductive interconnection structure embedded in the dielectric layer. The electronic integrated circuit is embedded in the dielectric layer corresponding to the first surface of the substrate. A first surface of the electronic integrated circuit is exposed to the first surface of the substrate and is used for flip-chip connection with a photonic integrated circuit. A first end of the conductive interconnection structure is electrically connected with a second surface of the electronic integrated circuit and the conductive circuit. A second end of the conductive interconnection structure extends to a second surface of the substrate. In the packaging board, the EIC and the PIC adopt a vertical stacking layout, avoiding the problem that the EIC occupies surface space and causes difficulty in fiber coupling. The EIC is embedded in the substrate, and the lower surface of the EIC is surrounded by the dielectric layer, avoiding the problem that the EIC and the substrate have a large difference in CTE, causing serious warping in the processing process.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate, a co-packaged optical structure, and a method for manufacturing the same. Background Technology

[0002] With the explosive growth in bandwidth demands from data centers and artificial intelligence, traditional pluggable optical modules can no longer meet power consumption and size requirements, leading to the emergence of co-packaged optics (CPO) technology. CPO technology tightly packages photonic integrated circuits (PICs) and electronic integrated circuits (EICs) onto the same substrate, significantly shortening the electrical interconnection path.

[0003] Currently, mainstream co-package optical structures typically employ 2D planar layouts or traditional 3D stacking, which present the following insurmountable challenges: (1) Severe competition for surface space, making optical path coupling difficult. In traditional solutions, EIC and PIC are placed side-by-side on the substrate surface. The EIC is large in volume and occupies a large amount of substrate surface space, resulting in extremely limited coupling space left for the fiber array or microlens array of the PIC. This leads to extremely high fiber density, and the presence of EIC severely hinders the contact and precise alignment of the fiber. (2) Severe package warpage leads to optical path misalignment. CPO packaging typically uses organic substrates, and the coefficient of thermal expansion (CTE) of silicon PIC / EIC differs greatly from that of organic substrates. In traditional double-sided lamination or reflow soldering processes, due to stress accumulation, the package is prone to severe warpage, affecting the alignment accuracy of the PIC. This results in a sharp decrease in the coupling efficiency between the fiber and the PIC grating or end face, and may even cause device failure. Summary of the Invention

[0004] This application provides a packaging carrier, an optical module, a co-packaged optical structure, and a manufacturing method thereof to solve the problem of difficult fiber coupling caused by the EIC occupying surface space in existing packaging carriers, while eliminating the serious warping problem caused by traditional double-sided lamination process.

[0005] A packaging substrate includes a substrate and an electronic integrated circuit; The first surface of the substrate is provided with conductive lines, and the substrate includes a dielectric layer and conductive interconnect structures embedded in the dielectric layer; The electronic integrated circuit is embedded in the dielectric layer corresponding to the first surface of the substrate, and the first surface of the electronic integrated circuit is exposed on the first surface of the substrate. The first surface of the electronic integrated circuit is used for flip-chip connection with the photonic integrated circuit. The first end of the conductive interconnect structure is electrically connected to the second surface of the electronic integrated circuit and the conductive line, and the second end of the conductive interconnect structure extends to the second surface of the substrate.

[0006] In one embodiment, the first surface of the substrate is further provided with a positioning element, and the first surface of the positioning element and the first surface of the electronic integrated circuit are flush with the first surface of the substrate; The positioning element has a positioning hole; the electronic integrated circuit is located inside the positioning hole.

[0007] In one embodiment, the distance between the outer side of the electronic integrated circuit and the inner sidewall of the positioning member is 0.5mm-1.5mm.

[0008] In one embodiment, the positioning element is a positioning copper sheet; The first surface of the positioning copper sheet and the first surface of the electronic integrated circuit are flush with the first surface of the substrate, and the second surface of the positioning copper sheet is electrically connected to the conductive interconnect structure.

[0009] In one embodiment, the positioning element is a positioning copper block; The first surface of the positioning copper block and the first surface of the electronic integrated circuit are flush with the first surface of the substrate. The depth of the second surface of the positioning copper block relative to the first surface of the substrate is greater than the depth of the second surface of the electronic integrated circuit relative to the first surface of the substrate.

[0010] In one embodiment, the substrate includes a plurality of stacked dielectric layers, each dielectric layer having an intralayer interconnect structure, and the intralayer interconnect structures in two adjacent dielectric layers being electrically connected to form the conductive interconnect structure; The electronic integrated circuit is embedded in the dielectric layer at the top.

[0011] A co-packaged optical structure includes a photonic integrated circuit and the aforementioned packaging substrate; the photonic integrated circuit and the first surface of the electronic integrated circuit are flip-chip connected.

[0012] A co-packaged optical structure includes a photonic integrated circuit, an application-specific integrated circuit, and the aforementioned packaging substrate; The photonic integrated circuit and the electronic integrated circuit are flip-chip connected on their first surfaces; The application-specific integrated circuit is electrically connected to the conductive lines on the first surface of the substrate.

[0013] A method for manufacturing a packaging carrier board, comprising: Conductive lines are processed on the surface of a separable substrate to obtain a first substrate, the first substrate including mutually spaced conductive lines and a chip placement area; An electronic integrated circuit is placed in the chip placement area such that the first surface of the electronic integrated circuit abuts against the first substrate. A dielectric layer is laminated onto the first substrate and the electronic integrated circuit, and a conductive interconnect structure is fabricated within the dielectric layer to obtain a second substrate; a first end of the conductive interconnect structure is electrically connected to the second surface of the electronic integrated circuit and the conductive line, and a second end of the conductive interconnect structure extends to the second surface of the dielectric layer; The second substrate is separated to remove the separable carrier board, resulting in a packaging carrier board.

[0014] In one embodiment, the process of fabricating conductive lines on the surface of a separable carrier to obtain a first substrate includes: Dry film is applied to the surface of a separable carrier plate, and exposure and development operations are performed to obtain a carrier plate containing a developed pattern area. Electroplating and film stripping operations are performed on the carrier plate containing the developed pattern area to obtain the first plate.

[0015] In one embodiment, the developing pattern area includes mutually separated line areas and positioning areas; The electroplating and peeling operations on the carrier plate containing the developed pattern area to obtain the first substrate include: Electroplating and film stripping are performed on both the circuit area and the positioning area of ​​the carrier board containing the developed pattern area, so that the circuit area forms a conductive circuit and the positioning area forms a positioning copper sheet, to obtain the first board material; positioning holes are formed on the positioning copper sheet to form a chip placement area; The step of placing the electronic integrated circuit within the chip placement area includes: The electronic integrated circuit is placed in the chip placement area such that the distance between the outer side of the electronic integrated circuit and the inner sidewall of the positioning copper sheet is 0.5mm-1.5mm.

[0016] In one embodiment, the developing pattern area includes mutually separated line areas and positioning areas; The electroplating and peeling operations on the carrier plate containing the developed pattern area to obtain the first substrate include: Electroplating and film stripping operations are performed on the circuit area of ​​the carrier board containing the developed pattern area, and film stripping operation is performed on the positioning area of ​​the carrier board containing the developed pattern area, so that the circuit area forms a conductive circuit and the positioning area is exposed, to obtain a first board material. The step of placing the electronic integrated circuit within the chip placement area includes: A positioning copper block is attached to the positioning area, and positioning holes are formed in the positioning copper block to form a chip placement area. The electronic integrated circuit is placed in the chip placement area such that the distance between the outer side of the electronic integrated circuit and the inner sidewall of the positioning copper block is 0.5mm-1.5mm, and the thickness of the positioning copper block is greater than the thickness of the electronic integrated circuit.

[0017] In one embodiment, the step of laminating a dielectric layer onto the first substrate and the electronic integrated circuit, and processing conductive interconnect structures within the dielectric layer to obtain a second substrate includes: Multiple layer-addition operations are performed on the first substrate and the electronic integrated circuit; Each layer addition operation includes: laminating the current dielectric layer onto the separable carrier and the electronic integrated circuit, or laminating the current dielectric layer onto the previous dielectric layer; performing drilling and metallization operations on the current dielectric layer to obtain an intralayer interconnect structure corresponding to the current dielectric layer, wherein the intralayer interconnect structures in two adjacent dielectric layers are electrically connected to form the conductive interconnect structure.

[0018] In one embodiment, the step of separating the second substrate to remove the separable carrier board and obtain the encapsulation carrier board includes: The second board is separated to remove the separable carrier plate, resulting in the third board. The third substrate is subjected to solder resist coating, exposure, development and curing operations to obtain a packaging carrier board containing a protective layer.

[0019] A method for manufacturing a co-packaged optical structure includes: Conductive lines are processed on the surface of a separable substrate to obtain a first substrate, the first substrate including mutually spaced conductive lines and a chip placement area; An electronic integrated circuit is placed in the chip placement area such that the first surface of the electronic integrated circuit abuts against the first substrate. A dielectric layer is laminated onto the first substrate and the electronic integrated circuit, and a conductive interconnect structure is fabricated within the dielectric layer to obtain a second substrate; a first end of the conductive interconnect structure is electrically connected to the second surface of the electronic integrated circuit and the conductive line, and a second end of the conductive interconnect structure extends to the second surface of the dielectric layer; The second board is separated to remove the separable carrier board, resulting in a packaging carrier board. The electronic integrated circuit is flip-chipped onto the first surface of the photonic integrated circuit to obtain a co-packaged optical structure; or, the electronic integrated circuit is flip-chipped onto the first surface of the photonic integrated circuit, and an application-specific integrated circuit is packaged on the first surface of the substrate to obtain a co-packaged optical structure.

[0020] The packaging substrate provided in this application embeds an electronic integrated circuit (EIC) on the first surface of a substrate, with the first surface flush with the substrate. A photonic integrated circuit (PIC) is disposed directly above the first surface of the EIC via flip-chip bonding. Compared to the prior art where the EIC and PIC are arranged side-by-side on the substrate surface, this method involves a vertical stacking of the substrate, EIC, and PIC. The PIC does not occupy any area on the first surface of the substrate, allowing the first surface to be fully utilized for arranging fiber optic arrays, microlens arrays, or fiber optic bonding structures, without physical obstruction by the EIC. This provides ample space for high-density fiber optic array arrangement, microlens mounting, and automated coupling equipment operation, significantly improving the optical channel integration density of the CPO. The EIC is embedded within the substrate, its lower surface surrounded by a dielectric layer rather than exposed to the substrate surface. During packaging processes such as reflow soldering or thermoforming, the EIC is mechanically constrained by the substrate, suppressing its thermal expansion. Simultaneously, the conductive interconnect structure is embedded within the dielectric layer, rather than on the surface, forming a uniform stress distribution layer within the package, providing stress buffering. By combining embedded structures and embedded interconnects, the warpage of the package is effectively controlled, thereby ensuring the alignment accuracy between the photonic integrated circuit and the optical fiber, maintaining high coupling efficiency, and preventing device failure. A flip-chip connection is used between the photonic integrated circuit and the electronic integrated circuit, resulting in a shorter interconnect path compared to traditional wire bonding schemes, effectively reducing signal loss and crosstalk. The first end of the conductive interconnect structure is electrically connected to both the second surface of the electronic integrated circuit and the conductive lines, achieving a centralized design of electrical interconnects and simplifying wiring complexity. Its second end extends to the second surface of the substrate, facilitating interface with external circuit boards. Furthermore, this structure is embedded within the dielectric layer, achieving interlayer electrical conduction without increasing substrate surface area, demonstrating a unity of structural compactness and functional integration. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a first structural diagram of the first structural form of the packaging carrier in the embodiments of this application.

[0023] Figure 2 This is a second structural diagram of the first structural form of the packaging carrier in the embodiments of this application.

[0024] Figure 3This is a structural diagram of the first structural form of the co-encapsulated optical structure in the embodiments of this application.

[0025] Figure 4 This is a first structural diagram of the second structural form of the packaging carrier in the embodiments of this application.

[0026] Figure 5 This is a second structural diagram of the second structural form of the packaging carrier in the embodiments of this application.

[0027] Figure 6 This is a structural diagram of the first structural form of the co-encapsulated optical structure in the embodiments of this application.

[0028] Figure 7 This is a step diagram of the manufacturing method of the packaging carrier board in the embodiments of this application.

[0029] Figure 8 This is a schematic diagram of the manufacturing process of the first structural form of the encapsulation carrier in the embodiments of this application.

[0030] Figure 9 This is a schematic diagram of the manufacturing process of the second structural form of the encapsulation carrier in the embodiments of this application.

[0031] Figure 10 This is a flowchart illustrating the manufacturing steps of the co-packaged optical structure in the embodiments of this application.

[0032] Among them, 10 is the substrate; 11 is the dielectric layer; 12 is the conductive interconnect structure; 121 is the first interconnect structure; 122 is the second interconnect structure; 20 is the electronic integrated circuit; 30 is the photonic integrated circuit; 40 is the conductive line; 50 is the application-specific integrated circuit; 60 is the positioning element; 61 is the positioning hole; 62 is the positioning copper sheet; and 63 is the positioning copper block. Detailed Implementation

[0033] To make the technical problems, technical solutions, and beneficial effects solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0034] This application provides a packaging carrier board, referring to... Figures 1-6The packaging substrate includes a substrate 10 and an electronic integrated circuit 20. The first surface of the substrate 10 is provided with conductive lines 40. The substrate 10 includes a dielectric layer 11 and a conductive interconnect structure 12 embedded in the dielectric layer 11. The electronic integrated circuit 20 is embedded in the dielectric layer 11 corresponding to the first surface of the substrate 10. The first surface of the electronic integrated circuit 20 is exposed on the first surface of the substrate 10. The first surface of the electronic integrated circuit 20 is used for flip-chip connection with the photonic integrated circuit 30. The first end of the conductive interconnect structure 12 is electrically connected to the second surface of the electronic integrated circuit 20 and the conductive lines 40. The second end of the conductive interconnect structure 12 extends on the second surface of the substrate 10.

[0035] As an example, substrate 10 includes a dielectric layer 11 and conductive interconnect structures 12 embedded within the dielectric layer 11. An ABF substrate is used as the dielectric layer 11, and a redistribution layer (RDL) is embedded within the dielectric layer 11 as the conductive interconnect structure 12. Conductive lines 40 are provided on the first surface (top surface) of substrate 10. The conductive lines 40 and the first end of the conductive interconnect structure 12 are on the same plane, together forming the pad area of ​​the electronic integrated circuit 20. A solder ball array is provided on the second surface (bottom surface) of substrate 10. The solder ball array is electrically connected to the second end of the conductive interconnect structure 12 for connection to an external motherboard.

[0036] The electronic integrated circuit 20 can be, but is not limited to, a SerDes chip or a DSP chip. The electronic integrated circuit 20 is embedded on the first surface of the substrate 10 using an embedding process, ensuring a tight connection between the electronic integrated circuit 20 and the dielectric layer 11 of the substrate 10. The first surface of the substrate 10 is flush with the second surface (back side, facing downwards) of the electronic integrated circuit 20. The second surface of the electronic integrated circuit 20 is electrically connected to the first end of the conductive interconnect structure 12 and the conductive line 40 via copper pillar bonding. The photonic integrated circuit 30 is a silicon photonics PIC chip. The photonic integrated circuit 30 is connected to the first surface of the electronic integrated circuit 20 via flip-chip bonding, using gold-tin eutectic solder. The waveguide end face of the photonic integrated circuit 30 faces the outer side of the first surface of the substrate 10, for optical coupling with an optical fiber array or microlens array. The photonic integrated circuit 30 is located directly above the electronic integrated circuit 20, which is embedded within the substrate 10 with its upper surface flush with the substrate. The three components form a 3D stacked structure in the vertical direction. The remaining area of ​​the first surface of the substrate 10, excluding the conductive lines 40, can be used to arrange the optical fiber bonding structure, and is not affected by the space occupied by the electronic integrated circuit 20.

[0037] In this example, the electronic integrated circuit 20 is embedded on the first surface of the substrate 10, with the first surface flush with the substrate 10. The photonic integrated circuit 30 is disposed directly above the first surface of the electronic integrated circuit 20 via flip-chip bonding. Compared with the prior art where the EIC and PIC are arranged side by side on the substrate surface, the substrate 10, electronic integrated circuit 20, and photonic integrated circuit 30 adopt a vertical 3D stacked layout. The photonic integrated circuit 30 does not occupy any area of ​​the first surface of the substrate 10. The first surface of the substrate 10 can be fully used to arrange fiber arrays, microlens arrays, or fiber bonding structures without being physically obstructed by the electronic integrated circuit 20. This provides ample space for the arrangement of high-density fiber arrays, the mounting of microlenses, and the operation of automated coupling equipment, significantly improving the optical channel integration density of the CPO. The electronic integrated circuit 20 is embedded inside the substrate 10, with its lower surface surrounded by the dielectric layer 11 rather than exposed on the substrate surface. During packaging processes such as reflow soldering or thermoforming, the electronic integrated circuit 20 is mechanically constrained by the substrate 10, its thermal expansion is suppressed, effectively reducing thermal stress and preventing device warping and cracking. Meanwhile, the conductive interconnect structure 12 is embedded inside the dielectric layer 11, rather than being placed on the surface, forming a uniform stress distribution layer within the package and acting as a stress buffer. The combination of the embedded structure and the embedded interconnect effectively controls the package warpage, thereby ensuring the alignment accuracy between the photonic integrated circuit 30 and the optical fiber, maintaining high coupling efficiency, and preventing device failure. The photonic integrated circuit 30 and the electronic integrated circuit 20 are connected via flip-chip bonding, resulting in a shorter interconnect path compared to traditional wire bonding schemes, effectively reducing signal loss and crosstalk. The first end of the conductive interconnect structure 12 is electrically connected to the second surface of the electronic integrated circuit 20 and the conductive line 40, achieving a centralized design of electrical interconnection and simplifying wiring complexity. Its second end extends to the second surface of the substrate 10, facilitating interface with external circuit boards. Furthermore, this structure is embedded inside the dielectric layer 11, completing interlayer electrical conduction without increasing substrate surface area, demonstrating a unity of structural compactness and functional integration.

[0038] In one embodiment, reference is made to Figure 1 and Figure 4The first surface of the electronic integrated circuit 20 is flush with the first surface of the substrate 10, indicating that the electronic integrated circuit 20 is completely covered by the dielectric layer 11 on all sides, rather than being exposed to the substrate surface. During the high-temperature processes of reflow soldering or hot pressing, the electronic integrated circuit 20 is subjected to the three-dimensional mechanical constraint of the dielectric layer 11, effectively limiting its thermal deformation caused by CTE mismatch. Simultaneously, since the electronic integrated circuit 20 does not protrude from the substrate surface, there are no local protrusions on the top surface of the package, avoiding non-uniform stress distribution caused by height differences. Therefore, the warpage of the package is effectively suppressed, and the alignment accuracy between the photonic integrated circuit 30 and the optical fiber remains stable after packaging and during long-term use. The first surface of the electronic integrated circuit 20 is flush with the first surface of the substrate 10, so that the first surface of the substrate 10 forms a continuous, flat plane without protrusions. It can be used to arrange fiber arrays, microlens arrays or fiber bonding structures without being blocked by the sidewalls or mesa of the electronic integrated circuit 20. This greatly reduces the fiber arrangement density requirements and significantly improves the alignment tolerance, ensuring the uniformity and alignment accuracy of the solder joints between the photonic integrated circuit 30 and the electronic integrated circuit 20. This, in turn, ensures the coupling alignment accuracy between the optical waveguide end face on the photonic integrated circuit 30 and the external optical fiber, and avoids optical path offset caused by uneven solder base surface.

[0039] In one embodiment, reference is made to Figure 1 and Figure 4 The second surface of substrate 10 is provided with connection pads for connecting external circuits. Combined with the feature that "the first surface of the electronic integrated circuit 20 is flush with the first surface of substrate 10", the first surface of substrate 10 forms a completely clear continuous plane. The first surface of substrate 10 does not need to be provided with any pads, solder balls, or lead structures for external connections, allowing the first surface of substrate 10 to be fully used for fiber optic array mounting, microlens array arrangement, or fiber optic mounting structures. This fundamentally eliminates the problem of "severe surface space contention and difficult optical path coupling" in existing technologies. The conductive interconnect structure 12 is embedded inside the dielectric layer 11. Its first end connects the electronic integrated circuit 20 and the conductive line 40 on the top surface, and its second end extends to the bottom surface to connect with the connection pads, forming a vertical through-connection path, significantly reducing parasitic inductance and capacitance. In CPO scenarios, high-speed electrical signals between the electronic integrated circuit 20 and the photonic integrated circuit 30 are transmitted through this short path, effectively ensuring signal integrity and facilitating higher-speed optoelectronic collaborative operation.

[0040] In one embodiment, reference is made to Figure 1 and Figure 4The conductive interconnect structure 12 includes a first interconnect structure 121 and a second interconnect structure 122. The first end of the first interconnect structure 121 is electrically connected to a conductive line 40 disposed on the first surface of the substrate 10, and the second end of the first interconnect structure 121 extends to the second surface of the substrate 10 and is electrically connected to a connection pad. The first end of the second interconnect structure 122 is electrically connected to the second surface of the electronic integrated circuit 20, and the second end of the second interconnect structure 122 extends to the second surface of the substrate 10 and is electrically connected to a connection pad. With this configuration, the first interconnect structure 121, originating from the first surface of the substrate 10, is dedicated to transmitting power supply and conventional electrical signals; the second interconnect structure 122, originating from the second surface of the electronic integrated circuit 20, is dedicated to transmitting high-speed photoelectric signals between the photonic integrated circuit 30 and the electronic integrated circuit 20. The two interconnect structures are independently routed within the dielectric layer 11 and do not intersect, achieving physical isolation between the high-speed signal path and the conventional signal path. This prevents power supply noise from coupling to the high-speed signal line through the interconnect structure and also prevents electromagnetic radiation interference of the high-speed signal from interfering with the conventional signal, thus fundamentally ensuring signal integrity.

[0041] In one embodiment, reference is made to Figures 1-6 The first surface of the substrate 10 is also provided with a positioning member 60, the first surface of the positioning member 60 and the first surface of the electronic integrated circuit 20 are flush with the first surface of the substrate 10; the positioning member 60 is provided with a positioning hole 61; the electronic integrated circuit 20 is located in the positioning hole 61.

[0042] As an example, the first surface of the substrate 10 is also provided with a positioning element 60, which has a positioning hole 61. During the packaging substrate processing, the electronic integrated circuit 20 can be placed in the positioning hole 61, so that there is a gap between the electronic integrated circuit 20 and the positioning element 60 around it for encapsulating dielectric materials. During the packaging process, the positioning element 60 provides mechanical protection to the periphery of the electronic integrated circuit 20, preventing micro-cracks from occurring at the edges of the electronic integrated circuit 20 due to collision or thermal stress during handling, mounting, reflow soldering, and other processes. This significantly reduces the probability of edge damage to the electronic integrated circuit 20 and improves the long-term reliability of the packaging substrate. In flip-chip bonding equipment, the edge of the positioning hole 61 can be directly used as the center alignment mark of the photonic integrated circuit 30, without the need for additional alignment marks, simplifying the flip-chip bonding process, reducing alignment steps, and improving packaging efficiency. The first surface of the positioning element 60, the first surface of the electronic integrated circuit 20, and the first surface of the substrate 10 are flush, and the three together form a continuous plane. The fiber array and microlens array can be directly attached to any position on this plane, including the gap area between the positioning elements 60. The positioning element 60 provides precise positioning while occupying zero additional fiber coupling space on the first surface of the substrate 10, overcoming the problem that the EIC occupies the substrate surface space, resulting in extremely limited PIC coupling space.

[0043] In one embodiment, the distance between the outer side of the electronic integrated circuit 20 and the inner sidewall of the positioning member 60 is 0.5mm-1.5mm.

[0044] As an example, the gap between the electronic integrated circuit 20 and the positioning member 60 is filled with dielectric material, i.e., within the dielectric layer 11 of the substrate 10, to provide an insulating and fixed connection between the two. When the distance between the outer side of the electronic integrated circuit 20 and the inner sidewall of the positioning member 60 is less than 0.5 mm, it is inconvenient to fill with bottom filler. When the distance between the outer side of the electronic integrated circuit 20 and the inner sidewall of the positioning member 60 is greater than 1.5 mm, the positioning accuracy of the electronic integrated circuit 20 is poor. Therefore, the distance between the outer side of the electronic integrated circuit 20 and the inner sidewall of the positioning member 60 is limited to 0.5 mm-1.5 mm, for example, it can be set to, but is not limited to, 0.5 mm, 0.8 mm, 1.0 mm, or 1.5 mm. This provides sufficient filling space for the dielectric material between the two, which acts as a stress buffer layer during temperature changes, absorbing the shear stress caused by CTE mismatch between the electronic integrated circuit 20 and the positioning member 60; this ensures positioning accuracy and reduces void ratio.

[0045] In one embodiment, reference is made to Figure 1 and Figure 2 The positioning element 60 is a positioning copper sheet 62; the first surface of the positioning copper sheet 62 and the first surface of the electronic integrated circuit 20 are flush with the first surface of the substrate 10, and the second surface of the positioning copper sheet 62 is electrically connected to the conductive interconnection structure 12.

[0046] As an example, the positioning element 60 is a positioning copper sheet 62, which serves both as a positioning element and as a conductive interconnect. Positioning holes 61 are provided on the positioning copper sheet 62 to constrain the position of the electronic integrated circuit 20 in the horizontal plane. The first surface (top surface) of the positioning copper sheet 62 is CMP planarized and is strictly flush with the first surface of the substrate 10. The second surface (bottom surface) of the positioning copper sheet 62 extends to the second surface of the substrate 10 through the conductive interconnect structure 12 and is electrically connected to the connection pads on the second surface of the substrate, providing an electrical path for the electronic integrated circuit 20. Meanwhile, no additional positioning or conductive structures are required on the first surface of the substrate 10. The first surface of the positioning copper sheet 62, the first surface of the electronic integrated circuit 20, and the first surface of the substrate 10 are flush, resulting in zero occupancy on the first surface of the packaging carrier (no protruding electronic integrated circuits, no protruding positioning elements, and no conductive pads occupying the surface). This allows for complete fiber optic array bonding, directly overcoming the problems of "severe surface space contention and difficult optical path coupling" in existing technologies from a spatial perspective.

[0047] In one embodiment, reference is made to Figure 4 and Figure 5The positioning element 60 is a positioning copper block 63; the first surface of the positioning copper block 63 and the first surface of the electronic integrated circuit 20 are flush with the first surface of the substrate 10; the depth of the second surface of the positioning copper block 63 relative to the first surface of the substrate 10 is greater than the depth of the second surface of the electronic integrated circuit 20 relative to the first surface of the substrate 10.

[0048] As an example, the positioning element 60 is a positioning copper block 63, which serves both positioning and heat dissipation functions. Positioning holes 61 are provided on the positioning copper block 63 to constrain the position of the electronic integrated circuit 20 in the horizontal plane. The first surface (top surface) of the positioning copper block 63 is strictly flush with the first surface of the substrate 10 and coplanar with the first surface of the electronic integrated circuit 20. The depth of the second surface of the positioning copper block 63 relative to the first surface of the substrate 10 is greater than the depth of the second surface of the electronic integrated circuit 20 relative to the first surface of the substrate 10, forming a vertical heat dissipation channel. The heat from the electronic integrated circuit no longer travels along a horizontal path but directly extends through the positioning copper block 63 and the conductive interconnect structure 12 to the second surface of the substrate 10 and dissipates rapidly, reducing thermal resistance and extending chip lifespan.

[0049] In one embodiment, reference is made to Figure 1 and Figure 4 The substrate 10 includes a plurality of stacked dielectric layers 11, each dielectric layer 11 having an in-layer interconnect structure, and the in-layer interconnect structures in two adjacent dielectric layers 11 being electrically connected to form a conductive interconnect structure 12; an electronic integrated circuit 20 is embedded in the top dielectric layer 11.

[0050] As an example, substrate 10 is composed of multiple stacked dielectric layers 11. Each dielectric layer 11 contains an internal interconnect structure (copper circuitry). The internal interconnect structures in adjacent dielectric layers 11 are electrically connected via μvia or via to form conductive interconnect structures 12. An electronic integrated circuit 20 is embedded in the top dielectric layer 11, and connection pads are provided on the second surface of the bottom dielectric layer 11. With this configuration, the first surface of the electronic integrated circuit 20 is flush with the first surface of substrate 10, and all traces of the conductive interconnect structure 12 are completed within the dielectric layers 11. The first surface of substrate 10 has no protruding electronic integrated circuits, no internal interconnect leads, and no connection pads, making the surface completely clear and solely for fiber coupling. The second surface of substrate 10 carries all external electrical connections and is completely isolated from the optical path area. By embedding all electrical structures within substrate 10 through multi-layer stacking, the fiber coupling area on the first surface of substrate 10 is completely freed in three-dimensional space, significantly reducing the fiber optic density requirements and significantly improving alignment tolerance. The stacking of multiple dielectric layers 11 forms a CTE gradient transition structure from the top layer to the bottom layer, which makes the thermal stress inside the package distributed in a gradient rather than concentrated at a single interface, and the warpage is reduced compared with the traditional single-layer substrate solution.

[0051] This application provides a co-packaged optical structure, referring to... Figure 3 and Figure 6 It includes the packaging substrate and photonic integrated circuit 30 in the above embodiments; the photonic integrated circuit 30 and the first surface of the electronic integrated circuit 20 are flip-chip connected.

[0052] As an example, the co-packaged optical structure includes a packaging substrate and a photonic integrated circuit 30; wherein, the packaging substrate is the packaging substrate in the above embodiment, and its related content will not be described again; the photonic integrated circuit 30 is a silicon photonics PIC chip. During installation, the photonic integrated circuit 30 and the first surface of the electronic integrated circuit 20 are flip-chip connected, with the photonic integrated circuit 30 located directly above the electronic integrated circuit 20. The electronic integrated circuit 20 is embedded in the substrate 10, and the first surface of the electronic integrated circuit 20 is flush with the first surface of the substrate 10, so that the first surface of the substrate 10 has no structural protrusions or occupancy, forming a completely usable continuous flat plane, and the fiber array and microlens array can be directly attached to any position on the continuous flat plane.

[0053] The photonic integrated circuit 30 is flip-chip mounted on the first surface of the electronic integrated circuit 20. The electronic integrated circuit 20 is embedded in the substrate 10 and its surface is flush with the substrate. The two form a compact 3D stack in the vertical direction. By vertically stacking the electronic integrated circuit 20 and the photonic integrated circuit 30, the planar competition is transformed into spatial layering, which reduces the fiber optic arrangement density requirement and improves the alignment tolerance. Moreover, the height from the first surface of the substrate 10 to the top surface of the photonic integrated circuit 30 is much smaller than the total height when the EIC and PIC are set side by side in the traditional solution. The lower stacking height means a smaller thermal arm, and the warping moment of the package when the temperature changes is greatly reduced.

[0054] This application provides a co-packaged optical structure, referring to... Figure 3 and Figure 6 It includes the packaging substrate, photonic integrated circuit 30 and application-specific integrated circuit 50 of the above embodiments; the first surface of the photonic integrated circuit 30 and the electronic integrated circuit 20 are flip-chip connected; the application-specific integrated circuit 50 is electrically connected to the conductive lines 40 on the first surface of the substrate 10.

[0055] As an example, the co-packaged optical structure includes a packaging substrate, a photonic integrated circuit 30, and an application-specific integrated circuit 50. That is, based on the co-packaged optical structure in the above embodiments, an application-specific integrated circuit 50 is added. The packaging substrate is the same as in the above embodiments, and its details will not be repeated. The photonic integrated circuit 30 is a silicon photonics PIC chip. The application-specific integrated circuit 50 is a silicon-based TIA (transimpedance amplifier) ​​+ driver application-specific integrated circuit, a silicon photonics DSP application-specific integrated circuit, or a driver application-specific integrated circuit. During installation, the photonic integrated circuit 30 is flip-chip connected to the first surface of the electronic integrated circuit 20; the application-specific integrated circuit 50 is electrically connected to the conductive lines 40 on the first surface of the substrate 10. This configuration allows the application-specific integrated circuit 50 and the electronic integrated circuit 20 to work together, shortening the high-speed signal transmission distance. In the CPO architecture, the high-speed electrical signal output from the SerDes of the electronic integrated circuit 20 needs to be transmitted to the modulator of the photonic integrated circuit 30, while the weak analog signal output from the detector of the photonic integrated circuit 30 needs to be transmitted to the TIA. The photonic integrated circuit 30 is flip-chip mounted on the first surface of the electronic integrated circuit 20, which is embedded within the substrate 10 with a flush surface. The two form a compact 3D stack in the vertical direction. This vertical stacking of the electronic integrated circuit 20 and photonic integrated circuit 30 transforms the planar competition into spatial layering, reducing the fiber optic density requirement and improving alignment tolerance. The weak current generated by the detector in the photonic integrated circuit 30 is first transmitted to the electronic integrated circuit 20. After initial amplification within the electronic integrated circuit 20, it is transmitted via conductive line 40 to the TIA input of the application-specific integrated circuit 50 via an extremely short path. Compared to traditional solutions where the detector signal needs to travel several millimeters within the substrate to reach the TIA, this solution shortens the signal transmission distance, reduces the bandwidth loss of the detector signal, and directly supports higher-speed optoelectronic collaboration.

[0056] As an example, the co-packaged optical structure is a silicon photonics CPO structure, which can be widely used in scenarios with extreme requirements for bandwidth, power consumption and size, including but not limited to: (1) Data center switches: optoelectronic co-packaging of ultra-large capacity switching chips. (2) Artificial intelligence and machine learning clusters: high-speed optical interconnects within AI accelerators (such as GPU and TPU clusters) and between nodes. (3) High-performance computing (HPC): high-density optical interconnect networks inside supercomputers. (4) 5G / 6G telecommunications infrastructure: miniaturization and high-efficiency evolution of core network routers and base station front-end optical modules.

[0057] This application provides a method for manufacturing a packaging carrier board, referring to... Figure 7 , Figure 8 and Figure 9 ,include: S1: Conductive lines 40 are processed on the surface of a separable carrier to obtain a first substrate, the first substrate including mutually separated conductive lines 40 and a chip placement area; S2: Place the electronic integrated circuit 20 in the chip placement area so that the first surface of the electronic integrated circuit 20 abuts against the first substrate; S3: A dielectric layer 11 is laminated onto the first substrate and the electronic integrated circuit 20, and a conductive interconnection structure 12 is processed in the dielectric layer 11 to obtain a second substrate; the first end of the conductive interconnection structure 12 is electrically connected to the second surface of the electronic integrated circuit 20 and the conductive line 40, and the second end of the conductive interconnection structure 12 extends to the second surface of the dielectric layer 11. S4: Perform a separation operation on the second substrate, remove the separable carrier board, and obtain the encapsulation carrier board.

[0058] As an example, in step S1, a separable substrate is first selected, and then conductive lines 40 are fabricated on its surface through a process of applying dry film → exposure → development → electroplating → film peeling, resulting in the first substrate. The conductive lines 40 extend from the center of the substrate outwards to form four sets of signal pad arrays and two sets of power pad arrays. The blank areas between the conductive lines 40 are the chip placement areas, used to place the chips.

[0059] As an example, in step S2, the installation of the electronic integrated circuit 20 can be carried out in two ways: First, a die bonding film (DFA) is selected, cut to the required shape, and applied to the surface of the chip placement area. A high-precision pick-and-place machine is used to place the electronic integrated circuit 20 with its second surface facing down and its first surface facing up on the die bonding film, ensuring complete adhesion between the first surface of the electronic integrated circuit 20 and the die bonding film. Subsequently, it is hot-pressed and cured at 180°C and 2MPa for 60 seconds, allowing the die bonding film to fully cure. The first surface of the electronic integrated circuit 20 is then firmly bonded to the chip placement area of ​​the first substrate, with the two surfaces tightly abutting each other, completing the installation of the electronic integrated circuit 20. The action of the die bonding film reduces pressure offset. Second, without using a die bonding film, the first surface of the electronic integrated circuit 20 is installed in the chip placement area of ​​the first substrate using direct bonding.

[0060] As an example, in step S3, a dielectric layer 11 (such as epoxy resin or polyimide) is first laminated onto the first substrate and the already bonded integrated circuit 20. The dielectric layer 11 completely covers the top surface and sidewalls of the first substrate and the integrated circuit 20, achieving insulation and isolation while enhancing structural strength and providing support for subsequent drilling and metallization. Then, laser technology is used to drill through-holes or blind holes in the laminated structure, opening up interlayer conductive pathways to prepare for metallization. Subsequently, the drilled structure undergoes metallization treatment (such as chemical copper plating or electroplating) to form interlayer conductive connections, i.e., processing intralayer interconnect structures. The first end of the interconnect structure is electrically connected to the second surface of the integrated circuit 20 via copper pillars, and the second end extends to the second surface of the dielectric layer 11. Multiple layers of dielectric layers 11 are then laminated sequentially to further insulate and isolate the metal layers, preventing signal crosstalk and reinforcing the overall structure. Finally, radium-drilled blind holes, metallization, and patterning are performed to form the circuit pattern. Each layer contains corresponding intralayer interconnect structures, and the layers are electrically connected vias to ultimately form a complete conductive interconnect structure 12. The second end of the conductive interconnect structure 12 extends from the second surface of the bottom dielectric layer 11 to form the second substrate.

[0061] As an example, in step S4, an ultraviolet laser is used to cut along the interface between the separable carrier and the top dielectric layer. The cutting depth is precisely controlled within the thickness range of the separable carrier to avoid damaging the top dielectric layer. After cutting, an automatic depaneling machine is used for depaneling, for example, by hot pressing at 150°C to peel off the separable carrier, exposing the bottom surface of the conductive lines 40. Subsequently, solder mask processing is performed on the second surface of the dielectric layer 11 to connect the pads, resulting in the encapsulation carrier.

[0062] In this example, the adhesive film completely fills the space between the first surface of the electronic integrated circuit 20 and the first substrate, and the first surface of the electronic integrated circuit 20 remains strictly flush with the first substrate after bonding. When the photonic integrated circuit 30 is flip-chip mounted on the first surface of the electronic integrated circuit 20, its solder joints directly contact the active surface of the electronic integrated circuit 20, with no adhesive film residue in between (the adhesive film is compressed to the area outside the edge of the electronic integrated circuit 20). In this way, the first surface of the substrate 10 (including the first surface of the electronic integrated circuit 20) forms a completely continuous flat plane, with no solder protrusions, no copper pillar protrusions, and no adhesive film overflow, allowing the fiber array to fully utilize this plane for coupling. After the adhesive film cures, a permanent bond is formed between the electronic integrated circuit 20 and the first substrate, which can withstand vibration acceleration of ±5g without displacement. This eliminates the need for additional fixtures between steps S2 and S3, simplifying the transfer process and improving yield. Precise control of the adhesive film thickness allows the gap to be stably maintained within the design range of 0.5mm-1.5mm, providing a precise process window for reliable filling of the subsequent bottom filler adhesive and directly supporting the realization of the gap range in the claims.

[0063] In one embodiment, reference is made to Figure 8 and Figure 9 In step S1, conductive lines 40 are processed on the surface of the separable carrier to obtain the first substrate, including: S11: Dry film is applied, exposed and developed on the surface of the separable carrier plate to obtain a carrier plate containing the developed pattern area; S12: Electroplating and film stripping operations are performed on the carrier plate containing the developed pattern area to obtain the first plate.

[0064] As an example, in step S11, a layer of dry film photoresist is first applied to the surface of the separable substrate, ensuring it is free of bubbles and wrinkles. Then, an LDI (Laser Direct Imaging) device with a wavelength of 405nm is used to pattern the dry film. The exposed pattern is a fine RDL wiring, including four signal pad arrays and two power pad arrays. The dry film is then developed using a sodium carbonate developer (1.0% concentration) for 45 seconds. After development, the dry film in the unexposed areas is dissolved and removed, while the dry film in the exposed areas remains, forming the developed pattern area. This developed pattern area serves as the seed layer for subsequent electroplating, while the exposed copper foil areas are etched away. This setup, by applying a dry film to the separable substrate, transferring the pattern onto the dry film through an exposure process, and then removing the unexposed areas through development, forms the initial circuit pattern, preparing for electroplating.

[0065] As an example, in step S12, pattern electroplating is first performed on the developed substrate. A nickel layer is first electroplated as a base, followed by a copper layer as the conductive substrate. After electroplating, the dry film is peeled off using a 2% sodium hydroxide solution (50°C) for 60 seconds. After the dry film is removed, the exposed copper foil areas not protected by electroplating are then etched away with an acidic etching solution (copper chloride system), leaving only the conductive lines 40 corresponding to the developed pattern area, ultimately obtaining the first substrate. This setup, with copper electroplating in the developed pattern area to form the conductive lines 40 and chip placement area, improves accuracy for subsequent chip mounting and alignment.

[0066] In this example, the development operation not only defines the pattern of the conductive line 40 but also precisely defines the boundary of the chip placement area. When the electronic integrated circuit 20 is placed in the chip placement area, the alignment accuracy of its edge with the boundary of the placement area is directly determined by the edge accuracy of the developed pattern. The stripping step uses an alkaline solution (NaOH) to remove the dry film. The interface between the dry film and the copper layer is chemically bonded, and the copper layer edge is not pulled during stripping. After stripping, the edges of the conductive line 40 have sharp vertical sidewalls, without copper layer burrs caused by dry film residue. The dry film pattern directly defines the final linewidth, and the linewidth accuracy is determined by the exposure accuracy and is independent of subsequent processes, reducing the risk of short circuits.

[0067] In one embodiment, reference is made to Figure 8The developing pattern area includes mutually separated line areas and positioning areas; Electroplating and stripping operations are performed on a carrier board containing the developed pattern area to obtain a first board material, including: electroplating and stripping operations are performed on both the circuit area and the positioning area of ​​the carrier board containing the developed pattern area, so that the circuit area forms a conductive line 40 and the positioning area forms a positioning copper sheet 62, to obtain the first board material; positioning holes 61 are formed in the positioning copper sheet 62 to form a chip placement area. Placing the electronic integrated circuit 20 within the chip placement area includes: placing the electronic integrated circuit 20 within the chip placement area such that the distance between the outer side of the electronic integrated circuit 20 and the inner sidewall of the positioning copper sheet 62 is 0.5mm-1.5mm.

[0068] As an example, the developed pattern area formed after the separable carrier board undergoes dry film application, LDI exposure, and development includes a circuit area and a positioning area. The circuit area is distributed along the four sides and center of the carrier board, and its pattern is a fine RDL, containing four signal pad arrays and two power pad arrays. The total area of ​​the circuit area occupies approximately 60% of the carrier board surface. There are four positioning areas, located at the four corners of the carrier board. Each positioning area has a square outer contour and a square opening in the center (this opening is the prototype of the subsequent positioning hole 61). The total area of ​​the positioning area occupies approximately 16% of the carrier board surface. An isolation strip separates the circuit area and the positioning area to ensure that they are completely separated and not interconnected in the developed pattern.

[0069] Electroplating and stripping operations are performed on a carrier board containing the developed pattern area to obtain the first substrate. The specific steps are as follows: First, both the circuit area and the positioning area of ​​the carrier board containing the developed pattern area are electroplated. Then, a stripping operation is performed. The circuit area and the positioning area are completed simultaneously in the same electroplating and stripping process, eliminating the need for separate processing steps, reducing the number of processes and equipment usage, and improving production efficiency. Specifically, after electroplating, the circuit area forms conductive lines 40, and after electroplating, the positioning area forms positioning copper sheets 62. After stripping, excess dry film is removed, retaining the copper layer structure on the circuit area and the positioning area, to obtain the first substrate.

[0070] The electronic integrated circuit 20 is placed in the chip placement area. Specifically, a positioning hole 61 is formed on the positioning copper sheet 62, penetrating the copper sheet 62 to create a chip placement area in the center of the copper sheet 62. The positioning hole 61 can be circular, square, or other regular shapes; in this embodiment, it is circular with a diameter matching the external dimensions of the electronic integrated circuit 20. Then, the electronic integrated circuit 20 is placed in the chip placement area. During placement, the distance between the outer edge of the electronic integrated circuit 20 and the inner wall of the positioning copper sheet 62 is controlled to be 0.5mm to 1.5mm, preferably 1.0mm. Specifically, the electronic integrated circuit 20 is fixed to the chip placement area by bonding or dispensing. The inner wall of the positioning copper sheet 62 provides circumferential positioning for the electronic integrated circuit 20, preventing it from shifting during subsequent processes or use. The positioning component 60 has a positioning hole 61 (i.e., a hollowed-out hole in the middle of a copper sheet or copper block). The size of the hollowed-out hole is the size of the electronic integrated circuit 20 plus 0.1mm on each side. The bottom of the positioning component 60 has an adhesive film. After positioning on the graphic circuit, the positioning component 60 is attached to the separable carrier board. The positioning component 60 is identified by the placement equipment, and the electronic integrated circuit 20 is placed in the hollowed-out position in the middle of the positioning component 60.

[0071] In this example, the distance between the outer edge of the electronic integrated circuit 20 and the inner wall of the positioning copper plate 62 is 0.5mm to 1.5mm. This ensures the effectiveness of circumferential positioning while avoiding thermal stress damage caused by an excessively small gap or positioning failure caused by an excessively large gap. It also provides a reasonable thermal expansion buffer space for the electronic integrated circuit 20, effectively absorbing thermal expansion deformation when the chip generates heat during operation, preventing mechanical interference between the chip edge and the positioning copper plate 62, and improving the long-term reliability of the product.

[0072] In one embodiment, reference is made to Figure 9 The developing pattern area includes mutually separated line areas and positioning areas; Electroplating and stripping operations are performed on a carrier board containing the developed pattern area to obtain a first board material, including: electroplating and stripping operations on the circuit area of ​​the carrier board containing the developed pattern area, and stripping operations on the positioning area of ​​the carrier board containing the developed pattern area, so that the circuit area forms a conductive line 40 and the positioning area is exposed, thereby obtaining the first board material. Placing the electronic integrated circuit 20 within the chip placement area includes: attaching a positioning copper block 63 to the positioning area, wherein the positioning copper block 63 has positioning holes 61 to form the chip placement area; placing the electronic integrated circuit 20 within the chip placement area such that the distance between the outer side of the electronic integrated circuit 20 and the inner sidewall of the positioning copper block 63 is 0.5mm-1.5mm, and the thickness of the positioning copper block 63 is greater than the thickness of the electronic integrated circuit 20.

[0073] As an example, the developed pattern area formed after dry film application, LDI exposure, and development of the separable carrier board includes a circuit area and a positioning area. The circuit area is distributed along the four sides and center of the carrier board, with a fine RDL pattern containing four signal pad arrays and two power pad arrays. The total area of ​​the circuit area occupies approximately 60% of the carrier board surface. There are four positioning areas, located at the four corners of the carrier board. Each positioning area has a square outer contour and a square opening in the center (this opening is the prototype of the subsequent positioning hole 61). The total area of ​​the positioning area occupies approximately 16% of the carrier board surface. An isolation strip separates the circuit area and the positioning area to ensure complete separation and non-interconnection in the developed pattern. The circuit area is electroplated to form conductive lines 40, while the positioning area is only stripped without electroplating, leaving the exposed copper surface for subsequent attachment of the positioning copper block 63. The two areas are treated differently, ensuring the conductivity of the circuit area while reserving an independent secondary processing interface for the positioning area, significantly improving process flexibility.

[0074] Electroplating and stripping operations are performed on the carrier board containing the developed pattern area to obtain the first board material. The specific steps are as follows: First, the circuit area of ​​the carrier board is electroplated to thicken the copper layer of the circuit area to the designed thickness. Then, a stripping operation is performed to remove the dry film on the circuit area to form conductive circuit 40. At the same time, the positioning area of ​​the carrier board is not electroplated, but only stripped to remove the dry film on the positioning area, so that the copper surface of the positioning area is exposed to obtain the first board material.

[0075] The electronic integrated circuit 20 is placed within the chip placement area. The specific steps are as follows: A positioning copper block 63 is attached to the exposed copper surface of the positioning area on the first substrate using conductive adhesive to ensure a reliable electrical connection and mechanical fixation between the positioning copper block 63 and the copper surface of the positioning area. A positioning hole 61 is formed in the positioning copper block 63, penetrating the block and creating a chip placement area in the center. In this embodiment, the side length of the positioning hole 61 is adapted to the external dimensions of the electronic integrated circuit 20. The electronic integrated circuit 20 is then placed within the chip placement area. During placement, the distance between the outer edge of the electronic integrated circuit 20 and the inner sidewall of the positioning copper block 63 is controlled to be 0.5mm to 1.5mm. The thickness of the positioning copper block 63 is greater than the thickness of the electronic integrated circuit 20, ensuring that the upper surface of the positioning copper block 63 is higher than the upper surface of the electronic integrated circuit 20, thus providing circumferential enclosure and height-direction restraint for the electronic integrated circuit 20.

[0076] In this example, the positioning copper block 63 is attached to the positioning area as an independent component. Its material and thickness can be selected individually according to the specific requirements of the electronic integrated circuit 20, without being limited by the original copper layer thickness of the carrier board. In this solution, the thickness of the positioning copper block 63 is greater than the thickness of the electronic integrated circuit 20, making the upper surface of the positioning copper block 63 higher than the upper surface of the chip, forming an effective height-direction limit to prevent the chip from falling out under vibration or impact. A distance of 0.5mm to 1.5mm is maintained between the outer side of the electronic integrated circuit 20 and the inner sidewall of the positioning copper block 63. This ensures the reliability of the circumferential limit of the electronic integrated circuit 20 by the positioning copper block 63, avoids thermal stress concentration caused by too small a distance and positioning failure caused by too large a distance, and also reserves a reasonable airflow channel for chip heat dissipation; it also provides a buffer for thermal expansion and reduces the risk of mechanical stress damage caused by temperature difference. The thickness of the positioning copper block 63 is greater than the thickness of the electronic integrated circuit 20. The positioning copper block 63 not only plays a positioning role, but also serves as a heat dissipation auxiliary structure, conducting the heat generated by the electronic integrated circuit 20 to the positioning area of ​​the carrier board through the positioning copper block 63, thus expanding the heat dissipation path.

[0077] In one embodiment, reference is made to Figure 8 and Figure 9 A dielectric layer 11 is laminated onto the first substrate and the electronic integrated circuit 20, and a conductive interconnect structure 12 is fabricated within the dielectric layer 11 to obtain a second substrate, comprising: Multiple layer-addition operations are performed on the first substrate and the electronic integrated circuit 20; Each layer addition operation includes: laminating the current dielectric layer onto the separable carrier and electronic integrated circuit 20, or laminating the current dielectric layer onto the previous dielectric layer; performing drilling and metallization operations on the current dielectric layer to obtain the intralayer interconnect structure corresponding to the current dielectric layer, wherein the intralayer interconnect structures in two adjacent dielectric layers 11 are electrically connected to form a conductive interconnect structure 12.

[0078] As an example, a dielectric layer 11 is laminated on the first substrate and the electronic integrated circuit 20, and a conductive interconnect structure 12 is processed in the dielectric layer 11 to obtain the second substrate. The specific steps are as follows: First, multiple layer addition operations are performed on the first substrate and the electronic integrated circuit 20. For example, when it is necessary to laminate three dielectric layers 11 and process their corresponding intra-layer interconnect structures, the processing process is as follows: (1) First, the first layer addition operation is performed. The first dielectric layer is laminated on the first substrate (the surface of the separable carrier board carries the conductive lines 40, and the electronic integrated circuit 20 has been fixed in the chip placement area by the adhesive film) and the electronic integrated circuit 20. The first dielectric layer completely covers the sidewalls and top surface of the electronic integrated circuit 20, and at the same time covers the conductive lines 40 on the surface of the first substrate. Then, laser drilling and electroplating copper metallization operations are performed in the first dielectric layer to form the first intra-layer interconnect structure. At this time, the first end of the first intra-layer interconnect structure is electrically connected to the second surface of the electronic integrated circuit 20, and its second end extends to the second surface of the first dielectric layer. (2) A second layering operation is performed. A second dielectric layer is laminated onto the second surface of the first dielectric layer. The first and second dielectric layers are bonded at the molecular level through thermo-pressing, resulting in a void-free interface. Laser drilling and copper plating are performed within the second dielectric layer to form an internal interconnect structure. At this point, the first end of the internal interconnect structure is electrically connected to the second end of the internal interconnect structure at the interface between the first and second dielectric layers. (3) Finally, a third layering operation is performed. A third dielectric layer is laminated onto the second surface of the second dielectric layer. Laser drilling and copper plating are performed within the third dielectric layer to form an internal interconnect structure. At this point, the internal interconnect structure is electrically connected to the internal interconnect structure of the second dielectric layer at the interface between the second and third dielectric layers. After all layering operations are completed, a second substrate is obtained.

[0079] In this example, each layer-adding operation only involves drilling and metallizing the current dielectric layer. The intra-layer interconnects between adjacent layers are electrically connected via through-holes, eliminating the need to drill all layers at once. This significantly reduces drilling alignment difficulty and improves the yield of inter-layer interconnects. During the initial lamination, a removable carrier board is used to cover the electronic integrated circuit 20, providing mechanical protection during lamination and drilling to prevent damage from pressure and drill debris. The removable carrier board is removed in subsequent operations without affecting the final product structure. By repeatedly performing layer-adding operations, the number of dielectric layers 11 can be easily increased to meet the interconnection needs of electronic integrated circuits 20 with varying complexity. The same process platform can cover multiple products, reducing production line switchover costs.

[0080] In one embodiment, reference is made to Figure 8 and Figure 9 The second substrate is separated to remove the separable carrier board, resulting in a packaging carrier board, including: The second board is separated by removing the separable carrier plate to obtain the third board. The third substrate is subjected to solder resist coating, exposure, development and curing operations to obtain a packaging carrier board containing a protective layer.

[0081] As an example, the second substrate is depaneled to remove the separable carrier board, resulting in a packaging carrier board. The specific steps are as follows: First, an ultraviolet laser is used to cut along the interface between the separable carrier board and the dielectric layer 11. After cutting, the separable carrier board is peeled off from the surface of the dielectric layer 11 using a depaneling machine to obtain the third substrate. Then, liquid photosensitive solder resist ink is first coated onto the top of the third substrate (the second surface of the top dielectric layer) using a spin-coating method. Next, LDI laser direct imaging is used to pattern the solder resist ink, retaining the pad area of ​​the conductive lines 40 in the exposed pattern, while the remaining areas are completely shielded. Then, a 1% sodium carbonate aqueous solution (30°C) is used for development for 45 seconds, dissolving and removing the solder resist ink in the unexposed areas, while retaining the exposed areas to form precise pad openings. Finally, the substrate is thermally cured at 200°C for 60 minutes, allowing the solder resist ink to fully cross-link and cure, forming a protective layer. Subsequently, the third substrate is flipped over, and the above coating → exposure → development → curing operation is repeated on the bottom (the second surface of the bottom dielectric layer, the surface where the pads are located). The exposure pattern retains the BGA pad array connecting the pads, while the remaining areas are covered with a solder mask. After curing, the copper surface of the connecting pads is exposed, completely protected by the solder mask. The final package substrate has protective layers on both the front and back. The pads of the conductive lines 40 and the top layer pads of the conductive interconnect structure 12 are exposed through solder mask openings, ready for subsequent soldering.

[0082] In this example, solder resist coating, exposure, development, and curing are performed on both the front and back sides, ensuring precise protection of the pads of the conductive lines 40 and the conductive interconnect structure 12 on both sides. The solder resist layer effectively prevents pad oxidation, short circuits, and solder bridging, significantly improving the electrical reliability and long-term storage stability of the package substrate. After curing, the solder resist layer has high hardness and strong adhesion, and can withstand the high-temperature impact of subsequent reflow soldering, preventing issues such as blistering, peeling, or warping, thus ensuring the structural integrity of the package substrate during multiple soldering processes. Performing the same solder resist process on both the front and back sides ensures symmetrical protective layer thickness and stress state on both sides, effectively offsetting board warping issues caused by single-sided coating, resulting in better flatness of the package substrate and facilitating precision control in subsequent surface mount and soldering processes.

[0083] This application provides a method for manufacturing a co-packaged optical structure, referring to... Figure 8 , Figure 9 and Figure 10 ,include: S1: Conductive lines 40 are processed on the surface of a separable carrier to obtain a first substrate, the first substrate including mutually separated conductive lines 40 and a chip placement area; S2: Place the electronic integrated circuit 20 in the chip placement area so that the first surface of the electronic integrated circuit 20 abuts against the first substrate; S3: A dielectric layer 11 is laminated onto the first substrate and the electronic integrated circuit 20, and a conductive interconnection structure 12 is processed in the dielectric layer 11 to obtain a second substrate; the first end of the conductive interconnection structure 12 is electrically connected to the second surface of the electronic integrated circuit 20 and the conductive line 40, and the second end of the conductive interconnection structure 12 extends to the second surface of the dielectric layer 11. S4: Perform a separation operation on the second board material to remove the separable carrier board and obtain the encapsulation carrier board; S5: Flip-chip the electronic integrated circuit 20 onto the first surface of the photonic integrated circuit 30 to obtain a co-packaged optical structure; or, flip-chip the electronic integrated circuit 20 onto the first surface of the photonic integrated circuit 30 and package the application-specific integrated circuit 50 onto the first surface of the substrate 10 to obtain a co-packaged optical structure.

[0084] As an example, steps S1-S4 are the same as the manufacturing method of the packaging substrate in the above embodiments, and will not be described again. Step S5 includes two methods: The first method involves taking a photonic integrated circuit 30 (such as a silicon photonics PIC chip) and placing it on a temporary carrier with its first surface (active surface) facing upwards. Then, take an electronic integrated circuit 20 from the packaging substrate (either by laser stripping or by using an additional identical electronic integrated circuit 20), and mount it onto the first surface of the photonic integrated circuit 30 with its second surface (pad surface) facing downwards using a flip-chip method. At this point, the first surface (active surface) of the electronic integrated circuit 20 is facing upwards, and the second surface (waveguide end face) of the photonic integrated circuit 30 is facing upwards, ultimately resulting in a co-packaged optical structure.

[0085] The second method involves using a dedicated integrated circuit 50 as a driver circuit chip (TIA / LA chip). A photonic integrated circuit 30 (such as a silicon photonics PIC chip) is taken and placed on a temporary carrier with its first surface (active surface) facing upwards. An electronic integrated circuit 20 is taken from the packaging substrate (either by laser peeling or by using an additional identical electronic integrated circuit 20), and its second surface (pad surface) is placed downwards on the first surface of the photonic integrated circuit 30 using a flip-chip method. At this point, the first surface (active surface) of the electronic integrated circuit 20 is facing upwards, and the second surface (waveguide end face) of the photonic integrated circuit 30 is facing upwards. Simultaneously, conductive adhesive is applied to the area on the first surface of the packaging substrate, adjacent to the photonic integrated circuit 30, and the dedicated integrated circuit 50 is placed in this area in a positive mounting manner. With its active surface facing upwards, the dedicated integrated circuit 50 is electrically connected to the conductive interconnection structure 12 pads on the first surface of the packaging substrate via the conductive adhesive. The application-specific integrated circuit 50 is used to perform electrical domain processing (such as transimpedance amplification, limiting amplification, etc.) on the optical signal of the photonic integrated circuit 30. Its output terminal is electrically connected to the electronic integrated circuit 20 through the conductive interconnect structure 12, realizing the coordinated processing of photoelectric signals, avoiding signal attenuation and noise introduction caused by long-distance transmission, and improving the signal-to-noise ratio of the photoelectric conversion link. The first surface of the substrate 10 sequentially carries the photonic integrated circuit 30, the flip-chip electronic integrated circuit 20, and the upright-mounted application-specific integrated circuit 50. The three are electrically interconnected through the conductive interconnect structure 12 and the solder layer, forming a complete optoelectronic co-package system. Compared with discrete device solutions, the package area is reduced and the system-level power consumption is reduced.

[0086] In this example, the electronic integrated circuit 20 is flip-chip mounted on the first surface of the photonic integrated circuit 30. The electrical connection path between the electronic integrated circuit 20 and the photonic integrated circuit 30 is extremely short, significantly reducing interconnect parasitic inductance and resistance compared to the conventional mounting scheme. This is beneficial for high-speed signal transmission and improves the photoelectric conversion efficiency and signal integrity of the co-packaged optical structure. The conductive interconnect structure 12 extends from the second surface (pad side, facing up) of the electronic integrated circuit 20 to the second surface of the dielectric layer 11, giving the second surface of the electronic integrated circuit 20 complete flip-chip pads. This allows the electronic integrated circuit 20 to be directly flip-chip mounted on the photonic integrated circuit 30 with its second surface facing down, eliminating the need for an additional redistribution layer (RDL) and simplifying the flip-chip process.

[0087] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A packaging carrier board, characterized in that, Including substrates and electronic integrated circuits; The first surface of the substrate is provided with conductive lines, and the substrate includes a dielectric layer and conductive interconnect structures embedded in the dielectric layer; The electronic integrated circuit is embedded in the dielectric layer corresponding to the first surface of the substrate, and the first surface of the electronic integrated circuit is exposed on the first surface of the substrate. The first surface of the electronic integrated circuit is used for flip-chip connection with the photonic integrated circuit. The first end of the conductive interconnect structure is electrically connected to the second surface of the electronic integrated circuit and the conductive line, and the second end of the conductive interconnect structure extends to the second surface of the substrate.

2. The packaging carrier board according to claim 1, characterized in that, The first surface of the substrate is further provided with a positioning element, and the first surface of the positioning element and the first surface of the electronic integrated circuit are flush with the first surface of the substrate. The positioning element has a positioning hole; the electronic integrated circuit is located inside the positioning hole.

3. The packaging carrier board according to claim 2, characterized in that, The distance between the outer side of the electronic integrated circuit and the inner sidewall of the positioning member is 0.5mm-1.5mm.

4. The packaging carrier board according to claim 2, characterized in that, The positioning element is a positioning copper sheet; The first surface of the positioning copper sheet and the first surface of the electronic integrated circuit are flush with the first surface of the substrate, and the second surface of the positioning copper sheet is electrically connected to the conductive interconnect structure.

5. The packaging carrier board according to claim 2, characterized in that, The positioning element is a positioning copper block; The first surface of the positioning copper block and the first surface of the electronic integrated circuit are flush with the first surface of the substrate. The depth of the second surface of the positioning copper block relative to the first surface of the substrate is greater than the depth of the second surface of the electronic integrated circuit relative to the first surface of the substrate.

6. The packaging carrier board according to claim 1, characterized in that, The substrate includes multiple stacked dielectric layers, each dielectric layer having an intralayer interconnect structure, and the intralayer interconnect structures in two adjacent dielectric layers being electrically connected to form the conductive interconnect structure. The electronic integrated circuit is embedded in the dielectric layer at the top.

7. A co-packaged optical structure, characterized in that, It includes a photonic integrated circuit and a packaging substrate as described in any one of claims 1-6; the photonic integrated circuit is flip-chip connected to the first surface of the electronic integrated circuit.

8. A co-packaged optical structure, characterized in that, It includes a photonic integrated circuit, an application-specific integrated circuit, and a packaging substrate as described in any one of claims 1-6; the photonic integrated circuit is flip-chip connected to the first surface of the electronic integrated circuit; the application-specific integrated circuit is electrically connected to the conductive lines on the first surface of the substrate.

9. A method for manufacturing a packaging carrier board, characterized in that, include: Conductive lines are processed on the surface of a separable substrate to obtain a first substrate, the first substrate including mutually spaced conductive lines and a chip placement area; An electronic integrated circuit is placed in the chip placement area such that the first surface of the electronic integrated circuit abuts against the first substrate. A dielectric layer is laminated onto the first substrate and the electronic integrated circuit, and a conductive interconnect structure is fabricated within the dielectric layer to obtain a second substrate; a first end of the conductive interconnect structure is electrically connected to the second surface of the electronic integrated circuit and the conductive line, and a second end of the conductive interconnect structure extends to the second surface of the dielectric layer; The second substrate is separated to remove the separable carrier board, resulting in a packaging carrier board.

10. A method for manufacturing a co-packaged optical structure, characterized in that, include: Conductive lines are processed on the surface of a separable substrate to obtain a first substrate, the first substrate including mutually spaced conductive lines and a chip placement area; An electronic integrated circuit is placed in the chip placement area such that the first surface of the electronic integrated circuit abuts against the first substrate. A dielectric layer is laminated onto the first substrate and the electronic integrated circuit, and a conductive interconnect structure is fabricated within the dielectric layer to obtain a second substrate; a first end of the conductive interconnect structure is electrically connected to the second surface of the electronic integrated circuit and the conductive line, and a second end of the conductive interconnect structure extends to the second surface of the dielectric layer; The second board is separated to remove the separable carrier board, resulting in a packaging carrier board. The electronic integrated circuit is flip-chipped onto the first surface of the photonic integrated circuit to obtain a co-packaged optical structure; Alternatively, the electronic integrated circuit can be flip-chipped onto the first surface of the photonic integrated circuit, and the application-specific integrated circuit can be packaged on the first surface of the substrate to obtain a co-packaged optical structure.

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