A method for manufacturing a packaging structure and a packaging structure

Abstract

The application provides a preparation method of a packaging structure and the packaging structure. The method comprises the following steps: simultaneously forming a first blind groove and a second blind groove which are arranged correspondingly and a through hole which penetrates the glass core plate and is arranged at intervals from the first blind groove and the second blind groove on the glass core plate; performing flame polishing treatment on each blind groove, reducing the surface roughness of the bottom of each blind groove, improving the maximum bending stress, improving the structural mechanical reliability of the bottom of each blind groove, and reducing the risk of glass cracking; the projection of the first blind groove and the second blind groove which are arranged correspondingly on the glass core plate in the thickness direction of the glass core plate overlaps, and the thickness of the glass core plate between the first blind groove and the second blind groove is controlled within the range of 50-300 μm; after an interconnection conductive column is made based on the through hole, an active chip and a passive device which are respectively embedded in the first blind groove and the second blind groove correspondingly and have their respective bonding pads facing the outside of the glass core plate, the planar packaging size, the lateral power supply path between the active chip and the passive device, and the parasitic inductance under high transient current are reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and relates to a method for preparing a packaging structure and the packaging structure itself. Background Technology

[0002] As semiconductor packaging technology evolves towards System-in-Package (SiP) and heterogeneous chip integration, higher demands are being placed on the signal transmission rate, power integrity, and structural stability of the packaging substrate. Glass substrates, with their advantages of high frequency and low loss, adjustable coefficient of thermal expansion (CTE) close to that of silicon, and high Young's modulus, are gradually becoming an important solution for high-performance chip packaging.

[0003] Existing glass-substrate embedded packaging typically employs a single-sided slotting process, embedding the chip into a blind slot on one side of the glass core, and achieving electrical interconnection through double-sided layering. Because the chip is only embedded on one side of the substrate, the substrate has an asymmetrical structure in the thickness direction. When heated, the stress on both sides cannot cancel each other out, easily leading to significant warping deformation, affecting subsequent photolithography alignment accuracy, and even causing microcracks or open interconnects in the chip. On the other hand, to meet the transient current requirements of high-performance chips, the package structure needs to integrate silicon capacitors to stabilize voltage and filter ripple. Current technologies often surface-mount the silicon capacitors on the layer surface or place them on the same side as the chip. This approach not only increases the XY plane dimensions of the package but also results in a longer lateral power supply path between the capacitor and the chip (typically several millimeters), introducing parasitic inductance that weakens the high-frequency decoupling effect of the silicon capacitor.

[0004] Therefore, there is an urgent need to develop a new packaging substrate structure and fabrication method to solve the problems of warpage and low integration of passive devices caused by single-sided embedding. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for preparing a packaging structure and a packaging structure, so as to solve the problems of warpage and low integration of passive devices in the packaging structure of the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for preparing an encapsulation structure, comprising the following steps:

[0007] A glass core board is provided, the glass core board including a first surface and a second surface disposed opposite to each other;

[0008] A first blind groove located on the first surface and a second blind groove located on the second surface are simultaneously formed, and the first blind groove and the second blind groove are flame polished to form a through hole penetrating the first surface and the second surface. The through hole is spaced apart from the first blind groove and the second blind groove. The first blind groove and the second blind groove are arranged one-to-one. The projections of the corresponding first blind groove and the second blind groove on the glass core plate overlap along the thickness direction of the glass core plate. The thickness range of the glass core plate between the corresponding first blind groove and the second blind groove is 50 μm - 300 μm.

[0009] Interconnected conductive pillars are formed to at least fill the through holes, and active chips and passive devices are respectively embedded in the first blind trench and the second blind trench. The active chip has a side with a first pad facing away from the bottom of the first blind trench, and the passive device has a side with a second pad facing away from the bottom of the first blind trench.

[0010] An interconnect structure electrically connected to the first pad and the second pad is formed on the first surface and the second surface;

[0011] A solder resist layer is formed that covers the side of the interconnect structure facing away from the glass core and exposes the surface of the metal interconnect layer in the interconnect structure;

[0012] Conductive bumps are formed that are electrically connected to the metal interconnect layer to obtain the package structure.

[0013] Optionally, the coefficient of thermal expansion of the glass core plate is 3 ppm / ℃-8 ppm / ℃; the thickness of the glass core plate is 0.2 mm-1.1 mm.

[0014] Optionally, the diameter of the through hole is greater than or equal to 30 μm.

[0015] Optionally, forming the first blind slot and the second blind slot includes the following steps:

[0016] Laser-induced technology is used to perform laser modification treatment on a first preset area on a first surface and a second preset area on a second surface to form a first modified area and a second modified area.

[0017] The first modified region and the second modified region are removed simultaneously by wet etching to form the first blind trench and the second blind trench.

[0018] Optionally, the flame temperature range of the flame polishing treatment is 1300 ℃-1600 ℃.

[0019] Optionally, the scanning speed of the flame polishing process is in the range of 8 mm / s to 15 mm / s.

[0020] Optionally, along the thickness direction of the glass core plate, the projection of the first blind groove on the glass core plate is located within the projection of the second blind groove on the glass core plate; or, along the thickness direction of the glass core plate, the projection of the second blind groove on the glass core plate is located within the projection of the first blind groove on the glass core plate.

[0021] Optionally, embedding the active chip and the passive device includes the following steps:

[0022] A first adhesive layer is formed on the side of the active chip facing away from the first pad, and a second adhesive layer is formed on the side of the passive device facing away from the second pad.

[0023] The active chip with the first adhesive layer is transferred into the first blind slot, with the first adhesive layer located between the active chip and the bottom of the first blind slot, and the first adhesive layer is cured.

[0024] The passive device having the second adhesive layer is transferred into the second blind groove, with the second adhesive layer located between the passive device and the bottom of the second blind groove, and the second adhesive layer is cured.

[0025] Optionally, the passive device is a silicon capacitor.

[0026] The present invention also provides a packaging structure, the packaging structure comprising:

[0027] A glass core board includes a first surface and a second surface arranged opposite to each other. The first surface has a first blind groove, and the second surface has a second blind groove. The first blind groove and the second blind groove are arranged in a one-to-one correspondence. The projections of the corresponding first blind groove and the second blind groove on the glass core board overlap along the thickness direction of the glass core board. The thickness range of the glass core board between the corresponding first blind groove and the second blind groove is 50 μm-300 μm. The glass core board has a through hole penetrating the first surface and the second surface, and the through hole is spaced apart from the first blind groove and the second blind groove.

[0028] An active chip is embedded in the first blind slot, and the side of the active chip with the first pad is disposed away from the bottom of the first blind slot.

[0029] A passive device is embedded in the second blind slot, and the side of the passive device having the second pad is disposed away from the bottom of the second blind slot.

[0030] Interconnected conductive pillars, at least filling the through-holes;

[0031] An interconnect structure is located on the first surface and the second surface and is electrically connected to the first pad and the second pad;

[0032] A solder mask layer covers the upper and lower surfaces of the interconnect structure and exposes the surface of the metal interconnect layer in the interconnect structure;

[0033] Conductive bumps are electrically connected to the metal interconnect layer.

[0034] As described above, the present invention provides a method for fabricating a packaging structure by simultaneously forming corresponding first and second blind slots on a glass core plate, forming through holes penetrating the glass core plate and spaced apart from the first and second blind slots. By flame polishing each blind slot, the surface roughness of the bottom of each blind slot is reduced, the maximum bending stress is increased, the structural mechanical reliability of the bottom of each blind slot is improved, and the risk of glass cracking is reduced. By overlapping the projections of the corresponding first and second blind slots on the glass core plate along the thickness direction, the thickness of the glass core plate between the corresponding first and second blind slots is controlled within the range of 50 μm-300 μm. After fabricating interconnect conductive pillars based on the through holes, active chips and passive devices with their respective pads facing the outside of the glass core plate are respectively embedded in the first and second blind slots. The active chips and passive devices are electrically connected based on the fabricated interconnect structure, thereby obtaining a packaging structure. This reduces the planar packaging size, the lateral power supply path between the active chips and passive devices, and reduces the parasitic inductance under high transient current. Attached Figure Description

[0035] Figure 1 The diagram shows a flow chart of the method for preparing the packaging structure of the present invention.

[0036] Figure 2 The diagram shows a cross-sectional view of a glass core plate after the interconnecting conductive pillars have been formed, which is a method for preparing the packaging structure of the present invention.

[0037] Figure 3 The diagram shows a cross-sectional view of the glass core plate after the active chip and passive device are embedded, which is a method for preparing the packaging structure of the present invention.

[0038] Figure 4 The diagram shown is a cross-sectional view of a glass core plate after an interconnect structure has been formed, illustrating the fabrication method of the packaging structure of the present invention.

[0039] Figure 5 The diagram shows a cross-sectional view of the glass core plate after forming another interconnect structure, as shown by the method for preparing the packaging structure of the present invention.

[0040] Figure 6 The diagram shown is a cross-sectional view of the packaging structure formed by the preparation method of the packaging structure of the present invention.

[0041] Explanation of reference numerals: 10-Glass core board; 11-First side; 12-Second side; 13-First blind slot; 14-Second blind slot; 15-Through hole; 20-Interconnect conductive pillar; 30-Active chip; 31-First pad; 32-First adhesive layer; 40-Passive device; 41-Second pad; 42-Second adhesive layer; 50-Interconnect structure; 51-Metal interconnect layer; 52-Dielectric layer; 60-Solder resist layer; 70-Conductive bump. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] Please see Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0044] This invention provides a method for fabricating a packaging structure; please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic flowchart of a method for preparing a packaging structure according to the present invention; wherein the method includes the following steps:

[0045] Step S1: Provide a glass core board 10, which includes a first surface 11 and a second surface 12 disposed opposite to each other.

[0046] Specifically, the planar dimensions, shape, and thickness of the glass core board 10 can be selected according to actual needs; the material of the glass core board 10 includes, but is not limited to, alkali-free glass, aluminosilicate glass, or borosilicate glass.

[0047] In one exemplary embodiment, the coefficient of thermal expansion of the glass core plate 10 is 3 ppm / ℃-8 ppm / ℃; the thickness of the glass core plate 10 is 0.2 mm-1.1 mm, which means that the thickness of the glass core plate 10 is 0.2 mm-1.1 mm before the first blind groove 13 and the second blind groove 14 are made.

[0048] Specifically, the coefficient of thermal expansion of the glass core plate 10 can be selected from 3 ppm / ℃, 5 ppm / ℃, 6 ppm / ℃, 7 ppm / ℃, 8 ppm / ℃, or any value within the range of 3~8 ppm / ℃; the thickness of the glass core plate 10 can be selected from 0.2 mm, 0.3 mm, 0.5 mm, 0.6 mm, 0.8 mm, 0.9 mm, 1.0 mm, 1.1 mm, or any value within the range of 0.2 mm~1.1 mm. The planar dimensions of the glass core plate 10 can be selected according to actual needs; for example, the planar dimensions of the glass core plate 10 are greater than 515 mm × 510 mm. The thickness of the glass core plate 10 refers to the shortest distance between the first surface 11 and the second surface 12.

[0049] Step S2: Simultaneously form a first blind groove 13 located on the first surface 11 and a second blind groove 14 located on the second surface 12, and perform flame polishing on the first blind groove 13 and the second blind groove 14 to form a through hole 15 penetrating the first surface 11 and the second surface 12. The through hole 15 is spaced apart from the first blind groove 13 and the second blind groove 14. The first blind groove 13 and the second blind groove 14 are arranged one-to-one. The projections of the corresponding first blind groove 13 and the second blind groove 14 on the glass core plate 10 overlap along the thickness direction of the glass core plate 10. The thickness range of the glass core plate 10 between the corresponding first blind groove 13 and the second blind groove 14 is 50 μm-300 μm.

[0050] Specifically, through holes 15 are made through the glass core plate 10, and the number of through holes 15 can be selected according to actual needs; simultaneously, first blind grooves 13 and second blind grooves 14 symmetrically formed are made, the number of first blind grooves 13 can be selected according to actual needs, and the number and position of second blind grooves 14 are matched with the first blind grooves 13. It should be noted that this application does not specifically limit the order of making through holes 15 and making blind grooves (first blind grooves 13 and second blind grooves 14), nor does this application specifically limit the order of making through holes 15 and performing flame polishing treatment on each blind groove (first blind groove 13 and second blind groove 14). For example, the first blind grooves 13, second blind grooves 14 and through holes 15 are formed simultaneously, and then the first blind grooves 13 and second blind grooves 14 are flame polished.

[0051] Specifically, the shape of the through hole 15 can be selected according to actual needs; preferably, the opening shape of the through hole 15 is circular. For example... Figure 2 As shown, the cross-section of the through hole 15 is circular. The cross-sectional dimensions at both ends of the through hole 15 are the same and the largest, while the cross-sectional dimension at the middle position of the through hole 15 is the smallest. That is to say, along the direction from the first surface 11 to the second surface 12, the cross-sectional dimension of the through hole 15 first decreases and then gradually increases.

[0052] In one exemplary embodiment, the diameter of the through hole 15 is greater than or equal to 30 μm.

[0053] Specifically, the diameter of the through hole 15 can be selected as 30 μm, 40 μm, or any value greater than 30 μm.

[0054] For example, the slot size of each blind slot (first blind slot 13 and second blind slot 14) can be at least 50 μm larger than the edge of the subsequently embedded active chip 30 or passive device 40. The slot depth of each blind slot is adapted to the thickness of the glass core plate 10 to ensure that it does not penetrate the glass core plate 10. The position of each blind slot avoids the area of ​​the through hole 15 to ensure that they do not interfere with each other.

[0055] Specifically, the glass thickness between the first blind groove 13 and the second blind groove 14 is 50 μm-300 μm, preferably 100 μm-200 μm, to balance mechanical strength, warpage, thermal performance, and electrical performance. The glass thickness between the first blind groove 13 and the second blind groove 14 can be selected as 50 μm, 100 μm, 200 μm, 300 μm, or any value within the range of 50 μm-300 μm. Preferably, the projections of the first blind groove 13 and the second blind groove 14 on the glass core plate 10 along the thickness direction of the glass core plate 10 completely overlap, and no conductive vias are provided in the glass core plate 10 within the projection area, to ensure vertical electrical isolation and structural integrity between the active chip 30 embedded in the first blind groove 13 and the silicon capacitor (the silicon capacitor serves as a passive device 40) embedded in the second blind groove 14. The thickness direction of the glass core plate 10 refers to the direction from the first surface 11 to the second surface 12 (equivalent to the direction from the second surface 12 to the first surface 11).

[0056] In one exemplary embodiment, forming the first blind groove 13 and the second blind groove 14 includes the following steps:

[0057] Laser-induced technology is used to modify a first preset area located on the first surface 11 and a second preset area located on the second surface 12 to form a first modified area and a second modified area.

[0058] The first modified region and the second modified region are removed simultaneously by wet etching to form the first blind trench and the second blind trench.

[0059] Specifically, laser-induced deep etching is used to form the first blind groove 13 and the second blind groove 14. The laser-induced deep etching step includes using laser energy to penetrate a pre-set modification area on the surface of the glass substrate to perform internal modification and obtain the modified area, and then combining it with wet etching to selectively remove the modified area. This allows blind grooves to be formed simultaneously on both sides of the glass in a single processing step, improving processing efficiency.

[0060] Specifically, nanosecond, picosecond, or femtosecond lasers are used to perform laser modification treatment on the glass core plate 10 from the surface inward based on the first and second preset regions, forming the first modified region and the second modified region. Then, the first modified region and the second modified region are removed by selective wet chemical etching with hydrofluoric acid or alkaline solution, so as to simultaneously create the first blind trench 13 and the second blind trench 14 symmetrically arranged at the top and bottom in one operation. Since the first blind trench 13 and the second blind trench 14 are symmetrically arranged with respect to the glass core plate 10, the thermal stress distribution caused by the CTE difference on both sides of the glass core plate 10 is symmetrical (for example, the first modified region and the second modified region have the same shape, planar size, and depth, and the positions of the first modified region and the second modified region are symmetrically arranged, that is, the projections of the first modified region and the second modified region on the glass core plate 10 along the thickness direction of the glass core plate 10 completely overlap), which can effectively offset the bending moment caused by the uneven stress on the front and back sides in the single-sided embedded structure, thereby suppressing warping deformation and improving the subsequent photolithography alignment accuracy and reflow soldering reliability. It should be noted that the first preset area is the preset position of the first blind groove 13 on the first surface 11, and the first modification area is obtained by laser modification of the glass core plate 10 from the surface to the inside based on the first preset area. The depth of the first modification area is the groove depth of the second blind groove 13. The second preset area is the preset position of the second blind groove 14 on the second surface 12, and the second modification area is obtained by laser modification of the glass core plate 10 from the surface to the inside based on the second preset area. The depth of the second modification area is the groove depth of the second blind groove 14.

[0061] In one exemplary embodiment, the method for forming the via 15 includes laser-induced deep etching, plasma etching, laser ablation, focused discharge, or other suitable methods. In this embodiment, laser-induced deep etching is preferred for fabricating the via 15. Glass vias fabricated using laser-induced deep etching exhibit excellent processing quality, high processing accuracy, large aspect ratio, high processing efficiency, and are suitable for mass production.

[0062] Specifically, nanosecond, picosecond, or femtosecond lasers are used to modify the area of ​​the pre-defined via 15 in the glass core board 10, forming a modified region. Then, selective wet chemical etching using hydrofluoric acid or an alkaline solution removes the material from the modified region, forming the via 15. This method enables the fabrication of defect-free vias 15, with sidewall perpendicularity >95% and an aspect ratio adjustable to over 10:1. Subsequent batch wet etching is highly efficient, meeting the requirements of high-density interconnects and suitable for large-scale mass production.

[0063] In one exemplary embodiment, along the thickness direction of the glass core plate 10, the projection of the first blind groove 13 on the glass core plate 10 is located within the projection of the second blind groove 14 on the glass core plate 10; or, along the thickness direction of the glass core plate 10, the projection of the second blind groove 14 on the glass core plate 10 is located within the projection of the first blind groove 13 on the glass core plate 10.

[0064] Preferably, the first blind groove 13 and the second blind groove 14 are exactly the same in size and shape and are symmetrically positioned, that is, the projections of the first blind groove 13 and the second blind groove 14 on the glass core plate 10 completely coincide along the thickness direction of the glass core plate 10.

[0065] Specifically, after the first blind groove 13 and the second blind groove 14 are manufactured, the first blind groove 13 and the second blind groove 14 are flame polished.

[0066] In one exemplary embodiment, the flame temperature range for flame polishing is 1300 °C to 1600 °C.

[0067] Specifically, the flame temperature for flame polishing can be selected from 1300 ℃, 1400 ℃, 1500 ℃, 1600 ℃, or any value within the range of 1300 ℃ to 1600 ℃.

[0068] In one exemplary embodiment, the scanning speed of the flame polishing process ranges from 8 mm / s to 15 mm / s.

[0069] Specifically, the scanning speed for flame polishing can be selected as 8 mm / s, 9 mm / s, 10 mm / s, 11 mm / s, 12 mm / s, 13 mm / s, 14 mm / s, 15 mm / s, or any value within the range of 8 mm / s to 15 mm / s.

[0070] Specifically, an oxyhydrogen flame torch was used, with the flame temperature controlled between 1300 ℃ and 1600 ℃. The bottom of each blind groove was rapidly and locally heated at a scanning speed of 8-15 mm / s, causing instantaneous melting and softening of the micro-layer on the glass surface at the bottom of each blind groove. Under the action of surface tension, the molten glass flowed and recoiled, thereby eliminating sharp protrusions and stress concentration points generated during the etching process. Subsequently, the glass cooled and solidified naturally, forming a smooth and dense surface layer. After flame polishing, the surface roughness of the bottom of each blind groove was significantly improved; simultaneously, because sharp protrusions and stress concentration points were effectively passivated or eliminated, the maximum bending stress of the glass at the bottom of each blind groove was increased. The characterization parameters of the glass core plate 10 before and after flame polishing are shown in Table 1. Flame polishing not only improves the uniformity of the bonding force between the subsequent adhesive layers (first adhesive layer 32 and second adhesive layer 42) and the corresponding groove bottom, but also enhances the structural mechanical reliability of the blind groove bottom, reducing the risk of glass cracking due to stress concentration during subsequent interconnection structure 50 fabrication (such as layering) processes or thermal cycling.

[0071] Table 1. Maximum bending stress and roughness of the bottom of the blind groove of glass core plate 10 before and after flame polishing

[0072]

[0073] A buffer layer (not shown in the figure) is fabricated on the surface of the glass core plate 10 (including the through holes 15 and each blind groove) using chemical vapor deposition. In this embodiment, the buffer layer material is phenelzine, and the types of phenelzine include p-toluene dimer, dichloro-p-toluene dimer, octafluoro-p-toluene dimer, or other modified p-xylenes. The fabrication process of the buffer layer includes: ultrasonic cleaning of the glass core plate 10, plasma surface treatment, and CVD (deposition of buffer layer, chemical vapor deposition) deposition of the buffer layer. The buffer layer is used to enhance the adhesion between the glass core plate 10 and the subsequent metal seed layer and acts as a stress buffer layer to prevent glass crack propagation.

[0074] Perform steps S3 and S4: Form interconnecting conductive pillars 20 that at least fill the via 15 (e.g. Figure 2 (As shown) and active chips 30 and passive devices 40 (such as) are respectively embedded in the first blind slot 13 and the second blind slot 14. Figure 3 As shown, the active chip 30 has one side of its first pad 31 facing away from the bottom of the first blind slot 13, and the passive device 40 has one side of its second pad 32 facing away from the bottom of the second blind slot 14. An interconnect structure 50 electrically connected to the first pad 31 and the second pad 32 is formed on the first surface 11 and the second surface 12. Figure 2 This is a schematic cross-sectional view of a glass core plate 10 after forming interconnecting conductive pillars 20, which is a method for preparing the packaging structure of the present invention. Figure 3 The diagram shows a cross-sectional view of the glass core plate 10 after the active chip 30 and passive device 40 are embedded in the packaging structure of the present invention.

[0075] In one exemplary embodiment, a first adhesive layer 32 is formed on the side of the active chip 30 facing away from the first pad 31, and a second adhesive layer 42 is formed on the side of the passive device 40 facing away from the second pad 41; the active chip 30 with the first adhesive layer 32 is transferred into the first blind slot 13 with the first adhesive layer 32 located between the active chip 30 and the bottom of the first blind slot 13, and the first adhesive layer 32 is cured; the passive device 40 with the second adhesive layer 42 is transferred into the second blind slot 42 with the second adhesive layer 42 located between the passive device 40 and the bottom of the second blind slot 42, and the second adhesive layer 42 is cured.

[0076] In one exemplary embodiment, the passive device 40 is a silicon capacitor.

[0077] This application considers that if the active chip 30 is mounted first and then electroplated to fill the vias, the active chip 30 will be coated with copper during the electroplating process. This can lead to short circuits between the pads and permanent damage to the active chip 30. Furthermore, the electroplating solution may seep into the edge gaps of the active chip 30, corroding the internal circuitry. Therefore, it is necessary to complete the electroplating and pattern fabrication of the interconnect conductive pillars 20 before mounting the active chip 30 and passive devices 40 to completely avoid the electroplating process. For example, the steps for fabricating the interconnect conductive pillars 20 include: sequentially depositing a seed layer, electroplating, copper thinning, dry film lamination, exposure, development, etching, film removal, flash etching, and Ti etching. Methods for fabricating the seed layer include, but are not limited to, chemical plating, atomic layer deposition, physical vapor deposition, or other suitable methods. In this embodiment, a Ti / Cu seed layer is sputtered using physical vapor deposition to form a Ti / Cu seed layer on the inner wall of the via 15 and the upper and lower surfaces of the glass core plate 10. The titanium layer thickness is >50 nm, the copper layer thickness is greater than the titanium layer thickness, and the process deviation of each layer thickness is <5%. After the conductive material is filled into the through-holes 15 and covered on the surface of the glass core board 10 by electroplating, the thickness of the conductive layer on the surface of the glass core board 10 is reduced to less than 15 μm and the surface flatness is less than 1 μm by chemical mechanical polishing or chemical etching. The conductive material (interconnecting conductive pillars 20) used to fill the through-holes 15 can be copper, nickel, tin, or other suitable alloy materials. Copper is preferred in this embodiment because of its excellent conductivity, good matching coefficient of thermal expansion with the glass core board, and the mature and relatively low cost of the electroplating filling process. After the dry film is applied, exposure can be performed using a g-line (a specific ultraviolet spectral line emitted by a high-pressure mercury lamp with a wavelength of 436 nm) or i-line (a specific ultraviolet spectral line generated by a high-pressure mercury lamp with a wavelength of 365 nm) ultraviolet light source. Development is then performed using alkaline solutions such as sodium hydroxide, sodium carbonate, or potassium carbonate. Etching is performed using one or more of NaOH, NaHCO3, Na2CO3, HCl, H3PO4, and H2O2. After film removal, flash etching and Ti etching are performed, ultimately forming a glass core board 10 with conductive vias 15, double-sided symmetrical blind trenches, and interconnecting conductive pillars 20. The interconnecting conductive pillars 20 not only fill each via 15 on the glass core board 10 but also interconnect the conductive pillars within each via 15.

[0078] An active chip 30 and a silicon capacitor (the silicon capacitor serves as a passive device 40) are provided. A first adhesive layer 32 is pre-attached to the back side of the active chip 30 (the side of the active chip 30 facing away from the first pad 31), and a second adhesive layer 42 is pre-attached to the back side of the silicon capacitor (the side of the silicon capacitor facing away from the second pad 41). The material of each adhesive layer (first adhesive layer 32 and second adhesive layer 42) is preferably DAF (Die Attach Film), which allows for precise thickness control. The active chip 30 (with the first adhesive layer 32 attached) is placed in the first blind slot 13 with its back side facing the bottom of the first blind slot 13. The first adhesive layer 32 is cured using a heating and pressurizing process, fixing the active chip 30 to the bottom of the first blind slot 13 without gaps. The glass core plate 10 is then flipped over, and the silicon capacitor is fixed to the bottom of the second blind slot 14 using the same process. The back side of the silicon capacitor is fixed to the bottom surface of the second blind slot 14 via the second adhesive layer 42. The front side of the silicon capacitor has its second pad 41 facing away from the bottom of the second blind slot 14, i.e., towards the outside of the glass core plate 10. This embodiment uses a single active chip 30 corresponding to two silicon capacitors as an example. Based on the symmetrical structural design of this invention, it should be noted that the first blind slot 13 can accommodate multiple active chips 30 or active devices, and the second blind slot 14 can accommodate multiple silicon capacitors, thereby achieving distributed decoupling of multiple power supplies. This embodiment adopts a symmetrical embedding method of chips and silicon capacitors, combined with the high Young's modulus and adjustable CTE characteristics of the glass core plate 10, further balancing the structural rigidity of the upper and lower structures. Compared with existing single-sided embedded or surface-mount silicon capacitors, this structure reduces the XY plane size of the package. Since the back side of the silicon capacitor is directly bonded to the bottom of the blind slot of the glass core plate 10 via a DAF film, the high thermal conductivity of the glass provides a low thermal resistance heat dissipation path in the vertical direction for the silicon capacitor, effectively reducing the junction temperature of the silicon capacitor under high-frequency charging and discharging, and improving system reliability. More importantly, the DAF film is attached to the back of the active chip 30 and the back of the silicon capacitor. The excess adhesive will only flow at the bottom of each blind slot and will never bypass the chip body to contaminate the first pad 31 on the front of the active chip 30 and the second pad 41 of the silicon capacitor, making the active chip 30 and the silicon capacitor themselves act as physical barriers.

[0079] Specifically, one or more active chips 30 can be embedded in the first blind slot 13, and one or more passive devices 40 can be embedded in the second blind slot 14. For example, a silicon capacitor is used as the passive device 40.

[0080] For example, after the active chip 30 and the silicon capacitor are respectively embedded on both sides of the glass core plate 10, an interconnect structure 50 covering the first side 11 and the second side 12 is formed (e.g., Figure 4 As shown, Figure 4The diagram shown is a cross-sectional view of the glass core plate 10 after the interconnect structure 50 is formed, as shown in the method for preparing the packaging structure of the present invention. Exemplarily, an additional layer is used as the interconnect structure 50, preferably at least two additional layers as the interconnect structure 50. Figure 5The diagram shows a cross-sectional view of the glass core board 10 after forming another interconnect structure 50, as shown in the preparation method of the packaging structure of the present invention. The added layer includes a dielectric layer 52 and a metal interconnect layer 51. The metal interconnect layer 51 is electrically connected to the first pad and the second pad. It should be noted that the metal interconnect layer 51 is electrically connected to the interconnect conductive pillars to ensure the electrical connection between the active chip 30 and the passive device 40. A dielectric layer 52 is formed by spin coating, slot coating or vacuum lamination. Preferably, a photosensitive dielectric layer 52 is used as the dielectric layer 52. The material of the photosensitive dielectric layer 52 can be photosensitive polyimide, photosensitive styrene, photosensitive epoxy resin-based acrylate dry film or liquid dielectric material. The thickness of the dielectric layer 52 ranges from 5 μm to 20 μm, preferably from 8 μm to 15 μm, to balance dielectric properties, flatness and photolithographic resolution. Subsequently, blind vias are formed directly in the photosensitive insulating dielectric layer 52 using photolithography (including exposure, development, and post-curing). These blind vias expose interconnecting conductive pillars 20, a first pad 31, and a second pad 41. The diameter of the blind vias is 5 μm to 30 μm, and more preferably 8 μm to 20 μm. The sidewall angle of the blind vias is 70° to 90° to facilitate uniformity of subsequent seed layer coverage and electroplating filling. A seed layer is deposited on the surface of the photosensitive insulating dielectric layer 52 and the inner wall of the blind vias using electroless electroless copper plating, physical vapor deposition, or other combinations thereof. The total thickness of the seed layer is 0.2 μm to 1.5 μm, wherein the thickness of the adhesion layer or barrier layer ranges from 20 nm to 100 nm, and the thickness of the copper seed layer is preferably 100 nm to 1000 nm. This seed layer provides a conductive basis for subsequent electroplating and ensures good adhesion to the glass core board 10 and the dielectric layer 52. On the seed layer, a layer of photoresist, preferably a photosensitive dry film resist, is laminated using vacuum lamination or roll forming. The thickness of the photoresist ranges from 5 μm to 15 μm, with a preferred thickness of 7 μm to 12 μm to support high-resolution patterns. Subsequently, selective exposure and development are performed using high-resolution direct imaging lithography or projection lithography to form the desired circuit pattern windows. Next, copper or copper alloy is filled into the pattern windows and blind vias using electroplating to form a metal interconnect layer 51. The linewidth / spacing of the metal interconnect layer 51 is ≤5 / 5 μm, and the electroplating thickness is 3 μm to 10 μm to meet resistance and current carrying requirements. This metal interconnect layer 51 is electrically connected to the interconnect conductive pillars 20, the first pad 31, and the second pad 41. Flash etching is then performed sequentially to complete the fabrication of the first layer. Multiple layers can be fabricated as needed. In the formed metal interconnect layer 51, the first pad 31 and the second pad 41 are electrically connected through the TGV (via 15) in the non-blind slot region and the double-sided add-in layer (RDL).Since the silicon capacitor is embedded in the second blind slot 14 opposite to the active chip 30, the power supply path is shortened compared to the surface mount solution, and the parasitic inductance is reduced accordingly, which improves the decoupling effect and power integrity under high transient current.

[0081] Perform step S5: Form a solder resist layer 60 that covers the side of the interconnect structure 50 facing away from the glass core plate 10 and exposes the surface of the metal interconnect layer 51 in the interconnect structure 50.

[0082] For example, the solder resist layer 60 can be fabricated through a process of film application, exposure, development and post-curing, and grooves can be made at preset positions to expose the metal interconnect layer 51.

[0083] Step S6: Form conductive bumps 70 electrically connected to the metal interconnect layer 51 to obtain a package structure, such as... Figure 6 As shown, Figure 6 The diagram shows a cross-sectional view of the glass core plate 10 after the solder resist layer 60 and conductive bumps 70 are formed, which is a method for preparing the packaging structure of the present invention.

[0084] Specifically, the methods for fabricating the conductive bumps 70 include, but are not limited to, reflow soldering and ball bonding.

[0085] The present invention also provides a packaging structure, which includes a glass core plate 10, an active chip 30, a passive device 40, interconnect conductive pillars 20, and an interconnect structure 50. The glass core plate 10 includes a first surface 11 and a second surface 12 disposed opposite to each other. A first blind groove 13 is provided on the first surface 11, and a second blind groove 14 is provided on the second surface 12. The first blind groove 13 and the second blind groove 14 are disposed in a one-to-one correspondence. The projections of the corresponding first blind groove 13 and the second blind groove 14 onto the glass core plate 10 overlap along the thickness direction of the glass core plate 10. The thickness of the glass core plate 10 between the corresponding first blind groove 13 and the second blind groove 14 ranges from 50 μm to 300 μm. μm, the glass core board 10 has through holes 15 penetrating the first surface 11 and the second surface 12, and the through holes 15 are spaced apart from the first blind slot 13 and the second blind slot 14; the active chip 30 is embedded in the first blind slot 13, and the side of the active chip 30 with the first pad is facing away from the bottom of the first blind slot 13; the passive device 40 is embedded in the second blind slot 14, and the side of the passive device 40 with the second pad is facing away from the bottom of the second blind slot 14; the interconnect conductive pillars 20 at least fill the through holes 15; the interconnect structure 50 is located on the first surface 11 and the second surface 12 and is electrically connected to the first pad and the second pad; the solder mask layer 60 covers the upper and lower surfaces of the interconnect structure 50 and exposes the surface of the metal interconnect layer 51 in the interconnect structure 50; the conductive bump 70 is electrically connected to the metal interconnect layer 51.

[0086] Specifically, the packaging structure provided by the present invention can be obtained by any of the above-mentioned packaging structure preparation methods, or by other methods.

[0087] Specifically, the interconnecting conductive posts 20 are made of materials including copper, gold, silver, aluminum, tantalum, nickel, titanium, tungsten, or other conductive materials. For example, copper is used as the material for the interconnecting conductive posts 20. It should be emphasized that the interconnecting conductive posts 20 in each through hole 15 are electrically connected to each other.

[0088] Specifically, the upper and lower surfaces of the interconnect structure 50 refer to the upper surface and the lower surface of the interconnect structure 50, and the upper and lower surfaces of the interconnect structure 50 are parallel to the first surface.

[0089] Specifically, the material and thickness of the solder resist layer 60 can be selected according to actual needs. The solder resist layer 60 exposes part of the surface of the metal interconnect layer 51. The material of the solder resist layer 60 includes photosensitive solder resist ink, dry film solder resist, or other suitable dielectric materials.

[0090] Specifically, the number, size, shape, and material of the conductive bumps 70 can be selected according to actual needs. The conductive bumps 70 include tin, copper, aluminum, silver, gold, nickel, titanium, indium, or other conductive materials. For example, tin balls are used as conductive bumps 70.

[0091] Specifically, the present invention provides a method for preparing an encapsulation structure and an encapsulation structure. This involves simultaneously forming corresponding first blind trenches 13 and second blind trenches 14 on a glass core plate 10, and forming through-holes 15 penetrating the glass core plate 10. The projections of the corresponding first blind trenches 13 and second blind trenches 14 onto the glass core plate 10 overlap along the thickness direction of the glass core plate 10. The thickness of the glass core plate 10 between the corresponding first blind trenches 13 and second blind trenches 14 is controlled within the range of 50 μm-300 μm. After fabricating conductive pillars 20 based on the through-holes 15, active chips 30 and passive devices 40 are respectively embedded in the first blind trenches 13 and second blind trenches 14. The active chip 30 has its first pad 31 facing away from the bottom of the first blind trench 13, and the passive device 40 has its second pad 41 facing away from the bottom of the second blind trench 14. The through-holes 15 penetrating the glass core plate 10 are spaced apart from the first blind trenches 13 and second blind trenches 14. The encapsulation structure 50, subsequently fabricated, connects the two blind trenches. The active chip 30 and the passive device 40 are electrically connected to form a package structure. The first pad 31 and the second pad 41 face the outside of the glass core plate 10, and the metal interconnection is directly achieved through layer build-up (RDL) (electroplated or physical vapor deposition). No additional solder balls or bumps are needed to achieve electrical connection, reducing the planar package size and shortening the lateral power supply path between the active chip 30 and the passive device 40. The thickness of the glass core plate 10 between the correspondingly set first blind slot 13 and second blind slot 14 is preferably 100 μm-200 μm, which provides sufficient structural rigidity. This allows the anti-warping effect of the double-sided symmetrical blind slot design to be fully utilized, effectively ensuring the flatness of the package structure in high-temperature processes to avoid warping. In addition, the silicon capacitor generates heat when it is working. The back of the silicon capacitor is directly attached to the bottom of the second blind slot 14 through DAF. The glass core plate 10 between the silicon capacitor and the active chip 30 forms an important vertical heat dissipation channel. With fixed materials and area, the smaller the thickness of the glass core plate 10, the lower the thermal resistance and the better the vertical heat dissipation effect. The corresponding first blind slot 13 and second blind slot 14 are controlled within 100 μm-200 μm, which can form an effective vertical heat dissipation channel to quickly conduct the heat of the silicon capacitor to the other side or dissipate it through the silicon via 15 or the metal layer, while also taking into account mechanical strength. This is the key to ensuring the low junction temperature and long-term reliability of the silicon capacitor. If the glass core plate 10 is too thin, the parasitic capacitance formed by the active chip 30 and the silicon capacitor in the vertical direction (perpendicular to the first surface 11, i.e., the thickness direction of the glass core plate 10) will increase significantly. According to the capacitance formula C = εA / d, where C represents capacitance, ε is dielectric constant, A is the effective area of ​​the two parallel plates (in this application, it refers to the active chip 30 and the silicon capacitor) overlapping each other, and d represents the vertical distance between the two plates. The smaller d is, the larger the parasitic capacitance is, which can easily generate high-frequency noise coupling and signal or power supply crosstalk, interfering with the normal decoupling function of the silicon capacitor.Therefore, the thickness of the glass core plate 10 between the first blind slot 13 and the second blind slot 14, which is 100-200 μm, i.e. the distance between the silicon capacitor and the active chip 30, can achieve a good balance between effectively suppressing parasitic capacitance, ensuring good high-frequency noise isolation and mechanical strength, avoiding significant near-field electromagnetic interference between the active chip and the silicon capacitor, ensuring power supply integrity, and reducing parasitic inductance under high transient current.

[0092] This invention employs a double-sided symmetrical blind slot design, embedding the active chip 30 and the silicon capacitor on opposite sides to achieve structural symmetry in the thickness direction of the package. In high-temperature processes, the double-sided symmetrical layout cancels out thermal stress, effectively suppressing the inherent warpage of a single-sided embedded structure and improving package flatness and subsequent photolithography alignment accuracy. Simultaneously, the silicon capacitor is vertically aligned and embedded beneath the chip. Current flows from the electrodes of the active chip 30 through short-distance lateral wiring into the via 15, then vertically through the glass core 10 to the electrodes of the silicon capacitor. This shortens the power supply path from several millimeters in traditional solutions to sub-millimeter levels, significantly reducing parasitic inductance and improving high-frequency decoupling and power integrity. Furthermore, the back of the silicon capacitor is directly bonded to the bottom of the second blind slot 14 via a DAF film, utilizing the thermal conductivity of glass to construct a vertical heat dissipation channel, effectively reducing the junction temperature of the silicon capacitor during high-frequency charging and discharging, and improving long-term reliability. Furthermore, this application introduces flame polishing after laser-induced deep etching, which can reduce the surface roughness of the bottom of each blind groove and increase the maximum bending stress. The flame polishing process enhances the structural mechanical reliability of the bottom of each blind groove and reduces the risk of glass cracking.

[0093] This invention utilizes a glass core board 10 combined with standard blind groove embedding and double-sided layering processes. The double-sided blind grooves can be formed simultaneously in one go using laser-induced etching, resulting in high processing efficiency. Compared to traditional TSV adapter board solutions, it avoids the complex processes of high aspect ratio TSV filling and temporary bonding carriers, simplifying the manufacturing process and reducing material and process costs. Simultaneously, it offers good process compatibility for large-size panels, reducing the unit cost during mass production.

[0094] The manufacturing method of this invention is highly compatible with existing glass substrate processing technology. It can directly use mature blind trench etching, active chip 30 and silicon capacitor mounting DAF, double-sided layering, solder resist and balling processes without the need for additional special equipment. The low warpage characteristics brought by the symmetrical structure also reduce the risk of subsequent photolithography alignment and reflow soldering processes, which is convenient for the transformation of existing production lines and large-scale mass production.

[0095] In summary, the encapsulation structure and its preparation method of the present invention improve the manufacturing process of the encapsulation structure by simultaneously forming corresponding first and second blind grooves on the glass core plate, forming through holes penetrating the glass core plate. These through holes are spaced apart from the first and second blind grooves. Flame polishing of each blind groove reduces the surface roughness at the bottom of each blind groove, increases the maximum bending stress, enhances the structural mechanical reliability of the bottom of each blind groove, and reduces the risk of glass cracking. Furthermore, the projections of the corresponding first and second blind grooves onto the glass core plate overlap along the thickness direction, and the thickness of the glass core plate between the corresponding first and second blind grooves is controlled between 50 μm and 300 μm. Within the μm range, after interconnecting the conductive pillars based on the via, active chips and passive devices are respectively embedded in the first and second blind slots. The side of the active chip with the first pad is set away from the bottom of the first blind slot, and the side of the passive device with the second pad is set away from the bottom of the second blind slot. Then, the active chip and passive device are electrically connected by the interconnect structure subsequently fabricated, thereby obtaining the package structure, reducing the planar package size, the lateral power supply path between the active chip and the passive device, and reducing the parasitic inductance under high transient current.

[0096] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging structure, characterized in that, Includes the following steps: A glass core board is provided, the glass core board including a first surface and a second surface disposed opposite to each other; A first blind groove located on the first surface and a second blind groove located on the second surface are simultaneously formed, and the first blind groove and the second blind groove are flame polished to form a through hole penetrating the first surface and the second surface. The through hole is spaced apart from the first blind groove and the second blind groove. The first blind groove and the second blind groove are arranged one-to-one. The projections of the corresponding first blind groove and the second blind groove on the glass core plate overlap along the thickness direction of the glass core plate. The thickness range of the glass core plate between the corresponding first blind groove and the second blind groove is 50μm-300μm. Interconnect conductive pillars are formed to at least fill the through holes, and active chips and passive devices are respectively embedded in the first blind trench and the second blind trench. The active chip has a side with a first pad facing away from the bottom of the first blind trench, and the passive device has a side with a second pad facing away from the bottom of the second blind trench. An interconnect structure electrically connected to the first pad and the second pad is formed on the first surface and the second surface; A solder resist layer is formed that covers the side of the interconnect structure facing away from the glass core and exposes the surface of the metal interconnect layer in the interconnect structure; Conductive bumps are formed that are electrically connected to the metal interconnect layer to obtain the package structure.

2. The method for preparing the packaging structure according to claim 1, characterized in that: The coefficient of thermal expansion of the glass core is 3 ppm / ℃-8 ppm / ℃; the thickness of the glass core is 0.2 mm-1.1 mm.

3. The method for preparing the packaging structure according to claim 1, characterized in that: The diameter of the through hole is greater than or equal to 30 μm.

4. The method for preparing the packaging structure according to claim 1, characterized in that, The formation of the first blind slot and the second blind slot includes the following steps: Laser-induced technology is used to perform laser modification treatment on a first preset area on a first surface and a second preset area on a second surface to form a first modified area and a second modified area. The first modified region and the second modified region are removed simultaneously by wet etching to form the first blind trench and the second blind trench.

5. The method for preparing the packaging structure according to claim 1, characterized in that: The flame temperature range for the flame polishing process is 1300 ℃-1600 ℃.

6. The method for preparing the packaging structure according to claim 1, characterized in that: The scanning speed range for the flame polishing process is 8 mm / s - 15 mm / s.

7. The method for preparing the packaging structure according to claim 1, characterized in that: Along the thickness direction of the glass core plate, the projection of the first blind groove on the glass core plate is located within the projection of the second blind groove on the glass core plate; or, along the thickness direction of the glass core plate, the projection of the second blind groove on the glass core plate is located within the projection of the first blind groove on the glass core plate.

8. The method for preparing the packaging structure according to claim 1, characterized in that: Embedding the active chip and the passive device includes the following steps: A first adhesive layer is formed on the side of the active chip facing away from the first pad, and a second adhesive layer is formed on the side of the passive device facing away from the second pad. The active chip with the first adhesive layer is transferred into the first blind slot, with the first adhesive layer located between the active chip and the bottom of the first blind slot, and the first adhesive layer is cured. The passive device having the second adhesive layer is transferred into the second blind groove, with the second adhesive layer located between the passive device and the bottom of the second blind groove, and the second adhesive layer is cured.

9. The method for preparing the packaging structure according to claim 1, characterized in that: The passive device is a silicon capacitor.

10. A packaging structure, characterized in that, The packaging structure includes: A glass core board includes a first surface and a second surface arranged opposite to each other. The first surface has a first blind groove, and the second surface has a second blind groove. The first blind groove and the second blind groove are arranged in a one-to-one correspondence. The projections of the corresponding first blind groove and the second blind groove on the glass core board overlap along the thickness direction of the glass core board. The thickness range of the glass core board between the corresponding first blind groove and the second blind groove is 50 μm-300 μm. The glass core board has a through hole penetrating the first surface and the second surface, and the through hole is spaced apart from the first blind groove and the second blind groove. An active chip is embedded in the first blind slot, and the side of the active chip with the first pad is disposed away from the bottom of the first blind slot. A passive device is embedded in the second blind slot, and the side of the passive device having the second pad is disposed away from the bottom of the second blind slot. Interconnected conductive pillars, at least filling the through-holes; An interconnect structure is located on the first surface and the second surface and is electrically connected to the first pad and the second pad; A solder mask layer covers the upper and lower surfaces of the interconnect structure and exposes the surface of the metal interconnect layer in the interconnect structure; Conductive bumps are electrically connected to the metal interconnect layer.

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