A glass-based power distribution network interposer structure embedding silicon-based decoupling beads

Abstract

The embodiment of the application relates to a glass-based power distribution network interlayer structure embedded with silicon-based decoupling particles, comprising: a glass panel base body having oppositely arranged first and second surfaces and provided with a through window penetrating through the first and second surfaces and a plurality of conductive glass through holes; a first redistribution layer is arranged on the first surface, the first redistribution layer comprising a first power supply line and a first ground line; a second redistribution layer is arranged on the second surface, and two ends of each conductive glass through hole are electrically connected with the first and second redistribution layers respectively; a passive silicon-based decoupling particle is embedded in the through window and comprises a silicon substrate and a decoupling capacitor structure, the decoupling capacitor structure comprising a deep trench capacitor array; the passive silicon-based decoupling particle has a connecting end surface facing the first redistribution layer, and the connecting end surface is provided with a power supply connecting terminal and a ground connecting terminal electrically connected with the first power supply line and the first ground line respectively.

Description

Technical Field

[0001] This application relates to the field of advanced semiconductor packaging technology, and in particular to a glass-based power distribution network interposer structure with embedded silicon-based decoupling cores. Background Technology

[0002] With the development of applications such as artificial intelligence computing, high-performance computing, and high-speed storage, the power consumption level and transient load variation in chip packaging are constantly increasing. For high-power chips, the package-level power distribution network needs to transmit external power to different functional areas of the chip and maintain stable power supply voltage when the load current changes rapidly. If the parasitic resistance and inductance of the power supply path are large, or if the connection path between the decoupling structure and the load power node is long, transient voltage drops and power supply ripples are likely to occur when the load changes, affecting the stable operation of the internal computing units, storage units, and interface units of the chip.

[0003] In advanced packaging structures, interposers are typically used to achieve high-density interconnects between the chip and the packaging substrate. Existing interposer materials mainly include silicon, organic materials, and glass. Silicon interposers offer high wiring accuracy and can be used to form decoupling structures such as deep trench capacitors using silicon-based processes. However, silicon interposers are costly and are easily limited by wafer size, warpage, and processing yield in large-size packages. Organic packaging substrates are easy to fabricate over large areas, but their dielectric loss, dimensional stability, and wiring accuracy are insufficient to meet the demands of high-power, high-density packaging. Glass interposers offer advantages such as low dielectric loss, good insulation, high dimensional stability, and suitability for large-size panel-level fabrication, thus gradually becoming an important development direction for advanced packaging interposers.

[0004] However, glass itself is not suitable for directly forming silicon-based deep trench capacitor structures. For the power distribution network of high-power chips, decoupling structures with high capacitance density and low connection parasitic parameters are usually required close to the load power nodes in the mid-frequency range. If decoupling is achieved solely through redistribution layers on the upper and lower surfaces of the glass interposer, package substrate capacitors, or externally mounted capacitors, the decoupling current needs to pass through long lateral wiring, solder joints, vias, or package substrate interconnect structures. The equivalent series inductance in the connection path is large, making it difficult to respond promptly to rapid changes in chip load.

[0005] Therefore, the existing glass-based power distribution network interlayer has the following technical problems: it is difficult to natively integrate a high capacitance density silicon-based deep trench decoupling structure into the glass substrate, resulting in a long connection path and large parasitic parameters between the decoupling structure and the power lines and ground lines on the surface of the glass-based interlayer, which in turn makes the decoupling capability of the glass-based power distribution network insufficient under medium frequency transient load conditions. Summary of the Invention

[0006] One objective of this application is to provide a glass-based power distribution network interposer structure with embedded silicon-based decoupling cores, at least to solve the aforementioned problems.

[0007] To achieve the above objectives, some embodiments of this application provide a glass-based power distribution network interposer structure with embedded silicon-based decoupling chips, comprising:

[0008] A glass panel substrate has a first surface and a second surface disposed opposite to each other. The glass panel substrate is provided with a through window that penetrates the first surface and the second surface and a plurality of conductive glass through holes.

[0009] A first wiring layer is disposed on the first surface, and the first wiring layer includes a first power line and a first ground line.

[0010] A second wiring layer is disposed on the second surface, and the two ends of each of the conductive glass through holes are electrically connected to the first wiring layer and the second wiring layer, respectively.

[0011] A passive silicon-based decoupling chip is embedded in the through window. The passive silicon-based decoupling chip includes a silicon substrate and a decoupling capacitor structure integrated on the silicon substrate. The decoupling capacitor structure includes a deep trench capacitor array.

[0012] The passive silicon-based decoupling chip has a connection end face facing the first redistribution layer. The connection end face is provided with a power connection terminal and a ground connection terminal that are electrically connected to the decoupling capacitor structure, respectively. The power connection terminal is electrically connected to the first power line, and the ground connection terminal is electrically connected to the first ground line.

[0013] Optionally, the decoupling capacitor structure further includes a metal-insulator-metal film capacitor array, which together with the deep trench capacitor array constitutes a composite decoupling capacitor structure and is electrically connected between the power supply connection terminal and the ground connection terminal, respectively.

[0014] Optionally, the silicon substrate is an N-type high-resistivity single-crystal silicon substrate, and the resistivity of the N-type high-resistivity single-crystal silicon substrate is not less than 1000 Ω·cm.

[0015] Optionally, the capacitance density of the deep trench capacitor array is not less than 340 nF / mm².

[0016] Optionally, the connection end face is provided with a core rewiring layer and a plurality of vertical interconnect copper pillars electrically connected to the core rewiring layer, and the power connection terminal and the ground connection terminal respectively include the corresponding vertical interconnect copper pillars.

[0017] Optionally, the passive silicon-based decoupling die also has a second end face facing away from the connection end face, and the second end face is not provided with connection terminals for external electrical connection.

[0018] Optionally, the thickness of the silicon substrate is less than the thickness of the glass panel substrate, the second end face of the passive silicon decoupling core facing away from the connection end face is flush with the second surface, and the end of the vertical interconnect copper pillar away from the silicon substrate is flush with the first surface.

[0019] Optionally, a sidewall gap is formed between the outer wall of the passive silicon-based decoupling core and the inner wall of the through window, and the sidewall gap is filled with a flexible adhesive material.

[0020] Optionally, the sidewall gap is no greater than 8 μm, and the flexible adhesive material is an organic flexible adhesive.

[0021] Optionally, the second redistribution layer includes a second power line and a second ground line, and the plurality of conductive glass vias include power conductive glass vias and ground conductive glass vias;

[0022] The two ends of the power conductive glass through hole are electrically connected to the first power line and the second power line, respectively, and the two ends of the ground conductive glass through hole are electrically connected to the first ground line and the second ground line, respectively.

[0023] Optionally, there are multiple through windows, at least two of which are respectively embedded with the passive silicon-based decoupling cores, and the multiple passive silicon-based decoupling cores are distributed at intervals along the planar direction of the glass panel substrate.

[0024] Optionally, the glass panel substrate has a storage power area corresponding to the storage cell of the chip to be connected and an interface power area corresponding to the interface cell of the chip to be connected in the planar direction, and at least a portion of the plurality of passive silicon-based decoupling chips are disposed in the storage power area and / or the interface power area.

[0025] Optionally, the glass panel substrate is further provided with an active chip through window that penetrates the first surface and the second surface. An active silicon-based power chip is embedded in the active chip through window, and the active silicon-based power chip is electrically connected to the first redistribution layer and the second redistribution layer, respectively.

[0026] Optionally, the active silicon-based power chip includes a doped silicon substrate, an integrated voltage regulation unit, a through-silicon via array penetrating the doped silicon substrate, and a power redistribution layer electrically connected to the through-silicon via array.

[0027] Optionally, the glass panel substrate has a main computing power area corresponding to the main computing unit of the chip to be connected, a storage power area corresponding to the storage unit of the chip to be connected, and an interface power area corresponding to the interface unit of the chip to be connected in the planar direction.

[0028] The active silicon-based power chip is disposed in the main computing power region, and the passive silicon-based decoupling chip is disposed in the storage power region and / or the interface power region.

[0029] Optionally, the connection end face of the passive silicon-based decoupling chip has at least two power routing areas corresponding to different sub-power domains, and a grounding shield redistribution layer is provided between adjacent power routing areas.

[0030] Optionally, the passive silicon-based decoupling core is provided with a plurality of grounding silicon vias, which are spaced apart along the grounding shield redistribution layer and electrically connected to the grounding shield redistribution layer.

[0031] Optionally, the thickness of the glass panel substrate is 50μm-300μm, and the linear thermal expansion coefficient of the glass panel substrate is 2.8ppm / ℃-3.2ppm / ℃.

[0032] Compared with related technologies, the solution provided in this application integrates a deep trench capacitor array, which is originally difficult to form directly in glass material, into the thickness range of the glass substrate by setting a through window that penetrates the first and second surfaces within the glass panel substrate and embedding passive silicon-based decoupling cores within the through window. In this way, the glass panel substrate no longer serves merely as a carrier for power and ground lines, but can achieve the high capacitance density characteristics of silicon-based deep trench capacitors by utilizing the embedded silicon-based decoupling cores, thereby compensating for the insufficient intermediate frequency decoupling capability of the glass-based power distribution network's intermediate layer.

[0033] Furthermore, the connection end face of the passive silicon-based decoupling chip is configured to face the first rewiring layer, and the power connection terminal is electrically connected to the first power line, and the ground connection terminal is electrically connected to the first ground line. Thus, the decoupling capacitor structure can be directly connected between the power line and ground line of the first rewiring layer. The decoupling current does not need to pass through the packaging substrate, external capacitor solder joints, or long lateral wiring before returning to the node to be decoupled, which can shorten the power decoupling loop and reduce parasitic inductance and parasitic resistance in the decoupling path.

[0034] Meanwhile, multiple conductive glass vias are formed within the glass panel substrate. The two ends of each via are electrically connected to the first and second wiring layers, respectively, allowing the power supply lines on the first and second surfaces to be connected along the thickness of the glass panel substrate. This structure enables external power supply to be transmitted to the first wiring layer via the second wiring layer and the conductive glass vias. The passive silicon-based decoupling chip is directly connected to the power and ground lines of the first wiring layer. Therefore, the vertical power supply path and the local decoupling path can be formed collaboratively within the glass substrate, reducing transient voltage drops caused by excessively long power supply paths during sudden load changes in high-power chips.

[0035] Therefore, while retaining the advantages of low loss, insulation and suitability for large-size interposer fabrication of glass panel substrate, a silicon-based deep trench capacitor array is connected to the glass-based power supply distribution network at close range by through embedded passive silicon-based decoupling cores. This enables the glass-based interposer to obtain mid-frequency decoupling capability with a shorter connection path and improves the transient voltage stability between power lines and ground lines under high dynamic load conditions. Attached Figure Description

[0036] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0037] Figure 1 This is a schematic diagram of the overall cross-sectional structure of the glass-based power distribution network interposer layer with embedded silicon-based decoupling chips provided in an embodiment of this disclosure;

[0038] Figure 2 This is a cross-sectional schematic diagram of an active silicon-based power chip provided in an embodiment of this disclosure;

[0039] Figure 3 This is a schematic cross-sectional view of the passive silicon-based decoupling chip provided in the embodiments of this disclosure;

[0040] Figure 4 This is a schematic diagram of the planar opening layout of the glass panel substrate provided in an embodiment of this disclosure;

[0041] Figure 5 This is a schematic diagram of the planar layout of the glass panel substrate after embedding silicon-based core particles according to an embodiment of this disclosure;

[0042] Figure 6 This is a structural schematic diagram of the functional partition plan of the AI ​​computing chip provided in the embodiments of this disclosure.

[0043] Figure label:

[0044] 1: Glass panel substrate; 13: Through window; 15: Conductive glass through hole; 2: First wiring layer; 3: Second wiring layer; 4: Passive silicon decoupling chip; 5: Active silicon power chip; 61: Main computing unit; 62: Storage unit; 63: Interface unit. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0047] In this disclosure, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for better description of the embodiments of this disclosure and their implementations, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to require them to be constructed and operated in a specific orientation. Furthermore, some of the aforementioned terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may in some cases indicate a dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in the embodiments of this disclosure according to the specific circumstances.

[0048] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0049] Unless otherwise stated, the term "multiple" means two or more.

[0050] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0051] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0052] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0053] The first and second surfaces are only used to distinguish the two opposing surfaces of the glass panel substrate and do not imply that the interposer layer must have a specific up-down orientation in use. In one packaging configuration, the first surface can be the side facing the chip or chip assembly to be connected, and the second surface can be the side facing the packaging substrate; in other packaging configurations, the orientations of the two can be interchanged.

[0054] Combination Figures 1 to 6 As shown in the figure, this disclosure provides a glass-based power distribution network interposer structure with embedded silicon-based decoupling cores. The glass-based power distribution network interposer structure of this embodiment includes a glass panel substrate 1, a first redistribution layer 2, a second redistribution layer 3, and at least one passive silicon-based decoupling core 4. The glass panel substrate 1 is a single-layer integrated glass substrate with a first surface and a second surface disposed opposite to each other. The glass panel substrate 1 has a through window 13 penetrating the first surface and the second surface, and a plurality of conductive glass vias 15. The through window 13 is used to accommodate the passive silicon-based decoupling core 4, ensuring that the passive silicon-based decoupling core 4 is within the thickness range of the glass panel substrate 1; the conductive glass vias 15 are used to establish a vertical conductive connection between the first surface and the second surface.

[0055] In this embodiment, the through-window 13 can be a rectangular window, a square window, or other through-opening adapted to the outer contour of the passive silicon-based decoupling core 4. The planar dimensions of the through-window 13 are slightly larger than the planar dimensions of the corresponding passive silicon-based decoupling core 4, thereby reserving an assembly gap between the outer sidewall of the passive silicon-based decoupling core 4 and the inner sidewall of the through-window 13. Compared with the scheme of mounting the capacitor components on the surface of the glass panel substrate 1, embedding the passive silicon-based decoupling core 4 in the through-window 13 allows the decoupling capacitor structure to be arranged within the thickness range of the glass panel substrate 1, reducing the space occupied by the decoupling core on the surface of the interposer, and allowing the decoupling capacitor structure to be close to the power lines and ground lines in the first redistribution layer 2.

[0056] A first wiring layer 2 is disposed on the first surface of the glass panel substrate 1, and includes a first power line and a first ground line. A second wiring layer 3 is disposed on the second surface of the glass panel substrate 1. Both the first wiring layer 2 and the second wiring layer 3 may include a patterned metal layer, an interlayer dielectric layer, and connection pads, wherein the patterned metal layer may be formed of copper or other conductive materials suitable for packaging interconnects. The first wiring layer 2 is used to connect computing chips, storage chips, interface chips, or other loads located on one side of the first surface, and the second wiring layer 3 is used to connect to the packaging substrate, power supply substrate, or other lower-level interconnect structures.

[0057] Multiple conductive glass vias 15 penetrate the glass panel substrate 1, with each end of the conductive glass via 15 electrically connected to the first redistribution layer 2 and the second redistribution layer 3, respectively. The conductive glass vias 15 can be formed by creating through-holes within the glass panel substrate 1, sequentially forming an adhesion layer and a conductive seed layer on the hole wall, and filling the hole with copper. In other embodiments, the conductive glass vias 15 can also employ a hole wall metallization or metal pillar filling structure. The conductive glass vias 15 directly connect the redistribution layers distributed on both sides of the glass panel substrate 1, shortening the transmission distance of power supply current and return current in the thickness direction of the interposer layer, and avoiding the need for all power supply current to bypass along the plane of the glass panel substrate 1.

[0058] A passive silicon-based decoupling chip 4 is embedded within the through-window 13. The passive silicon-based decoupling chip 4 includes a silicon substrate and a decoupling capacitor structure integrated into the silicon substrate. The decoupling capacitor structure includes at least a deep trench capacitor array. The deep trench capacitor array is formed by creating multiple deep trenches in the silicon substrate and placing electrode layers and dielectric layers within the deep trenches. By utilizing the three-dimensional trench surface within the silicon substrate as the effective capacitor area, a capacitance value higher than that of ordinary planar capacitors can be obtained within the limited planar dimensions of the chip.

[0059] The passive silicon-based decoupling core 4 has a connection end face facing the first rewiring layer 2. The connection end face is provided with a power connection terminal and a ground connection terminal, which are electrically connected to the two ends of the decoupling capacitor structure, respectively. The power connection terminal is connected to the first power line in the first rewiring layer 2, and the ground connection terminal is connected to the first ground line, so that the deep trench capacitor array is connected between the first power line and the first ground line.

[0060] When the load current changes rapidly, the deep trench capacitor array can provide local transient current to the corresponding power line through the power connection terminal and the ground connection terminal. Since the passive silicon-based decoupling core 4 is directly embedded in the glass panel substrate 1, its connection terminal does not need to pass through a long lateral trace on the packaging substrate to the first power line and the first ground line. The closed loop of the decoupling current is confined to the passive silicon-based decoupling core 4 and its adjacent redistribution area. Thus, while retaining the low dielectric loss and large-size fabrication characteristics of the glass panel substrate 1, silicon-based deep trench capacitors that cannot be directly formed by glass materials can be introduced into the glass substrate interlayer to supplement the intermediate frequency decoupling capability of the glass substrate power distribution network.

[0061] In some embodiments, the decoupling capacitor structure further includes a metal-insulator-metal thin-film capacitor array, hereinafter referred to as a MIM thin-film capacitor array. The MIM thin-film capacitor array and the deep trench capacitor array are electrically connected between the power connection terminal and the ground connection terminal, respectively, and together they constitute a composite decoupling capacitor structure. The deep trench capacitor array utilizes the trench sidewalls in the longitudinal direction to obtain a high capacitance per unit area, while the MIM thin-film capacitor array utilizes a relatively short electrode lead-out path to form another decoupling branch. After the two capacitor structures are connected to the same power node and ground node, the impedance characteristics of the passive silicon-based decoupling core 4 can be avoided from being completely determined by a single capacitor structure and its parasitic parameters, enabling the decoupling core to provide bypass current to the load over a wider frequency range.

[0062] In some alternative embodiments, the deep trench capacitor array and the MIM film capacitor array can be connected in parallel, or they can be connected to a common power connection terminal and a ground connection terminal respectively through a core redistribution layer. Both connection methods enable the deep trench capacitor array and the MIM film capacitor array to form a composite decoupling branch between the load power supply and ground. The specific number of capacitors, array shape, and connection method can be determined based on the rated voltage, load transition amplitude, and target impedance of the corresponding power domain.

[0063] In some embodiments, the silicon substrate is an N-type high-resistivity single-crystal silicon substrate with a resistivity of not less than 1000 Ω·cm. No active circuits for performing logic operations or power conversion are disposed in the high-resistivity silicon substrate; the silicon substrate is mainly used to support deep trench capacitor arrays, MIM thin-film capacitor arrays, and corresponding interconnect structures. By increasing the resistivity of the silicon substrate, leakage paths and substrate coupling formed through the silicon substrate between adjacent capacitor units or different power wiring areas can be reduced, preventing the passive silicon-based decoupling core 4 from weakening the electrical isolation between decoupling branches due to substrate conductivity when undertaking multiple decoupling operations.

[0064] In one specific embodiment, the resistivity of the N-type high-resistivity single-crystal silicon substrate is 1200 Ω·cm. This parameter is above the lower limit of 1000 Ω·cm, which can limit the parasitic current generated between capacitor arrays through the silicon substrate while maintaining the conditions for silicon-based microfabrication. The passive silicon-based decoupling chip 4 does not contain transistor voltage regulator units, and its internal effective area can be mainly used to arrange deep trench capacitor arrays, MIM thin-film capacitor arrays, and power supply and ground interconnections.

[0065] In some embodiments, the capacitance density of the deep trench capacitor array is not less than 340 nF / mm². Capacitance density can be understood as the ratio of the total capacitance of the deep trench capacitor array to the projected area of ​​the deep trench capacitor array on the silicon substrate. By limiting the capacitance density within the above range, capacitance for mid-frequency transient response can be obtained under conditions where the size of the through-window 13 is limited, reducing the need to increase the number of passive silicon-based decoupling chips 4 or expand the area of ​​the through-window 13 to achieve the target decoupling capacitance value.

[0066] In one specific embodiment, the capacitance density of the deep trench capacitor array is 360 nF / mm². Taking a passive silicon-based decoupling chip 4 with a planar size of 2 mm × 2 mm as an example, even after deducting the connection terminals, grounding shielding structure, and chip edge process area, the remaining area can still accommodate a deep trench capacitor array with a large total capacitance value. This allows the decoupling chips to be distributed in the storage power area and the interface power area, without having to concentrate all the decoupling capacitors in the central area of ​​the interposer.

[0067] The passive silicon-based decoupling chip 4 has a chip redistribution layer and multiple vertical interconnect copper pillars electrically connected to the chip redistribution layer on its connection end face. The chip redistribution layer connects the internal electrodes of the deep trench capacitor array and the MIM thin film capacitor array to the corresponding vertical interconnect copper pillars. The power connection terminal and the ground connection terminal each include at least one vertical interconnect copper pillar. The vertical interconnect copper pillars included in the power connection terminal are connected to the first power line, and the vertical interconnect copper pillars included in the ground connection terminal are connected to the first ground line.

[0068] The vertical interconnect copper pillars serve two purposes: firstly, they provide the electrical connection between the passive silicon-based decoupling core 4 and the first rewiring layer 2; secondly, they compensate for the difference in thickness between the silicon substrate and the glass panel substrate 1. Since capacitive current can flow in parallel through multiple vertical interconnect copper pillars, the current at the connection end face does not need to be concentrated through a single slender lead, thus reducing the local connection impedance between the core redistribution layer and the first rewiring layer 2. The vertical interconnect copper pillars also provide clearly defined bonding locations, facilitating the alignment of the power connection terminals and ground connection terminals with the first power line and the first ground line, respectively.

[0069] In some embodiments, the passive silicon-based decoupling chip 4 also has a second end face facing away from the connection end face, and the second end face is not provided with connection terminals for external electrical connection. In other words, the passive silicon-based decoupling chip 4 adopts a single-sided lead-out structure, and its internal decoupling capacitor structure is connected to the first rewiring layer 2 through the connection end face, and the second end face is not provided with power terminals or ground terminals that are directly connected to the second rewiring layer 3.

[0070] With a single-sided lead-out structure, the power input and ground return current of the passive silicon-based decoupling chip 4 are concentrated on the side closest to the load to be decoupled, eliminating the need for it to extend through the chip thickness direction to the second wiring layer 3 and then back to the first wiring layer 2. This avoids adding unnecessary double-sided lead-out paths for the passive decoupling function, keeping the decoupling current loop near the connection end face. The second end face also lacks external electrical connection terminals, further distinguishing it from the double-sided conductive structure of the active silicon-based power chip 5 described later, allowing the two types of chips to perform decoupling and voltage conversion functions respectively.

[0071] In an optional embodiment, through-silicon vias (TSVs) may be provided inside the passive silicon-based decoupling core 4. However, these TSVs are only used to connect the internal electrodes of the deep trench capacitor array to the core redistribution layer on the connection end face, and do not extend beyond the second end face to form an external connection. The second end face of the passive silicon-based decoupling core 4 can be a silicon surface without metal pads, or it can be covered with an insulating protective layer or molded insulating material, as long as the second end face does not form external power supply terminals and ground terminals that are directly connected to the second redistribution layer 3.

[0072] In some embodiments, the thickness of the silicon substrate is less than the thickness of the glass panel substrate 1. The second end face of the passive silicon decoupling chip 4, facing away from the connection end face, is flush with the second surface of the glass panel substrate 1, and the end face of the vertical interconnect copper pillar, away from the silicon substrate, is flush with the first surface of the glass panel substrate 1. The chip redistribution layer can be located between the silicon substrate and the vertical interconnect copper pillar, and its thickness is included in the overall height of the passive silicon decoupling chip 4. By selecting the silicon substrate thickness, the chip redistribution layer thickness, and the height of the vertical interconnect copper pillar, the passive silicon decoupling chip 4 is made to be flush with the corresponding surfaces of the glass panel substrate 1 on both sides in the thickness direction.

[0073] Instead of grinding the silicon substrate to make its overall thickness exactly the same as the glass panel substrate 1, this structure uses vertical interconnect copper pillars to compensate for the thickness difference between the silicon substrate and the glass panel substrate 1. This reduces the risk of damage to the trench capacitor structure caused by significant thinning or full-surface grinding of the silicon substrate where the deep trench capacitor array is located, and allows the first and second rewiring layers 2 and 3 to form continuous wiring on relatively flat surfaces. The passive silicon decoupling core 4 is flush with the glass panel substrate 1 on both sides, which can also reduce the abrupt change in local dielectric layer thickness caused by unilateral protrusions or depressions, and reduce stress concentration at the edge of the through window 13 during encapsulation curing and thermal cycling.

[0074] In one specific embodiment, the glass panel substrate 1 has a thickness of 280 μm, the passive silicon-based decoupling core 4 has a silicon substrate thickness of 220 μm, the signal redistribution layer on the connection end face has a thickness of 1 μm, the power supply and shielding redistribution layer has a thickness of 2 μm, and the vertical interconnect copper pillar has a height of 57 μm. The combined height of the above layers in the thickness direction is 280 μm, making the second end face flush with the second surface and the outer end of the vertical interconnect copper pillar flush with the first surface.

[0075] In other embodiments where the overall height of the passive silicon-based decoupling core 4 is less than the thickness of the glass panel substrate 1, a molding insulating material can be filled between the second end face and the second surface of the core, or in the remaining space around the connecting end face. The molding insulating material is used to fill voids created by localized steps in the core and to provide a continuous insulating bearing surface for subsequent redistribution layers. The molding insulating material does not replace the flexible adhesive material at the sidewalls of the through window 13; the former is primarily used to fill areas of thickness difference, while the latter is primarily used for flexible connection and stress transition between the core and the glass.

[0076] In some embodiments, a sidewall gap is formed between the outer sidewall of the passive silicon-based decoupling core 4 and the inner sidewall of the through window 13, and the sidewall gap is filled with a flexible adhesive material. The flexible adhesive material can be an organic adhesive that still has elastic deformation capability after curing, and it is respectively attached to the outer sidewall of the passive silicon-based decoupling core 4 and the inner sidewall of the through window 13.

[0077] The sidewall gaps provide the necessary assembly allowance for the core particle to be inserted into the through-window 13. The flexible adhesive material, after filling these gaps, restricts the displacement of the core particle in the plane of the glass panel substrate 1. Since the deformation of the silicon substrate and the glass panel substrate 1 during temperature changes is not entirely the same, the flexible adhesive material can absorb some of the relative displacement between the two materials through its own shear deformation, avoiding direct concentration of thermal cycling shear stress at the edges of the silicon core particle and the sharp corners of the through-window 13. This structure simultaneously considers core particle positioning and stress transition between dissimilar materials, rather than simply locking the core particle within the glass window using rigid fillers.

[0078] In some embodiments, the sidewall gap is no greater than 8 μm, and the flexible adhesive material is an organic flexible adhesive. Controlling the sidewall gap to within 8 μm limits the thickness of the flexible adhesive layer and the offset of the core particles within the through-window 13, preventing significant deviations in the predetermined connection positions of the core particle connection terminals relative to the first rewiring layer 2. Simultaneously, this gap still allows the organic flexible adhesive to form a continuous adhesive layer to withstand shear deformation under thermal cycling conditions.

[0079] In one specific embodiment, the gap between the outer wall of the passive silicon-based decoupling core 4 and the inner wall of the through window 13 is 5 μm, and the gap is filled with a low-modulus organic flexible adhesive. After the adhesive cures, it continuously surrounds at least part of the circumferential sidewall of the passive silicon-based decoupling core 4, so that a flexible transition interface is formed between the core and the glass panel substrate 1.

[0080] In some embodiments, the second redistribution layer 3 includes a second power line and a second ground line, and the plurality of conductive glass vias 15 include power conductive glass vias 15 and ground conductive glass vias 15. The two ends of the power conductive glass vias 15 are electrically connected to the first power line and the second power line, respectively, and the two ends of the ground conductive glass vias 15 are electrically connected to the first ground line and the second ground line, respectively.

[0081] The power conductive glass via 15 and the ground conductive glass via 15 form separate vertical power supply channels and vertical grounding channels within the glass panel substrate 1. External power can be transmitted to the first power line via the second power line and the power conductive glass via 15, and the load return current can return to the second grounding line via the first grounding line and the ground conductive glass via 15. By configuring conductive glass vias 15 for power supply and grounding respectively, the power supply path and return path can be matched in the thickness direction of the interlayer, reducing large-area current loops formed due to unclear return paths.

[0082] In some alternative embodiments, the power conductive glass vias 15 and the ground conductive glass vias 15 can be arranged in pairs, or they can form power via arrays and ground via arrays, respectively. The ground conductive glass vias 15 can be arranged around or adjacent to the power conductive glass vias 15 to constrain the high-frequency return path. Some of the conductive glass vias 15 can also be connected to a larger ground metal area, so that the copper filling the vias simultaneously forms a heat conduction channel in the thickness direction of the glass panel substrate 1. Therefore, while undertaking vertical electrical connections, the conductive glass vias 15 can transfer heat generated near the first surface to the packaging substrate or heat dissipation structure on the second surface side.

[0083] In one specific embodiment, the diameter of the conductive glass via 15 is 60 μm, and the center-to-center distance between adjacent conductive glass vias 15 is 300 μm. Multiple conductive glass vias 15 are distributed around the through window 13 and the corresponding power supply area, with some connected to the first and second power lines and others connected to the first and second ground lines. This dimension is a specific application example and does not constitute a limitation on the size of the conductive glass via 15.

[0084] In some embodiments, there are multiple through windows 13, and at least two of the multiple through windows 13 are respectively embedded with passive silicon-based decoupling cores 4. The multiple passive silicon-based decoupling cores 4 are distributed at intervals along the planar direction of the glass panel substrate 1. Different passive silicon-based decoupling cores 4 are respectively connected to the first power line and the first ground line in the adjacent area, so that the decoupling capacitors are not concentrated in a single location.

[0085] After distributing the passive silicon-based decoupling cores 4, the transient current in each load area can be preferentially supplied by the adjacent decoupling cores, reducing the lateral transmission distance of transient current in the first wiring layer 2. Compared with related technologies that use a single large-area central decoupling core, multiple passive silicon-based decoupling cores 4 can adjust their number and position according to the load density of different areas, so that storage loads and interface loads far from the central area on the interposer layer also have shorter decoupling connection paths.

[0086] In some embodiments, the glass panel substrate 1 has a storage power region corresponding to the storage cell 62 of the chip to be connected, and an interface power region corresponding to the interface cell 63 of the chip to be connected, in a planar direction. The chip to be connected can be a single large chip, or a combination of chips consisting of a main computing chip, a storage chip, and an interface chip. At least a portion of the plurality of passive silicon-based decoupling chips 4 are disposed in the storage power region and / or the interface power region.

[0087] By placing the passive silicon-based decoupling core 4 in the storage power area and the interface power area, the decoupling capability can correspond to the location of the corresponding load, rather than simply relying on the available area of ​​the interposer layer. The power supply voltage, switching activity, and load change mode of the storage unit 62 and the interface unit 63 are different from those of the main computing unit 61. The partitioned configuration of the passive silicon-based decoupling core 4 allows for adjustment of the number of cores, capacitor area, and connection lines in each area, reducing voltage disturbance coupling caused when different power domains share long-distance decoupling paths.

[0088] In some embodiments, the glass panel substrate 1 is further provided with an active chip through-window 13 that penetrates the first surface and the second surface, and an active silicon-based power chip 5 is embedded in the active chip through-window 13. The active silicon-based power chip 5 is electrically connected to the first redistribution layer 2 and the second redistribution layer 3 respectively, thereby forming a double-sided conductive structure.

[0089] The active silicon-based power chip 5 converts the input voltage received by the second wiring layer 3 into an output voltage suitable for use by the main computing unit 61, and transmits the converted power to the main computing unit 61 via the first wiring layer 2. Since the active silicon-based power chip 5 is embedded throughout the glass panel substrate 1, its input end can connect to the packaging substrate towards the second wiring layer 3, and its output end can connect to the load towards the first wiring layer 2. The voltage conversion path is established along the thickness direction of the interposer layer. This arrangement moves the final stage voltage regulation location to the vicinity of the main computing load, reducing the transmission distance of low-voltage, high-current in the planar direction between the packaging substrate and the interposer layer.

[0090] When the active silicon-based power supply chip 5 and the passive silicon-based decoupling chip 4 are arranged together within the same glass panel substrate 1, the active silicon-based power supply chip 5 is responsible for voltage conversion and continuous power supply, while the passive silicon-based decoupling chip 4 is responsible for local charge compensation during rapid load changes. The two types of chips do not perform the same power supply function, but act on the power distribution network at different time scales, avoiding reliance solely on the active regulation loop to respond to rapid load changes, and also avoiding reliance solely on passive capacitors to handle continuous power transmission.

[0091] In some embodiments, the active silicon-based power chip 5 includes a doped silicon substrate, an integrated voltage regulation unit, a through-silicon via (TSV) array penetrating the doped silicon substrate, and a power redistribution layer electrically connected to the TSV array. The integrated voltage regulation unit may include power switching devices, control circuitry, and passive components cooperating therewith. The TSV array connects the power redistribution layers on the first and second sides of the active silicon-based power chip 5, enabling input and output currents to be transmitted along the chip thickness direction.

[0092] The power redistribution layer can form a mesh-like or planar thick copper conductive structure to disperse the large current flowing through the active silicon-based power chip 5. Multiple through-silicon vias (TSVs) are connected in parallel to form a current channel penetrating the doped silicon substrate, reducing the current density carried by a single TSV. Thus, the active silicon-based power chip 5 can form a double-sided low-resistance power path within a limited planar size and directly transmit the output of the integrated voltage regulation unit to the first redistribution layer 2.

[0093] In one specific embodiment, the active silicon-based power chip 5 has a planar dimension of 6mm × 6mm and an overall thickness of 280μm. The doped silicon substrate thickness is 220μm, the signal redistribution layer thickness is 2μm, the power and shielding redistribution layer thickness is 2.5μm, the metal pad thickness on the second end face is 2.5μm, and the height of the vertical interconnect copper pillars on the first end face is 53μm. The silicon via diameter within the active silicon-based power chip 5 is 15μm, and the via spacing is 80μm.

[0094] The second end face of the active silicon-based power chip 5 is provided with metal pads and a C4 bump array. The metal pads are connected to the integrated voltage regulation unit via a through-silicon via array, and the C4 bump array is connected to the second redistribution layer 3 or the packaging substrate. The first end face of the active silicon-based power chip 5 is provided with a power redistribution layer and vertical interconnect copper pillars, which are connected to the first redistribution layer 2. In one power supply state, the active silicon-based power chip 5 receives a 48V input voltage and outputs a 0.8V voltage to provide a nearby low-voltage, high-current power supply to the main computing unit 61. The above input and output voltages are only specific examples; the active silicon-based power chip 5 can also be configured with other conversion ratios according to the operating voltage of the chip to be connected.

[0095] In some embodiments, the glass panel substrate 1 has a main computing power region, a storage power region, and an interface power region in a planar direction. The main computing power region corresponds to the main computing unit 61 of the chip to be connected, the storage power region corresponds to the storage unit 62, and the interface power region corresponds to the interface unit 63. An active silicon-based power chip 5 is disposed in the main computing power region, and a passive silicon-based decoupling chip 4 is disposed in the storage power region and / or the interface power region.

[0096] The main computing unit 61 typically corresponds to a large continuous power and high transient current. Therefore, an active silicon-based power supply chip 5 is arranged in the main computing power supply area, where the final stage voltage conversion can be completed. The storage unit 62 and interface unit 63 are distributed around the main computing unit 61. Passive silicon-based decoupling chips 4 are arranged in the corresponding areas, which can shorten the local decoupling path in these areas. This layout allows different functional areas to obtain power supply units corresponding to their power supply characteristics, avoiding the need to concentrate active voltage regulation and passive decoupling in a single area and then distribute them to all loads via long-distance lines.

[0097] Physical isolation zones can be formed between adjacent power supply areas using the portion of the glass panel substrate 1 without through windows 13. The glass material itself is electrically insulating, and maintaining a millimeter-level spacing between different functional power supply areas reduces direct electric field coupling between adjacent cores and their redistribution lines. This physical isolation zone does not require additional cross-core shielding and can achieve spatial separation of different macroscopic power supply areas using the glass substrate retained between the through windows 13.

[0098] In some embodiments, the connection end face of the passive silicon-based decoupling chip 4 has at least two power routing areas corresponding to different sub-power domains, and a ground shield redistribution layer is provided between adjacent power routing areas. The ground shield redistribution layer is connected to a ground connection terminal and can be arranged in a continuous strip between adjacent power routing areas, or it can be arranged around at least one power routing area.

[0099] When a passive silicon-based decoupling chip 4 corresponds to multiple sub-power domains, the distance between the power lines and decoupling capacitor units of each sub-power domain on the chip connection end face is small. After the ground shield redistribution layer is set between adjacent power routing areas, a conductive boundary connected to the ground potential can be formed between the two power routing areas, so that the electric field coupling current generated by one sub-power domain is preferentially discharged through the ground shield redistribution layer, rather than directly coupled to the adjacent sub-power domain. This structure is used to solve the power crosstalk problem under the small spacing inside a single chip, and in conjunction with the physical isolation between different chips on the glass panel substrate 1, a structure combining macroscopic partition isolation and chip internal shielding is formed.

[0100] In some embodiments, the passive silicon-based decoupling core 4 is provided with a plurality of grounding silicon vias, which are spaced apart along the grounding shield redistribution layer and electrically connected to the grounding shield redistribution layer. The grounding silicon vias can be arranged along the length of the grounding shield redistribution layer or along its circumference. The plurality of grounding silicon vias connect the grounding shield redistribution layer to the grounding metal layer or grounding node within the core, so that the grounding shield redistribution layer is not grounded by a single end connection point.

[0101] By setting multiple grounding silicon vias along the grounding shield redistribution layer, the impedance between different locations of the shield redistribution layer and the grounding node can be reduced, preventing the long shielding metal strip from generating a significant potential difference at high frequencies due to its own parasitic inductance. The grounding shield redistribution layer and the grounding silicon vias together constitute a three-dimensional grounding shield structure that penetrates the local thickness of the core, used to block the transverse electric field coupling and part of the magnetic field coupling between adjacent sub-power domains.

[0102] In one specific embodiment, an electrical isolation gap with a width of 40 μm is provided between adjacent sub-power domains. A grounding copper shielding strip with a width of 50 μm and a thickness of 2.5 μm is provided at the edge of the electrical isolation gap. Grounding silicon vias with a diameter of 10 μm and a spacing of 40 μm are uniformly arranged along the grounding copper shielding strip. The grounding copper shielding strip and the multiple grounding silicon vias form a continuous low-resistance grounding boundary to reduce synchronous switching crosstalk between different sub-power domains within a single chip.

[0103] In some embodiments, the thickness of the glass panel substrate 1 is 50 μm-300 μm, and the linear coefficient of thermal expansion of the glass panel substrate 1 is 2.8 ppm / ℃-3.2 ppm / ℃. The lower limit of the thickness of the glass panel substrate 1 enables the formation of through windows 13 with continuous hole walls and conductive glass vias 15, and provides lateral support for the embedded passive silicon-based decoupling core 4; the upper limit of the thickness is used to limit the overall thickness of the interposer and the length of the conductive glass vias 15, avoiding a significant increase in the vertical electrical connection path as the glass thickness increases.

[0104] By controlling the linear thermal expansion coefficient of the glass panel substrate 1 within the range of 2.8 ppm / ℃ to 3.2 ppm / ℃, the in-plane deformation difference between the glass panel substrate 1 and the silicon-based core particles during temperature changes can be reduced. This range of thermal expansion coefficients, combined with the flexible sidewall bonding structure and the double-sided flush-mount structure, ensures that thermal stress is not concentrated and is borne by a single interface, thereby reducing the risk of cracking or delamination at the edge of the through window 13, the redistribution layer cross-border area, and the core particle connection terminals.

[0105] In one specific embodiment, the glass panel substrate 1 has a thickness of 280 μm and a linear thermal expansion coefficient of 3.0 ppm / ℃. This thickness is sufficient to accommodate an active silicon-based power chip 5 and a passive silicon-based decoupling chip 4, both 280 μm thick, such that the two sides of each chip are flush with the first and second surfaces of the glass panel substrate 1, respectively.

[0106] In some optional embodiments, corresponding metal electrode regions can be respectively provided in the first redistribution layer 2 and the second redistribution layer 3, and the corresponding metal electrode regions form glass-based planar capacitors with the glass panel substrate 1 as the dielectric. These glass-based planar capacitors can be connected to a power distribution network to form a glass-based low-frequency decoupling network; the deep trench capacitor array and MIM thin-film capacitor array within the passive silicon-based decoupling core 4 constitute a silicon-based mid-frequency decoupling network. The glass-based planar capacitor has a large electrode area, and the silicon-based composite decoupling capacitor has a high capacitance density per unit area and a short local connection path; both can jointly undertake charge compensation in different frequency ranges.

[0107] In one specific implementation, the silicon-based composite decoupling capacitor primarily covers decoupling requirements in the 100kHz-100MHz range. The planar capacitors formed by the redistribution layers on both sides of the glass panel substrate 1 handle low-frequency charge storage and, together with the packaging substrate capacitors and chip-side capacitors, extend the effective decoupling frequency band of the power distribution network. By adjusting the capacitance values, connection positions, and parasitic parameters of the deep trench capacitor array, MIM thin-film capacitor array, and glass-based planar capacitors, the power distribution network of the interposer can maintain a low target impedance in the 100kHz-5GHz range. The above frequency bands are specific design examples; the actual frequency bands can be adjusted according to the load's switching frequency and package interconnect parameters.

[0108] For example, this embodiment is used for AI computing chip packaging with a diameter of 700mm² or more and a power consumption of 1000W or more. The chip assembly to be connected includes a main computing unit 61GCD located in the middle, four high-bandwidth storage units 62HBM distributed on both sides of the main computing unit 61, and four interface units 63IOD, wherein two HBMs and two IODs are provided on each side.

[0109] The glass panel substrate 1 has a thickness of 280 μm and a linear coefficient of thermal expansion of 3.0 ppm / ℃. An active chip through-window 13 is provided in the center of the glass panel substrate 1, and an active silicon-based power chip 5 with a planar size of 6 mm × 6 mm is embedded within the active chip through-window 13. The second end of the active silicon-based power chip 5 is connected to the second rewiring layer 3 via metal pads and a C4 bump array, and the first end is connected to the first rewiring layer 2 via vertical interconnect copper pillars. This active silicon-based power chip 5 converts the 48V voltage input from the packaging substrate to a 0.8V voltage and supplies power to the central GCD via the first rewiring layer 2.

[0110] Four passive core-particle through-windows 13 are respectively arranged on both sides of the glass panel substrate 1. Each passive core-particle through-window 13 embeds a passive silicon-based decoupling core 4 with a planar size of 2mm×2mm. The eight passive silicon-based decoupling cores 4 correspond to four HBMs and four IODs respectively. Each passive silicon-based decoupling core 4 uses an N-type high-resistivity single crystal silicon substrate with a resistivity of 1200Ω·cm, and internally sets a deep trench capacitor array and a MIM thin film capacitor array with a capacitance density of 360nF / mm². The power connection terminal of each passive silicon-based decoupling core 4 is connected to the first power line of the corresponding storage power area or interface power area, and the ground connection terminal is connected to the adjacent first ground line.

[0111] The passive silicon-based decoupling chip 4 has a silicon substrate thickness of 220 μm, a signal redistribution layer thickness of 1 μm on the connection end face, a power and shielding redistribution layer thickness of 2 μm, and a vertical interconnect copper pillar height of 57 μm. The second end face is flush with the second surface of the glass panel substrate 1, and the outer end of the vertical interconnect copper pillar is flush with the first surface. A 5 μm sidewall gap is maintained between the passive silicon-based decoupling chip 4 and the through window 13, and the sidewall gap is filled with organic flexible adhesive.

[0112] An array of conductive glass vias 15, each with a diameter of 60 μm and a spacing of 300 μm, is provided within the glass panel substrate 1. The power conductive glass vias 15 are connected to the first power line and the second power line, respectively, while the ground conductive glass vias 15 are connected to the first ground line and the second ground line, respectively. Some of the ground conductive glass vias 15 are arranged near the power conductive glass vias 15 to provide a nearby return path for the vertical power supply current. The copper-filled conductive glass vias 15 simultaneously transfer some of the heat from the first surface area to one side of the second surface.

[0113] During operation, the active silicon-based power chip 5 provides a continuous low-voltage, high-current power supply to the GCD. When the GCD load rises rapidly, the active silicon-based power chip 5 first supplies power to the GCD through the adjacent power redistribution layer; when the regulation loop has not yet completed output adjustment, the glass-based planar capacitor and capacitors in the adjacent power supply network provide initial charge compensation. When the HBM or IOD experiences a load transition, the passive silicon-based decoupling chip 4 in the corresponding area releases charge to that area through a shorter power connection terminal and a ground connection terminal, preventing the transient current from being transmitted entirely from the central active silicon-based power chip 5 through the long first redistribution layer 2.

[0114] Physical isolation zones are formed between different HBM and IOD power regions by maintaining a glass substrate. For multiple sub-power routing areas within the same passive silicon-based decoupling core 4, a grounded shielding redistribution layer is provided between adjacent routing areas, and grounded silicon vias arranged along the shielding redistribution layer are connected to the grounding node. Thus, the interposer achieves spatial isolation between cores using the glass substrate, and local shielding within the core using the grounded shielding redistribution layer and grounded silicon vias, reducing the impact of the switching current of one power domain on adjacent power domains.

[0115] In this embodiment, active voltage regulation, silicon-based composite decoupling, glass-based flat-plate decoupling, vertical power supply, and grounding channels are arranged within the same glass panel substrate 1. The active silicon-based power chip 5 handles voltage conversion in the main computing power region, while the passive silicon-based decoupling chip 4 handles local intermediate frequency decoupling in the storage power region and the interface power region, respectively. The first rewiring layer 2 and the second rewiring layer 3 form a low-frequency charge storage and global power distribution structure. Each functional structure is distributed according to the location of the power domain, rather than being uniformly centralized within the interposer layer, thus ensuring that the continuous power supply path, local transient current path, and ground return path are matched to the locations of their respective loads.

[0116] In this embodiment, the glass-based power distribution network interposer structure serves as an intermediate interconnect carrier within the packaging structure, situated between the upper plurality of bare dies and the lower packaging substrate. The upper plurality of bare dies may include one or more of main computing dies, storage dies, and interface dies; the lower packaging substrate is used to receive external power, grounding, and signal lines, and further connects to the circuit board or other lower-level carriers. That is, the glass panel substrate, the first rewiring layer, the second rewiring layer, the conductive glass vias, and the passive silicon-based decoupling dies embedded within the through-windows described in this embodiment are all components of the interposer structure, and not components of the lower packaging substrate.

[0117] Taking the illustrated orientation as an example, the first surface of the glass panel substrate faces the bare core chip above. The first rewiring layer is disposed on the first surface and is electrically connected to the main computing bare core chip, storage bare core chip, or interface bare core chip via metal microbumps disposed above the interposer layer. The metal microbumps are used to achieve close-range interconnection between the bare core chip and the interposer layer, and their spacing and size can be set according to the pad arrangement, power supply terminal density, and signal interconnection density of the bare core chip. The connection end face of the passive silicon-based decoupling chip faces the first rewiring layer, allowing its power connection terminals and ground connection terminals to be connected close to the power and ground nodes of the corresponding bare core chip via the first rewiring layer, thereby shortening the local decoupling path on the bare core chip side.

[0118] The second surface of the glass panel substrate faces the underlying encapsulation substrate. A second redistribution layer is disposed on the second surface and electrically connected to the encapsulation substrate via metal C4 bumps disposed below the interposer. The metal C4 bumps are used to achieve power, ground, and signal connections between the interposer and the encapsulation substrate, and their size and spacing are typically larger than the metal microbumps above the interposer used to connect bare chips. The encapsulation substrate is located below the metal C4 bumps and may include an organic substrate, a ceramic substrate, or other encapsulation carrier, but the encapsulation substrate is not equivalent to the glass-based power distribution network interposer structure of this application.

[0119] The conductive glass via penetrates the glass panel substrate and connects the first and second redistribution layers, establishing a vertical electrical connection path from the encapsulation substrate side to the bare die side within the interposer layer. External power can be transmitted sequentially through the encapsulation substrate, metal C4 bumps, the second redistribution layer, and the conductive glass via to the first redistribution layer, and then supplied to the upper bare die through metal microbumps. Correspondingly, the ground return current from the bare die side can also return to the encapsulation substrate via metal microbumps, the first redistribution layer, the conductive glass via, the second redistribution layer, and the metal C4 bump. In the above power supply path, the glass panel substrate and its two side redistribution layers constitute an interposer layer interconnection structure between the bare die and the encapsulation substrate, rather than the encapsulation substrate itself.

[0120] In this embodiment, a through-window is formed within the glass panel substrate, and a passive silicon-based decoupling chip is embedded within the through-window. Therefore, the passive silicon-based decoupling chip is integrated within the thickness of the interposer. This passive silicon-based decoupling chip connects to the power and ground lines on the bare chip side via its connection end face facing the first redistribution layer, rather than being disposed as an external capacitor on the surface of the package substrate. Thus, the decoupling structure in this embodiment is an interposer-embedded decoupling structure, its operational position being close to the power supply node of the upper bare chip, which can reduce parasitic inductance and parasitic resistance introduced by the package substrate traces, C4 bumps, and interconnect paths below the interposer.

[0121] In some embodiments, the metal microbumps above the interposer correspond to the power pads, ground pads, or signal pads of the bare die, and the metal C4 bumps below the interposer correspond to the power pads, ground pads, or signal pads of the package substrate. The metal microbumps and metal C4 bumps are located on opposite sides of the interposer, and are used to connect packaged objects at different levels: the metal microbumps connect the bare die to the interposer, and the metal C4 bumps connect the interposer to the package substrate. This hierarchical division clarifies that the interposer structure described in this embodiment is located between the bare die and the package substrate, and the conductive glass vias, through windows, and passive silicon-based decoupling dies integrated within it all serve the power distribution network of the interposer level.

[0122] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. Embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims, and the foregoing embodiments should be considered exemplary and non-limiting.

Claims

1. A glass-based power distribution network interposer structure with embedded silicon-based decoupling cores, characterized in that, include: A glass panel substrate has a first surface and a second surface disposed opposite to each other. The glass panel substrate is provided with a through window that penetrates the first surface and the second surface and a plurality of conductive glass through holes. A first wiring layer is disposed on the first surface, and the first wiring layer includes a first power line and a first ground line. A second wiring layer is disposed on the second surface, and the two ends of each of the conductive glass through holes are electrically connected to the first wiring layer and the second wiring layer, respectively. A passive silicon-based decoupling chip is embedded in the through window. The passive silicon-based decoupling chip includes a silicon substrate and a decoupling capacitor structure integrated on the silicon substrate. The decoupling capacitor structure includes a deep trench capacitor array. The passive silicon-based decoupling chip has a connection end face facing the first redistribution layer. The connection end face is provided with a power connection terminal and a ground connection terminal that are electrically connected to the decoupling capacitor structure, respectively. The power connection terminal is electrically connected to the first power line, and the ground connection terminal is electrically connected to the first ground line.

2. The glass-based power distribution network interposer structure with embedded silicon-based decoupling cores according to claim 1, characterized in that, The decoupling capacitor structure further includes a metal-insulator-metal film capacitor array, which together with the deep trench capacitor array forms a composite decoupling capacitor structure and is electrically connected between the power connection terminal and the ground connection terminal, respectively.

3. The glass-based power distribution network interposer structure with embedded silicon-based decoupling cores according to claim 1, characterized in that, The connection end face is provided with a core rewiring layer and a plurality of vertical interconnect copper pillars electrically connected to the core rewiring layer. The power connection terminal and the ground connection terminal respectively include the corresponding vertical interconnect copper pillars.

4. The glass-based power distribution network interposer structure with embedded silicon-based decoupling cores according to claim 3, characterized in that, The passive silicon-based decoupling core also has a second end face facing away from the connection end face, and the second end face is not provided with connection terminals for external electrical connection.

5. The glass-based power distribution network interposer structure with embedded silicon-based decoupling cores according to claim 3, characterized in that, The thickness of the silicon substrate is less than the thickness of the glass panel substrate, the second end face of the passive silicon decoupling core facing away from the connection end face is flush with the second surface, and the end of the vertical interconnect copper pillar away from the silicon substrate is flush with the first surface.

6. The glass-based power distribution network interposer structure with embedded silicon-based decoupling cores according to claim 1, characterized in that, The second redistribution layer includes a second power line and a second ground line, and the plurality of conductive glass vias include power conductive glass vias and ground conductive glass vias; The two ends of the power conductive glass through hole are electrically connected to the first power line and the second power line, respectively, and the two ends of the ground conductive glass through hole are electrically connected to the first ground line and the second ground line, respectively.

7. The glass-based power distribution network interposer structure with embedded silicon-based decoupling cores according to claim 1, characterized in that, The glass panel substrate is further provided with an active chip through window that penetrates the first surface and the second surface. An active silicon-based power chip is embedded in the active chip through window. The active silicon-based power chip is electrically connected to the first redistribution layer and the second redistribution layer, respectively.

8. The glass-based power distribution network interposer structure with embedded silicon-based decoupling cores according to claim 7, characterized in that, The glass panel substrate has a main computing power area corresponding to the main computing unit of the chip to be connected, a storage power area corresponding to the storage unit of the chip to be connected, and an interface power area corresponding to the interface unit of the chip to be connected in the planar direction. The active silicon-based power chip is disposed in the main computing power region, and the passive silicon-based decoupling chip is disposed in the storage power region and / or the interface power region.

9. The glass-based power distribution network interposer structure with embedded silicon-based decoupling cores according to claim 1, characterized in that, The connection end face of the passive silicon-based decoupling chip has at least two power routing areas corresponding to different sub-power domains, and a grounding shield redistribution layer is provided between adjacent power routing areas.

10. The glass-based power distribution network interposer structure with embedded silicon-based decoupling cores according to claim 9, characterized in that, The passive silicon-based decoupling core has multiple grounding silicon vias, which are spaced apart along the grounding shield redistribution layer and electrically connected to the grounding shield redistribution layer.

Images