Packaging debugging parameter self-adaptive method for gallium nitride chip

Abstract

This invention provides an adaptive method for packaging and debugging parameters of gallium nitride (GaN) chips. The method includes processing multimodal image data and extracting features to obtain a packaging feature vector. The packaging feature vector is then input into a semi-physical mapping model, which outputs a second set of packaging and debugging parameters. The semi-physical mapping model consists of a physical prior structure, production line calibration coefficients, and a residual correction network. The second set of packaging and debugging parameters is distributed to the packaging production line to adaptively adjust the packaging and debugging parameters of the next batch of GaN power devices across batches. After the debugging action is executed, multimodal image data of the packaged object is collected again, and a yield feedback index is calculated. If the yield feedback index is lower than a preset yield threshold, the production line calibration coefficients and the network parameters of the residual correction network are iteratively updated based on a historical sample set until the yield threshold is reached. This achieves continuous correction of the debugging parameters as the material properties and equipment status drift between batches.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a method for adaptive packaging and debugging parameters of gallium nitride chips. Background Technology

[0002] In gallium nitride (GaN) power device packaging lines, packaging conditions such as chip offset, solder void ratio, hotspot peak temperature, and temperature gradient directly affect the debugging parameters corresponding to parasitic inductance, thermal resistance, and dynamic on-resistance testing and aging tests. Because GaN devices are extremely sensitive to packaging parasitic parameters, parasitic inductance during high-frequency switching can cause voltage overshoot and ringing, while excessively high void area ratio in the adhesive can affect the electrical and thermal performance of the product. The industry typically needs to control the void area ratio within a certain range and significantly reduce the risk of voids by increasing adhesive thickness, but this can lead to an increase in chip tilt, thus imposing stringent requirements on the matching relationship between various debugging parameters.

[0003] Currently, gallium nitride (GaN) power device packaging production lines primarily rely on manual sampling or offline automated optical inspection for quality control and process debugging. Manual debugging is inefficient and highly subjective; offline inspection typically only provides binary defect identification and cannot provide real-time feedback to the production line for process parameter adjustments. Furthermore, when yield feedback indicators are abnormal, subsequent process parameter corrections heavily depend on engineers' experience-based manual adjustments, resulting in a lag in this open-loop control model. Moreover, in current technology, defect detection, analysis, and debugging are disconnected, making it impossible to immediately implement precise parameter corrections in subsequent processing within the same batch or across batches, thus failing to prevent the recurrence of defects. Summary of the Invention

[0004] To address the aforementioned issues, this invention aims to provide an adaptive method for packaging and debugging parameters of gallium nitride (GaN) chips. This method involves acquiring multimodal image data from the packaging production line, extracting packaging feature vectors, inputting them into a semi-physical mapping model, and outputting gate drive voltage spike compensation, bonding process power-time parameters, dynamic on-resistance test excitation amplitude, and aging test stress amplitude. These parameters are then sent to the production line to adaptively adjust the packaging and debugging parameters of the next batch of GaN power devices across batches. Furthermore, when the yield feedback index falls below a preset yield threshold, the method iteratively updates the production line calibration coefficients and the network parameters of the residual correction network based on historical sample sets.

[0005] This invention provides an adaptive method for packaging and debugging parameters of a gallium nitride chip, comprising:

[0006] Acquire multimodal image data from the packaging production line of gallium nitride power devices;

[0007] Image processing and feature extraction are performed on multimodal image data to obtain packaging feature vectors that include at least chip patch offset, void ratio, hot spot peak temperature and temperature gradient;

[0008] Input the package feature vector into the semi-physical mapping model and output a second set of package debugging parameters, including at least the gate drive voltage spike compensation amount, bonding process power-time parameters, dynamic on-resistance test excitation amplitude, and aging test stress amplitude.

[0009] The semi-physical mapping model consists of the physical prior structure of gallium nitride power devices, production line calibration coefficients based on historical sample sets, and a residual correction network. The physical prior structure outputs the first set of packaging debugging parameters based on sub-mapping, and the residual correction network outputs the residual correction amount. The sum of the first set of packaging debugging parameters and the residual correction amount is used as the second set of packaging debugging parameters.

[0010] The second set of packaging debugging parameters is sent to the packaging production line to adaptively adjust the packaging debugging parameters of the next batch of gallium nitride power devices across batches.

[0011] After the debugging action is performed, multimodal image data of the packaged object is collected again and the yield feedback index is calculated. If the yield feedback index is lower than the preset yield threshold, the production line calibration coefficient and the network parameters of the residual correction network are iteratively updated based on the historical sample set until the yield threshold is reached.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] By extracting packaging feature vectors from multimodal image data, a quantitative correlation between the physical state of the package and the debugging parameters was established, thereby improving the problem of decoupling between the debugging parameters and the physical state of the package.

[0014] The second packaging debugging parameter set is output by a semi-physical mapping model consisting of physical prior structure, production line calibration coefficients and residual correction network, thereby improving the fit between the output second packaging debugging parameter set and the actual packaging state.

[0015] By adaptive adjustment across batches and iterative updates based on yield feedback indicators, the debugging parameters are continuously corrected as material properties and equipment status drift between batches. Attached Figure Description

[0016] Figure 1 The execution flowchart of the gallium nitride chip packaging debugging parameter adaptive method of the present invention is shown.

[0017] Figure 2 The diagram shows the semi-physical mapping model architecture and data flow of the gallium nitride chip packaging and debugging parameter adaptive method of the present invention. Detailed Implementation

[0018] The present invention will now be described in detail with reference to the accompanying drawings, such as... Figure 1 , Figure 2 As shown below, the adaptive method for packaging and debugging parameters of a gallium nitride chip will be described in detail.

[0019] The present invention provides an adaptive method for packaging and debugging parameters of gallium nitride chips. First, a multimodal image acquisition system is deployed on the packaging production line of gallium nitride power devices to obtain multimodal image data that can comprehensively reflect the physical state of the packaged device.

[0020] In one embodiment, the acquisition of multimodal image data covers the post-mount, post-curing, post-bonding, and final inspection stations of the packaging production line. Specific acquisition methods include:

[0021] Visible light images are acquired using industrial cameras. These cameras are deployed at post-placement and post-bonding stations to acquire images of the chip placement location and bonding wire morphology. The resolution of the industrial cameras can be configured according to the production line's accuracy requirements; as an example rather than a limitation, industrial cameras with a resolution of five megapixels or higher can be selected.

[0022] X-ray imaging is acquired using an X-ray imaging device. This device is deployed at the post-curing station to obtain images of the internal structure of the chip's adhesive layer and solder joints, enabling the detection of voids and defects within the adhesive layer and solder joints. The X-ray imaging device can employ a microfocus X-ray source, with the focal spot size selected based on the required inspection accuracy.

[0023] Infrared thermal imagers are used to acquire infrared thermal distribution images. These imagers are deployed at the final inspection station to obtain surface temperature distribution images of packaged devices under powered-on operating conditions. The thermal sensitivity of the infrared imager can be configured according to temperature measurement accuracy requirements. As an example and not a limitation, an infrared imager with a thermal sensitivity not exceeding 50mK can be selected.

[0024] The visible light images, X-ray images, and infrared thermal distribution images acquired by the industrial camera, X-ray imaging equipment, and infrared thermal imager, respectively, constitute a set of multimodal image data, denoted as multimodal image data. This multimodal image data serves as the input data basis for subsequent image processing and feature extraction steps, carrying multi-dimensional packaging quality information such as chip placement offset, adhesive layer voids, and packaging hotspot temperatures.

[0025] It should be noted that the specific parameters such as the model, resolution, and sensitivity of the image acquisition equipment configured at each of the above workstations are all conventional choices that can be made by those skilled in the art based on actual production line conditions, cost budgets, and detection accuracy requirements. The specific values ​​mentioned in this specification are only optional implementation examples and do not constitute a limitation on the scope of protection of this invention.

[0026] Since factors such as lighting conditions in the packaging production line, contrast differences in X-ray imaging, and temperature measurement noise of infrared thermal imagers can all affect the stability and accuracy of image analysis results, it is necessary to perform image enhancement processing on multimodal image data to obtain an enhanced image set.

[0027] In one embodiment, the image enhancement process is as follows:

[0028] First, the multimodal image data is converted to the YUV color space, and the luminance channel is extracted. Each pixel value in the luminance channel represents the current luminance of the corresponding pixel. The purpose of converting the image from the original color space to the YUV color space and extracting the luminance channel separately is to separate the luminance information from the chrominance information of the image, so that subsequent enhancement processing only applies to the luminance component and avoids introducing chrominance distortion.

[0029] Next, the local brightness of each pixel's neighborhood is calculated based on the brightness channel. Specifically, for each pixel in the brightness channel, the average brightness is calculated within its local neighborhood window, centered on that pixel, and this average brightness is used as the local brightness estimate for the corresponding position of that pixel. As an optional implementation, the size of the local neighborhood window can be a 5×5 pixel rectangular window. It should be noted that the specific size of the neighborhood window is a conventional adjustment that can be made by those skilled in the art based on image resolution and enhancement effect requirements, and this specification does not limit it.

[0030] Then, the pixel-level exposure threshold is calculated based on the aforementioned local brightness. In one embodiment, the local brightness of each pixel can be directly used as the pixel-level exposure threshold for that pixel. This pixel-level exposure threshold is used to characterize the brightness of a local area of ​​the pixel, providing a criterion for subsequent brightness adjustment. When the local area is generally dark, the corresponding pixel-level exposure threshold is low, indicating that the area needs to be brightened; when the local area is generally bright, the corresponding pixel-level exposure threshold is high, indicating that the area needs to be darkened.

[0031] Then, based on the comparison between the pixel-level exposure judgment threshold and the current pixel brightness, the brightness adjustment amount of each pixel is determined by the symmetric brightness remapping function, and the brightness of each pixel is adjusted based on the brightness adjustment amount to obtain the adjusted brightness channel.

[0032] The symmetrical brightness remapping function adaptively calculates the brightness adjustment amount for each pixel based on the difference between its current brightness and the pixel-level exposure threshold. This moderately increases the brightness of overly dark areas and moderately suppresses the brightness of overly bright areas, achieving exposure balance. The symmetrical brightness remapping function can be implemented using a brightness remapping curve known in the art. As an example and not a limitation, it can be constructed based on an S-curve or a piecewise linear function. Its function form satisfies the following: when the current brightness of a pixel is lower than the pixel-level exposure threshold, the brightness adjustment amount is positive, and the pixel is brightened; when the current brightness of a pixel is higher than the pixel-level exposure threshold, the brightness adjustment amount is negative, and the pixel is darkened. The magnitude of the brightness adjustment amount is controlled by a preset adaptive gain coefficient and a cropping upper limit to avoid over-enhancing and introducing artifacts while enhancing image contrast. The typical range of the adaptive gain coefficient is 0.5 to 2.0, and the typical range of the cropping upper limit is 0 to 50 gray levels. Specific values ​​can be determined through offline calibration of the image enhancement effect on the production line.

[0033] Finally, for the visible light image, the adjusted luminance channel is merged with the original chroma channel and converted back to the original color space to obtain the visible light enhanced image. For the X-ray transmission image and the infrared thermal distribution image, both of which are grayscale images, their grayscale channels are directly used as the luminance channels to perform the above luminance adjustment, resulting in the X-ray transmission enhanced image and the infrared thermal distribution enhanced image. The above image enhancement processing is performed on the visible light image, the X-ray transmission enhanced image, and the infrared thermal distribution image respectively to obtain an enhanced image set containing the visible light enhanced image, the X-ray transmission enhanced image, and the infrared thermal distribution enhanced image.

[0034] It should be noted that the specific parameter settings for the above image enhancement processing, including but not limited to neighborhood window size, adaptive gain coefficient, and cropping upper limit, are all conventional choices that can be made by those skilled in the art based on the actual image quality and subsequent feature extraction accuracy requirements. The specific numerical values ​​or function forms mentioned in this specification are only optional implementation examples.

[0035] After acquiring the enhanced image set, image analysis is performed on each type of enhanced image in the set to extract packaging feature vectors. These packaging feature vectors include at least chip mount offset, void ratio, hotspot peak temperature, and temperature gradient. These four types of features characterize the physical packaging state of gallium nitride power devices from four dimensions: geometric location, internal defects, hotspot temperature, and thermal distribution uniformity, providing quantitative input for subsequent semi-physical mapping models.

[0036] The extraction methods for each type of feature are explained below:

[0037] Edge detection and template matching are performed on the visible light enhanced image to extract the chip patch offset.

[0038] Specifically, the edge contour of the chip is extracted. This edge detection can be implemented using edge detection algorithms known in the art; as an example and not a limitation, the Canny edge detection algorithm can be used. Subsequently, the extracted chip edge contour is matched with a preset standard chip placement template, and the offsets of the actual chip placement position relative to the standard placement position in the horizontal and vertical directions are calculated, denoted as the chip placement horizontal offset and chip placement vertical offset, respectively. These two offsets together constitute the chip placement offset, which is used to characterize the impact of placement accuracy on parasitic inductance in subsequent analyses.

[0039] Thresholding segmentation and connected component analysis are performed on X-ray enhanced images to extract the porosity.

[0040] Specifically, in X-ray fluoroscopic images, the grayscale values ​​of regions with voids and those without voids within the adhesive layer differ significantly. Void regions appear brighter in the image due to less X-ray attenuation, while void-free regions are relatively darker. Based on this imaging characteristic, threshold segmentation is performed on the X-ray fluoroscopic enhanced image to divide the image into void and non-void regions. This threshold segmentation can be implemented using known automatic threshold segmentation algorithms; as an example and not a limitation, the Otsu threshold segmentation algorithm can be used. After segmentation, the total area of ​​void regions is statistically analyzed using connected component analysis, and the percentage of the total void region area to the total area of ​​the chip adhesive layer is calculated. This percentage is the void ratio. The void ratio characterizes the degree of internal defects in the chip adhesive layer and is a key basis for subsequent evaluation of packaging thermal resistance and determining whether bonding process parameters need to be adjusted.

[0041] Temperature field analysis was performed on the enhanced infrared thermal distribution image to extract the peak temperature of hot spots.

[0042] Specifically, the grayscale or color value of each pixel in the infrared thermal distribution image corresponds to the temperature value at that location on the surface of the packaged device under test, and this mapping relationship is determined by the temperature calibration curve of the infrared thermal imager. Based on this temperature calibration curve, the value of each pixel in the enhanced infrared thermal distribution image is converted into the corresponding temperature value, obtaining the temperature field data of the packaged device surface. In the temperature field data, the global maximum temperature is identified; this maximum value is the hotspot peak temperature. The hotspot peak temperature characterizes the highest temperature point of the packaged device under powered-on operating conditions and is an important input feature for subsequently determining the excitation amplitude of the dynamic on-resistance test.

[0043] The temperature gradient is extracted based on the difference between the peak temperature of the hot spot and the average temperature of the packaging area.

[0044] Specifically, the average temperature of the encapsulation region is calculated by taking the arithmetic mean of the temperature values ​​of all pixels within the region. Then, the difference between the peak temperature of the hotspot and the average temperature of the encapsulation region is calculated. Finally, this difference is divided by the Euclidean distance between the hotspot location and the center of the encapsulation region to obtain the temperature gradient. The temperature gradient characterizes the non-uniformity of the temperature distribution on the surface of the encapsulated device. A larger temperature gradient indicates more prominent local hotspots and more uneven heat dissipation, making it an important input feature for determining the stress amplitude in subsequent aging tests.

[0045] The chip placement offset, void ratio, hotspot peak temperature, and temperature gradient mentioned above together constitute the package feature vector. This package feature vector serves as the input to the semi-physical mapping model in subsequent steps, driving the semi-physical mapping model to output a second set of package debugging parameters that match the current physical state of the package.

[0046] It should be noted that the specific algorithms involved in the above feature extraction process, including edge detection algorithms, threshold segmentation algorithms, connected component analysis methods, and temperature field analysis methods, are all mature technologies in the fields of image processing and infrared thermometry. Those skilled in the art can fully implement the corresponding feature extraction functions based on the teachings of this specification. The specific algorithm names mentioned in this specification are only optional implementation examples and do not constitute a limitation on the scope of protection of this invention.

[0047] A semi-physical mapping model is constructed, which consists of the physical prior structure of gallium nitride power devices, production line calibration coefficients based on historical sample sets, and a residual correction network.

[0048] The physical prior structure forms the skeleton of the semi-physical mapping model. The structure of its mapping function is determined by prior knowledge of the device physics and packaging physics of gallium nitride power devices, ensuring the physical interpretability of the debugging parameter generation process. In one embodiment, the physical prior structure includes the following four sub-mappings, each corresponding to the generation logic of a type of GaN-specific debugging parameter:

[0049] A monotonic mapping from chip surface offset to parasitic inductance to gate drive voltage spike compensation.

[0050] Understandably, in gallium nitride (GaN) power device packaging, chip misalignment alters the geometry of the power circuit, leading to changes in parasitic inductance. Under high-speed switching conditions (current change rates can reach the order of hundreds of amperes per nanosecond) in GaN devices, this increased parasitic inductance can trigger significant voltage spikes in the gate drive circuit, threatening the reliability of the gate oxide layer. Therefore, the greater the chip misalignment, the greater the parasitic inductance, and the greater the required compensation for gate drive voltage spikes; these three factors form a monotonically increasing mapping relationship.

[0051] Specifically, this sub-mapping first maps the chip mount offset to the loop parasitic inductance, and then maps the loop parasitic inductance to the gate drive voltage spike compensation. The mapping relationship between the chip mount offset and the loop parasitic inductance is determined by finite element electromagnetic simulation combined with production line measured data. This mapping can be approximated as a linear relationship within a small offset range, and can be described by a lookup table or a higher-order polynomial within a large offset range. The mapping relationship between the parasitic inductance and the gate drive voltage spike compensation is established through a voltage spike coupling coefficient, which is obtained by regression calibration of the gate voltage spike data measured on the production line.

[0052] Threshold triggering mapping from void ratio to thermal resistance to bonding process power-time parameters.

[0053] Understandably, the void area ratio in the chip bonding layer directly affects the package thermal resistance. A higher void ratio results in a smaller effective thermal conductivity area between the chip and the substrate, leading to greater package thermal resistance. For gallium nitride power devices, increased thermal resistance causes a rise in junction temperature during operation, accelerating performance degradation. Bonding process parameters, including bonding power and bonding time, directly impact the microstructure and reliability of the bonding interface: appropriately increasing bonding power or bonding time can, to some extent, compensate for the increased local thermal resistance caused by voids in the bonding layer, and improve local thermal conductivity by forming a more complete intermetallic compound layer at the bonding interface.

[0054] Specifically, this sub-mapping employs a threshold-triggered mechanism. When the void ratio is lower than or equal to a preset void ratio acceptable threshold, the bonding process power-time parameter maintains its nominal value without adjustment, thus avoiding unnecessary disturbances at already acceptable process points. When the void ratio is higher than the preset void ratio acceptable threshold, the bonding process power-time parameter is monotonically adjusted relative to its nominal value. It should be noted that the preset void ratio acceptable threshold can be set according to production line process specifications and product quality level requirements. As an optional implementation example, this threshold can be set to five percent.

[0055] The non-monotonic mapping from the peak temperature of the hot spot to the excitation amplitude of the dynamic on-resistance test.

[0056] Understandably, the dynamic on-resistance of gallium nitride (GaN) high electron mobility transistors (HEMTs) exhibits temperature dependence. This dynamic on-resistance not only changes monotonically with temperature but may also display non-monotonic characteristics within specific temperature ranges. This stems from the complex relationship between the charge / discharge time constant of the trap level in GaN HEMTs and temperature. Dynamic on-resistance testing requires setting the test excitation amplitude according to industry standards, including parameters such as supply voltage, load inductance, gate operating voltage, on-state pulse width, off-state pulse width, and the cumulative number of dual-pulse tests. Furthermore, the device's switching speed between on and off must meet specified conditions.

[0057] Specifically, this sub-mapping maps the hotspot peak temperature to the dynamic on-resistance test excitation amplitude. The mapping relationship is established through dual-pulse test calibration. Under different temperature conditions, GaN power devices are subjected to industry-standard dual-pulse tests, and the optimal test excitation amplitude for each temperature point is recorded, constructing the mapping relationship between temperature and test excitation amplitude. This mapping relationship can be stored in the form of a segmented lookup table to accurately reflect the full-temperature range characteristics of the GaN HEMT's dynamic on-resistance as a function of temperature.

[0058] A monotonic mapping from temperature gradient to stress amplitude in aging tests.

[0059] Understandably, the temperature gradient on the surface of a packaged device reflects the non-uniformity of the internal heat flux distribution. Areas with larger temperature gradients exhibit more significant thermal stress concentration, making them more prone to thermo-mechanical coupling failures during long-term service. Aging tests are used to accelerate the evaluation of device long-term reliability. The stress amplitude needs to be differentiated based on the device's thermal characteristics. Devices with larger temperature gradients should have higher applied aging test stress amplitudes to fully expose potential reliability weaknesses within a limited test time.

[0060] Specifically, this sub-mapping monotonically maps the temperature gradient to the stress amplitude of the aging test. The mapping relationship is determined through thermo-mechanical coupling simulation combined with accelerated aging data from the production line. This mapping exhibits a monotonically increasing structure, meaning that the greater the temperature gradient, the higher the stress amplitude of the aging test.

[0061] The debugging parameters output by the four sub-mappings mentioned above together constitute the first encapsulation debugging parameter set.

[0062] While the structural form of each sub-mapping in the physical prior structure is determined by the physical prior, the specific mapping coefficients involved need to be calibrated using historical production line data. This embodiment of the invention calibrates the production line calibration coefficients based on a historical sample set, which includes historical packaging image data from multiple batches, corresponding optimal debugging parameter records, and yield labels. During the calibration process, high-yield samples are assigned higher weights to ensure that the calibration results converge towards a high-yield process window. The calibration methods for the mapping coefficients corresponding to each sub-mapping are described below:

[0063] The mapping coefficient from chip mount offset to parasitic inductance is calibrated through regression calculation using finite element electromagnetic simulation combined with production line measured data from a historical sample set. Specifically, firstly, a finite element electromagnetic simulation tool (Q3D electromagnetic simulation software can be used as an example, not a limitation) is used to perform three-dimensional electromagnetic field simulation on the power circuit under different mount offset conditions to obtain simulation data on the variation of parasitic inductance of the circuit with the offset. Then, the simulation data is jointly regressed with the gate voltage spike data measured on the production line to calibrate the mapping coefficient from chip mount offset to parasitic inductance and the voltage spike coupling coefficient.

[0064] The mapping coefficient from void ratio to thermal resistance was calibrated using regression calculations, combining thermal simulation with accelerated aging data from a historical sample set. Specifically, firstly, thermal simulation tools (as an example and not a limitation, FloTHERM thermal simulation software can be used) were employed to simulate the thermal conduction of the chip bonding layer under different void area ratios, obtaining simulation data on the variation of package thermal resistance with void ratio. Then, the simulation data was jointly regressed with the measured data from high-temperature reverse-bias accelerated aging tests to calibrate the mapping coefficient from void ratio to thermal resistance.

[0065] The mapping relationship between the hotspot peak temperature and the dynamic on-resistance test excitation amplitude is established through a dual-pulse test based on the dynamic on-resistance test specification. Specifically, according to the industry standard's dynamic on-resistance test method for gallium nitride high electron mobility transistors, dual-pulse tests are performed under different temperature conditions to collect dynamic on-resistance data and optimal test excitation parameters at each temperature point, establishing a mapping relationship between the hotspot peak temperature and the dynamic on-resistance test excitation amplitude. This mapping relationship is stored in the form of a piecewise lookup table. During the inference phase, the corresponding test excitation amplitude is obtained by looking up the table and interpolating based on the currently input hotspot peak temperature.

[0066] The mapping coefficient between temperature gradient and aging test stress amplitude is calibrated using aging test data from historical sample sets through regression calculations. Specifically, based on historical aging test data from the production line, the temperature gradient of each sample is used as the independent variable, and the optimal aging test stress amplitude confirmed by process engineers is used as the dependent variable. The mapping coefficient between the two is calibrated through regression analysis.

[0067] While physical prior structures can capture the main physical mapping laws, the complexity of actual packaging processes makes it difficult for them to completely exhaust all influencing factors. To compensate for the residuals of physical prior structures under complex operating conditions, this embodiment of the invention introduces a residual correction network to extract deep features from multimodal image data and perform residual correction on the first packaging debugging parameter set output by the physical prior structure.

[0068] In one embodiment, the residual correction network comprises two parts: a feature extraction subnetwork and a residual mapping subnetwork.

[0069] The feature extraction subnetwork is a convolutional neural network (CNN), which takes multimodal image data as input and outputs a fixed-dimensional deep feature vector. The CNN automatically extracts deep image features related to encapsulation and debugging parameters from the multimodal image data through multiple layers of convolution, pooling, and nonlinear activation operations. These deep features may contain implicit information that the physical prior structure has not explicitly modeled, such as subtle differences in bonding wire morphology, spatial distribution patterns of voids in the adhesive layer, and morphological characteristics of infrared hot spots. As an optional implementation, the feature extraction subnetwork can be built using a residual network structure to balance feature extraction capability and training stability. It should be noted that the specific CNN structure (including network depth, kernel size, number of channels, etc.) is a conventional design choice that can be made by those skilled in the art based on computational resource constraints and feature extraction accuracy requirements, and this specification does not limit it to any specific type.

[0070] The residual mapping subnetwork takes the deep feature vector output by the feature extraction subnetwork as input and outputs a residual correction amount for the first encapsulation and debugging parameter set. The residual mapping subnetwork can be implemented using a multilayer perceptron structure, mapping the deep feature vector to a residual correction amount that matches the dimension of the first encapsulation and debugging parameter set. The residual correction amount characterizes the output deviation of the physical prior structure on the current input sample and is used to correct and compensate for the output of the physical prior structure.

[0071] The training objective of the residual correction network is to minimize the weighted mean square error between the sum of the physical prior structure output and the residual correction amount, and the optimal debugging parameters in the historical sample set. The weights are determined by the yield feedback index corresponding to each historical sample; samples with higher yields are assigned higher training weights, thus optimizing the network parameters towards a high-yield process window. After training, the residual correction network and the physical prior structure are integrated into a unified semi-physical mapping model.

[0072] The physical prior structure in the semi-physical mapping model is used to output the first set of encapsulated debugging parameters based on the sub-mapping. The multimodal image data is input into the residual correction network to output the residual correction amount. The sum of the two is the second set of encapsulated debugging parameters finally output by the semi-physical mapping model.

[0073] It should be noted that the specific simulation tool names, simulation parameter settings, regression algorithm selection, specific parameter configurations for double-pulse testing, and specific architecture designs of convolutional neural networks involved in the calibration process of the aforementioned production line calibration coefficients are all conventional choices that can be made by those skilled in the art based on actual engineering conditions. The specific tool names and algorithm names mentioned in this specification are only optional implementation examples and do not constitute a limitation on the scope of protection of this invention.

[0074] The packaged feature vector is input into the physical prior structure in the semi-physical mapping model. The physical prior structure receives the chip mount offset, void ratio, hotspot peak temperature, and temperature gradient from the packaged feature vector, processes them in parallel through four sub-mappings, and outputs the corresponding debugging parameters.

[0075] Specifically, the chip mount offset is monotonically mapped from chip mount offset to parasitic inductance to gate drive voltage spike compensation, outputting the gate drive voltage spike compensation. This mapping process, as described previously, first converts the chip mount offset into an estimated value of the loop parasitic inductance, and then converts the parasitic inductance into the gate drive voltage spike compensation using a voltage spike coupling coefficient. This compensation is used in subsequent gate drive tests to correct the setpoint of the gate drive voltage, thus offsetting the gate voltage spike effect caused by the increased parasitic inductance due to the mount offset.

[0076] The void ratio is mapped from void ratio to thermal resistance to bonding process power-time parameters via a threshold triggering process, outputting the bonding process power-time parameters. This mapping process first calculates the corresponding estimated package thermal resistance based on the void ratio, and then determines the adjustment direction and magnitude of the bonding process parameters based on the deviation of the package thermal resistance. The bonding process power-time parameters include two dimensions: bonding power and bonding time, used to set the process parameters of the ultrasonic bonding equipment during the bonding process.

[0077] The peak temperature of the hotspot is mapped non-monotonically to the dynamic on-resistance test excitation amplitude, outputting the dynamic on-resistance test excitation amplitude. This mapping process determines the corresponding dynamic on-resistance test excitation amplitude based on the input peak temperature of the hotspot by consulting a pre-built segmented lookup table. This dynamic on-resistance test excitation amplitude is used in subsequent dynamic on-resistance test steps to set test parameters such as the power supply voltage, load inductance, gate operating voltage, and pulse width for the dual-pulse test.

[0078] The temperature gradient is monotonically mapped to the aging test stress amplitude, outputting the aging test stress amplitude. This mapping process calculates the corresponding aging test stress amplitude based on the temperature gradient value using calibrated mapping coefficients. A larger aging test stress amplitude indicates stronger aging stress applied to the device, which is used to accelerate the exposure of potential reliability defects in the device during the aging test process.

[0079] The gate drive voltage spike compensation, bonding process power-time parameters, dynamic on-resistance test excitation amplitude, and aging test stress amplitude output from the above four sub-mappings together constitute the first package debugging parameter set.

[0080] During the process of outputting the first set of packaging debugging parameters in the physical prior structure, a void-free adjustment constraint is applied to the bonding process power-time parameters.

[0081] Specifically, the void-free adjustment constraint determines whether the current input void rate exceeds a preset void rate acceptable threshold. If the void rate is less than or equal to the preset void rate acceptable threshold, it indicates that the degree of internal defects in the chip bonding layer of the current device is within an acceptable range, and the bonding process power-time parameters remain at their nominal values ​​without being adjusted in the opposite direction due to changes in the void rate. If the void rate exceeds the preset void rate acceptable threshold, it indicates that the degree of internal defects in the chip bonding layer of the current device exceeds an acceptable range, and the bonding process power-time parameters are monotonically adjusted relative to their nominal values, with the adjustment direction being monotonically increasing. That is, both the bonding power and bonding time are adjusted in an increasing direction to partially compensate for the increased local thermal resistance caused by voids in the bonding layer by improving the bonding interface quality.

[0082] The purpose of void non-reverse adjustment constraint is to avoid introducing additional process disturbances due to unnecessary parameter adjustments when the device packaging quality has met the process specifications. Parameter adjustment is only triggered when the packaging quality deviates from the qualified range, and the adjustment direction is consistent with physical laws. The higher the void ratio, the more sufficient the intermetallic compound needs to be formed at the bonding interface to improve local thermal conductivity.

[0083] In parallel with the processing flow of the physical prior structure, the multimodal image data is input into the residual correction network in the semi-physical mapping model. The feature extraction subnetwork of the residual correction network performs multi-layer convolution and nonlinear transformations on the input multimodal image data to extract deep image features related to the encapsulation and debugging parameters, and outputs a deep feature vector. This deep feature vector is then input into the residual mapping subnetwork, and after multi-layer fully connected mapping, outputs the residual correction amount.

[0084] The dimension of the residual correction amount is consistent with the dimension of the first package debugging parameter set, that is, it is a four-dimensional vector, which corresponds to the residual correction amount of the gate drive voltage spike compensation amount, the residual correction amount of the bonding process power-time parameter, the residual correction amount of the dynamic on-resistance test excitation amplitude, and the residual correction amount of the aging test stress amplitude, respectively.

[0085] The residual correction network captures and quantifies implicit factors that may be missed by the physical prior structure. These implicit factors include, for example, subtle geometric differences in the bonding wire morphology, the spatial distribution of voids in the adhesive layer, the shape characteristics of infrared hotspots, and correlation patterns between multimodal images that are not explicitly modeled by the physical prior structure. The residual correction value characterizes the additional influence of these implicit factors on the packaging and debugging parameters, and is used to refine the output of the physical prior structure.

[0086] The first set of package debugging parameters is added element-wise to the residual correction amount to obtain the second set of package debugging parameters.

[0087] Specifically, the gate drive voltage spike compensation amount output by the physical prior structure is added to the residual correction amount corresponding to the gate drive voltage spike compensation amount in the residual correction network to obtain the final gate drive voltage spike compensation amount; the bonding process power-time parameters output by the physical prior structure are added to the corresponding residual correction amount to obtain the final bonding process power-time parameters; the dynamic on-resistance test excitation amplitude output by the physical prior structure is added to the corresponding residual correction amount to obtain the final dynamic on-resistance test excitation amplitude; and the aging test stress amplitude output by the physical prior structure is added to the corresponding residual correction amount to obtain the final aging test stress amplitude.

[0088] The above four final debugging parameters together constitute the second package debugging parameter set. The second package debugging parameter set includes at least the gate drive voltage spike compensation amount, bonding process power-time parameters, dynamic on-resistance test excitation amplitude, and aging test stress amplitude.

[0089] Through the dual-channel synthesis method of the above-mentioned physical prior structure output and residual correction network compensation, the second package debugging parameter set not only retains the benchmark value derived from the physical laws of gallium nitride devices, but also integrates the complex working condition correction amount learned from multimodal image data, thus taking into account both the physical interpretability of parameter generation and the actual fitting accuracy.

[0090] After synthesizing the second set of packaging debugging parameters, boundary constraints are applied to each parameter in the set to ensure that the gate drive voltage spike compensation, bonding process power-time parameters, dynamic on-resistance test excitation amplitude, and aging test stress amplitude all fall within the preset physical feasible range.

[0091] The purpose of applying boundary constraints is to ensure that the debugging parameters output by the semi-physical mapping model are within the executable range of each piece of equipment on the packaging production line, avoiding equipment malfunctions or device damage due to out-of-bounds model output parameters. For example, the bonding power in the bonding process power-time parameters cannot exceed the maximum output power of the bonding equipment, nor can it be lower than the minimum power required to form a reliable bonding interface; the bonding time cannot exceed the maximum time allowed by the production line cycle time, nor can it be shorter than the minimum time required to form a sufficient intermetallic compound. Similarly, the supply voltage in the dynamic on-resistance test excitation amplitude must be within the safe output range of the test equipment, and the aging test stress amplitude must be within a reasonable range that the device can withstand and that can effectively accelerate the aging process to expose defects.

[0092] In one embodiment, for each parameter in the second packaging debugging parameter set, it is compared with the corresponding upper and lower bounds of the physical feasible region: if the value of the parameter is greater than the upper bound of the physical feasible region, it is truncated to the upper bound value; if the value of the parameter is less than the lower bound of the physical feasible region, it is truncated to the lower bound value; if the value of the parameter is within the physical feasible region, it remains unchanged. After boundary constraint processing, all parameters in the second packaging debugging parameter set meet the actual executable conditions of the production line equipment.

[0093] The physical feasible region is determined by the physical prior structure.

[0094] Specifically, in constructing each sub-mapping, the physical prior structure not only determines the structural form and mapping coefficients of the mapping function, but also, based on the physical characteristics of gallium nitride power devices and the specifications of the packaging production line equipment, determines the reasonable range of values ​​for each debugging parameter. This reasonable range is the physical feasible region, which means that the debugging parameters within this range can meet the effectiveness requirements of testing and process without exceeding the physical limits of the device or the execution capability of the equipment.

[0095] The upper and lower bounds of each debugging parameter in the physical feasible domain can be determined based on the following methods: the feasible domain of the gate drive voltage spike compensation is jointly determined by the gate withstand voltage specification of the gallium nitride high electron mobility transistor and the safe operating range of the drive circuit; the feasible domain of the bonding process power-time parameter is jointly determined by the rated power range, rated time range of the bonding equipment, and the process window for bonding interface reliability; the feasible domain of the dynamic on-resistance test excitation amplitude is jointly determined by the test parameter setting range specified by industry standards and the output capability of the test equipment; the feasible domain of the aging test stress amplitude is jointly determined by the safe operating area of ​​the device and the recommended stress range of the accelerated aging test standard.

[0096] It should be noted that the specific numerical range of the physically feasible domain is a conventional engineering parameter that can be determined by those skilled in the art based on the actual gallium nitride power device model, packaging production line equipment specifications and process specifications used. This specification does not list the specific values ​​of the feasible domain for each parameter one by one. The above description of the method for determining the feasible domain is sufficient to enable those skilled in the art to implement this invention.

[0097] The second set of packaging and debugging parameters is sent to the packaging production line to adaptively adjust the packaging and debugging parameters of the next batch of gallium nitride power devices across batches.

[0098] Specifically, the gate drive voltage spike compensation value is sent to the gate drive test equipment to compensate and correct the gate voltage setting value in the gate drive test of subsequent batches of devices; the bonding process power-time parameters are sent to the bonding equipment to set the ultrasonic power and bonding time of the bonding process for the next batch of devices; the dynamic on-resistance test excitation amplitude is sent to the dynamic on-resistance test equipment to set the various excitation parameters for the double-pulse test of the next batch of devices; and the aging test stress amplitude is sent to the aging test equipment to set the stress conditions for the aging test of the next batch of devices.

[0099] Each device performs corresponding debugging or testing actions on the next batch of gallium nitride power devices to be packaged, based on the received debugging parameters. Since the debugging parameters for each batch of devices are adaptively generated based on the multimodal image data of the previous batch of devices through a semi-physical mapping model, the debugging parameters for different batches are dynamically adjusted as the physical state of the packaged device changes, thus achieving cross-batch adaptive debugging.

[0100] After the debugging process for the next batch of devices is completed, the multimodal image acquisition process is restarted to acquire multimodal image data of the packaged objects in this batch. At the same time, test result data for this batch of devices is collected, including pass or fail records for dynamic on-resistance testing and aging testing.

[0101] Based on the above test results, the yield feedback index for the current batch is calculated. This yield feedback index is used to quantitatively evaluate the actual effect of the current batch's debugging parameters and is a key criterion for determining whether to trigger iterative updates to the model parameters.

[0102] In one embodiment, the yield feedback index is calculated as follows: the pass rate of the current batch of devices under the dynamic on-resistance test excitation amplitude is obtained and recorded as the dynamic on-resistance test pass rate; the pass rate of the current batch of devices under the aging test stress amplitude is obtained and recorded as the aging test pass rate; the dynamic on-resistance test pass rate and the aging test pass rate are weighted and summed according to preset weights to obtain the yield feedback index.

[0103] As an optional implementation example, the weight of the dynamic on-resistance test pass rate can be set to 0.6, and the weight of the aging test pass rate can be set to 0.4. It should be noted that the above weight values ​​are only optional examples. Those skilled in the art can adjust the weight values ​​according to factors such as the importance attached to different test items in the actual production line and the correlation between each test item and the final product quality. The specific values ​​mentioned above do not constitute a limitation on the scope of protection of this invention. Furthermore, if the yield feedback index is lower than the preset yield threshold, the production line calibration coefficients and the network parameters of the residual correction network are iteratively updated based on the historical sample set until the yield threshold is reached. The weight of the dynamic on-resistance test pass rate is greater than that of the aging test pass rate because the dynamic on-resistance test more directly reflects the switching performance degradation (charge trapping effect) of GaN HEMTs, while the aging test reflects long-term reliability degradation. The former is more sensitive to short-term feedback from production line debugging parameters.

[0104] After calculating the yield feedback index for the current batch, this index is compared with a preset yield threshold. If the yield feedback index is greater than or equal to the preset yield threshold, it indicates that the parameters of the current semi-physical mapping model can effectively guide the adaptive generation of packaging debugging parameters, the production line debugging effect meets the requirements, and the existing model parameters can be maintained to continue running.

[0105] If the yield feedback index is lower than the preset yield threshold, it indicates that there is a deviation between the output of the current semi-physical mapping model and the optimal debugging parameters, and it is necessary to trigger the iterative update of the model parameters to adapt to the current process status of the production line.

[0106] The iterative update of model parameters includes updating the production line calibration coefficients and updating the network parameters of the residual correction network.

[0107] For updating the production line calibration coefficients, in one embodiment, a recursive update strategy with a forgetting factor is adopted.

[0108] Specifically, the multimodal image data of the current batch, the packaging feature vector, and the optimal debugging parameters confirmed by process engineers or determined through yield data backtesting are added as new samples to the historical sample set. Based on the expanded historical sample set, the mapping coefficients of each sub-mapping in the physical prior structure are recalibrated. During the calibration process, a forgetting factor is introduced to weight the historical samples, giving recent samples a higher contribution weight in the calibration, while the contribution weight of older samples decays over time, thus enabling the production line calibration coefficients to adapt to the slow drift of the production line process. As an optional implementation, the forgetting factor can be set to 0.95 to apply a moderate weight decay to early samples in each update cycle. As an optional implementation, the batch update of the production line calibration coefficients can be set to be performed once after every five batches of packaging are completed, balancing computational overhead and the timeliness of model updates.

[0109] In one embodiment, the network parameters of the residual correction network are updated using an online incremental learning method.

[0110] Specifically, based on the newly added sample data in the current batch, the network parameters are updated through several steps of gradient descent according to the training loss function of the residual correction network. A relatively small learning rate can be used during the update process to avoid drastic fluctuations in network parameters that could lead to unstable model output. The incrementally updated residual correction network can gradually absorb newly emerging image feature patterns on the production line, continuously improving the accuracy of residual correction.

[0111] The combined iterative strategy of recursive updating of production line calibration coefficients and incremental updating of residual correction networks enables the semi-physical mapping model to form a complete closed loop encompassing image acquisition, feature extraction, parameter generation, execution, yield feedback, and model updating. As production line batches accumulate, the semi-physical mapping model continuously absorbs new production line data, gradually converging to the optimal parameter configuration adapted to the current production line process state, thereby achieving adaptive and continuous optimization of gallium nitride power device packaging and debugging parameters. This closed-loop iterative process continues until the yield feedback index reaches or exceeds the preset yield threshold.

[0112] It should be noted that the specific forgetting factor values, batch update intervals, batch number, learning rate, and other parameters involved in the above iterative update process are all conventional engineering choices that can be made by those skilled in the art based on the production line operation rhythm, process drift speed, and computing resource conditions. The specific values ​​mentioned in this specification are only optional implementation examples and do not constitute a limitation on the scope of protection of this invention.

Claims

1. A method for adaptive packaging and debugging parameters of a gallium nitride chip, characterized in that, The method includes: Acquire multimodal image data from the packaging production line of gallium nitride power devices; Image processing and feature extraction are performed on multimodal image data to obtain packaging feature vectors that include at least chip patch offset, void ratio, hot spot peak temperature and temperature gradient; Input the package feature vector into the semi-physical mapping model and output a second set of package debugging parameters, including at least the gate drive voltage spike compensation amount, bonding process power-time parameters, dynamic on-resistance test excitation amplitude, and aging test stress amplitude. The semi-physical mapping model consists of the physical prior structure of gallium nitride power devices, production line calibration coefficients based on historical sample sets, and a residual correction network. The physical prior structure outputs the first set of packaging debugging parameters based on sub-mapping, and the residual correction network outputs the residual correction amount. The sum of the first set of packaging debugging parameters and the residual correction amount is used as the second set of packaging debugging parameters. The second set of packaging debugging parameters is sent to the packaging production line to adaptively adjust the packaging debugging parameters of the next batch of gallium nitride power devices across batches. After the debugging action is performed, multimodal image data of the packaged object is collected again and the yield feedback index is calculated. If the yield feedback index is lower than the preset yield threshold, the production line calibration coefficient and the network parameters of the residual correction network are iteratively updated based on the historical sample set until the yield threshold is reached.

2. The method according to claim 1, characterized in that, The image processing and feature extraction include image enhancement processing of multimodal image data to obtain an enhanced image set, image analysis of the enhanced image set, and extraction of encapsulated feature vectors.

3. The method according to claim 2, characterized in that, The image enhancement process includes: Multimodal image data is converted to the YUV color space to extract the luminance channel. The pixel value of each pixel in the luminance channel is the current luminance of the corresponding pixel. The local brightness of each pixel's neighborhood is calculated based on the brightness channel, and the pixel-level exposure judgment threshold is calculated based on the local brightness. Based on the comparison between the pixel-level exposure judgment threshold and the current pixel brightness, the brightness adjustment amount of each pixel is determined by the symmetric brightness remapping function, and the local brightness is adjusted based on the brightness adjustment amount to obtain an enhanced image set including visible light enhanced image, X-ray perspective enhanced image and infrared thermal distribution enhanced image.

4. The method according to claim 2, characterized in that, The image analysis includes: Perform edge detection and template matching on the visible light enhanced image to extract the chip patch offset; Thresholding segmentation and connected component analysis are performed on X-ray enhanced images to extract the porosity. Temperature field analysis was performed on the enhanced infrared thermal distribution image to extract the peak temperature of hot spots; The temperature gradient is extracted based on the difference between the peak temperature of the hot spot and the average temperature of the packaging area.

5. The method according to claim 1, characterized in that, The physical prior structure includes the following sub-mappings: Monotonic mapping from chip surface offset to parasitic inductance to gate drive voltage spike compensation; Threshold triggering mapping from void ratio to thermal resistance to bonding process power-time parameters; Non-monotonic mapping from hotspot peak temperature to dynamic on-resistance test excitation amplitude; A monotonic mapping from temperature gradient to stress amplitude in aging tests.

6. The method according to claim 1, characterized in that, The calibration method for the production line calibration coefficient includes: By combining finite element electromagnetic simulation with production line measured data from historical sample sets, the mapping coefficient from chip mounting offset to parasitic inductance is calculated through regression. By combining thermal simulation with accelerated aging data from historical sample sets, the mapping coefficient from void ratio to thermal resistance is calculated through regression. Based on the dynamic on-resistance test specification, a mapping relationship between the hotspot peak temperature and the excitation amplitude of the dynamic on-resistance test is established through dual-pulse testing. Using aging test data from a historical sample set, the mapping coefficient from temperature gradient to aging test stress amplitude is calculated through regression.

7. The method according to claim 1, characterized in that, The residual correction network includes a feature extraction subnetwork and a residual mapping subnetwork: The feature extraction subnetwork is a convolutional neural network that takes multimodal image data as input and outputs deep features. The residual mapping subnetwork takes deep features as input and outputs the residual correction amount for the first encapsulation debugging parameter set; The residual correction network is trained using a weighted mean square error loss based on yield feedback metrics.

8. The method according to claim 1, characterized in that, Also includes: A void-free adjustment constraint is applied to the bonding process power-time parameter in the first packaging debugging parameter set. When the void rate is greater than the preset void rate threshold, the adjustment direction of the bonding process power-time parameter is monotonically increasing. Boundary constraints are applied to each parameter in the second package debugging parameter set to ensure that the gate drive voltage spike compensation, bonding process power-time parameters, dynamic on-resistance test excitation amplitude, and aging test stress amplitude all fall within the preset physical feasible domain. The physical feasible region is determined by the physical prior structure.

9. The method according to claim 1, characterized in that, The acquisition methods for the multimodal image data include: Visible light images are captured using industrial cameras; Infrared thermal distribution images are acquired using an infrared thermal imager; X-ray images are acquired using X-ray fluoroscopy equipment.

10. The method according to claim 1, characterized in that, The yield feedback index is calculated by weighting the current batch's pass rate under dynamic on-resistance test excitation amplitude and the pass rate under aging test stress amplitude according to preset weights.

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