Optoelectronic co-packaging structure and method of manufacturing the same

Abstract

The photoelectric co-encapsulation structure and the preparation method thereof provided by the embodiment of the present application relate to the chip packaging technical field, and the photoelectric co-encapsulation structure comprises a carrier plate, a first rewiring layer, an adapter plate, an electric chip, a plastic encapsulation layer, a second rewiring layer, a light shielding layer, an optical chip, a plurality of conductive connecting columns and a plurality of optical waveguides. Compared with the prior art, the embodiment of the present application realizes high-density integrated packaging by the integrated mode of the electric chip and the optical chip, effectively reduces the chip size, reduces the packaging area, and solves the problem that the traditional photoelectric integrated structure is difficult to meet the high-density integrated packaging demand. Meanwhile, the multiple optical waveguides are adopted to realize the simultaneous coupling interconnection of multiple optical signals, so that more signal interconnection channels are provided, and the transmission performance is improved. Moreover, the light shielding layer formed by the gluing photoetching process is used to shield the surrounding of the optical port structure, so that the interference of the external environment on the optical signal is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to an optoelectronic co-packaging structure and its preparation method. Background Technology

[0002] With the rapid development of fields such as artificial intelligence, the Internet of Things, and telemedicine, global data traffic is experiencing explosive growth, placing higher demands on the transmission rate, latency, and energy efficiency of circuits. Traditional electrical chips, connected via circuits, suffer from latency and loss issues, failing to meet these requirements. To address this problem, the industry generally believes that introducing optical technology into semiconductor manufacturing processes can reduce chip size, lower costs and power consumption, while improving reliability. By integrating electrical and optical chips, the flexibility of electrical chips and the low latency and low loss advantages of optical chips can be combined, thereby improving overall performance.

[0003] However, existing optoelectronic integrated semiconductor packaging structures still have some problems. Traditional optoelectronic integrated structures typically bond optical and electrical integrated chips directly onto a carrier board and connect them through wire bonding or inverted bonding. This method is difficult to meet the requirements of high-density integrated packaging. Summary of the Invention

[0004] The purpose of this invention is to provide an optoelectronic co-packaging structure and its fabrication method, which integrates electrical and optical chips, achieving high-density integrated packaging, effectively reducing chip size and packaging area. It also enables simultaneous coupling and interconnection of multiple optical signals, providing more signal interconnection channels. Furthermore, it effectively mitigates interference from the external environment on the optical signals.

[0005] In one aspect, embodiments of the present invention provide an optoelectronic co-packaging structure, comprising: Carrier plate; The first wiring layer is located on the front side of the carrier board; The adapter board is mounted on the first wiring layer from the front. The electrical chip is mounted on the first wiring layer and spaced apart from the adapter board. A molding layer is disposed on the first rewiring layer and covers the sidewalls and front side of the adapter board and the electrical chip; The second wiring layer is disposed on the molding layer and is electrically connected to the adapter board; Multiple conductive connection posts are disposed on the second rewiring layer and extend in a direction away from the carrier board; Multiple optical waveguides are mounted on the back side of the second wiring layer; A light-shielding layer is disposed on the second redistribution layer and the optical waveguide, and exposes a plurality of conductive connecting posts and a portion of the front side of the plurality of optical waveguides; The optical chip is mounted on the conductive connecting post on the front side and is electrically connected to the second redistribution layer through the conductive connecting post. The front side of the optical chip has multiple photosensitive areas, and the multiple photosensitive areas are optically coupled to a portion of the front side of the multiple optical waveguides.

[0006] In an optional embodiment, the plurality of optical waveguides include a first waveguide and a second waveguide spaced apart. The back side of the first waveguide is attached to the second redistribution layer. A first coupling port is provided on the front side of the first waveguide. A second coupling port is provided on the sidewall of the first waveguide. The first coupling port and the second coupling port are exposed in the light-shielding layer. The first coupling port is optically coupled to the photosensitive area. The back of the second waveguide is mounted on the second rewiring layer, and the front of the second waveguide is provided with a third coupling port and a fourth coupling port. The third coupling port and the fourth coupling port are exposed on the light-shielding layer, and the third coupling port is optically coupled to the photosensitive area.

[0007] In an optional embodiment, the middle portion of the second waveguide protrudes in a direction away from the carrier plate to form a boss portion, the fourth coupling port is disposed on the boss portion, and the third coupling port is offset from the boss portion.

[0008] In an optional embodiment, the height of the fourth coupling port relative to the second rewiring layer is less than or equal to the height of the side surface of the light-shielding layer away from the carrier plate relative to the second rewiring layer.

[0009] In an optional embodiment, the front side of the optical chip is attached to the surface of the light-shielding layer away from the carrier, so that a photosensitive sealing cavity is formed between the photosensitive area and the corresponding portion of the front side of the optical waveguide.

[0010] In an optional embodiment, the front side of the optical chip is further provided with conductive bumps, which are spaced apart from the photosensitive area. The conductive connecting post is recessed in the light-shielding layer, and the conductive bumps are correspondingly connected to the conductive connecting post.

[0011] In an optional embodiment, a third wiring layer is provided on the back side of the carrier board, and solder balls are provided on the side of the third wiring layer away from the carrier board.

[0012] In an optional embodiment, a first conductive post is further disposed through the carrier board, and the third wiring layer is electrically connected to the first wiring layer through the first conductive post.

[0013] In an optional embodiment, the front side of the electrical chip is provided with a flip-chip bump, the front side of the adapter board is provided with an adapter bump, both the flip-chip bump and the adapter bump are connected to the first rewiring layer, the back side of the electrical chip and the back side of the adapter board are exposed to the molding layer, and the second rewiring layer covers the back side of the adapter board.

[0014] In an optional embodiment, a second conductive post is further disposed through the adapter plate, and the first rewiring layer is electrically connected to the second rewiring layer through the second conductive post and the adapter bump.

[0015] In another aspect, embodiments of the present invention provide a method for preparing an optoelectronic co-packaging structure, comprising: A carrier board is provided, wherein a first wiring layer is provided on the front side of the carrier board; The front side of the adapter board is mounted on the first wiring layer; The front side of the electrical chip is mounted on the first wiring layer; A molding compound is formed on the first redistribution layer, wherein the molding compound covers the sidewalls and front side of the adapter board and the electrical chip; A second wiring layer is formed on the molding layer, wherein the second wiring layer is electrically connected to the adapter board; Multiple conductive connection pillars are formed on the second rewiring layer; Multiple optical waveguides are back-mounted onto the second wiring layer; A light-shielding layer is formed on the second redistribution layer and the optical waveguide, wherein the light-shielding layer exposes a portion of the front side of the plurality of conductive connection posts and the plurality of optical waveguides; The front side of the optical chip is mounted on the conductive connection post, wherein the optical chip is electrically connected to the second redistribution layer through the conductive connection post, and the front side of the optical chip has multiple photosensitive areas, and the multiple photosensitive areas are optically coupled to a portion of the front side of the multiple optical waveguides respectively.

[0016] In an optional implementation, prior to the step of forming a plurality of conductive connection posts on the second redistribution layer, the method further includes: A third wiring layer is formed on the back side of the carrier board; Solder balls are formed on the third wiring layer.

[0017] The beneficial effects of the embodiments of the present invention include: The optoelectronic co-packaging structure and its fabrication method provided in this invention have a first wiring layer on the front side of a carrier substrate. An adapter board and an electronic chip are mounted on and electrically connected to the first wiring layer. A molding compound covers the adapter board and the electronic chip. A second wiring layer is disposed on the molding compound and electrically connected to the adapter board. Multiple conductive pillars are disposed on the second wiring layer and extend away from the carrier substrate. The back sides of multiple optical waveguides are all mounted on the second wiring layer. A light-shielding layer is disposed on the second wiring layer and the optical waveguides, exposing a portion of the front side of the conductive pillars and the optical waveguides. The optical chip is mounted on the conductive pillars and electrically connected to the second wiring layer through the conductive pillars. Multiple photosensitive areas of the optical chip are optically coupled to portions of the front side of the multiple optical waveguides.

[0018] Compared to existing technologies, this invention achieves high-density integrated packaging by integrating electrical and optical chips, effectively reducing chip size and packaging area, and solving the problem that traditional optoelectronic integrated structures cannot meet the requirements of high-density integrated packaging. Simultaneously, multiple optical waveguides are used to couple and interconnect multiple optical signals, thereby providing more signal interconnection channels and improving transmission performance. Furthermore, a light-shielding layer formed by photolithography effectively mitigates interference from the external environment around the optical port structure. In addition, the optoelectronic co-packaging structure of this invention achieves high-density integration, reduces system and device power consumption, improves reliability, meets the demands of the explosive growth of global data traffic, and provides a new solution for the further development of optoelectronic integration technology. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of an optoelectronic co-packaging structure provided in an embodiment of the present invention; Figures 2 to 11 This is a schematic diagram of the process flow for the fabrication method of the optoelectronic co-packaging structure provided in an embodiment of the present invention.

[0021] Icons: 100 - Optoelectronic co-package structure; 110 - Carrier board; 111 - First redistribution layer; 112 - Third redistribution layer; 113 - Solder ball; 114 - First conductive post; 120 - Adapter board; 121 - Adapter bump; 122 - Second conductive post; 130 - Electrical chip; 131 - Flip chip bump; 140 - Molding layer; 141 - Second redistribution layer; 150 - Light-shielding layer; 160 - Optical chip; 161 - Photosensitive area; 162 - Photosensitive sealing cavity; 163 - Conductive bump; 170 - Conductive connection post; 180 - First optical waveguide; 181 - First coupling port; 182 - Second coupling port; 190 - Second optical waveguide; 191 - Third coupling port; 192 - Fourth coupling port; 200 - Temporary substrate. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0026] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0027] As disclosed in the background section, existing optoelectronic integrated semiconductor packaging structures still have some problems. Traditional optoelectronic integrated structures typically bond optical and electrical integrated chips directly to a carrier board, connecting them via wire bonding or inverted bonding. This method is difficult to meet the requirements of high-density integrated packaging. Furthermore, traditional optoelectronic integrated structures can usually only achieve single-channel optical signal coupling and interconnection, resulting in fewer signal interconnection channels and lower transmission efficiency. Moreover, the coupling ports of the optical chips are directly exposed, making effective protection difficult and prone to damage. Additionally, external environmental interference significantly affects the optical signal, impacting transmission performance.

[0028] Therefore, a novel optoelectronic co-packaging structure is urgently needed to address the aforementioned issues. This structure should enable high-density integrated packaging, reduce system and device power consumption, improve reliability, and meet the demands of the explosive growth in global data traffic. Furthermore, it is necessary to consider how to form a molding compound on the surface of the optoelectronic chip while avoiding damage to the optical coupling interface to ensure the practical use of the optoelectronic chip. Solving these problems will help promote the further development of optoelectronic integration technology and provide new solutions for high-performance, low-power integrated circuit packaging.

[0029] Furthermore, to address the aforementioned problems, embodiments of the present invention provide an optoelectronic co-packaging structure and its fabrication method. It should be noted that, unless otherwise specified, features in the embodiments of the present invention can be combined with each other.

[0030] See Figure 1 This invention provides an optoelectronic co-packaging structure 100 that integrates an electrical chip 130 and an optical chip 160, achieving high-density integrated packaging, effectively reducing chip size and packaging area. It also enables simultaneous coupling and interconnection of multiple optical signals, providing more signal interconnection channels. Furthermore, it effectively mitigates interference from the external environment on the optical signals.

[0031] The optoelectronic co-packaging structure 100 provided in this embodiment of the invention includes a carrier board 110, a first rewiring layer 111, an adapter board 120, an electrical chip 130, a molding compound 140, a second rewiring layer 141, a light-shielding layer 150, an optical chip 160, multiple conductive connecting posts 170, and multiple optical waveguides. The first rewiring layer 111 is disposed on the front side of the carrier board 110. The front side of the adapter board 120 is mounted on the first rewiring layer 111. The front side of the electrical chip 130 is mounted on the first rewiring layer 111 and spaced apart from the adapter board 120. The molding compound 140 is disposed on the first rewiring layer 111 and covers the sidewalls and front side of the adapter board 120 and the electrical chip 130. The second rewiring layer 141 is disposed on the molding compound 140 and is electrically connected to the adapter board 120. Multiple conductive connecting posts 170 are disposed on the second rewiring layer 141 and extend in a direction away from the carrier board 110. The back sides of multiple optical waveguides are all mounted on the second wiring layer 141. A light-shielding layer 150 is disposed on the second wiring layer 141 and the optical waveguides, exposing multiple conductive connecting posts 170 and portions of the front sides of the multiple optical waveguides. The front side of the optical chip 160 is mounted on the conductive connecting posts 170 and electrically connected to the second wiring layer 141 through the conductive connecting posts 170. The front side of the optical chip 160 has multiple photosensitive areas 161, and the multiple photosensitive areas 161 are optically coupled to portions of the front sides of the multiple optical waveguides.

[0032] It should be noted that the embodiments of the present invention achieve high-density integrated packaging by integrating the electrical chip 130 and the optical chip 160, effectively reducing chip size and packaging area, and solving the problem that traditional optoelectronic integrated structures cannot meet the requirements of high-density integrated packaging. Simultaneously, multiple optical waveguides are used to achieve simultaneous coupling and interconnection of multiple optical signals, thereby providing more signal interconnection channels and improving transmission performance. Furthermore, the light-shielding layer 150, formed by photolithography, effectively blocks interference from the external environment on the optical signal and provides good protection for the optical coupling port. In addition, the optoelectronic co-packaging structure 100 of the present invention achieves high-density integration, reduces system and device power consumption, improves reliability, meets the needs of the explosive growth of global data traffic, and provides a new solution for the further development of optoelectronic integration technology.

[0033] In some embodiments, the plurality of optical waveguides include first waveguides and second waveguides spaced apart. The back side of the first waveguide is mounted on the second redistribution layer 141. A first coupling port 181 is provided on the front side of the first waveguide, and a second coupling port 182 is provided on the sidewall of the first waveguide. The first coupling port 181 and the second coupling port 182 are exposed on the light-shielding layer 150. The first coupling port 181 is optically coupled to the photosensitive area 161. Specifically, the first coupling port 181 is located on the front side of the first optical waveguide 180 and is exposed on the side of the light-shielding layer 150 away from the carrier plate 110. The second coupling port 182 is located on the sidewall of the first optical waveguide 180 and is exposed on the side of the light-shielding layer 150. Neither the first coupling port 181 nor the second coupling port 182 is blocked by the light-shielding layer 150. The back of the second waveguide is mounted on the second rewiring layer 141. The front of the second waveguide has a third coupling port 191 and a fourth coupling port 192, both exposed on the light-shielding layer 150. The third coupling port 191 is optically coupled to the photosensitive area 161. Specifically, both the third coupling port 191 and the fourth coupling port 192 are located on the front of the second waveguide and are exposed on the side of the light-shielding layer 150 away from the carrier plate 110, thus not being obstructed by the light-shielding layer 150.

[0034] It should be noted that both the first and second waveguides are made of waveguide materials, enabling the transmission of optical signals. There can be one or more first and second waveguides; this invention will be described in detail using two first waveguides and one second waveguide as an example. Furthermore, there can be two optical chips 160. Each optical chip 160 has two photosensitive areas 161 on its front side. One photosensitive area 161 is coupled to the first coupling port 181 of the first waveguide, and the other photosensitive area 161 is coupled to the third coupling port 191 of the second waveguide. The second coupling port 182 and the fourth coupling port 192 are both used for coupling with external fiber optic modules. By setting up the first and second waveguides, multiple optical signals can be transmitted, improving transmission performance. It should be noted that the two optical chips 160 can be interconnected via the second waveguide.

[0035] In some embodiments, the middle portion of the second waveguide protrudes in a direction away from the carrier plate 110 to form a boss portion, and the fourth coupling port 192 is disposed on the boss portion, while the third coupling port 191 is offset from the boss portion. Specifically, the first waveguide is rectangular in shape, and the second waveguide layer is convex, so that the position of the third coupling port 191 is relatively lower, and the position of the fourth coupling port 192 is relatively higher, which facilitates the direct exposure of the fourth coupling port 192 to the light-shielding layer 150 and facilitates the coupling of external fiber optic modules. Of course, in other preferred embodiments of the present invention, a platform-shaped second waveguide can also be used, so that the third coupling port 191 and the fourth coupling port 192 are flush.

[0036] In some embodiments, the height of the fourth coupling port 192 relative to the second rewiring layer 141 is less than or equal to the height of the side surface of the light-shielding layer 150 away from the carrier plate 110 relative to the second rewiring layer 141. Specifically, the fourth coupling port 192 is recessed within the light-shielding layer 150 and exposed outside the light-shielding layer 150. This facilitates the coupling of external fiber optic modules and allows the light-shielding layer 150 to provide circumferential shielding, preventing external environmental factors from affecting the transmission of optical signals. It also protects the fourth coupling port 192 from damage.

[0037] In some embodiments, the front side of the optical chip 160 is mounted on the surface of the light-shielding layer 150 away from the carrier plate 110, so that a photosensitive sealing cavity 162 is formed between the photosensitive area 161 and the corresponding front side of the optical waveguide. Specifically, the front side of the optical chip 160 and the surface of the light-shielding layer 150 can be bonded and fixed by an adhesive layer, and the photosensitive area 161 is optically coupled to the first coupling port 181 of the first optical waveguide 180 and the third coupling port 191 of the second optical waveguide 190, forming different photosensitive sealing cavities 162. By forming the photosensitive sealing cavity 162, on the one hand, the light signal can be transmitted using the photosensitive sealing cavity 162 without obstruction, and on the other hand, external impurities can be effectively prevented from entering between the photosensitive area 161 and the coupling port, ensuring the reliability of the light signal transmission.

[0038] Furthermore, the front side of the optical chip 160 is also provided with conductive bumps 163, which are spaced apart from the photosensitive area 161. Conductive connecting posts 170 are recessed within the light-shielding layer 150, and the conductive bumps 163 are correspondingly connected to the conductive connecting posts 170. Specifically, the protrusion height of the conductive bumps 163 needs to match the recess depth of the conductive connecting posts 170, so that while the front side of the optical chip 160 is attached to the surface of the light-shielding layer 150, the conductive bumps 163 can correspondingly connect with the conductive connecting posts 170.

[0039] In some embodiments, a third wiring layer 112 is provided on the back side of the carrier board 110, and solder balls 113 are provided on the side of the third wiring layer 112 away from the carrier board 110. Specifically, the third wiring layer 112 is electrically connected to the carrier board 110 and is electrically interconnected with the first wiring layer 111 through the carrier board 110.

[0040] Furthermore, a first conductive post 114 is also disposed through the carrier 110, and the third wiring is electrically connected to the first wiring layer 111 through the first conductive post 114. Specifically, the carrier 110 can be a glass substrate, i.e., a TGV (Through Glass Via) carrier 110, with a thickness of 100-200 μm, and the first conductive post 114 is disposed on it. The first conductive post 114 is a metal post, such as a copper post. The first conductive post 114 realizes the electrical interconnection between the first wiring layer 111 on the front side of the carrier 110 and the third wiring layer 112 on the back side.

[0041] In some embodiments, a flip-chip bump 131 is provided on the front side of the electrical chip 130, and a transition bump 121 is provided on the front side of the adapter board 120. Both the flip-chip bump 131 and the transition bump 121 are connected to the first rewiring layer 111. The back sides of the electrical chip 130 and the back sides of the adapter board 120 are exposed to the molding compound 140, and the second rewiring layer 141 covers the back side of the adapter board 120. Specifically, in this embodiment of the invention, the first rewiring layer 111, the second rewiring layer 141, and the third rewiring layer 112 are all RDL layers, and their specific manufacturing processes can refer to existing RDL circuits. Furthermore, the surface of the first rewiring layer 111 has metal pads. The flip-chip bump 131 on the front side of the electrical chip 130 and the transition bump 121 on the front side of the adapter board 120 are both metal bumps and are correspondingly soldered to the metal pads on the surface of the first rewiring layer 111 to achieve electrical interconnection with the first rewiring layer 111.

[0042] Furthermore, a second conductive post 122 is also disposed through the adapter board 120, and the first redistribution layer 111 is electrically connected to the second redistribution layer 141 through the second conductive post 122 and the adapter bump 121. Specifically, the adapter board 120 here can be a silicon substrate 110, that is, it can be a TSV (Through Silicon Via) adapter board 120, and the second conductive post 122 is a conductive metal post, such as a copper post, and is electrically connected to the adapter bump 121 on the front side of the adapter board 120.

[0043] It should be noted that the height of the adapter board 120 can be the same as the height of the electrical chip 130, so that the back of the adapter board 120 and the back of the electrical chip 130 are flush and exposed to the molding compound 140.

[0044] This invention also provides a method for preparing an optoelectronic co-packaging structure 100, which includes the following steps: S1: A carrier board 110 is provided, wherein a first wiring layer 111 is provided on the front side of the carrier board 110.

[0045] See also Figure 2Specifically, a TGV carrier board 110 with a thickness of 100-200um can be prepared first, and a first conductive post 114 penetrating through the carrier board 110 can be set on it. Then, a front RDL layer is made on the front side of the TGV carrier board 110 to form a first rewiring layer 111, and metal pads are made on the surface of the first rewiring layer 111.

[0046] S2: Attach the front side of the adapter board 120 to the first wiring layer 111, and attach the front side of the electrical chip 130 to the first wiring layer 111.

[0047] See also Figure 3 Specifically, the TSV adapter board 120 and the electrical chip 130 can be mounted on the front side (i.e., the side away from TGV) of the first wiring layer 111. The TSV adapter board 120 has a second conductive post 122 inside, and an adapter bump 121 is made on the front side (i.e., the side close to TGV) of the TSV adapter board 120. A flip-chip bump 131 is made on the front side of the electrical chip 130. Both the adapter bump 121 and the flip-chip bump 131 are metal bumps and are soldered to the metal pads on the surface of the first wiring layer 111, thereby realizing the electrical connection between the adapter board 120 and the electrical chip 130 and the first wiring layer 111.

[0048] S3: A molding layer 140 is formed on the first redistribution layer 111, wherein the molding layer 140 covers the sidewalls and front side of the adapter board 120 and the electrical chip 130.

[0049] See also Figure 4 Specifically, the front side of the TGV carrier board 110 can be encapsulated with epoxy resin to form an encapsulation layer 140 on the first rewiring layer 111. The encapsulation layer 140 covers the first rewiring layer 111 and the electrical chip 130 and the adapter board 120 mounted on the first rewiring layer 111. Then, the encapsulation layer 140 can be thinned by a grinding process to expose the back side of the electrical chip 130 and the adapter board 120, at which time the second conductive post 122 in the adapter board 120 can be exposed simultaneously.

[0050] S4: A second wiring layer 141 is formed on the molding layer 140, wherein the second wiring layer 141 is electrically connected to the adapter board 120.

[0051] See also Figure 5 Specifically, an RDL layer is fabricated on the back of the adapter board 120 and the electrical chip 130 to form a second wiring layer 141. The second wiring layer is electrically connected to the second conductive post 122 in the adapter board 120. The second wiring layer 141 typically has 2-4 wiring layers with line width and spacing between 2-10 μm. At the same time, metal pads are also provided on the surface of the second wiring layer 141.

[0052] S5: A third wiring layer 112 is formed on the back side of the carrier board 110.

[0053] See also Figure 6 Specifically, a temporary substrate 200 can first be bonded to the surface of the second redistribution layer 141 using temporary bonding adhesive, providing temporary protection. Then, the packaging structure is flipped over, and a redistribution layer is fabricated on the back side of the TGV carrier 110, thus forming a third redistribution layer 112. The third redistribution layer 112 is electrically connected to the first conductive post 114 in the TGV carrier 110.

[0054] S6: Solder balls 113 are formed on the third wiring layer 112.

[0055] See Figure 7 Specifically, solder balls can be formed on the surface of the third wiring layer 112 by electroplating or ball-planting processes, thereby serving as electrical connection ports for the package structure to communicate with the outside.

[0056] S7: Multiple conductive connection posts 170 are formed on the second wiring layer 141.

[0057] See also Figure 8 Specifically, temporary bonding adhesive can be reused to bond another temporary side to the surface of the solder ball for protection. Then, a laser debonding process is used to ablate the temporary bonding adhesive on one side of the second wiring layer 141, removing its adhesiveness and allowing the corresponding temporary substrate 200 to be removed, exposing the second wiring layer 141. Residual adhesive is then removed using a descaling machine. Conductive connection pillars 170, which are metal pillars such as copper pillars, are then formed on the metal pads on the surface of the second wiring layer 141 through an electroplating process. Specifically, grooves corresponding to the exposed metal pads can be formed by photoresist patterning, followed by electroplating to form the metal conductive pillars and then removing the photoresist.

[0058] In other preferred embodiments of the present invention, the conductive connecting post 170 can also be prepared in advance and mounted by copper post mounting process, which eliminates the electroplating step and simplifies the process steps.

[0059] S8: The back side of multiple optical waveguides is mounted on the second rewiring layer 141.

[0060] See Figure 9 Specifically, the first waveguide and the second waveguide are respectively mounted on the second rewiring layer 141. The front side of the first waveguide has a first coupling port 181 and the side wall of the first waveguide has a second coupling port 182. The front side of the second waveguide has a third coupling port 191 and a fourth coupling port 192 distributed at different heights.

[0061] S9: A light-shielding layer 150 is formed on the second wiring layer 141 and the optical waveguide, wherein the light-shielding layer 150 exposes a plurality of conductive connecting posts 170 and a portion of the front side of the plurality of optical waveguides.

[0062] See Figure 10 Specifically, a light-shielding layer 150 can be formed on the surfaces of the second redistribution layer 141, the first waveguide, and the second waveguide using a photolithography process. That is, the light-shielding layer 150 is first formed using a photolithography process, and then the first coupling port 181, the third coupling port 191, and the fourth coupling port 192 are exposed by creating grooves using a photolithography process. The sidewalls of the light-shielding layer 150 can be flush with the sidewall of the first waveguide having the second coupling port 182; alternatively, a dicing process can be used to make the sidewalls of the light-shielding layer 150 flush with the sidewall of the first waveguide having the second coupling port 182.

[0063] S10: Mount the front side of the optical chip 160 onto the conductive connecting post 170.

[0064] See Figure 11 The optical chip 160 is electrically connected to the second wiring layer 141 through the conductive connection post 170, and the front side of the optical chip 160 has multiple photosensitive areas 161, which are optically coupled to a portion of the front side of multiple optical waveguides.

[0065] Specifically, the optical chip 160 is mounted on the surface of the conductive connecting post 170. The front side of the optical chip 160 is provided with two photosensitive areas 161 and conductive bumps 163. The two photosensitive areas 161 are optically coupled to the first coupling port 181 of the first optical waveguide 180 and the third coupling port 191 of the second optical waveguide 190, respectively, while the conductive bumps 163 are electrically connected to the conductive connecting post 170.

[0066] It should be noted that the front side of the optical chip 160 can be adhered to the surface of the light-shielding adhesive using adhesive, thereby forming a photosensitive sealing cavity 162 between the photosensitive area 161 and the corresponding optical coupling port, which is beneficial for light shielding and protection. The width of this photosensitive sealing cavity 162 needs to be greater than or equal to the width of the photosensitive area 161 to ensure the transmission effect of the optical signal.

[0067] Please continue reading Figure 1Finally, the temporary bonding adhesive can be ablated using a laser debonding process to remove its adhesiveness, allowing the temporary substrate 200 to be removed and the solder balls 113 exposed, completing the fabrication process of the optoelectronic co-package structure 100. At this point, the optoelectronic co-package structure 100 includes one or more electrical chips 130, two or more optical chips 160, and incorporates TSV and TGV structures. Electrical signal interconnection with the outside world is achieved through the solder balls 113, and multi-channel optical signal coupling with the outside world is achieved through the second coupling port 182 and the fourth coupling port 192. Optical signal interconnection between two optical chips 160 is achieved through a second waveguide.

[0068] In summary, the optoelectronic co-packaging structure 100 and its fabrication method provided in this embodiment of the invention have a first rewiring layer 111 on the front side of a carrier substrate 110. An adapter board 120 and an electrical chip 130 are mounted on the first rewiring layer 111 and electrically connected to it. A molding compound 140 covers the adapter board 120 and the electrical chip 130. A second rewiring layer 141 is disposed on the molding compound 140 and electrically connected to the adapter board 120. Multiple conductive pillars are disposed on the second rewiring layer 141 and extend away from the carrier substrate 110. The back sides of multiple optical waveguides are all mounted on the second rewiring layer 141. Simultaneously, a light-shielding layer 150 is disposed on the second rewiring layer 141 and the optical waveguides, exposing the conductive connecting pillars 170 and a portion of the front side of the optical waveguides. The optical chip 160 is mounted on the conductive connection post 170 and electrically connected to the second wiring layer 141 through the conductive connection post 170. The multiple photosensitive areas 161 of the optical chip 160 are optically coupled to the front of multiple optical waveguides.

[0069] Compared to existing technologies, this invention achieves high-density integrated packaging by integrating the electrical chip 130 and the optical chip 160, effectively reducing chip size and packaging area, and solving the problem that traditional optoelectronic integrated structures cannot meet the requirements of high-density integrated packaging. Simultaneously, multiple optical waveguides are used to couple and interconnect multiple optical signals, thereby providing more signal interconnection channels and improving transmission performance. Furthermore, the light-shielding layer 150, formed by photolithography, effectively mitigates interference from the external environment on the optical signals by blocking the area around the optical port structure. In addition, the optoelectronic co-packaging structure 100 of this invention achieves high-density integration, reduces system and device power consumption, improves reliability, meets the needs of the explosive growth of global data traffic, and provides a new solution for the further development of optoelectronic integration technology.

[0070] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A photoelectric co-packaging structure, characterized in that, include: Carrier plate; The first wiring layer is located on the front side of the carrier board; The adapter board is mounted on the first wiring layer from the front. The electrical chip is mounted on the first wiring layer and spaced apart from the adapter board. A molding compound is disposed on the first redistribution layer and covers the adapter board and the electrical chip; The second wiring layer is disposed on the molding layer and is electrically connected to the adapter board; Multiple conductive connection posts are disposed on the second rewiring layer and extend in a direction away from the carrier board; Multiple optical waveguides are mounted on the back side of the second wiring layer; A light-shielding layer is disposed on the second redistribution layer and the optical waveguide, and exposes a plurality of conductive connecting posts and a portion of the front side of the plurality of optical waveguides; The optical chip is mounted on the conductive connecting post on the front side and is electrically connected to the second redistribution layer through the conductive connecting post. The front side of the optical chip has multiple photosensitive areas, and the multiple photosensitive areas are optically coupled to a portion of the front side of the multiple optical waveguides.

2. The optoelectronic co-packaging structure according to claim 1, characterized in that, The plurality of optical waveguides include a first waveguide and a second waveguide spaced apart. The back side of the first waveguide is attached to the second redistribution layer. A first coupling port is provided on the front side of the first waveguide. A second coupling port is provided on the side wall of the first waveguide. The first coupling port and the second coupling port are exposed in the light-shielding layer. The first coupling port is optically coupled to the photosensitive area. The back of the second waveguide is mounted on the second rewiring layer, and the front of the second waveguide is provided with a third coupling port and a fourth coupling port. The third coupling port and the fourth coupling port are exposed on the light-shielding layer, and the third coupling port is optically coupled to the photosensitive area.

3. The optoelectronic co-packaging structure according to claim 2, characterized in that, The middle part of the second waveguide protrudes in a direction away from the carrier plate to form a boss, the fourth coupling port is disposed on the boss, and the third coupling port is offset from the boss.

4. The optoelectronic co-packaging structure according to claim 3, characterized in that, The height of the fourth coupling port relative to the second rewiring layer is less than or equal to the height of the side surface of the light-shielding layer away from the carrier plate relative to the second rewiring layer.

5. The optoelectronic co-packaging structure according to claim 1, characterized in that, The front side of the optical chip is attached to the side of the light-shielding layer away from the carrier plate, so that a photosensitive sealing cavity is formed between the photosensitive area and the corresponding front side of the optical waveguide.

6. The optoelectronic co-packaging structure according to claim 5, characterized in that, The front side of the optical chip is also provided with conductive bumps, which are spaced apart from the photosensitive area. The conductive connecting post is recessed in the light-shielding layer, and the conductive bump is correspondingly connected to the conductive connecting post.

7. The optoelectronic co-packaging structure according to claim 1, characterized in that, A third wiring layer is provided on the back of the carrier board, and solder balls are provided on the side of the third wiring layer away from the carrier board.

8. The optoelectronic co-packaging structure according to claim 7, characterized in that, A first conductive post is also disposed through the carrier board, and the third wiring layer is electrically connected to the first wiring layer through the first conductive post.

9. The optoelectronic co-packaging structure according to claim 1, characterized in that, The front side of the electrical chip is provided with a flip-chip bump, and the front side of the adapter board is provided with an adapter bump. Both the flip-chip bump and the adapter bump are connected to the first rewiring layer. The back side of the electrical chip and the back side of the adapter board are exposed to the molding layer, and the second rewiring layer covers the back side of the adapter board.

10. The optoelectronic co-packaging structure according to claim 9, characterized in that, The adapter board also has a second conductive post running through it, and the first rewiring layer is electrically connected to the second rewiring layer through the second conductive post and the adapter bump.

11. A method for fabricating an optoelectronic co-packaging structure, characterized in that, include: A carrier board is provided, wherein a first wiring layer is provided on the front side of the carrier board; The front side of the adapter board is attached to the first wiring layer; The front side of the electrical chip is mounted on the first wiring layer; A molding layer is formed on the first redistribution layer, wherein the molding layer covers the sidewalls and front side of the adapter board and the electrical chip; A second wiring layer is formed on the molding layer, wherein the second wiring layer is electrically connected to the adapter board; Multiple conductive connection pillars are formed on the second rewiring layer; Multiple optical waveguides are back-mounted onto the second wiring layer; A light-shielding layer is formed on the second redistribution layer and the optical waveguide, wherein the light-shielding layer exposes a portion of the front surface of the plurality of conductive connection posts and the plurality of optical waveguides; The front side of the optical chip is mounted on the conductive connection post, wherein the optical chip is electrically connected to the second redistribution layer through the conductive connection post, and the front side of the optical chip has multiple photosensitive areas, and the multiple photosensitive areas are optically coupled to a portion of the front side of the multiple optical waveguides respectively.

12. The method for preparing the optoelectronic co-packaging structure according to claim 11, characterized in that, Prior to the step of forming multiple conductive connection pillars on the second wiring layer, the method further includes: A third wiring layer is formed on the back side of the carrier board; Solder balls are formed on the third wiring layer.

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