A stress relief pad structure for improving thermal reliability of a TSV adapter plate and a preparation method thereof

Abstract

The application discloses a stress relief pad structure for improving the thermal reliability of a TSV adapter plate and a preparation method thereof. A second Ti layer is formed on a substrate, a TiW layer is formed on the second Ti layer, a Cu layer is formed on the TiW layer, a first Ti layer is formed on the Cu layer, edges of Au layers and Ni layers are coincident, edges of the Cu layer, the TiW layer and the second Ti layer are coincident, the edge of the Cu layer is extended outward by d compared with the edge of the Ni layer, the first Ti layer is formed on the Cu layer outside the Ni layer, an outward extension area of the first Ti layer is coincident with the Cu layer, and a stepped structure is formed.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a stress relief pad technology for improving the thermal reliability of TSV adapter boards. Background Technology

[0002] As high-reliability RF electronic modules continue to evolve towards miniaturization, lightweighting, and multifunctional integration, their form is rapidly transforming from traditional large-volume discrete components to high-density RF microsystems. Thystic Silicon Via (TSV) adapter boards, with their manufacturing technology featuring high transmission rates, low transmission losses, and significantly increased integration density, have become a core process technology for RF electronic modules, achieving a 100-fold reduction in size and weight and a 100-fold increase in integration density.

[0003] Although TSV adapter boards are a mature application in the digital and consumer electronics fields, high-reliability RF microsystems place higher demands on the reliability of TSV adapter boards, requiring them to not only carry high-density current and achieve low-loss, low-crosstalk signal transmission, but also withstand more severe environmental loads.

[0004] In TSV adapter boards, the substrate material, such as silicon, and the filler metal material, such as copper or tungsten, exhibit thermal mismatch. Existing research on their thermal reliability largely focuses on the interface between the substrate and the filler metal, lacking reliability studies on surface pad structures, which are also interfaces between silicon and metal. Summary of the Invention

[0005] In order to significantly reduce the proportion of pad failures caused by residual stress in the film layer and thermal stress during the manufacturing and service of radio frequency microsystems, and to solve the problem of TSV adapter board failure caused by silicon oxide fracture and pad detachment due to excessive residual stress and thermal stress, this invention proposes a stress-relieving pad structure with a stepped structure.

[0006] The pads adopt a stepped structure, from top to bottom, consisting of a centrally overlapping Au layer, Ni layer, Cu layer, TiW layer, second Ti layer, and a silicon substrate with a SiO2 passivation layer. The edges of the Au layer and Ni layer overlap, as do the edges of the Cu layer, TiW layer, and second Ti layer. The edge of the Cu layer extends outward by d compared to the edge of the Ni layer. There is a first Ti layer on the Cu layer outside the Ni layer, and the outward extension area of ​​the first Ti layer overlaps with the Cu layer.

[0007] Furthermore, the Au and Ni layers are circular with diameters ranging from 10 μm to 200 μm and diameters ranging from 2 μm to 50 μm.

[0008] Preferably, the diameter of the Au layer and the Ni layer is 160 μm, and d is 10 μm, 15 μm, or 20 μm.

[0009] Furthermore, the thickness of the Au layer is 0.5±0.2μm, the thickness of the Ni layer is 3±0.5μm, the thickness of the Cu layer is 2±0.5μm, the thickness of the TiW layer is 100±50nm, the thickness of the first Ti layer is 100±50nm, the thickness of the second Ti layer is 100±50nm, and the thickness of the SiO2 passivation layer is 1±0.5μm.

[0010] Preferably, the Au layer has a thickness of 0.5 μm, the Ni layer has a thickness of 3 μm, the Cu layer has a thickness of 2 μm, the TiW layer has a thickness of 75 nm, the first Ti layer has a thickness of 100 nm, the second Ti layer has a thickness of 100 nm, and the SiO2 passivation layer has a thickness of 1 μm.

[0011] Using chemical vapor deposition (CVD), a SiO2 passivation layer is formed on a silicon substrate as the base. Then, using DC magnetron sputtering, a second Ti layer, a TiW layer, a Cu layer, and a first Ti layer are sequentially formed on the substrate. The first Ti layer is divided into three regions: Region 1, Region 2, and Region 3. Region 1 corresponds to the Au and Ni layers, Region 2 is the extended portion of Region 1, and Region 3 is the extended portion of Region 2. Region 2 is coated with photoresist and patterned. Region 1 is removed, while Regions 2 and 3 are retained. Using electroplating, a Ni layer is sequentially formed on the exposed Cu layer, followed by an Au layer. The photoresist is then removed. Photoresist is then coated and patterned on the Au, Ni, Regions 2 and 3 layers, retaining the Au layer and the photoresist in Region 2. The photoresist in Region 3 is removed. This process is repeated sequentially, removing Region 3, the Cu layer, the TiW layer, and the Ti layer, and finally removing the photoresist, resulting in a stress-relieving pad structure.

[0012] Specifically, the chemical vapor deposition (CVD) technique uses tetraethoxysilane as the material, with a high-frequency power of 700±50W, a low-frequency power of 300±50W, and a chamber pressure of 350±50Pa. To form the second Ti layer on the substrate, a Ti target is used, with a DC power of 1200±100W and a sputtering pressure of 0.8±0.1Pa. To form the TiW layer on the second Ti layer, a Ti target is used. 10 W 90 The target has a DC power of 1500±100W and a sputtering pressure of 0.8±0.1Pa. The Cu layer is formed on the TiW layer using a Cu target with a DC power of 1800±100W and a sputtering pressure of 1±0.1Pa. The first Ti layer is formed on the Cu layer using a Ti target with a DC power of 1200±100W and a sputtering pressure of 0.8±0.1Pa.

[0013] The photoresist is either positive or negative, and the coating method is spin coating or spray coating with a thickness of ≥4μm. The photolithography method is ultraviolet lithography or laser direct writing. The photoresist is removed using acetone-based remover, ethanol-based remover, N-methylpyrrolidone-based remover, dimethyl sulfoxide-based remover, or tetramethylammonium hydroxide-based remover.

[0014] The removal of area one is carried out using HF-based etchant, the main component of which is 5% to 10% HF solution by volume. The outer area of ​​removal area two is also etched using HF-based etchant, the main component of which is 5% HF solution by volume. Cu removal is carried out using H2SO4-based etchant, first H2O2-based etchant, ferric chloride-based etchant, copper chloride-based etchant, and persulfate-based etchant. TiW removal is carried out using second H2O2-based etchant, the main component of which is 20% to 25% H2O2 solution by volume.

[0015] The Ni electroplating uses a nickel sulfamate solution system, with the main component being a 300 g / L to 450 g / L nickel sulfamate solution. The current density for Ni electroplating is 150 ± 10 A / m. 2 The Au electroplating process uses a potassium gold cyanide system, with the main component being an 8 g / L to 12 g / L potassium gold cyanide solution. The current density for Au electroplating is 20 ± 2 A / m. 2 .

[0016] This invention does not change the pad fabrication process, but improves the reliability of high-density silicon-based radio frequency microsystems by mitigating stress at single stress concentration points, significantly reducing stress extremes and stress changes during thermal loading. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the pad structure.

[0018] Figure 2 This is a flowchart of the preparation method.

[0019] Figure 3 This is a schematic diagram of a typical TSV structure.

[0020] Figure 4 This is a flowchart of the manufacturing process for silicon-based radio frequency microsystem modules.

[0021] Figure 5 This is a diagram showing the failure of the TSV adapter board due to the solder pads falling off.

[0022] Figure 6 This is a photograph of the failed cross-section of the TSV adapter board.

[0023] Figure 7 This is a schematic diagram of a wafer stress simulation model.

[0024] Figure 8 This is a simulation model diagram of the solder pads.

[0025] Figure 9 This is a stress distribution diagram of the solder pads between 20℃ and 340℃.

[0026] Figure 10 This is a schematic diagram of the stress relief pad structure.

[0027] Figure 11 This is a stress distribution diagram of the stress relief structure pads.

[0028] Figure 12 This is a schematic diagram of the preparation process.

[0029] Figure 13 These are schematic diagrams of pads with different expansion amounts. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the embodiments and the accompanying drawings.

[0031] Pad structure as follows Figure 1 As shown, it has a stepped structure, consisting of, from top to bottom, a centrally overlapping Au layer, a Ni layer, a Cu layer, a TiW layer, a second Ti layer, and a silicon substrate with a SiO2 passivation layer. The edges of the Au layer and the Ni layer overlap, as do the edges of the Cu layer, the TiW layer, and the second Ti layer. The edge of the Cu layer extends outward by d compared to the edge of the Ni layer. There is a first Ti layer on the Cu layer outside the Ni layer, and the outward extension region of the first Ti layer overlaps with the Cu layer.

[0032] The thickness of the Au layer is 0.5±0.2μm, preferably 0.5μm; the thickness of the Ni layer is 3±0.5μm, preferably 3μm; the thickness of the Cu layer is 2±0.5μm, preferably 2μm; the thickness of the TiW layer is 100±50nm, preferably 75nm; the thickness of the first Ti layer is 100±50nm, preferably 100nm; the thickness of the second Ti layer is 100±50nm, preferably 100nm; 2μm≤d≤50μm, preferably 10μm, 15μm or 20μm.

[0033] The Au and Ni layers are circular with a diameter of 10 to 200 μm, preferably 160 μm; the SiO2 passivation layer has a thickness of 1 ± 0.5 μm, preferably 1 μm.

[0034] The method includes: using chemical vapor deposition (CVD) to form a SiO2 passivation layer on a silicon substrate as a base; using DC magnetron sputtering, sequentially forming a second Ti layer, a TiW layer on the second Ti layer, a Cu layer on the TiW layer, and a first Ti layer on the Cu layer; dividing the first Ti layer into region 1, region 2, and region 3, where region 1 corresponds to the Au and Ni layers, region 2 is the extended portion of region 1, and region 3 is the extended portion of region 2; coating region 2 with photoresist and patterning it; removing region 1 and retaining regions 2 and 3; using electroplating, sequentially forming a Ni layer on the exposed Cu layer and an Au layer on the Ni layer; removing the photoresist; coating the Au layer, Ni layer, region 2, and region 3 with photoresist and patterning it; retaining the Au layer and the photoresist in region 2; removing the photoresist in region 3; sequentially removing region 3, the Cu layer, the TiW layer, and the Ti layer; and finally removing the photoresist to obtain a stress-relieving pad structure.

[0035] The chemical vapor deposition (CVD) technique uses tetraethoxysilane as the material, with a high-frequency power of 700±50W (preferably 700W) and a low-frequency power of 300±50W (preferably 300W), and a chamber pressure of 350±50Pa (preferably 350Pa). To form the second Ti layer on the substrate, a Ti target is used, with a DC power of 1200±100W (preferably 1200W) and a sputtering pressure of 0.8±0.1Pa (preferably 0.8Pa). To form a TiW layer on the second Ti layer, a Ti target is used. 10 W 90 The target has a DC power of 1500±100W, preferably 1500W, and a sputtering pressure of 0.8±0.1Pa, preferably 0.8Pa; the Cu layer is formed on the TiW layer using a Cu target with a DC power of 1800±100W, preferably 1800W, and a sputtering pressure of 1±0.1Pa, preferably 1Pa; the first Ti layer is formed on the Cu layer using a Ti target with a DC power of 1200±100W, preferably 1200W, and a sputtering pressure of 0.8±0.1Pa, preferably 0.8Pa.

[0036] The photoresist is either positive or negative, preferably AZ4620 photoresist. The coating method is spin coating or spray coating, with a thickness of ≥4μm, preferably 7μm. The photolithography method is ultraviolet lithography or laser direct writing. The photoresist is removed using acetone-based remover, ethanol-based remover, N-methylpyrrolidone-based remover, dimethyl sulfoxide-based remover, or tetramethylammonium hydroxide-based remover, preferably tetramethylammonium hydroxide-based remover.

[0037] The first removal area is etched with an HF-based etchant, the main component of which is an HF solution with a volume fraction of 5% to 10%, preferably 5%; the outer area of ​​the second removal area is etched with an HF-based etchant, the main component of which is an HF solution with a volume fraction of 5%.

[0038] The Ni electroplating uses a nickel sulfamate solution system, with the main component being a nickel sulfamate solution of 300 g / L to 450 g / L, preferably 350 g / L. The current density for Ni electroplating is 150 ± 10 A / m. 2 150A / m is preferred 2 The Au electroplating uses a potassium gold cyanide system, with the main component being an 8 g / L to 12 g / L potassium gold cyanide solution, preferably 10 g / L. The current density for Au electroplating is 20 ± 2 A / m. 2 20A / m is preferred 2 .

[0039] Cu removal uses H2SO4-based etching solution, first H2O2-based etching solution, ferric chloride-based etching solution, copper chloride-based etching solution, and persulfate-based etching solution, preferably the first H2O2-based etching solution, whose main components are 5% to 10% H2O2 solution and 3.5% to 4.5% HCl solution, preferably 5% H2O2 solution and 3.5% HCl solution; TiW removal uses second H2O2-based etching solution, whose main components are 20% to 25% H2O2 solution, preferably 20%.

[0040] This invention addresses the need for highly reliable TSV adapter boards in high-density RF microsystems. Based on experimental measurements and finite element simulation correction of thin film residual stress, it simulates and analyzes the stress distribution of the TSV adapter board surface pads at room temperature and high temperature, explaining the cause of pad failure from a mechanistic perspective.

[0041] This invention comprehensively considers the effects of residual stress and thermal stress in the film layer, overcomes the shortcomings of the Stoney method in measuring the stress of large warp films, analyzes the mechanism of surface pad fracture failure of TSV adapter boards, and proposes a stepped pad structure that can alleviate stress.

[0042] This invention achieves accurate modeling of multi-layer pad stress. Through simulation analysis and experimental verification, it can significantly reduce the proportion of pad failure caused by residual stress in the film layer and thermal stress during the manufacturing and service of RF microsystems, thereby improving the reliability of high-reliability silicon-based high-density RF microsystems.

[0043] TSV adapter board surface RDL failure mechanism analysis: The TSV adapter board achieves interlayer electrical interconnection through the TSV structure distributed in the silicon substrate and penetrating the entire silicon substrate, thereby greatly shortening the interconnection length and improving the integration density of the RF microsystem.

[0044] A typical TSV structure usually consists of a silicon substrate, a silicon oxide passivation layer, a titanium adhesion / barrier layer, a copper internal conductor, and titanium, copper, nickel, and gold surface RDLs, such as... Figure 3 As shown.

[0045] The most significant factor affecting the reliability of TSV adapter boards is the difference in the coefficients of thermal expansion of the aforementioned materials, which leads to substantial thermal stress during the manufacturing and service of the adapter boards. In terms of the difference in coefficients of thermal expansion, silicon oxide differs from several metals by more than 10 times. The location of the greatest thermal stress in the TSV adapter board is at the interface between silicon oxide and the metals.

[0046] Typical failure modes of the pad / SiO2 interface: The main process flow for manufacturing silicon-based RF microsystem modules is as follows Figure 4 As shown, the module undergoes thermal loads during wafer bonding, die mounting, wire bonding, capping, and ball bonding processes. By the time the capping process is completed, approximately 50% or more of the RDLs located on the outside of the module fail, leaving imprints on the substrate surface that perfectly match the RDL outline. Figure 5 As shown.

[0047] Existing technologies are mainly aimed at Figure 5 At position ①, methods such as annealing, annular TSV, and rugby ball-shaped hollow TSV are used to reduce interfacial thermal stress. This invention differs from the prior art in that it mainly focuses on the failure and optimization of position ②, namely the interface between the surface pad and SiO2.

[0048] In high-reliability silicon-based RF microsystem modules, surface pads typically serve multiple functions, including chip interface fan-in / fan-out, intra-layer / inter-layer electrical interconnection, and module external interconnection. The composition of the film layers varies depending on the function, but generally includes at least an adhesion / barrier layer, a seed layer, a solder resist layer, and a conductor / solder layer. The complex film layer system and different fabrication processes make stress analysis of the pads and redistribution layers themselves quite difficult. During module manufacturing and service, they need to withstand various thermal loads, including wafer bonding, module soldering, chip heat dissipation, and external environmental factors, with temperatures ranging from -55℃ (for module testing) to 340℃ (for Au-Sn wafer bonding), a very wide range. These two factors result in TSV adapter board pads and pad / SiO2 interfaces being prone to failure, difficult to analyze, and difficult to optimize.

[0049] Scanning electron microscope for Figure 5 Energy dispersive spectroscopy (EDS) analysis was performed at points ① and ②, and the atomic percentages of each element are shown in Table 1.

[0050] Table 1

[0051] In the area ① covered by the pads, only Si elements were detected, indicating that SiO2 had completely fallen off. In the area ② not covered by the surface pads, the percentage of Si to O atoms was 1:2, indicating that SiO2 was completely covered on the surface of the adapter board.

[0052] Samples with loose but not completely detached surface pads were cut using a triion beam, with the cross-section shown below. Figure 6 As shown, 6(a) is a top view of the failed pad, and 6(b) is a cross-section of the failed pad. Locating the cause and location of the failure, it can be clearly observed that the SiO2 on the TSV substrate surface fractured from the edge of the pad and extended inward along the Si / SiO2 interface, causing the surface pad to detach. Based on the failure mode and location, the main causes of the failure are as follows:

[0053] First, the pads consist of four metal films: 100nm Ti, 2μm Cu, 3μm Ni, and 500nm Au. Ti and Cu are deposited via magnetron sputtering, while Ni and Au are grown via electroplating. The passivation layer is a 1μm SiO2 deposit using PECVD. The films themselves contain residual stress, continuously generating tensile or compressive stress on the TSV adapter surface. Second, after the thermal loading process, a significant difference in CTE exists between the pad metal films and the SiO2, resulting in rapidly changing thermal stress at their interface. The combined effect of these two stress factors exceeds the SiO2 fracture limit, causing the SiO2 to fail at the pad edges.

[0054] Residual stress calculation of film layers based on the Stoney formula: To verify the above judgment, the residual stress of each metal film layer in the pad was measured based on the substrate curvature method. First, six 8-inch 100-oriented bare silicon wafers were selected. Using an FST5000 thin film stress meter, the arc height of the wafers was scanned along a 180mm path at 45° intervals and passing through the wafer center. Then, 1μm SiO2, 100nm Ti, 75nm TiW, and 2μm Cu were deposited on three of the wafers by PECVD and magnetron sputtering, respectively. For electroplated films, 2μm Cu was first deposited as a seed layer on the remaining two wafers, and then 3μm Ni and 500nm Au were electroplated, respectively. The arc height of the wafers after film deposition was obtained using the same scanning parameters. The arc height and average curvature of the five wafers before and after film growth were measured and are shown in Table 2.

[0055] Table 2

[0056] As shown in Table 2, the wafer has the largest arc height after growing 2μm Cu, 2μm Cu and 1μm Ni on the wafer surface, which means that the wafer has the largest deformation after growing the film.

[0057] Substitute the results from Table 2 into the Stoney formula for multilayer thin films. Calculate the residual stress σfilm of the film, where E s h is the Young's modulus of the substrate. s h is the substrate thickness. f ν is the film thickness. s R is the substrate Poisson's ratio. s R is the radius of curvature of the substrate before thin film deposition. f The radius of curvature of the substrate after film deposition is given, and the residual stress of the six film layers is obtained, as shown in Table 3.

[0058] Table 3

[0059] Table 3 shows that Ti, TiW, and Cu deposited by magnetron sputtering exhibit compressive stress at room temperature, while Ni and Au films grown by electroplating exhibit tensile stress. It is noteworthy that the compressive stress of Ti and TiW films, which cause the smallest wafer warp among the six films, is significantly greater than that of Cu films, which cause the largest wafer warp. This is due to the limitations of the Stoney formula itself: after depositing a 2μm Cu film, the wafer arc height is 163.03μm, reaching 22.49% of the wafer thickness, which does not satisfy the small deformation assumption that the deformation is much smaller than the substrate thickness. This leads to a deviation between the stress value calculated by the Stoney formula and the actual residual stress of the film.

[0060] Residual stress correction based on finite element simulation fitting: To address the inaccuracy of stress calculation results caused by the limitations of the Stoney formula, the wafer bow height is fitted using the commercial finite element simulation software COMSOL Multiphysics based on measured bow height data. The wafer model is as follows: Figure 7 As shown, 7(a) represents the bare wafer model, 7(b) represents the arc height data extraction path, and 7(c) represents the deformed wafer after adding thin film residual stress. The material parameters used in the simulation are shown in Table 4.

[0061] Table 4

[0062] In COMSOL Multiphysics, the stress field can be set as a second-order stress tensor, using the formula... It means that σ xy =σ yx σ xz =σ zx σ yz =σ zy This represents the shear stress component. The silicon substrate, SiO2, and various metal films are isotropic; therefore, in the stress tensor matrix, except for the principal stresses, the shear stress component is zero, i.e., σ0. xy =σ yx =σxz =σ zx =σ yz =σ zy =0. Since the thickness of SiO2 and various metal films is much smaller than the thickness of the silicon substrate, the stress tensor can be further simplified to a biaxial stress mode, i.e., σ xx =σ yy And σ zz =0, use the formula express.

[0063] The σxx function was used to fit the simulated bow height data with the experimentally measured bow height data, correcting the stress calculation error caused by the limitations of the Stoney formula, and obtaining a more realistic residual stress for each membrane layer. The residual stresses of each membrane layer obtained from the simulation are shown in Table 5.

[0064] Table 5

[0065] Among them, the residual stress obtained from simulation and measurement of Ti and TiW films is the closest. For Cu and Ni films, due to excessive deformation of the wafer, the deviation between simulation and measurement has reached more than 100%, further proving that the classic Stoney formula is no longer applicable under large deformation conditions.

[0066] Analysis of the failure mechanism of the pad / SiO2 interface in silicon-based RF microsystem modules: Modeling and reconstructing the pads on the silicon substrate, such as... Figure 8 As shown, 8(a) represents the overall model of the pad, and 8(b) represents the pad and substrate film system.

[0067] The thickness of each membrane layer remained consistent with the research analysis. The corrected residual stress in Table 5 was substituted into the corresponding membrane layer as the prestress, and simulations were performed at 20°C intervals. Figure 8 The stress at the pad / SiO2 interface from room temperature (20℃) to the highest thermal load of Au-Sn wafer bonding (340℃) during fabrication was analyzed, and the Von Mises stress at the interface was extracted. Figure 9 As shown, to clearly illustrate the changes, only the stress distribution at 20℃ and 340℃ is highlighted, while the rest are marked in gray.

[0068] The simulation results effectively explain the failure phenomenon and mechanism of the pad / SiO2 interface fracture near the pad edge: at room temperature (20℃), the residual stress of the pad film layer plays a dominant role, keeping the pad / SiO2 interface in a high-stress state for a long time, with a Von Mises stress of 1459 MPa. During the fabrication of the silicon-based RF microsystem module, the temperature rises, and the thermal stress generated by the CTE difference between the film layers offsets part of the residual stress, causing the overall stress of the pad / SiO2 interface to drop rapidly to 1088 MPa. After fabrication, the temperature returns to room temperature, and the interface returns to a high-stress state. During this process, the stress concentration point does not change, causing the region to rapidly undergo a high-stress-low-stress-high-stress process in a short period of time, during which the Von Mises stress change reaches 371 MPa, causing irreversible damage to the SiO2 film layer under the stress concentration point, and ultimately leading to fracture failure under high stress.

[0069] The pads on the surface of the TSV adapter board serve as interconnects between multiple layers, including the package substrate, devices, and modules. They are the most fundamental and core component of silicon-based RF microsystem modules, and even a small percentage of failures can lead to the paralysis of critical functions at the module or even system level. Pad / SiO2 interface failure is undoubtedly a significant risk factor for the application of TSV adapter boards in high-reliability microsystem RF modules. The problems exposed by the simulation above, such as high stress at room temperature at the pad / SiO2 interface and large stress variations during module manufacturing, can be addressed through both process and design approaches.

[0070] The first approach involves modifying the commonly used pad and film layer system by adopting a low-stress film layer to reduce the overall stress of the pads. Simultaneously, it involves improving the overall manufacturing process of silicon-based RF microsystem modules, narrowing the temperature range of the thermal load during the process to reduce the magnitude of stress changes. The second approach is to directly optimize the pad structure by using stress-relieving structures to reduce the peak stress at stress concentration points while simultaneously reducing the magnitude of stress changes during thermal loading.

[0071] For the first approach, controlling residual stress in the film layer and manufacturing processes for silicon-based modules with low temperature spans have always been research hotspots in the industry. The growth of low-stress multi-layer systems involves multiple factors such as raw materials, substrates, and process control during film growth, as well as their inter-coupling, making it extremely difficult. Achieving interconnection and encapsulation of multiple layers in silicon-based modules at relatively low temperature spans also requires addressing multiple challenges in integrated packaging material systems and processes.

[0072] This invention addresses the issue of pad / SiO2 interface failure by adding stress-relieving structures to the pads, without altering the existing film system and silicon-based microsystem fabrication process.

[0073] Design of Pad Stress Relief Structure Based on Finite Element Simulation: From Figure 9 Based on the stress simulation results shown at room temperature, the main source of stress is the tensile stress of 2.952 GPa caused by Ni electroplating. Although the underlying Cu, TiW, and Ti films all exhibit compressive stress, the values ​​are small and insufficient to completely offset their pulling effect on the SiO2 located below the films. Since the film layers of the pads have the same external dimensions, the stress is released at their boundaries, making the pad / SiO2 interface near the edge of the pad a stress concentration point.

[0074] from Figure 9 The stress simulation results at 340℃ show that, since the coefficient of thermal expansion (CTE) of Au, Ni, Cu, TiW, and Ti films is greater than that of Si and SiO2 below them, the thermal stress exerted by the pad film on Si and SiO2 is compressive stress when the temperature rises. However, since the compressive stress is still insufficient to completely offset the tensile stress brought by the electroplating of Ni, the situation that the pad / SiO2 interface is a stress concentration point near the edge of the pad remains unchanged.

[0075] Based on the existing pads, the Ti / TiW / Cu film layer is expanded outward on one side, making the pads have a stepped shape overall, such as... Figure 10 As shown in (a), it has two advantages: First, the size of the Ni / Au film is slightly smaller than that of the Ti / TiW / Cu film at the bottom, and the tensile stress introduced is released slowly on the Cu film; Second, due to the difference in size between the Ni and Cu films, the stress is released at multiple interfaces at the same time, avoiding the problem of stress always being concentrated in one place.

[0076] The stress distribution at the pad / SiO2 interface at temperatures ranging from 20℃ to 340℃ is as follows: Figure 10 As shown in (b) and (c), the stress concentration point located at the edge of the Ni / Au film is called the first stress concentration point, and the stress concentration point located at the edge of the Cu / TiW / Ti film is called the second stress concentration point.

[0077] Will Figure 9 and Figure 10 Compared to (b) and (c), the stress at the first stress concentration point is tensile, while the stress at the second stress concentration point is compressive. The two stresses superimpose, resulting in a significant decrease in stress at the first stress concentration point. Furthermore, this paper simulates the stress distribution under different unilateral expansion amounts to find the most suitable stress-relieving pad structure parameters. The simulation results are as follows: Figure 11 As shown.

[0078] As the unilateral expansion of the Cu / TiW / Ti film increases, the numerical changes of the first stress concentration point are shown in Table 6. As the unilateral expansion increases, the stress extreme values ​​of the first stress concentration point at 20℃ and 340℃ both increase, but the magnitude of the change decreases as the expansion increases.

[0079] Table 6

[0080] The stress extreme values ​​at the second stress concentration point exhibit different variation patterns. The stress extreme values ​​at 20℃ and 340℃ both decrease with increasing outward expansion, while the variation range decreases with increasing outward expansion, as shown in Table 7.

[0081] Table 7

[0082] Regardless of the amount of expansion, compared to conventional pads, the stress extreme value at the first stress concentration point of the pad with stress relief structure is significantly reduced at 20℃ and 340℃, with reductions of 64.0% and 73.4%, 63.9% and 72.5%, and 61.7% and 67.1%, respectively, greatly reducing the risk of pad detachment due to stress mismatch.

[0083] Reliability verification based on stress-relief pad structure: On the same 8-inch wafer, ... Figure 2 The process flow was used to prepare Ti / TiW / Cu films with single-sided pad structures without outward expansion and with outward expansion of 10μm, 15μm, and 20μm pads for experimental verification.

[0084] Fabricating different structures on a single wafer in a single run eliminates the influence of subtle differences in film thickness and stress between batches, ensuring that the only variable is the unilateral expansion. Each structure is fabricated with four 20×20 arrays with a spacing of 800 μm. Figure 12 As shown.

[0085] An 8-inch wafer was cut into a 16-pad array according to its structure. After undergoing 200 temperature shock cycles according to GJB360B method, quasi-synchronous laser balling technology was used to implant balls onto each pad. Figure 13 As shown.

[0086] After all the solder balls were pushed away using a push-pull force tester, the number of solder pads that fell off due to silicon oxide fracture was counted, and the results are shown in Table 8.

[0087] Table 8

[0088] The proportion of pads falling off with different expansion amounts decreased significantly, but the proportions between them were not much different. This is because the stress relief pad structure significantly reduced the stress extremes at the first and second stress concentration points at 20℃ and 340℃ to below the tensile strength of the PECVD deposited silicon oxide, effectively avoiding silicon oxide fracture caused by stress.

[0089] Based on the comprehensive simulation and experimental results, and considering the following factors: first, the stress change during module manufacturing should be minimized; second, the module should be kept at room temperature for most of its service life; and third, the impact of pad expansion and TSV via impedance matching, the optimal pad expansion on one side should be 15μm.

[0090] This invention addresses the high integration density and high reliability requirements of high-reliability RF microsystems. First, it uses simulation fitting to correct the residual stress in the thin film calculated by the classic Stoney formula, overcoming its limitation of only being applicable to small deformation scenarios. Based on this, considering the effects of residual film stress and thermal stress, the mechanism of pad fracture failure on the TSV adapter board surface is analyzed, and a stepped pad structure capable of mitigating stress is proposed. Simulation analysis and experimental verification show that this structure can significantly reduce the proportion of pad failure caused by residual film stress and thermal stress during the manufacturing and service of RF microsystems, effectively improving the reliability of high-reliability silicon-based high-density RF microsystems.

[0091] The simulation and analysis methods used in this invention, and the proposed pad release structure, can be extended to the surface wiring design and manufacturing of adapter boards in high-density, high-reliability application scenarios, and have certain reference value for improving the reliability of high-density RF microsystems.

[0092] Although the above embodiments have provided a detailed description of the present invention, they are only some embodiments of the present invention and not all embodiments. People can obtain other embodiments based on these embodiments without creative effort, and these embodiments all fall within the protection scope of the present invention.

Claims

1. A stress-relieving pad structure for improving the thermal reliability of a TSV adapter board, characterized in that, include: The pads adopt a stepped structure, from top to bottom, consisting of a centrally overlapping Au layer, Ni layer, Cu layer, TiW layer, second Ti layer, and a silicon substrate with a SiO2 passivation layer. The edges of the Au layer and Ni layer overlap, as do the edges of the Cu layer, TiW layer, and second Ti layer. The edge of the Cu layer extends outward by d compared to the edge of the Ni layer. There is a first Ti layer on the Cu layer outside the Ni layer, and the outward extension area of ​​the first Ti layer overlaps with the Cu layer.

2. The stress-relieving pad structure for improving the thermal reliability of TSV adapter boards according to claim 1, characterized in that, The Au and Ni layers are circular with a diameter of 10 μm to 200 μm and a diameter of 2 μm to 50 μm.

3. The stress-relieving pad structure for improving the thermal reliability of TSV adapter boards according to claim 2, characterized in that, The diameter of the Au layer and Ni layer is 160 μm, and d is 10 μm, 15 μm, or 20 μm.

4. The stress-relieving pad structure for improving the thermal reliability of TSV adapter boards according to claim 1, characterized in that, The thickness of the Au layer is 0.5±0.2μm, the thickness of the Ni layer is 3±0.5μm, the thickness of the Cu layer is 2±0.5μm, the thickness of the TiW layer is 100±50nm, the thickness of the first Ti layer is 100±50nm, the thickness of the second Ti layer is 100±50nm, and the thickness of the SiO2 passivation layer is 1±0.5μm.

5. The stress-relieving pad structure for improving the thermal reliability of TSV adapter boards according to claim 4, characterized in that, The Au layer has a thickness of 0.5 μm, the Ni layer has a thickness of 3 μm, the Cu layer has a thickness of 2 μm, the TiW layer has a thickness of 75 nm, the first Ti layer has a thickness of 100 nm, the second Ti layer has a thickness of 100 nm, and the SiO2 passivation layer has a thickness of 1 μm.

6. A method for fabricating a stress-relieving pad structure to improve the thermal reliability of a TSV adapter board, characterized in that, include: A SiO2 passivation layer was formed on a silicon substrate using chemical vapor deposition technology; Using DC magnetron sputtering, a second Ti layer, a TiW layer, a Cu layer, and a first Ti layer are sequentially formed on the substrate. The first Ti layer is divided into three regions: region 1, region 2, and region 3. Region 1 corresponds to the Au and Ni layers, region 2 is the portion extending outward from region 1, and region 3 is the portion extending outward from region 2. Region 2 is coated with photoresist and patterned. Region 1 is removed, while regions 2 and 3 are retained. Using electroplating, a Ni layer is sequentially formed on the exposed Cu layer, and an Au layer is formed on the Ni layer. Remove the photoresist, coat and pattern the Au layer, Ni layer, region 2 and region 3 with photoresist, retain the photoresist in the Au layer and region 2, and remove the photoresist in region 3. Region 3, Cu layer, TiW layer, and Ti layer were removed sequentially, and the photoresist was removed to obtain the stress-relieving pad structure.

7. The method for preparing the stress-relieving pad structure for improving the thermal reliability of the TSV adapter board according to claim 6, characterized in that, The chemical vapor deposition technique uses tetraethoxysilane as the material, with a high-frequency power of 700±50W, a low-frequency power of 300±50W, and a chamber pressure of 350±50Pa. To form the second Ti layer on the substrate, a Ti target is used, with a DC power of 1200±100W and a sputtering pressure of 0.8±0.1Pa. To form a TiW layer on the second Ti layer, a Ti target is used. 10 W 90 The target has a DC power of 1500±100W and a sputtering pressure of 0.8±0.1Pa. The Cu layer is formed on the TiW layer using a Cu target with a DC power of 1800±100W and a sputtering pressure of 1±0.1Pa. The first Ti layer is formed on the Cu layer using a Ti target with a DC power of 1200±100W and a sputtering pressure of 0.8±0.1Pa.

8. The method for preparing the stress-relieving pad structure for improving the thermal reliability of the TSV adapter board according to claim 6, characterized in that, The photoresist is either positive or negative, and the coating method is spin coating or spray coating with a thickness ≥4μm. The photolithography method is ultraviolet lithography or laser direct writing. The photoresist is removed using acetone-based remover, ethanol-based remover, N-methylpyrrolidone-based remover, dimethyl sulfoxide-based remover, or tetramethylammonium hydroxide-based remover.

9. The method for preparing the stress-relieving pad structure for improving the thermal reliability of the TSV adapter board according to claim 6, characterized in that, The first removal area is etched using an HF-based etchant, the main component of which is a 5% to 10% HF solution by volume. The outer area of ​​the second removal area is etched using an HF-based etchant, the main component of which is a 5% HF solution by volume. Cu removal uses an H2SO4-based etchant, a first H2O2-based etchant, a ferric chloride-based etchant, a copper chloride-based etchant, and a persulfate-based etchant. TiW removal uses a second H2O2-based etchant, the main component of which is a 20% to 25% H2O2 solution by volume.

10. The method for preparing the stress-relieving pad structure for improving the thermal reliability of the TSV adapter board according to claim 6, characterized in that, The electroplating of Ni uses a nickel sulfamate solution system, with the main component being a 300 g / L to 450 g / L nickel sulfamate solution. The current density for Ni electroplating is 150 ± 10 A / m. 2 The Au electroplating process uses a potassium gold cyanide system, with the main component being an 8 g / L to 12 g / L potassium gold cyanide solution. The current density for Au electroplating is 20 ± 2 A / m. 2 .

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