Packaging method and packaging system

Abstract

This disclosure relates to the semiconductor field, providing a packaging method and packaging system. The packaging method includes: providing a first wafer, the first wafer including a plurality of chips and dicing channels located between adjacent chips, the front side of the chips having a first bonding surface; dicing the first wafer along the dicing channels to divide the first wafer into a plurality of chips; providing a second wafer, the front side of the second wafer having a second bonding surface; fixing the second wafer above the plurality of chips such that the second bonding surface is opposite to the first bonding surface; and performing a bonding process to bond the second bonding surface of the second wafer to the first bonding surface of the plurality of chips.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and in particular to a packaging method and packaging system. Background Technology

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer, and then the individual dies on the wafer are separated by dicing between the integrated circuits along scribe lines. These individual dies are typically packaged individually, in multi-chip modules, or in other types of packages.

[0003] In semiconductor packaging, chip-to-wafer hybrid bonding technology is the core technology for achieving high-performance three-dimensional heterogeneous integration.

[0004] Currently, there are two main methods for achieving chip-to-wafer hybrid bonding: one is to transfer the chip to a wafer carrier and then perform wafer-to-wafer hybrid bonding, which is called indirect chip-to-wafer hybrid bonding; the other is to directly bond the chip to the wafer, which is called direct chip-to-wafer hybrid bonding.

[0005] Compared to indirect chip-to-wafer hybrid bonding methods, direct chip-to-wafer hybrid bonding offers higher bonding precision and more flexible multilayer bonding processes. However, it is more sensitive to chip surface cleanliness and is more difficult to implement. Currently, it is not possible to achieve direct chip-to-wafer hybrid bonding using a complete and mature process flow. Summary of the Invention

[0006] This disclosure provides a packaging method and packaging system that can at least prevent impurities generated during the dicing process from affecting the bonding of the chip and the second wafer.

[0007] According to some embodiments of this disclosure, one aspect of this disclosure provides a packaging method, comprising: providing a first wafer, the first wafer including a plurality of chips and dicing channels located between adjacent chips, the front side of the chips having a first bonding surface; dicing the first wafer along the dicing channels to divide the first wafer into a plurality of chips; providing a second wafer, the second wafer having a second bonding surface formed on its front side; fixing the second wafer above the plurality of chips such that the second bonding surface is disposed opposite to the first bonding surface; and performing a bonding process to bond the second bonding surface of the second wafer to the first bonding surface of the plurality of chips.

[0008] In some embodiments, the first bonding surface includes a first interlayer insulating layer and a first bonding pad embedded in the first interlayer insulating layer, and the second bonding surface includes a second interlayer insulating layer and a second bonding pad embedded in the second interlayer insulating layer.

[0009] In some embodiments, bonding the second bonding surface of the second wafer to the first bonding surfaces of the plurality of chips includes: bonding the first interlayer insulating layer to the second interlayer insulating layer and the first bonding pad to the second bonding pad.

[0010] In some embodiments, the bonding process further includes: performing gas supply and gas extraction during the bonding process, wherein the gas supply direction is along the direction from the second wafer to the chip, and the gas extraction speed is greater than the gas supply speed.

[0011] In some embodiments, the process parameters for the gas transmission treatment include: introducing an inert gas or nitrogen, with a gas flow rate of 300–2000 sccm; and the process parameters for the gas extraction treatment include: a gas flow rate of 500–2500 sccm.

[0012] In some embodiments, the step of dicing the first wafer along the dicing track includes: providing a support stage and attaching a coating to the surface of the support stage; fixing the first wafer to the surface of the coating and dicing the first wafer along the dicing track to divide the first wafer into a plurality of the chips.

[0013] In some embodiments, the step of fixing the first wafer to the surface of the coating includes: contacting and fixing the first bonding surface to the coating.

[0014] In some embodiments, the process further includes performing a thinning process on the first wafer before dicing the first wafer into a plurality of the chips.

[0015] According to some embodiments of this disclosure, another aspect of this disclosure also provides a packaging system for performing the above-described packaging method, comprising: a wafer processing unit for processing a first wafer to cut the first wafer into multiple chips, wherein the front side of the chips has a first bonding surface; and a packaging unit for fixing a second wafer above the multiple chips and bonding the second bonding surface of the second wafer to the first bonding surface of the multiple chips.

[0016] In some embodiments, the wafer processing unit includes: a support stage for supporting the first wafer; and a dicing device for dicing the first wafer into a plurality of the chips.

[0017] In some embodiments, the packaging unit includes: a first fixing device for fixing the chip on the first wafer; an alignment device for aligning the second wafer with the chip, wherein the first bonding surface of the chip has a first alignment mark and the second bonding surface of the second wafer has a second alignment mark, the alignment device for detecting the first alignment mark and the second alignment mark, and controlling the first fixing device to align the first alignment mark and the second alignment mark; a second fixing device for fixing the second wafer, the second fixing device being located above the first fixing device; and a packaging chamber including an air inlet device and an air extraction device, wherein the first fixing device, the second fixing device, and the alignment device are all disposed within the packaging chamber.

[0018] The technical solution provided by the embodiments of this disclosure has at least the following advantages: the first wafer is divided to obtain multiple separate chips, and the second wafer is fixed above the chips so that the first bonding surface and the second bonding surface are arranged opposite to each other. Then the bonding process is performed so that impurities will not fall between the first bonding surface and the second bonding surface under the influence of gravity, thereby improving the reliability of the bonding between the chip and the second wafer. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart corresponding to an embodiment of the encapsulation method provided in this disclosure;

[0021] Figure 2 This is a schematic diagram of the structure of a first wafer provided in an embodiment of the present disclosure;

[0022] Figure 3 This is a schematic diagram of the structure of a support platform provided in an embodiment of the present disclosure;

[0023] Figure 4 This is a schematic diagram of a structure in which a first wafer is fixed on a support stage according to an embodiment of the present disclosure;

[0024] Figure 5This is a schematic diagram of the structure of a first wafer after thinning, provided in an embodiment of the present disclosure;

[0025] Figures 6-7 This is a schematic diagram of the structure before and after cutting a first wafer into multiple chips, according to an embodiment of the present disclosure;

[0026] Figure 8 This is a schematic diagram of the structure of multiple chips bonded to a second wafer according to an embodiment of the present disclosure;

[0027] Figure 9 This is a schematic diagram of a packaging system structure provided in one embodiment of the present disclosure. Detailed Implementation

[0028] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0029] In chip-to-wafer hybrid bonding technology, impurities are generated during the wafer dicing process. If these impurities are displaced between the bonding surfaces during the bonding process, they will affect the reliability of the packaged product during subsequent bonding processes. Therefore, improving bonding reliability has become an urgent problem to be solved.

[0030] Therefore, in order to solve the above problems, this disclosure proposes a new packaging method. The packaging method provided by this disclosure will be described below with reference to the accompanying drawings. Figure 1 A flowchart corresponding to an embodiment of the encapsulation method provided in this disclosure; Figure 2 This is a schematic diagram of the structure of a first wafer provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of the structure of a support platform provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram of a structure in which a first wafer is fixed on a support stage according to an embodiment of the present disclosure; Figure 5 This is a schematic diagram of the structure of a first wafer after thinning, provided in an embodiment of the present disclosure; Figures 6-7 This is a schematic diagram of the structure before and after cutting a first wafer into multiple chips, according to an embodiment of the present disclosure. Figure 8 This is a schematic diagram of the structure of multiple chips bonded to a second wafer according to an embodiment of the present disclosure; the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Step S100: Provide a first wafer 100, the first wafer 100 includes a plurality of chips 110 and dicing channels 150 located between adjacent chips 110, and a first bonding surface S1 is formed on the front side of the chip 110.

[0032] In some embodiments, reference Figures 1-2 The first wafer 100 contains a plurality of chips 110. Each chip 110 can be a single chip obtained by dicing the first wafer 100, that is, the part that implements the function of the first wafer 100. The first wafer 100 also includes dicing channels 150 that space the plurality of chips 110. The dicing channels 150 are located in the blank areas between the chips and are used for subsequent dicing processes to separate the chips 110 from the wafer.

[0033] S200: The first wafer 100 is cut along the dicing track 150 to divide the first wafer 100 into multiple chips 110.

[0034] In some embodiments, reference Figures 2-7 The step of dicing the first wafer 100 along the dicing groove 150 may include: providing a carrier stage 101 and attaching a coating 102 to the surface of the carrier stage 101; fixing the first wafer 100 to the surface of the coating 102; and dicing the first wafer 100 along the dicing groove 150 to divide the first wafer 100 into multiple chips 110. The dicing of the first wafer 100 may be achieved by mechanical cutting or laser cutting. Exemplarily, the carrier stage 101 may be a device for supporting the first wafer 100, thereby facilitating the operation of the first wafer 100 by fixing the first wafer 100 on the carrier stage 101.

[0035] In some embodiments, reference Figure 3 Before fixing the first wafer 100 onto the carrier stage 101, a coating film 102 is attached to the surface of the carrier stage 101. On the one hand, the coating film 102 can isolate the first wafer 100 from the carrier stage 101, thereby preventing dirt from the carrier stage 101 from contaminating the first wafer 100. On the other hand, the coating film 102 has a certain degree of adhesive stability, which can fix the wafer while preventing the wafer from breaking due to cutting stress. Moreover, during the cutting of the first wafer 100, some impurities will inevitably fall off the first wafer 100. By setting the coating film 102, when these impurities fall onto the surface of the coating film 102, these impurities can be fixed on the coating film 102, thereby preventing these impurities from shifting and falling onto the surface of the first bonding pad 130.

[0036] In some embodiments, the coating 102 can be a UV film or a blue film. For example, when the coating 102 is a UV film, the peel viscosity of the UV film decreases after being irradiated with ultraviolet light, thus facilitating the peeling of the diced chips 110 from the coating 102. However, the cost of the UV film is relatively high. When the coating 102 is a blue film, the cost of the blue film is lower, but the blue film may produce adhesive residue due to temperature variations. Generally speaking, a UV film is typically used for small-sized first wafers 100, while a blue film is typically used for large-sized first wafers 100.

[0037] In some embodiments, reference Figures 2-4 The step of fixing the first wafer 100 onto the surface of the coating 102 may include: contacting and fixing the first bonding surface S1 with the coating 102, that is, setting the first bonding surface S1 toward the direction close to the support stage 101, thereby protecting the first bonding surface S1. On the one hand, during the dicing process, the first bonding surface S1 is subjected to stress transmitted from the back side, which can reduce the possibility of the first bonding surface S1 breaking during the dicing process. On the other hand, setting the first bonding surface S1 toward the support stage 101 can shield the surface of the first bonding surface S1, thereby preventing impurities generated during the dicing process from falling onto the surface of the first bonding surface S1, thus preventing the first bonding surface S1 from being contaminated and improving the reliability of subsequent bonding.

[0038] In some embodiments, after the first wafer 100 is cut along the dicing path 150 and the chip 110 is peeled off from the coating 102, the peeled chip 110 is further cleaned to remove residual adhesive from the coating 102 on the surface of the chip 110.

[0039] In some embodiments, reference Figures 4-5 The first wafer 100 may further include a first substrate 120. Before dividing the first wafer 100 into multiple chips 110, a thinning process is performed on the first wafer 100 to obtain chips 110 of the required thickness. Exemplarily, the thinning process may be chemical mechanical polishing (CMP). By thinning a portion of the first substrate 120 of the first wafer 100 along the direction from the back side to the front side, the thickness of the first substrate 120 of the first wafer 100 can be reduced from t1 to t2. The thinning thickness can be adjusted according to the requirements of the packaged product to reduce the volume of the package structure. During the thinning process, since the first bonding surface S1 is in direct contact and fixed with the coating 102, the surface of the first substrate 120 can be directly thinned, thus eliminating the need to adjust the position of the first wafer 100 for the thinning process.

[0040] S300: Provides a second wafer 103, on the front side of which a second bonding surface S2 is formed.

[0041] In some embodiments, reference Figure 8 The second wafer 103 has a second bonding surface S2 formed on its front side. The second wafer 103 may also include multiple second chips. However, the second wafer 103 does not need to be cut. It can be understood that the process of bonding chip 110 to the second wafer 103 is the process of bonding chip 110 to the second chip in the second wafer 103.

[0042] In some embodiments, reference Figures 2-8 The first bonding surface S1 includes a first interlayer insulating layer 140 and a first bonding pad 130 embedded in the first interlayer insulating layer 140. The second bonding surface S2 includes a second interlayer insulating layer 133 and a second bonding pad 123 embedded in the second interlayer insulating layer 133. The first interlayer insulating layer 140 is a dielectric layer used to isolate adjacent first bonding pads 130, and the second interlayer insulating layer 133 is a dielectric layer used to isolate adjacent second bonding pads 123. The materials of the first interlayer insulating layer 140 and the second interlayer insulating layer 133 can be silicon dioxide (SiO2), organosilicon carbide (SiCOH), or fluorine-doped oxides. The materials of the first bonding pad 130 and the second bonding pad 123 can be copper (Cu) or aluminum (Al). The first bonding pad 130 and the second bonding pad 123 can also be microbumps or have a flat surface flush with the surface of the first interlayer insulating layer 140 and the second interlayer insulating layer 133 to meet the bonding process requirements, such as thermoforming.

[0043] In some embodiments, continue to refer to Figures 1-5 The chip 110 obtained after dicing the first wafer 100 may include a first substrate 120, with a first interlayer insulating layer 140 and a first bonding pad 130 located on the surface of the first substrate 120, i.e., a first bonding surface S1 is formed on the front side of the chip 110; the second wafer 103 may include a second substrate 113, with a second interlayer insulating layer 133 and a second bonding pad 123 located on the surface of the second substrate 113. Various circuit structures, such as transistor structures, word lines, and bit lines, can be formed within the first substrate 120 and the second substrate 113 to realize the functions of memory cells or logic circuits. For example, in a memory chip, word lines and bit lines can be used to address memory cells, while transistor structures can serve as the core part of the memory cell for storing data; in addition, other circuit modules, such as logic control circuits and input / output circuits, can be integrated within the first substrate 120 and the second substrate 113 to realize the complete logic operation function of the chip.

[0044] S400: The second wafer 103 is fixed above the plurality of chips 110 so that the second bonding surface S2 is positioned opposite to the first bonding surface S1.

[0045] In some embodiments, reference Figure 8 During the bonding process, the second wafer 103 can be fixed above the chip 110 so that the second bonding surface S2 is positioned opposite to the first bonding surface S1. Specifically, the second bonding pad 123 and the second interlayer insulating layer 133 are positioned opposite to the first bonding pad 130 and the second interlayer insulating layer 140 of the chip 110, that is, the first bonding surface S1 faces upward. Thus, during the bonding process, since the first bonding surface S1 faces upward, impurities generated during the dicing of the first wafer 100 will move away from the first bonding surface S1 under the action of gravity, thereby preventing impurities from falling between the first bonding surface S1 and the second bonding surface S2, thereby improving the reliability of the semiconductor structure after bonding.

[0046] S500: Perform a bonding process to bond the second bonding surface S2 of the second wafer 103 to the first bonding surface S1 of the plurality of chips 110.

[0047] In some embodiments, continue to refer to Figures 7-8 After the first wafer 100 is cut, multiple chips 110 can be conveyed to the chamber where the carrier stage 101 is located via a conveyor belt. After the chip 110 is picked up, its orientation can be adjusted so that the first bonding surface S1 is opposite to the second bonding surface S2 of the second wafer 103 fixed above the chip 110. During the bonding process, the chip 110 is moved until the first bonding surface S1 contacts the second bonding surface S2 of the second wafer 103, thereby bonding the chip 110 to the second wafer 103. Then, an annealing process is performed to complete the bonding.

[0048] Specifically, the first bonding surface S1 includes a first interlayer insulating layer 140 and a first bonding pad 130 embedded in the first interlayer insulating layer 140, and the second bonding surface S2 includes a second interlayer insulating layer 133 and a second bonding pad 123 embedded in the second interlayer insulating layer 133. Bonding the second bonding surface S2 of the second wafer 103 to the first bonding surface S1 of multiple chips 110 can include bonding the first interlayer insulating layer 140 of the first bonding surface S1 to the second interlayer insulating layer 133 of the second bonding surface S2, and bonding the first bonding pad 130 of the first bonding surface S1 to the second bonding pad 123 of the second bonding surface S2. That is, a hybrid bonding method can be used to bond the chips 110 to the second wafer 103. During the bonding process, the first interlayer insulating layer 140 of the first bonding surface S1 and the second bonding surface S2 can be bonded together at a first bonding temperature. 2. The second interlayer insulating layer 133 is bonded. Then, at the second bonding temperature, the first bonding pad 130 of the first bonding surface S1 and the second bonding pad 123 of the second bonding surface S2 are bonded. Since the coefficient of thermal expansion of the first bonding pad 130 and the second bonding pad 123 is greater than that of the first interlayer insulating layer 140 and the second interlayer insulating layer 133, the first bonding pad 130 and the second bonding pad 123 will continue to expand during the high-temperature annealing process, thereby filling the gap between the first bonding pad 130 and the second bonding pad 123, and achieving the final bonding. The first bonding temperature and the second bonding temperature can be the same or different, and both the first bonding temperature and the second bonding temperature can be in the range of 100℃~400℃.

[0049] In some embodiments, the bonding process may further include activating the surface of the chip 110 and the surface of the second wafer 103 using a plasma activation process to achieve hydrophilic oxide-oxide bonding, thereby improving the contact performance of the bonding interface.

[0050] In some embodiments, reference Figure 8 After bonding one chip 110 to the second wafer 103, the process also includes bonding multiple chips 110 to the second wafer 103 respectively, so as to finally complete the bonding of multiple chips 110 to the second wafer 103.

[0051] In some embodiments, reference Figure 8During the bonding process, gas delivery and extraction processes can also be performed. The gas delivery process involves airflow from the second wafer 103 towards the chip 110, while the extraction process can have a higher extraction speed than the delivery speed. Specifically, by performing gas delivery with the airflow direction from the second wafer 103 towards the chip 110, impurities are blown away from the first bonding surface S1. The extraction process also prevents excessive gas pressure in the accommodating chambers containing the chip 110 and the second wafer 103. Furthermore, the extraction process removes impurities blown away by the gas delivery process from the accommodating chambers containing the chip 110 and the second wafer 103. In addition, setting the extraction speed to be greater than the delivery speed of the gas delivery process maintains a negative pressure in the accommodating chambers containing the chip 110 and the second wafer 103, thereby maximizing the removal of impurities blown away by the gas delivery process from the accommodating chambers containing the chip 110 and the second wafer 103. During the dicing of the first wafer 100, particulate impurities generated during dicing will adhere to the sidewalls of the formed chip 110. The above-mentioned gas supply and gas extraction operations can effectively prevent particulate impurities generated during wafer dicing from falling between the first bonding surface S1 and the second bonding surface S2, thereby improving the reliability of bonding between the chip 110 and the second wafer 103.

[0052] On the other hand, the gas supply process can also purify the gas environment of the bonding process, thereby preventing the surfaces of the first bonding surface S1 and the second bonding surface S2 from being contaminated during the bonding process. For example, the gas introduced in the gas supply process can be an inert gas or nitrogen. For example, the inert gas can be helium or argon. Nitrogen has a lower cost and also has relatively stable chemical properties, which can improve the safety and reliability of the entire packaging method. In addition, the flow rate of the introduced gas can be in the range of 300 to 2000 sccm, and the flow rate of the extracted gas in the extraction process can be in the range of 500 to 2500 sccm. When the gas flow rate is less than 300 sccm, there may be a problem that the gas environment of the entire bonding process cannot be completely purified. When the gas flow rate is greater than 2000 sccm, there may be a waste of gas flow due to excessive gas flow, and it may also cause the chip 110 to shift due to excessive gas flow. As for the gas extraction process, if the gas extraction flow rate is too small, it may be impossible to ensure that all impurities are extracted from the containment chamber where the chip 110 and the second wafer 103 are located. If the gas extraction flow rate is too large, it will also increase the cost too much, resulting in a higher cost for the entire manufacturing process.

[0053] In this embodiment of the present disclosure, the first wafer 100 is divided to obtain a plurality of separate chips 110, and the second wafer 103 is fixed above the chips 110 so that the first bonding surface S1 and the second bonding surface S2 are arranged opposite to each other. Then the bonding process is performed so that impurities will not fall between the first bonding surface S1 and the second bonding surface S2 under the influence of gravity, thereby improving the reliability of the bonding between the chip 110 and the second wafer 103.

[0054] Another embodiment of this disclosure also provides a packaging system that can be used to perform the packaging methods in some or all of the above embodiments. Figure 9 This is a schematic diagram of a packaging system structure provided in one embodiment of the present disclosure. The following will describe another packaging system provided in one embodiment of the present disclosure with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to the above embodiments can be referred to the above embodiments, and will not be repeated hereafter.

[0055] In some embodiments, reference Figures 8-9 The packaging system 10 may include a wafer processing unit 20 for processing a first wafer 100 to cut the first wafer 100 into multiple chips 110, the front side of each chip 110 having a first bonding surface S1; and a packaging unit 30 for fixing a second wafer 103 above the multiple chips 110 and bonding the second bonding surface S2 of the second wafer 103 to the first bonding surface S1 of the multiple chips 110. Exemplarily, the wafer processing unit 20 may include a support stage 101 for supporting the first wafer; and a dicing device 111 for dicing the first wafer 100 into multiple chips 110. Exemplarily, the dicing device 111 may be a mechanical blade or a laser emitter. Mechanical blade cutting is less expensive, but it may cause chip 110 to chip or crack, resulting in product damage. Therefore, a buffer can be installed on the support stage 101 to provide additional support for the first wafer 100, thereby preventing the chip 110 from cracking after cutting. Laser cutting is suitable for thinner first wafers 100, which can reduce the stress on the first wafer 100 and reduce the probability of chip 110 chipping or cracking, thereby improving the yield of the cutting process. Furthermore, since the laser beam can be focused to a small spot size, complex cutting patterns can be achieved, and the chip 110 can be separated with minimal spacing.

[0056] In some embodiments, continue to refer to Figures 8-9The packaging unit 30 may include: a first fixing device 114 for fixing the chip 110 of the first wafer 100; an alignment device 105 for aligning the second wafer 103 with the chip 110, wherein the first bonding surface S1 of the chip 110 has a first alignment mark and the second bonding surface S2 of the second wafer S2 has a second alignment mark, the alignment device 105 for detecting the first alignment mark and the second alignment mark and controlling the first fixing device 114 to align the first alignment mark and the second alignment mark; a second fixing device 124 for fixing the second wafer 103, the second fixing device 124 being located above the first fixing device 114; and a packaging chamber 104, the packaging chamber 104 including an air inlet device 106 and an air extraction device 107, wherein the first fixing device 114, the second fixing device 124, and the alignment device 105 are all disposed within the packaging chamber 104. For example, the second fixing device 124 can be a vacuum adsorption platform or an electrostatic adsorption platform, and the second wafer 103 can be fixed by vacuum adsorption or electrostatic adsorption; the first fixing device 114 can be a vacuum chuck, and the chip 110 is fixed by the first fixing device 114 after entering the packaging chamber 104; wherein, the second fixing device 124 is located above the first fixing device 114, so that the second wafer can be fixed above the chip 110, thereby so that the second bonding surface S2 is opposite to the first bonding surface S1. In addition, by controlling the first fixing device 114 to move towards the second fixing device 124, the bonding of the second bonding surface S2 and the first bonding surface S1 can be completed, and the bonding of the chip 110 and the second wafer 103 can be completed by the annealing process.

[0057] Before bonding the chip 110 and the second wafer 103, the process includes aligning the chip 110 and the second wafer 103. For example, a plurality of first alignment marks and a plurality of second alignment marks can be respectively set on the first bonding surface S1 of the chip 110 and the second bonding surface S2 of the second wafer 103. The alignment device 105 can obtain the positions of the first alignment marks and the second alignment marks, and generate corresponding position information based on the positions of the first alignment marks and the second alignment marks. After obtaining the position information, the first fixing device 114 can adjust the corresponding position of the first fixing device 114 so that the first bonding surface S1 of the chip 110 and the second bonding surface S2 of the second wafer 103 are aligned, thereby improving the alignment accuracy and reliability of the bonding process.

[0058] It should be noted that, Figure 8The alignment device 105 shown is disposed between the chip 110 and the second wafer 103. In fact, it is only a diagram for the purpose of understanding the illustration. The alignment device 105 may be located between the chip 110 and the second wafer 103 when acquiring the first alignment mark and the second alignment mark, and may be removed from between the chip 110 and the second wafer 103 after acquisition is completed.

[0059] In some embodiments, an air intake device 106 is fixed to the top of the encapsulation chamber 104, i.e., the side of the second fixing device 124 away from the first fixing device 114, for supplying gas into the encapsulation chamber 104; and an air extraction device 107 is fixed to the bottom of the encapsulation chamber 104, i.e., the side of the first fixing device 114 away from the second fixing device 124, for extracting gas from the encapsulation device 104.

[0060] The inlet gas device 106 continuously supplies gas into the packaging chamber 104 during the bonding process to blow away impurities generated during the dicing of the first wafer 100 in a direction away from the first bonding surface S1, thereby preventing impurities from falling between the first bonding surface S1 and the second bonding surface S2, thus improving the reliability of bonding. The extraction gas device 107 continuously extracts gas from the packaging chamber 104 during the bonding process. The extraction gas device 107 can also extract impurities blown away by the inlet gas device 106 from the packaging chamber 104, thereby further preventing impurities from falling between the first bonding surface S1 and the second bonding surface S2. The extraction gas device 107 can be uniformly arranged below the first fixing device 114, so that the airflow during the extraction process is uniformly extracted in any direction, thereby preventing impurity particles from moving between chips, thus improving the reliability of bonding.

[0061] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A packaging method, characterized in that, include: A first wafer is provided, the first wafer including a plurality of chips and dicing channels located between adjacent chips, wherein a first bonding surface is formed on the front side of the chips; The first wafer is cut along the dicing path to divide the first wafer into a plurality of the chips; A second wafer is provided, wherein a second bonding surface is formed on the front side of the second wafer; The second wafer is fixed above the plurality of chips such that the second bonding surface is positioned opposite to the first bonding surface; A bonding process is performed to bond the second bonding surface of the second wafer to the first bonding surface of the plurality of chips.

2. The packaging method according to claim 1, characterized in that, The first bonding surface includes a first interlayer insulating layer and a first bonding pad embedded in the first interlayer insulating layer, and the second bonding surface includes a second interlayer insulating layer and a second bonding pad embedded in the second interlayer insulating layer.

3. The packaging method according to claim 2, characterized in that, Bonding the second bonding surface of the second wafer to the first bonding surface of the plurality of chips includes: The first interlayer insulating layer is bonded to the second interlayer insulating layer, and the first bonding pad is bonded to the second bonding pad.

4. The packaging method according to claim 1, characterized in that, The bonding process further includes: gas supply and gas extraction during the bonding process, wherein the gas supply direction is along the second wafer pointing towards the chip, and the gas extraction speed is greater than the gas supply speed.

5. The packaging method according to claim 4, characterized in that, The process parameters for the gas transmission treatment include: introducing inert gas or nitrogen, with a gas flow rate of 300–2000 sccm; and the process parameters for the gas extraction treatment include: a gas flow rate of 500–2500 sccm.

6. The packaging method according to claim 1, characterized in that, The step of dicing the first wafer along the dicing path includes: Provide a support platform, and attach a film to the surface of the support platform; The first wafer is fixed on the surface of the coating and cut along the dicing path to divide the first wafer into multiple chips.

7. The packaging method according to claim 6, characterized in that, The step of fixing the first wafer to the surface of the coating includes: contacting and fixing the first bonding surface to the coating.

8. The packaging method according to claim 1, characterized in that, Before dividing the first wafer into multiple chips, the process further includes: performing a thinning process on the first wafer.

9. A packaging system for performing the packaging method as described in any one of claims 1 to 8, characterized in that, include: A wafer processing unit is used to process a first wafer to cut the first wafer into multiple chips, wherein the front side of the chips has a first bonding surface; A packaging unit is used to fix a second wafer above a plurality of chips and to bond a second bonding surface of the second wafer to a first bonding surface of the plurality of chips.

10. The packaging system according to claim 9, characterized in that, The wafer processing unit includes: The support platform is used to support the first wafer; A dicing apparatus for dicing the first wafer into a plurality of the chips.

11. The packaging system according to claim 9, characterized in that, The packaging unit includes: A first fixing device is used to fix the chip of the first wafer; An alignment device is used to align the second wafer with the chip, wherein the first bonding surface of the chip has a first alignment mark and the second bonding surface of the second wafer has a second alignment mark. The alignment device is also used to detect the first alignment mark and the second alignment mark, and to control the first fixing device to align the first alignment mark and the second alignment mark. A second fixing device is used to fix the second wafer, and the second fixing device is located above the first fixing device; The encapsulation chamber includes an air inlet device and an air extraction device, and the first fixing device, the second fixing device, and the alignment device are all disposed within the encapsulation chamber.

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