Chip packaging structure, preparation method thereof and electronic device

Abstract

The embodiment of the application provides a chip packaging structure and a preparation method thereof and an electronic device, relates to the technical field of chip packaging, and is used for improving the problem of stress concentration at the gap between two adjacent chips in the chip packaging structure when the temperature changes. The chip packaging structure comprises a circuit structure, a first chip, a second chip, a filling layer and a plastic sealing layer. The first chip and the second chip are located on the same side of the circuit structure, and the first chip and the second chip have a gap therebetween. The first chip comprises a first chip corner, a second chip corner, a third chip corner and a fourth chip corner, and the second chip comprises a fifth chip corner, a sixth chip corner, a seventh chip corner and an eighth chip corner. The filling layer is located in the gap, and the filling layer wraps the first chip corner, the second chip corner, the fifth chip corner and the sixth chip corner. The plastic sealing layer is located on the side wall of the filling layer, the side wall of the first chip and the side wall of the second chip. The above chip packaging structure is applied to the electronic device, and the performance of the electronic device is improved.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip packaging structure and its fabrication method, and an electronic device. Background Technology

[0002] With the surge in demand for computing power from high-speed data communication and artificial intelligence, chip integration has been further improved, and multi-chip packaging technology has been widely adopted.

[0003] To further reduce chip costs and improve production efficiency, fan-out packaging structures have emerged. Multi-chip fan-out packaging structures arrange multiple chips horizontally side-by-side, encapsulating them with a molding compound that also fills the gaps between the chips. Because the coefficient of thermal expansion of the molding compound differs from that of the chips, stress concentration can easily occur at the gaps between adjacent chips when temperatures change, leading to chip damage. Summary of the Invention

[0004] This application provides a chip packaging structure and its fabrication method, as well as an electronic device, to improve the problem of stress concentration at the gap between two adjacent chips in the chip packaging structure when the temperature changes, thereby improving the reliability of the chip packaging structure and extending its service life.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a chip packaging structure is provided. The chip packaging structure includes a circuit structure, a first chip, a second chip, a fill layer, and a molding compound layer. The first chip and the second chip are located on the same side of the circuit structure, and a gap exists between the first chip and the second chip. The first chip includes a first chip corner, a second chip corner, a third chip corner, and a fourth chip corner near the gap, and the second chip includes a fifth chip corner, a sixth chip corner, a seventh chip corner, and an eighth chip corner near the gap. In the thickness direction of the chip packaging structure, the first chip corner and the second chip corner are both farther away from the circuit structure than the third chip corner and the fourth chip corner; the fifth chip corner and the sixth chip corner are both farther away from the circuit structure than the seventh chip corner and the eighth chip corner.

[0007] A filler layer is located within the gap and covers the first chip corner, the second chip corner, the fifth chip corner, and the sixth chip corner. A molding compound is located on the sidewalls of the filler layer, the sidewalls of the first chip, and the sidewalls of the second chip, and the molding compound is also located between the filler layer and the circuit structure, between the first chip and the circuit structure, and between the second chip and the circuit structure.

[0008] In the chip packaging structure provided in this application embodiment, a filling layer is provided in the gap between the first chip and the second chip. The material of the filling layer is different from that of the molding compound layer, so that the molding compound layer can fill only part of the gap or be completely outside the gap. When the temperature changes (including changes in the external ambient temperature and changes in the internal temperature caused by the heat generated by the operation of the first and second chips), even if the coefficient of thermal expansion of the molding compound layer differs significantly from that of the first chip, and the coefficient of thermal expansion of the molding compound layer differs significantly from that of the second chip, the stress exerted by the molding compound layer on the first and second chips at the gap can be small, or even non-existent. The filling layer can effectively protect the first and second chips.

[0009] Furthermore, the filler layer covers the first and second chip corners of the first chip near the gap, as well as the fifth and sixth chip corners of the second chip near the gap. In this way, the filler layer not only protects the sidewalls of the first chip near the gap, but also protects the first and second chip corners, mitigating stress concentration and preventing cracking at these corners. Similarly, the filler layer not only protects the sidewalls of the second chip near the gap, but also protects the fifth and sixth chip corners, mitigating stress concentration and preventing cracking at these corners.

[0010] In some embodiments, the filling layer also covers the third chip corner, the fourth chip corner, the seventh chip corner, and the eighth chip corner.

[0011] In this embodiment, the filling layer not only covers the first, second, fifth, and sixth chip corners, but also the third, fourth, seventh, and eighth chip corners. This allows the filling layer to protect not only the first and second chip corners of the first chip, but also the third and fourth chip corners of the first chip. Similarly, it protects not only the fifth and sixth chip corners of the second chip, but also the seventh and eighth chip corners of the second chip. The filling layer also helps to mitigate stress concentration at the third, fourth, seventh, and eighth chip corners, preventing cracking at these corners.

[0012] In some embodiments, the Young's modulus of the filler layer is less than that of the molding compound layer, and / or the coefficient of thermal expansion of the filler layer is less than that of the molding compound layer.

[0013] When the Young's modulus of the filler layer is less than that of the molding compound layer, the filler layer is more prone to deformation than the molding compound layer. Even if the temperature changes (including changes in the external ambient temperature and changes in the internal temperature caused by the heat generated by the first and second chips), and the volumes of the first and second chips and the filler layer change, the filler layer can still deform under the action of the first and second chips. This relieves the stress exerted by the first and second chips on the gap, alleviates the stress concentration problem at the gap, and can protect the first and second chips on both sides of the gap. This is beneficial to improving the reliability of the chip packaging structure and extending the service life of the chip packaging structure.

[0014] When the coefficient of thermal expansion of the filler layer is less than that of the molding compound layer, the filler layer deforms less than the molding compound layer under the same temperature difference. Thus, even with temperature changes, the dimensional change of the filler layer in the gap is smaller, and the stress exerted by the filler layer on the first and second chips is also smaller. This effectively alleviates stress concentration at the gap, protects the first and second chips, improves the reliability of the chip package structure, and extends the service life of the chip package structure.

[0015] When the Young's modulus of the filler layer is less than that of the molding compound layer, and the coefficient of thermal expansion of the filler layer is also less than that of the molding compound layer, the stress exerted by the filler layer on the first and second chips is smaller. Furthermore, the stress exerted by the first and second chips on the filler layer can be partially released through the deformation of the filler layer. When the temperature changes, the filler layer can effectively alleviate the stress concentration problem at the gap between the first and second chips, thus protecting both chips.

[0016] It is understood that the filling layer provided in the gaps in this application embodiment is unlikely to affect the stress distribution in other areas of the chip package structure, nor is it likely to affect the packaging effect of the chip package structure. In other words, the filling layer provided in this application embodiment can improve the reliability of the chip package structure and extend its service life without affecting the overall stability of the device.

[0017] In some embodiments, in the thickness direction of the chip package structure, the size of the filling layer is greater than or equal to the size of the gap.

[0018] In this way, the filler layer can fill the gap, so that the molding compound layer is completely outside the gap. This avoids the problem of stress concentration at the gap caused by the mismatch of the thermal expansion coefficients between the molding compound layer and the first and second chips, thus effectively protecting the first and second chips.

[0019] In some embodiments, in the direction of extension of the gap, the filling layer includes a first extension surface and a second extension surface disposed opposite to each other; both the first extension surface and the second extension surface are curved surfaces.

[0020] In this way, the first and second extension surfaces can transfer the stress at the corners of the first and second chips to the first and second extension surfaces. Since both the first and second extension surfaces are curved surfaces, they can effectively disperse the stress, thereby further improving the stress concentration problem at the corners of the first and second chips.

[0021] In some embodiments, in the extending direction of the gap, both the first extending surface and the second extending surface protrude in a direction away from the gap.

[0022] In some embodiments, in the extending direction of the gap, both the first extending surface and the second extending surface are recessed toward the gap.

[0023] In some embodiments, the material of the filler layer includes an underfill adhesive or polyimide.

[0024] At this time, the Young's modulus of the filler layer is less than that of the molding compound layer. The filler layer is more prone to deformation than the molding compound layer. Even if the temperature changes (including changes in the external ambient temperature and changes in the internal temperature caused by the heat generated by the first and second chips), and the volumes of the first and second chips and the filler layer change, the filler layer can still deform under the action of the first and second chips. This relieves the stress exerted by the first and second chips on the gap, alleviates the problem of stress concentration in the gap, and can protect the first and second chips on both sides of the gap. This is beneficial to improving the reliability of the chip packaging structure and extending the service life of the chip packaging structure.

[0025] In some embodiments, the circuit structure includes a redistribution layer and an electrical connection structure; the electrical connection structure is located on the side of the redistribution layer away from the first chip. The first chip has a first conductive bump located on the surface of the first chip near the circuit structure, and the second chip has a second conductive bump located on the surface of the second chip near the circuit structure; the first conductive bump and the second conductive bump penetrate the molding compound and are connected to the redistribution layer.

[0026] Secondly, a method for fabricating a chip package structure is provided. The method includes: placing a first chip and a second chip on a carrier substrate; a gap exists between the first chip and the second chip. The first chip includes a first chip corner, a second chip corner, a third chip corner, and a fourth chip corner near the gap; the second chip includes a fifth chip corner, a sixth chip corner, a seventh chip corner, and an eighth chip corner near the gap; in the thickness direction of the chip package structure, the first chip corner and the second chip corner are both closer to the carrier substrate than the third chip corner and the fourth chip corner; the fifth chip corner and the sixth chip corner are both farther from the carrier substrate than the seventh chip corner and the eighth chip corner.

[0027] A filler layer is formed in the gap. The filler layer covers the first chip corner, the second chip corner, the fifth chip corner, and the sixth chip corner.

[0028] A molding compound is formed on the side of the filler layer, the first chip, and the second chip away from the carrier. The molding compound is also located on the sidewalls of the filler layer, the first chip, and the second chip.

[0029] A circuit structure is formed on the side of the encapsulation layer away from the carrier board.

[0030] In some embodiments, the Young's modulus of the filler layer is less than that of the molding compound layer, and / or the coefficient of thermal expansion of the filler layer is less than that of the molding compound layer.

[0031] In some embodiments, the filling layer also covers the third chip corner, the fourth chip corner, the seventh chip corner, and the eighth chip corner.

[0032] In some embodiments, in the direction of extension of the gap, the filling layer includes a first extension surface and a second extension surface disposed opposite to each other; both the first extension surface and the second extension surface are curved surfaces.

[0033] In some embodiments, in the extending direction of the gap, both the first extending surface and the second extending surface protrude in a direction away from the gap.

[0034] In some embodiments, in the extending direction of the gap, both the first extending surface and the second extending surface are recessed toward the gap.

[0035] In some embodiments, forming a filling layer in the gap includes: forming a filling layer in the gap using a dispensing process.

[0036] In some embodiments, forming a filler layer in the gap includes: filling one end of the gap with adhesive; heating the carrier plate and the adhesive to extend the adhesive into the gap; and curing the adhesive to form a filler layer.

[0037] In some embodiments, the preparation method further includes cleaning the sidewalls of the first chip and the second chip, as well as the surface of the carrier plate facing the gap, to enhance the hydrophilicity of the sidewalls of the first chip and the second chip, and the hydrophilicity of the surface of the carrier plate facing the gap.

[0038] In some embodiments, the first chip has a first conductive bump, and the second chip has a second conductive bump, wherein the first conductive bump is located on a surface of the first chip away from the carrier, and the second conductive bump is located on a surface of the second chip away from the carrier. The fabrication method further includes: grinding the molding layer until the surfaces of the first conductive bump and the second conductive bump away from the carrier are exposed.

[0039] Thirdly, an electronic device is provided. This electronic device includes a circuit board, a chip packaging structure provided in the above embodiments, or a chip packaging structure prepared by the preparation method provided in the above embodiments. The chip packaging structure is located on the circuit board and is electrically connected to the circuit board.

[0040] The technical effects of any of the design methods in the second and third aspects can be found in the technical effects of different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0042] Figure 1 A schematic diagram of a fan-out chip packaging structure provided for related technologies;

[0043] Figure 2 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0044] Figure 3 This is a top view schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0045] Figure 4 This is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0046] Figure 5A This is a top view schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0047] Figure 5B A top view schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0048] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0049] Figure 7 A flowchart illustrating a method for fabricating a chip packaging structure provided in this application embodiment;

[0050] Figure 8 This is a schematic diagram of the chip packaging structure during fabrication corresponding to step S100 provided in the embodiments of this application;

[0051] Figure 9 This is a top view of the chip packaging structure during fabrication corresponding to step S100 provided in the embodiments of this application;

[0052] Figure 10 This is a schematic diagram of the chip packaging structure during fabrication corresponding to step S200 provided in the embodiments of this application;

[0053] Figure 11 A flowchart illustrating another method for fabricating a chip packaging structure provided in this application embodiment;

[0054] Figure 12 A flowchart illustrating another method for fabricating a chip packaging structure provided in this application embodiment;

[0055] Figure 13 A flowchart illustrating another method for fabricating a chip packaging structure provided in this application embodiment;

[0056] Figure 14 This is a schematic diagram of the chip packaging structure during fabrication corresponding to step S300 provided in the embodiments of this application;

[0057] Figure 15 This is a schematic diagram of the chip packaging structure during fabrication corresponding to step S301 provided in the embodiments of this application;

[0058] Figure 16 This is a schematic diagram of the chip packaging structure during fabrication corresponding to step S400 provided in the embodiments of this application;

[0059] Figure 17 This is a schematic diagram of the chip packaging structure during fabrication corresponding to another step S200 provided in an embodiment of this application;

[0060] Figure 18 This is a top view of the chip packaging structure during fabrication, corresponding to step S200 provided in the embodiments of this application. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0062] In the following embodiments of this application, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0063] In the embodiments of this application, "upper", "lower", "left" and "right" are not limited to the orientation of the components in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0064] In this application, unless the context otherwise requires, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to," throughout the specification and claims. In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0065] In embodiments of this application, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the specified value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the specified quantity (i.e., the limitations of the measurement system).

[0066] Exemplary embodiments are described in this application with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0067] With the surge in demand for computing power from high-speed data communication and artificial intelligence, chip integration has further increased, leading to the widespread adoption of multi-chip packaging technology. To further reduce chip costs and improve production efficiency, fan-out packaging structures have emerged.

[0068] Figure 1 A fan-out chip package structure is shown. For example... Figure 1 As shown, in a fan-out chip package structure, multiple chips are arranged horizontally side-by-side, with a molding compound covering the chips and filling the gaps between any two adjacent chips. The circuit structure is disposed on the molding compound and connected to the multiple chips.

[0069] Because the coefficient of thermal expansion of the molding compound differs significantly from that of the chip, stress concentration can easily occur at the gap between adjacent chips during temperature changes (e.g., during temperature cycling in reliability testing). This mismatch in thermal expansion coefficients severely impacts the chip's structural stability. In particular, when stress concentrates at the chip corners on either side of the gap, it can easily lead to cracks at the chip corners, affecting chip reliability.

[0070] Based on this, this application provides a chip packaging structure 100. Figure 2 This is a schematic diagram of a chip packaging structure 100 provided in an embodiment of this application. Figure 2 As shown, the chip package structure 100 may include a first chip 10, a second chip 20, a fill layer 30, a molding layer 40, and a circuit structure 50.

[0071] In this circuit structure 50, the first chip 10 and the second chip 20 are located on the same side, and a gap L exists between them. The first chip 10 includes a first chip corner J1, a second chip corner J2, a third chip corner J3, and a fourth chip corner J4 near the gap L. The second chip 20 includes a fifth chip corner J5, a sixth chip corner J6, a seventh chip corner J7, and an eighth chip corner J8 near the gap L. In the thickness direction Z of the chip package structure 50, the first chip corner J1 and the second chip corner J2 are both farther away from the circuit structure 50 than the third chip corner J3 and the fourth chip corner J4. The fifth chip corner J5 and the sixth chip corner J6 are both farther away from the circuit structure 50 than the seventh chip corner J7 and the eighth chip corner J8.

[0072] like Figure 2 As shown, in the thickness direction Z of the chip package structure 100, the first chip corner J1 can be located on the side away from the circuit structure 50 of the third chip corner J3, the second chip corner J2 can be located on the side away from the circuit structure 50 of the fourth chip corner J4, the fifth chip corner J5 can be located on the side away from the circuit structure 50 of the seventh chip corner J7, and the sixth chip corner J6 can be located on the side away from the circuit structure 50 of the eighth chip corner J8.

[0073] In some examples, both the first chip 10 and the second chip 20 can be bare dies.

[0074] In some examples, both the first chip 10 and the second chip 20 can be logic chips. In other examples, both the first chip 10 and the second chip 20 can be memory chips. In still other examples, one of the first chip 10 and the second chip 20 is a logic chip, and the other is a memory chip.

[0075] In some examples, both the first chip 10 and the second chip 20 can be a single chip. In other examples, both the first chip 10 and the second chip 20 can include multiple chips stacked in three dimensions, where three-dimensional stacking as described herein refers to stacking along the thickness direction of the chip package structure.

[0076] It is understood that the chip package structure 100 may include only the first chip 10 and the second chip 20, or it may include three or more chips, with any two adjacent chips serving as the first chip 10 and the second chip 20.

[0077] The filling layer 30 is located in the gap L, and the filling layer 30 covers the first chip corner J1, the second chip corner J2, the fifth chip corner J5 and the sixth chip corner J6.

[0078] Figure 3This is a top view schematic diagram of the chip packaging structure 100 provided in an embodiment of this application. The diagram is provided to clearly illustrate the positional relationship between the filling layer 30, the first chip 10, and the second chip 20. Figure 3 The circuit structure 50 is not shown in the figure.

[0079] like Figure 3 As shown, the first chip 10 includes a first sidewall S1, a second sidewall S2, and a third sidewall S3, and the second chip 20 includes a fourth sidewall S4, a fifth sidewall S5, and a sixth sidewall S6. The first sidewall S1 and the fourth sidewall S4 are positioned opposite each other, defining a gap L. The second sidewall S2 and the third sidewall S3 are positioned opposite each other and are both connected to the first sidewall S1. The fifth sidewall S5 and the sixth sidewall S6 are positioned opposite each other and are both connected to the fourth sidewall S4.

[0080] When the filling layer 30 wraps the first chip corner J1, the filling layer 30 extends from the first sidewall S1 to the third sidewall S3; when the filling layer 30 wraps the second chip corner J2, the filling layer 30 extends from the first sidewall S1 to the second sidewall S2; when the filling layer 30 wraps the fifth chip corner J5, the filling layer 30 extends from the fourth sidewall S4 to the fifth sidewall S5; when the filling layer 30 wraps the sixth chip corner J6, the filling layer 30 extends from the fourth sidewall S4 to the sixth sidewall S6.

[0081] The molding layer 40 is located on the sidewall of the filling layer 30, the sidewall of the first chip 10, and the sidewall of the second chip 20. The molding layer 40 is also located between the filling layer 30 and the circuit structure 50, between the first chip 10 and the circuit structure 50, and between the second chip 20 and the circuit structure 50.

[0082] In some examples, the material of the encapsulation layer 40 may include an encapsulating polymer (MUF). The encapsulating polymer (MUF) may include silica (SiO2), epoxy resin, hardener, flame retardant, catalyst, etc.

[0083] The molding compound 40 protects the first chip 10 and the second chip 20 from mechanical impact damage and provides structural support. Simultaneously, the molding compound 40 also provides insulation, sealing, moisture protection, corrosion resistance, and dust protection.

[0084] In the chip packaging structure 100 provided in this application embodiment, a filling layer 30 is provided in the gap L between the first chip 10 and the second chip 20. The material of the filling layer 30 is different from the material of the molding compound 40, so that the molding compound 40 can fill only part of the gap L or be completely outside the gap L. When the temperature changes (including changes in the external ambient temperature and changes in the internal temperature caused by the heat generated by the operation of the first and second chips), even if the coefficient of thermal expansion of the molding compound 40 differs greatly from that of the first chip 10 and the second chip 20, the stress exerted by the molding compound 40 on the first chip 10 and the second chip 20 at the gap L can be small, or even no stress can be exerted on the first chip 10 or the second chip 20. The filling layer 30 can effectively protect the first chip 10 and the second chip 20.

[0085] Furthermore, the filler layer 30 covers the first chip corner J1 and the second chip corner J2 of the first chip 10 near the gap L, as well as the fifth chip corner J5 and the sixth chip corner J6 of the second chip 20 near the gap L. In this way, the filler layer 30 not only protects the sidewalls of the first chip 10 near the gap L, but also protects the first chip corner J1 and the second chip corner J2 of the first chip 10, mitigating stress concentration at these points and preventing cracking. Similarly, the filler layer 30 not only protects the sidewalls of the second chip 20 near the gap L, but also protects the fifth chip corner J5 and the sixth chip corner J6 of the second chip 20, mitigating stress concentration at these points and preventing cracking.

[0086] In some embodiments, such as Figure 2 As shown, the first chip 10 may have a first conductive bump 11, which is located on the surface of the first chip 10 near the circuit structure 50. The second chip 20 may have a second conductive bump 21, which is located on the surface of the second chip 20 near the circuit structure 50. Both the first conductive bump 11 and the second conductive bump 21 penetrate the molding compound 40. The first chip 10 can be connected to the circuit structure 50 through the first conductive bump 11, and the second chip 20 can be connected to the circuit structure 50 through the second conductive bump 21.

[0087] For example, the first conductive bump 11 and the second conductive bump 21 can be metal pillars (e.g., copper pillars).

[0088] For example, the first chip 10 may include a plurality of first conductive bumps 11, and the second chip 20 may include a plurality of second conductive bumps 21. In this embodiment, the number of first conductive bumps 11 and second conductive bumps 21 is not limited and can be designed according to actual needs.

[0089] In some examples, such as Figure 2 As shown, the circuit structure 50 may include a redistribution layer (RDL) 51 and an electrical connection structure 52.

[0090] For example, the redistribution layer 51 may include multiple layers of conductive traces spaced apart by multiple insulating layers. The redistribution layer 51 connects the first chip 10 and the second chip 20, thereby rerouting the signals of the first chip 10 and the second chip 20 to locations suitable for external connections, allowing the first chip 10 and the second chip 20 to adapt to different package forms. Applying the redistribution layer 51 to the chip package structure 100 can improve signal integrity and integration density.

[0091] For example, the electrical connection structure 52 may include a plurality of solder balls, such as a ball grid array (BGA) or a plurality of metal pillars.

[0092] In the case where the first chip 10 includes a first conductive bump 11 and the second chip 20 includes a second conductive bump 21, the first conductive bump 11 and the second conductive bump 21 can penetrate the molding compound 40 and be connected to the redistribution layer 51 in the circuit structure 50.

[0093] In some embodiments, such as Figure 2 As shown, the filling layer 30 not only wraps the first chip corner J1, the second chip corner J2, the fifth chip corner J5 and the sixth chip corner J6, but also wraps the third chip corner J3, the fourth chip corner J4, the seventh chip corner J7 and the eighth chip corner J8.

[0094] Continue reading Figure 3 When the filling layer 30 wraps the third chip corner J3, the filling layer 30 extends from the first sidewall S1 to the third sidewall S3; when the filling layer 30 wraps the fourth chip corner J4, the filling layer 30 extends from the first sidewall S1 to the second sidewall S2; when the filling layer 30 wraps the seventh chip corner J7, the filling layer 30 extends from the fourth sidewall S4 to the fifth sidewall S5; when the filling layer 30 wraps the eighth chip corner J8, the filling layer 30 extends from the fourth sidewall S4 to the sixth sidewall S6.

[0095] Figure 4 This is a schematic diagram of another chip packaging structure 100 provided in an embodiment of this application. (See attached diagram.) Figure 4As shown, when the filling layer 30 wraps the third chip corner J3 and the fourth chip corner J4, the filling layer 30 extends not only from the first sidewall S1 to the second sidewall S2 and the third sidewall S3, but also from the first sidewall S1, the second sidewall S2 and the third sidewall S3 to the surface of the first chip 10 near the circuit structure 50; similarly, when the filling layer 30 wraps the seventh chip corner J7 and the eighth chip corner J8, the filling layer 30 extends not only from the fourth sidewall S4 to the fifth sidewall S5 and the sixth sidewall S6, but also from the fourth sidewall S4, the fifth sidewall S5 and the third sidewall S3 to the surface of the second chip 20 near the circuit structure 50.

[0096] In this embodiment, the filling layer 30 not only wraps the first chip corner J1, the second chip corner J2, the fifth chip corner J5, and the sixth chip corner J6, but also wraps the third chip corner J3, the fourth chip corner J4, the seventh chip corner J7, and the eighth chip corner J8. This allows the filling layer 30 to protect not only the first chip corner J1 and the second chip corner J2 of the first chip 10, but also the third chip corner J3 and the fourth chip corner J4 of the first chip 10. Similarly, the filling layer 30 can protect not only the fifth chip corner J5 and the sixth chip corner J6 of the second chip 20, but also the seventh chip corner J7 and the eighth chip corner J8 of the second chip 20. The filling layer 30 can also improve the stress concentration at the third chip corner J3, the fourth chip corner J4, the seventh chip corner J7, and the eighth chip corner J8, preventing the third chip corner J3, the fourth chip corner J4, the seventh chip corner J7, and the eighth chip corner J8 from cracking.

[0097] In some embodiments, such as Figure 4 As shown, in the thickness direction Z of the chip package structure 100, the size d1 of the filling layer 30 can be greater than or equal to the size d2 of the gap L. Figure 4 The following example illustrates the situation where, in the thickness direction Z, the dimension d1 of the filling layer 30 is greater than the dimension d2 of the gap L.

[0098] In this way, the filling layer 30 can fill the gap L, so that the molding compound 40 is completely outside the gap L. This avoids the problem of stress concentration at the gap L caused by the mismatch of the thermal expansion coefficients between the molding compound and the first chip and the second chip when the molding compound 40 is filled in the gap L, thus effectively protecting the first chip 10 and the second chip 20.

[0099] See Figure 4In the thickness direction Z of the chip package structure 100, if the size of the filling layer 30 is larger than the size of the gap L, the filling layer 30 can also extend to the surface of the first chip 10 near the circuit structure 50 and the surface of the second chip 20 near the circuit structure 50, thereby protecting the edges of the first chip 10 and the second chip 20 near the gap L and further ensuring the yield of the first chip 10 and the second chip 20.

[0100] In some embodiments, the Young's modulus of the filler layer 30 is less than that of the molding compound 40, and / or the coefficient of thermal expansion of the filler layer 30 is less than that of the molding compound 40.

[0101] It is understood that the above-mentioned "the Young's modulus of the filler layer 30 is less than the Young's modulus of the molding compound 40, and / or the coefficient of thermal expansion of the filler layer 30 is less than the coefficient of thermal expansion of the molding compound 40" includes the following cases: the Young's modulus of the filler layer 30 is less than the Young's modulus of the molding compound 40, but the coefficient of thermal expansion of the filler layer 30 is greater than the coefficient of thermal expansion of the molding compound 40; the Young's modulus of the filler layer 30 is greater than the Young's modulus of the molding compound 40, but the coefficient of thermal expansion of the filler layer 30 is less than the coefficient of thermal expansion of the molding compound 40; and the Young's modulus of the filler layer 30 is less than the Young's modulus of the molding compound 40, and the coefficient of thermal expansion of the filler layer 30 is less than the coefficient of thermal expansion of the molding compound 40.

[0102] When the Young's modulus of the filler layer 30 is less than that of the molding compound layer 40, the filler layer 30 is more prone to deformation than the molding compound layer 40. Even if the temperature changes and the volumes of the first chip 10, the second chip 20, and the filler layer 30 change, the filler layer 30 can still deform under the action of the first chip 10 and the second chip 20, thereby relieving the stress applied by the first chip 10 and the second chip 20 to the gap L, alleviating the stress concentration problem in the gap L, and thus protecting the first chip 10 and the second chip 20 on both sides of the gap L. This is beneficial to improving the reliability of the chip packaging structure 100 and extending the service life of the chip packaging structure 100.

[0103] When the coefficient of thermal expansion of the filler layer 30 is less than that of the molding compound layer 40, the deformation of the filler layer 30 is smaller than that of the molding compound layer 40 under the same temperature difference. Thus, even with temperature changes, the dimensional change of the filler layer 30 located in the gap L is smaller, and the stress exerted by the filler layer 30 on the first chip 10 and the second chip 20 is also smaller. This effectively alleviates the stress concentration problem at the gap L, protects the first chip 10 and the second chip 20, improves the reliability of the chip package structure 100, and extends the service life of the chip package structure 100.

[0104] When the Young's modulus of the filler layer 30 is less than that of the molding compound layer 40, and the coefficient of thermal expansion of the filler layer 30 is less than that of the molding compound layer 40, the stress exerted by the filler layer 30 on the first chip 10 and the second chip 20 is smaller. The stress exerted by the first chip 10 and the second chip 20 on the filler layer 30 can also be partially released through the deformation of the filler layer 30. When the temperature changes, the filler layer 30 can effectively alleviate the stress concentration problem at the gap L between the first chip 10 and the second chip 20, protecting both chips.

[0105] It is understood that in this embodiment, a filling layer 30 is provided in the gap L. The filling layer 30 only changes the coefficient of thermal expansion (CTE) relationship at the gap L between the first chip 10 and the second chip 20. The filling layer 30 is unlikely to affect the stress distribution in other areas of the chip package structure 100, nor is it likely to affect the packaging effect of the chip package structure 100. In other words, the filling layer 30 provided in this embodiment can improve the reliability of the chip package structure 100 and extend its service life without affecting the overall stability of the device.

[0106] Figure 5A This is a top view schematic diagram of another chip packaging structure 100 provided in an embodiment of this application. Figure 5B This is a top view schematic diagram of another chip packaging structure 100 provided in an embodiment of this application. The diagram is shown to illustrate the positional relationship between the filling layer 30, the first chip 10, and the second chip 20, as well as the shape of the filling layer 30. Figure 5A and Figure 5B The circuit structure 50 is not shown in the diagram.

[0107] like Figure 3 , Figure 5A and Figure 5B As shown, in some embodiments, in the extension direction X of the gap L, the filling layer 30 includes a first extension surface S31 and a second extension surface S32 disposed opposite to each other. Both the first extension surface S31 and the second extension surface S32 are curved surfaces.

[0108] In this way, the first extension surface S31 and the second extension surface S32 can transfer the stress at the corner of the first chip 10 and the second chip 20 to the first extension surface S31 and the second extension surface S32. Since the first extension surface S31 and the second extension surface S32 are both curved surfaces, they can effectively disperse the stress, thereby further improving the stress concentration problem at the corner of the first chip 10 and the second chip 20.

[0109] During the preparation of filler layer 30, when the amount of filler adhesive used to form filler layer 30 is moderate or excessive, such as Figure 3 and Figure 5B As shown, in the extension direction X of the gap L, the first extension surface S31 and the second extension surface S32 of the filling layer 30 both protrude in a direction away from the gap L.

[0110] It is understandable that, such as Figure 3 As shown, when the amount of filler adhesive used to form the filler layer 30 is large, the protrusion of the first extension surface S31 and the second extension surface S32 of the filler layer 30 is greater. Figure 5B As shown, when the amount of filler adhesive used to form the filler layer 30 is moderate, the protrusion of the first extension surface S31 and the second extension surface S32 of the filler layer 30 is relatively small.

[0111] like Figure 3 As shown, when the amount of filler adhesive used to form the filler layer 30 is large, the angle between the first extension surface S31 and the second extension surface S32 and the sidewall of the first chip 10 is large. Figure 5B As shown, when the amount of filler adhesive used to form the filler layer 30 is appropriate, the angle between the first extension surface S31 and the second extension surface S32 and the sidewall of the first chip 10 is small.

[0112] Similarly, when the amount of filler adhesive used to form the filler layer 30 is large, the angle between the first extension surface S31 and the second extension surface S32 and the sidewall of the second chip 20 is large; when the amount of filler adhesive used to form the filler layer 30 is moderate, the angle between the first extension surface S31 and the second extension surface S32 and the sidewall of the second chip 20 is small.

[0113] During the preparation of filler layer 30, when the amount of filler adhesive used to form filler layer 30 is small, such as Figure 5A As shown, in the extension direction X of the gap L, the first extension surface S31 and the second extension surface S32 of the filling layer 30 are both recessed towards the gap L.

[0114] In some embodiments, the material of the filler layer 30 may include underfill (UF) or polyimide (PI).

[0115] At this time, the Young's modulus of the filling layer 30 is less than that of the molding layer 40. The filling layer 30 is more prone to deformation than the molding layer 40. Even if the temperature changes and the volumes of the first chip 10, the second chip 20, and the filling layer 30 change, the filling layer 30 can still deform under the action of the first chip 10 and the second chip 20, thereby relieving the stress applied by the first chip 10 and the second chip 20 to the gap L, alleviating the stress concentration problem in the gap L, and thus protecting the first chip 10 and the second chip 20 on both sides of the gap L. This is beneficial to improving the reliability of the chip packaging structure 100 and extending the service life of the chip packaging structure 100.

[0116] This application provides an electronic device. Figure 6 This is a schematic diagram of the structure of an electronic device 1000 provided in an embodiment of this application. Figure 6 The electronic device 1000 may include a chip package structure 100 and a circuit board 200. The chip package structure 100 is located on the circuit board 200 and is electrically connected to the circuit board 200. The chip package structure 100 can achieve signal interconnection with other chip package structures or other electronic modules on the circuit board 200 through the circuit board 200. The circuit board 200 may be a printed circuit board (PCB).

[0117] For example, such as Figure 6 As shown, the electronic device 1000 may include multiple chip package structures 100, all of which are disposed on the circuit board 200.

[0118] When the circuit structure of the chip package structure 100 includes a redistribution layer 51 and an electrical connection structure 52, the chip package structure 100 can be connected to the circuit board 200 through the electrical connection structure 52.

[0119] Electronic devices include consumer electronics, home electronics, automotive electronics, financial electronics, servers, and workstations. Consumer electronics include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearables (e.g., smartwatches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, and drones. Home electronics include smart locks, televisions, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuums). Automotive electronics include car navigation systems and car DVD players. Financial electronics include ATMs and self-service electronic devices.

[0120] This application provides a method for fabricating a chip packaging structure. Figure 7 A flowchart illustrating the preparation method provided in the embodiments of this application. Figure 7 As shown, the preparation method includes steps S100 to S400.

[0121] S100, such as Figure 8 and Figure 9 As shown, a first chip 10 and a second chip 20 are disposed on a carrier 101. The first chip 10 and the second chip 20 have a gap L.

[0122] For example, the carrier 101 may be a glass carrier, a silicon wafer, or other board structure that can carry a chip.

[0123] In some examples, the first chip 10 and the second chip 20 can be arranged on the carrier board 101 by die recombination.

[0124] In some examples, after the first chip 10 and the second chip 20 are placed on the carrier plate 101, a high-temperature baking method can be used to increase the adhesion between the first chip 10 and the carrier plate 101, and to increase the adhesion between the second chip 20 and the carrier plate 101, so as to avoid the problem of displacement of the first chip 10 and the second chip 20 during subsequent fabrication.

[0125] In some examples, both the first chip 10 and the second chip 20 can be bare dies.

[0126] In some examples, both the first chip 10 and the second chip 20 can be logic chips. In other examples, both the first chip 10 and the second chip 20 can be memory chips. In still other examples, one of the first chip 10 and the second chip 20 is a logic chip, and the other is a memory chip.

[0127] See Figure 8 The first chip 10 includes a first chip corner J1, a second chip corner J2, a third chip corner J3, and a fourth chip corner J4 near the gap L. The second chip 20 includes a fifth chip corner J5, a sixth chip corner J6, a seventh chip corner J7, and an eighth chip corner J8 near the gap L. In the thickness direction Z of the chip package structure 100, the first chip corner J1 and the second chip corner J2 are closer to the carrier plate 101 than the third chip corner J3 and the fourth chip corner J4. The fifth chip corner J5 and the sixth chip corner J6 are closer to the carrier plate 101 than the seventh chip corner J7 and the eighth chip corner J8.

[0128] Figure 9 This is a top view of the chip packaging structure during fabrication corresponding to step S100. In some examples, such as... Figure 9 As shown, in the extension direction X of the gap L, the chip corners of the first chip 10 and the second chip 20 near the gap L are staggered. That is, in the extension direction X, the first chip corner J1, the fifth chip corner J5, the second chip corner J2 and the sixth chip corner J6 are arranged in sequence, and the third chip corner J3, the seventh chip corner J7, the fourth chip corner J4 and the eighth chip corner J8 are arranged in sequence.

[0129] This arrangement reduces the facing area of ​​the first chip 10 and the second chip 20, shortens the gap L, and thus reduces the size of the stress concentration area in the chip packaging structure 100, which helps improve the structural stability of the chip packaging structure 100. Furthermore, in the extension direction X, the chip corners of the first chip 10 and the second chip 20 near the gap L are staggered, which can reduce the stress on individual chip corners and mitigate the problem of cracks appearing at the chip corners.

[0130] S200, such as Figure 10 As shown, a filling layer 30 is formed in the gap L. The filling layer 30 covers the first chip corner J1, the second chip corner J2, the fifth chip corner J5, and the sixth chip corner J6.

[0131] In some embodiments, a dispensing process may be used to form a filling layer 30 in the gap L.

[0132] Among these advantages, dispensing technology offers benefits such as improved production efficiency, reduced costs, ensured product quality and reliability, and versatility in various application scenarios. Using dispensing to prepare the filler layer 30 can effectively improve the fabrication efficiency of chip packaging structures, reduce fabrication costs, and enhance the quality and reliability of chip packaging structures. Furthermore, forming the filler layer 30 within the gap L using dispensing technology allows for precise control of the filler layer 30's volume, preventing issues such as the filler layer 30 being too small or too large, which could negatively impact the overall internal stress of the chip packaging structure.

[0133] In some embodiments, such as Figure 11 As shown, before step S200, the preparation method also includes step S201.

[0134] S201. Clean the sidewalls of the first chip 10 and the second chip 20, as well as the surface of the carrier plate 101 facing the gap L, to enhance the hydrophilicity of the sidewalls of the first chip 10 and the second chip 20, and the hydrophilicity of the surface of the carrier plate 101 facing the gap L.

[0135] For example, plasma can be used to clean the sidewalls of the first chip 10 and the second chip 20, as well as the surface of the carrier 101 facing the gap L.

[0136] The embodiments of this application can reduce the water droplet angle between the filler adhesive and the sidewall of the first chip 10, the water droplet angle between the filler adhesive and the sidewall of the second chip 20, and the water droplet angle between the filler adhesive and the surface of the carrier 101 facing the gap L through the above cleaning process. This results in higher hydrophilicity of the sidewalls of the first chip 10 and the second chip 20, as well as the surface of the carrier 101 facing the gap L. Consequently, the wetting properties between the filler adhesive and the first chip 10, between the filler adhesive and the second chip 20, and between the filler adhesive and the carrier 101 are higher, allowing the filler adhesive to fill the gap L more easily and quickly.

[0137] In some embodiments, such as Figure 12 As shown, step S200 may include steps S210 to S230.

[0138] S210, fill one end of the gap L with adhesive.

[0139] For example, a nozzle can be used to fill adhesive at one end of the gap L.

[0140] S220, heating the carrier plate 101 and the filler adhesive to extend the filler adhesive into the gap L.

[0141] Heating the carrier plate 101 and the filler adhesive increases the temperature of the filler adhesive, thereby increasing its fluidity. This increased fluidity allows the filler adhesive to automatically fill the gap L via capillary action.

[0142] S230, cure the filler adhesive to form filler layer 30.

[0143] For example, the filler adhesive can be cured by high-pressure baking to form the filler layer 30. In this embodiment, the pressure and baking temperature used for high-pressure baking are not limited; pressures and temperatures disclosed in the art can be used.

[0144] In this embodiment, adhesive is filled at one end of the gap L, and the adhesive diffuses from one end of the gap L to the other end, allowing gas in the gap L to escape through the other end. This reduces the likelihood of air bubbles forming in the prepared filling layer 30, thus improving the quality of the filling layer 30.

[0145] In some embodiments, such as Figure 13 As shown, step S200 may further include step S240.

[0146] S240. Check if the filler extends to the other end of the gap L.

[0147] In some examples, step S230 is performed if the detection result in step S240 is "yes", and step S250 is performed if the detection result in step S240 is "no".

[0148] S250, fill the other end of the gap L with glue.

[0149] S300, such as Figure 14 As shown, a molding compound 40 is formed on the side of the filler layer 30, the first chip 10, and the second chip 20 away from the carrier substrate 101. The molding compound 40 is also located on the sidewalls of the filler layer 30, the first chip 10, and the second chip 20.

[0150] In some examples, a molding process can be used to form a molding layer 40 on the side of the filler layer 30, the first chip 10, and the second chip 20 away from the carrier 101.

[0151] The material of the encapsulation layer 40 may include an encapsulating colloid MUF. The encapsulating colloid MUF may include silica, epoxy resin, hardener, flame retardant, catalyst, etc.

[0152] In this embodiment, the thickness of the molding compound 40 is not limited and can be designed according to actual needs. For example, the thickness of the molding compound 40 can be adjusted so that it can protect both the first chip 10 and the second chip 20 without causing the chip package structure to be too large.

[0153] In some embodiments, such as Figure 15As shown, the first chip 10 has a first conductive bump 11, and the second chip 20 has a second conductive bump 21. The first conductive bump 11 is located on the surface of the first chip 10 away from the carrier plate 101, and the second conductive bump 21 is located on the surface of the second chip 20 away from the carrier plate 101.

[0154] At this point, after step S300, the preparation method further includes step S301.

[0155] S301, such as Figure 15 As shown, the molding layer 40 is ground until the surface of the first conductive bump 11 away from the carrier plate 101 and the surface of the second conductive bump 21 away from the carrier plate 101 are exposed.

[0156] For example, the molding layer 40 can be processed by a topside grinding process.

[0157] In this embodiment, the molding layer 40 is polished to expose the first conductive bump 11 of the first chip 10 and the second conductive bump 21 of the second chip. This allows the first conductive bump 11 of the first chip 10 to be connected to the circuit structure 50 formed in the subsequent step S400, and the second conductive bump 21 of the second chip 20 to be connected to the circuit structure 50 formed in the subsequent step S400.

[0158] S400, such as Figure 16 As shown, a circuit structure 50 is formed on the side of the molding layer 40 away from the carrier board 101.

[0159] In some examples, such as Figure 16 As shown, step S400 may include steps S410 and S420.

[0160] S410, A redistribution layer 51 is formed on the side of the molding layer 40 away from the carrier board 101.

[0161] For example, a redistribution layer 51 can be formed on the side of the molding layer 40 away from the carrier 101 using deposition and etching processes.

[0162] S420. An electrical connection structure 52 is formed on the side of the redistribution layer 51 away from the carrier board 101.

[0163] For example, the electrical connection structure 52 may include a plurality of solder balls. In this case, a ball-mounting process can be used to form the electrical connection structure 52 on the side of the redistribution layer 51 away from the carrier board 101.

[0164] Understandably, see Figure 16 After the circuit structure 50 is formed, the carrier board 101 can be peeled off.

[0165] In the preparation method provided in this application embodiment, the first chip 10 and the second chip 20 are first disposed on the carrier board 101, and then a filling layer 30 is formed in the gap L between the first chip 10 and the second chip 20. After that, a molding compound 40 covering the first chip 10, the second chip 20 and the filling layer 30 is formed, and finally a circuit structure 50 is formed on the side of the molding compound 40 away from the carrier board 101.

[0166] Thus, in the chip package structure 100 prepared using the preparation method provided in this application embodiment, the filling layer 30, which is made of a material different from the molding compound 40, is located in the gap L. This allows the molding compound 40 to fill only part of the gap L or be completely located outside the gap L. When the temperature changes, even if the coefficient of thermal expansion of the molding compound 40 differs significantly from that of the first chip 10 and the second chip 20, the stress exerted by the molding compound 40 on the first chip 10 and the second chip 20 at the gap L can be small, or even no stress can be applied to the first chip 10 or the second chip 20. The filling layer 30 can effectively protect the first chip 10 and the second chip 20.

[0167] Furthermore, the filler layer 30 also covers the first chip corner J1 and the second chip corner J2 of the first chip 10 near the gap L, as well as the fifth chip corner J5 and the sixth chip corner J6 of the second chip 20 near the gap L. In this way, the filler layer 30 not only protects the sidewalls of the first chip 10 near the gap L, but also protects the first chip corner J1 and the second chip corner J2 of the first chip 10, mitigating stress concentration at these points and preventing cracking. Similarly, the filler layer 30 not only protects the sidewalls of the second chip 20 near the gap L, but also protects the fifth chip corner J5 and the sixth chip corner J6 of the second chip 20, mitigating stress concentration at these points and preventing cracking.

[0168] In some embodiments, such as Figure 10 As shown, in the thickness direction Z of the chip packaging structure, the surface of the filling layer 30 away from the carrier plate 101 can be flush or approximately flush with the surface of the first chip 10 away from the carrier plate 101, and / or, the surface of the filling layer 30 away from the carrier plate 101 can be flush or approximately flush with the surface of the second chip 20 away from the carrier plate 101.

[0169] It is understood that, in the thickness direction Z of the chip package structure, the surface of the filling layer 30 away from the carrier plate 101 is flush or approximately flush with the surface of the first chip 10 away from the carrier plate 101. This includes the case where, in the thickness direction Z of the chip package structure, the surface of the filling layer 30 away from the carrier plate 101 is completely flush with the surface of the first chip 10 away from the carrier plate 101, and also the case where, in the thickness direction Z of the chip package structure, there is a height difference between the surface of the filling layer 30 away from the carrier plate 101 and the surface of the first chip 10 away from the carrier plate 101, but this difference is within the error range acceptable to those skilled in the art.

[0170] Similarly, in the thickness direction Z of the chip package structure, the surface of the filling layer 30 away from the carrier plate 101 can be flush or approximately flush with the surface of the second chip 20 away from the carrier plate 101. This includes the case where the surface of the filling layer 30 away from the carrier plate 101 is completely flush with the surface of the second chip 20 away from the carrier plate 101 in the thickness direction Z of the chip package structure, and also the case where there is a height difference between the surface of the filling layer 30 away from the carrier plate 101 and the surface of the second chip 20 away from the carrier plate 101 in the thickness direction Z of the chip package structure, but the difference is within the error range acceptable to those skilled in the art.

[0171] In other embodiments, such as Figure 17 As shown, the filling layer 30 can cover part of the surface of the first chip 10 away from the carrier board 101, and at the same time cover part of the surface of the second chip 20 away from the carrier board 101.

[0172] At this time, the contact area between the filling layer 30 and the corner of the first chip 10 away from the carrier plate 101 is larger, and the contact area between the filling layer 30 and the corner of the second chip 20 away from the carrier plate 101 is also larger. The filling layer 30 can effectively protect the corners of the first chip 10 and the second chip 20 away from the carrier plate 101, thereby improving the problem of cracking at the corners of the first chip 10 and the second chip 20 away from the carrier plate 101, and protecting the first chip 10 and the second chip 20.

[0173] In some embodiments, such as Figure 17 As shown, the filling layer 30 not only wraps the first chip corner J1, the second chip corner J2, the fifth chip corner J5 and the sixth chip corner J6, but also wraps the third chip corner J3, the fourth chip corner J4, the seventh chip corner J7 and the eighth chip corner J8.

[0174] In this way, the filling layer 30 can protect not only the first chip corner J1 and the second chip corner J2 of the first chip 10, but also the third chip corner J3 and the fourth chip corner J4 of the first chip 10. This allows the filling layer 30 to protect not only the fifth chip corner J5 and the sixth chip corner J6 of the second chip 20, but also the seventh chip corner J7 and the eighth chip corner J8 of the second chip 20. The filling layer 30 can also improve the stress concentration at the third chip corner J3, the fourth chip corner J4, the seventh chip corner J7 and the eighth chip corner J8, and prevent the cracking of the third chip corner J3, the fourth chip corner J4, the seventh chip corner J7 and the eighth chip corner J8.

[0175] It is understandable that when fabricating the chip package structure using the above-described fabrication method of this application, the fifth chip corner J5 and the sixth chip corner J6 of the first chip 10 are closer to the circuit structure than the seventh chip corner J7 and the eighth chip corner J8 of the second chip 20. If the fifth chip corner J5, the sixth chip corner J6, the seventh chip corner J7, and the eighth chip corner J8 crack, the crack will extend towards the circuit structure, easily damaging the circuit structure. In the embodiments of this application, the filling layer 30 wraps around the fifth chip corner J5, the sixth chip corner J6, the seventh chip corner J7, and the eighth chip corner J8, which can prevent cracks from appearing at the fifth chip corner J5, the sixth chip corner J6, the seventh chip corner J7, and the eighth chip corner J8, thereby preventing the cracks from extending to the circuit structure and protecting the circuit structure 50.

[0176] In some embodiments, the Young's modulus of the filler layer 30 is less than that of the molding compound 40, and / or the coefficient of thermal expansion of the filler layer 30 is less than that of the molding compound 40.

[0177] When the Young's modulus of the filler layer 30 is less than that of the molding layer 40, the filler layer 30 is more prone to deformation than the molding layer 40. Even if the temperature changes and the volumes of the first chip 10, the second chip 20, and the filler layer 30 change, the filler layer 30 can still deform under the action of the first chip 10 and the second chip 20, thereby relieving the stress applied by the first chip 10 and the second chip 20 to the gap L, alleviating the stress concentration problem in the gap L, and thus protecting the first chip 10 and the second chip 20 on both sides of the gap L.

[0178] When the coefficient of thermal expansion of the filler layer 30 is less than that of the molding compound layer 40, the deformation of the filler layer 30 is smaller than that of the molding compound layer 40 under the same temperature difference. Thus, even if the temperature changes, the dimensional change of the filler layer 30 located in the gap L is small, and the stress exerted by the filler layer 30 on the first chip 10 and the second chip 20 is also smaller, effectively alleviating the stress concentration problem at the gap L and protecting the first chip 10 and the second chip 20.

[0179] When the Young's modulus of the filler layer 30 is less than that of the molding compound layer 40, and the coefficient of thermal expansion of the filler layer 30 is less than that of the molding compound layer 40, the stress exerted by the filler layer 30 on the first chip 10 and the second chip 20 is smaller. The stress exerted by the first chip 10 and the second chip 20 on the filler layer 30 can also be partially released through the deformation of the filler layer 30. When the temperature changes, the filler layer 30 can effectively alleviate the stress concentration problem at the gap L between the first chip 10 and the second chip 20, protecting both chips.

[0180] In some examples, the material of the filler layer 30 may include an underfill adhesive or polyimide.

[0181] In some embodiments, such as Figure 18 As shown, in the extension direction X of the gap L, the filling layer 30 includes a first extension surface S31 and a second extension surface S32 disposed opposite to each other. Both the first extension surface S31 and the second extension surface S32 are curved surfaces.

[0182] In this way, the first extension surface S31 and the second extension surface S32 can transfer the stress at the corner of the first chip 10 and the second chip 20 to the first extension surface S31 and the second extension surface S32. Since the first extension surface S31 and the second extension surface S32 are both curved surfaces, they can effectively disperse the stress, thereby further improving the stress concentration problem of the first chip 10 and the second chip 20.

[0183] Depending on the amount of filler adhesive used in step S200, the states of the first extension surface S31 and the second extension surface S32 of the filler layer 30 will also be different.

[0184] For example, when the amount of filler is appropriate, refer to Figure 5B In the extension direction X of the gap L, the first extension surface S31 and the second extension surface S32 protrude away from the gap L.

[0185] For example, when the amount of filler is large, such as Figure 18 As shown, in the extension direction X of the gap L, the first extension surface S31 and the second extension surface S32 protrude in a direction away from the gap L.

[0186] Among them, compared to Figure 5B The filling layer 30 shown is shown. Figure 18 In the filling layer 30 shown, the angle between the first extension surface S31 and the sidewall of the first chip 10 and the sidewall of the second chip 20 is larger, and the angle between the second extension surface S32 and the sidewall of the first chip 10 and the sidewall of the second chip 20 is also larger.

[0187] Similarly, compared to Figure 5B The filling layer 30 shown is shown. Figure 18 In the filling layer 30 shown, in the extension direction X of the gap L, the distance from the vertex of the first extension surface S31 to the sidewall of the first chip 10 or the second chip 20 is relatively large, and the distance from the vertex of the second extension surface S32 to the sidewall of the first chip 10 or the second chip 20 is also relatively large.

[0188] For example, when the amount of filler is small, refer to... Figure 5A In the extension direction X of the gap L, the first extension surface S31 and the second extension surface S32 are recessed in a direction away from the gap L.

[0189] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0190] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: Circuit structure, A first chip and a second chip are located on the same side of the circuit structure, with a gap between them. The first chip includes a first chip corner, a second chip corner, a third chip corner, and a fourth chip corner near the gap, and the second chip includes a fifth chip corner, a sixth chip corner, a seventh chip corner, and an eighth chip corner near the gap. In the thickness direction of the chip package structure, the first chip corner and the second chip corner are both farther away from the circuit structure than the third chip corner and the fourth chip corner; the fifth chip corner and the sixth chip corner are both farther away from the circuit structure than the seventh chip corner and the eighth chip corner. A filling layer is located in the gap, and the filling layer covers the first chip corner, the second chip corner, the fifth chip corner, and the sixth chip corner; A molding compound is located on the sidewalls of the filler layer, the sidewalls of the first chip, and the sidewalls of the second chip, and the molding compound is also located between the filler layer and the circuit structure, between the first chip and the circuit structure, and between the second chip and the circuit structure; the material of the filler layer is different from the material of the molding compound.

2. The chip packaging structure according to claim 1, characterized in that, The filling layer also covers the third chip corner, the fourth chip corner, the seventh chip corner, and the eighth chip corner.

3. The chip packaging structure according to claim 1 or 2, characterized in that, The Young's modulus of the filler layer is less than that of the molding compound layer, and / or the coefficient of thermal expansion of the filler layer is less than that of the molding compound layer.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that, In the thickness direction of the chip package structure, the size of the filling layer is greater than or equal to the size of the gap.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that, In the direction of the gap's extension, the filling layer includes a first extending surface and a second extending surface disposed opposite to each other; both the first extending surface and the second extending surface are curved surfaces.

6. The chip packaging structure according to claim 5, characterized in that, In the direction of the gap's extension, both the first and second extension surfaces protrude away from the gap.

7. The chip packaging structure according to claim 5, characterized in that, In the direction of the gap's extension, both the first and second extension surfaces are recessed toward the gap.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that, The filler layer is made of materials including underfill adhesive or polyimide.

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that, The circuit structure includes a redistribution layer and an electrical connection structure; the electrical connection structure is located on the side of the redistribution layer away from the first chip; The first chip has a first conductive bump located on the surface of the first chip near the circuit structure, and the second chip has a second conductive bump located on the surface of the second chip near the circuit structure; the first conductive bump and the second conductive bump penetrate the molding layer and are connected to the redistribution layer.

10. A method for fabricating a chip packaging structure, characterized in that, include: A first chip and a second chip are disposed on a carrier board; a gap exists between the first chip and the second chip; the first chip includes a first chip corner, a second chip corner, a third chip corner, and a fourth chip corner near the gap, and the second chip includes a fifth chip corner, a sixth chip corner, a seventh chip corner, and an eighth chip corner near the gap; in the thickness direction of the chip package structure, the first chip corner and the second chip corner are both closer to the carrier board than the third chip corner and the fourth chip corner; the fifth chip corner and the sixth chip corner are both closer to the carrier board than the seventh chip corner and the eighth chip corner. A filling layer is formed in the gap, the filling layer covering the first chip corner, the second chip corner, the fifth chip corner and the sixth chip corner; A molding compound is formed on the side of the filler layer, the first chip, and the second chip away from the carrier substrate; the molding compound is also located on the sidewalls of the filler layer, the sidewalls of the first chip, and the sidewalls of the second chip. A circuit structure is formed on the side of the encapsulation layer away from the carrier board.

11. The preparation method according to claim 10, characterized in that, The Young's modulus of the filler layer is less than that of the molding compound layer, and / or the coefficient of thermal expansion of the filler layer is less than that of the molding compound layer.

12. The preparation method according to claim 10 or 11, characterized in that, The filling layer also covers the third chip corner, the fourth chip corner, the seventh chip corner, and the eighth chip corner.

13. The preparation method according to any one of claims 10 to 12, characterized in that, In the direction of the gap's extension, the filling layer includes a first extending surface and a second extending surface disposed opposite to each other; both the first extending surface and the second extending surface are curved surfaces.

14. The preparation method according to claim 13, characterized in that, In the direction of the gap's extension, both the first and second extension surfaces protrude away from the gap.

15. The preparation method according to claim 13, characterized in that, In the direction of the gap's extension, both the first and second extension surfaces are recessed toward the gap.

16. The preparation method according to any one of claims 10 to 15, characterized in that, The process of forming a filling layer in the gap includes: A filling layer is formed in the gap using a dispensing process.

17. The preparation method according to any one of claims 10 to 16, characterized in that, The process of forming a filling layer in the gap includes: Fill one end of the gap with adhesive; The carrier plate and the filler adhesive are heated to cause the filler adhesive to extend into the gap; The filler adhesive is cured to form a filler layer.

18. The preparation method according to any one of claims 10 to 17, characterized in that, The preparation method further includes: Clean the sidewalls of the first chip and the second chip, as well as the surface of the carrier plate facing the gap, to enhance the hydrophilicity of the sidewalls of the first chip and the second chip, and the hydrophilicity of the surface of the carrier plate facing the gap.

19. The preparation method according to any one of claims 10 to 18, characterized in that, The first chip has a first conductive bump, and the second chip has a second conductive bump. The first conductive bump is located on the surface of the first chip away from the carrier plate, and the second conductive bump is located on the surface of the second chip away from the carrier plate. The preparation method further includes: The molding layer is ground until the surfaces of the first conductive bump away from the carrier plate and the second conductive bump away from the carrier plate are exposed.

20. An electronic device, characterized in that, include: circuit board, The chip packaging structure as described in any one of claims 1 to 9, or the chip packaging structure prepared by the preparation method as described in any one of claims 10 to 19; The chip package structure is located on the circuit board and is electrically connected to the circuit board.

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