A recessed passivation layer structure and a preparation method of a GaN HEMT device structure

Abstract

The application discloses a recess passivation layer structure and a preparation method of a GaN HEMT device structure, and comprises an epitaxial substrate, characterized in that further comprising: a first passivation layer and a second passivation layer, the first passivation layer and the second passivation layer are sequentially stacked on the epitaxial substrate, and an interlayer interface is arranged between the first passivation layer and the second passivation layer; a first groove is arranged in the first passivation layer and the second passivation layer, the depth of the first groove is greater than the thickness of the first passivation layer and less than the total thickness of the first passivation layer and the second passivation layer; wherein the first groove intersects with a leakage path of the interlayer interface, and is used for blocking the leakage path. The application has the effect of improving the performance of a gallium nitride high electron mobility transistor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor fabrication, specifically relating to a method for fabricating a groove passivation layer structure and a GaN HEMT device structure. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) have been widely used in power electronics and radio frequency communications due to their excellent physical properties, such as high breakdown electric field, high saturation electron drift velocity, and low on-resistance. However, the presence of numerous dangling bonds, surface defects, and polarization charges on the GaN heterojunction surface can easily lead to a "current collapse" effect when the device operates at high voltage, thus limiting the dynamic performance and reliability of GaN power devices.

[0003] To address the current collapse problem caused by surface traps, existing technologies typically employ a method of depositing a stacked passivation layer on the surface of the epitaxial wafer. This method usually involves sequentially depositing a bottom passivation layer and an upper passivation layer on the barrier layer surface of the epitaxial substrate. Generally, the bottom passivation layer is a relatively thin layer of silicon-rich silicon nitride (Si-rich silicon nitride). The thin film, and the upper passivation layer is usually a thicker layer of nitrogen-rich silicon nitride (N-rich silicon nitride). )film.

[0004] However, the conventional stacked passivation structure introduces interface states at the interlayer interface, forming new leakage channels and increasing the gate leakage current. This limits the breakdown voltage of the device to a low level, allowing it to operate only under low voltage conditions, which restricts its power output capability and thus affects the performance of GaN HEMT. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a method for fabricating a groove passivation layer structure and a GaNHEMT device structure. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a groove passivation layer structure, comprising an epitaxial substrate, and further comprising: A first passivation layer and a second passivation layer are stacked sequentially on an epitaxial substrate, and an interlayer interface is provided between the first passivation layer and the second passivation layer. The first trench is formed in the first passivation layer and the second passivation layer. The depth of the first trench is greater than the thickness of the first passivation layer and less than the total thickness of the first passivation layer and the second passivation layer. The first trench intersects with the leakage path at the interlayer interface, thereby blocking the leakage path.

[0006] In one embodiment of the present invention, there are multiple first trenches arranged in an array to release the total interlayer stress between the first passivation layer and the second passivation layer.

[0007] In one embodiment of the present invention, the first groove is a cuboid or a cylinder.

[0008] In one embodiment of the present invention, the epitaxial substrate is further provided with a drain and a gate; the first trench is disposed between the gate and the drain, wherein the first trench intersects with the leakage path between the gate and the drain, and is used to block the leakage path between the gate and the drain.

[0009] In one embodiment of the present invention, the number of the first trenches is one.

[0010] In one embodiment of the present invention, the total thickness of the first passivation layer and the second passivation layer is 120 nm, and the depth of the first trench is 95 nm to 115 nm.

[0011] In one embodiment of the present invention, the first trench extends downward through the first passivation layer and into the interior of the second passivation layer to a depth of 5 nm to 25 nm.

[0012] In one embodiment of the present invention, the first passivation layer and the second passivation layer include: The first passivation layer and the second passivation layer are made of different materials; the first passivation layer uses nitrogen-rich materials. The second passivation layer is prepared using silicon-rich materials. preparation.

[0013] Secondly, the present invention provides a method for fabricating a GaN HEMT device structure, the method comprising: S1. Prepare an epitaxial substrate, wherein the epitaxial substrate comprises, from bottom to top, a substrate layer, a buffer layer, a channel layer and a barrier layer; S2. Fabricate source and drain electrodes on the barrier layer; S3. A first passivation layer and a second passivation layer are grown on the barrier layer between the source electrode and the drain electrode, and an array structure is prepared. The first passivation layer and the second passivation layer are stacked sequentially from top to bottom on the barrier layer, and there is an interlayer interface between the first passivation layer and the second passivation layer. S4. Photolithographically etch the gate region on the passivation layer and evaporate the gate metal to prepare a T-shaped gate; S5. Photolithographically etch metal interconnect regions on the source electrode, drain electrode, and second passivation layer, and evaporate to form a metal interconnect layer.

[0014] In one embodiment of the present invention, the step of growing a first passivation layer and a second passivation layer on the barrier layer between the source electrode and the drain electrode and fabricating an arrayed structure includes: S31. Perform surface pretreatment on the device surface to remove particles and the natural oxide layer; S32. Preparation of silicon-rich substrate by PECVD The passivation layer serves as the second passivation layer, and the silicon-rich layer... The passivation layer thickness is 30nm; S33. Preparation of nitrogen-rich upper layer by PECVD The passivation layer serves as the first passivation layer, and the nitrogen-rich layer... The passivation layer thickness is 90 nm; the total thickness of the passivation layer is 120 nm. S34. Use EBL lithography to design an array pattern on the surface of the passivation layer; S35. Etch the passivation layer to a depth of 95~115nm to transfer the arrayed pattern onto the passivation layer.

[0015] Compared with the prior art, the beneficial effects of the present invention are: This invention creates a first trench within a first passivation layer and a second passivation layer sequentially stacked on an epitaxial substrate. The depth of the first trench is greater than the thickness of the first passivation layer, while ensuring that the first trench does not penetrate the second passivation layer. This physical structure design physically hollows out and blocks the continuous interlayer interface originally formed by the sequential stacking and contact of the first and second passivation layers within the space of the first trench. This completely severs the originally continuously extending interlayer leakage path at the interlayer interface, reducing the gate leakage current of the device, increasing the breakdown voltage of the semiconductor device, enabling it to operate stably under high voltage conditions, thereby releasing the power output capability of the device and optimizing the electrical performance of semiconductor devices (such as GaN HEMTs).

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a groove passivation layer structure provided in an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of various arrayed passivation structures in the groove passivation layer structure provided in the embodiments of the present invention.

[0019] Figure 3 This is a schematic diagram of a groove passivation layer structure with multiple pattern combinations after the gate is fabricated, provided in an embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of a single-sided arrayed groove passivation layer structure provided in an embodiment of the present invention after the gate is fabricated.

[0021] Figure 5 This is a schematic flowchart of a method for fabricating a GaN HEMT device structure according to an embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of the epitaxial substrate structure in a method for fabricating a GaN HEMT device structure provided in an embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of the epitaxial substrate having source and drain electrodes in a method for fabricating a GaN HEMT device structure according to an embodiment of the present invention.

[0024] Figure 8 This is a schematic diagram of the fabrication process of the passivation layer and array structure in a GaN HEMT device structure fabrication method provided in an embodiment of the present invention.

[0025] Figure 9 The method for fabricating a GaN HEMT device structure provided in this embodiment of the invention has silicon-rich components. A schematic diagram of the epitaxial substrate with a passivation layer.

[0026] Figure 10 This invention provides a method for fabricating a GaN HEMT device structure that incorporates nitrogen-rich components. A schematic diagram of the epitaxial substrate with a passivation layer.

[0027] Figure 11 This is a method for fabricating a GaN HEMT device structure provided in an embodiment of the present invention. A schematic diagram of the epitaxial substrate structure after the passivation layer has been etched.

[0028] Figure 12 This is a schematic diagram of the epitaxial substrate with a photolithographic gate trench region in a method for fabricating a GaN HEMT device structure according to an embodiment of the present invention.

[0029] Figure 13 This is a schematic diagram of the epitaxial substrate with a T-type gate electrode in a method for fabricating a GaN HEMT device structure according to an embodiment of the present invention.

[0030] Figure 14 This is a comparative schematic diagram of the transfer characteristics of a grooved passivation layer structure provided in an embodiment of the present invention.

[0031] Figure 15 This is a comparative schematic diagram of the collapse characteristics of a grooved passivation layer structure provided in an embodiment of the present invention.

[0032] Figure 16 This is a comparative schematic diagram of the breakdown characteristics of a grooved passivation layer structure provided in an embodiment of the present invention. Detailed Implementation

[0033] Due to the presence of deep-level traps on the surface of the GaN HEMT heterojunction, the gate voltage switches frequently between positive and negative values ​​during operation. The trap charging and discharging rates lag far behind signal changes, resulting in a common phenomenon: current collapse. Passivation layers can effectively improve this problem. For RF GaN HEMTs, the intrinsic tensile stress of the thin film can induce polarization charges, increasing 2DEG concentration and high-frequency characteristics, which makes... Passivation layers have become an indispensable surface thin film structure for current radio frequency GaN HEMT devices.

[0034] Current research has found that plasma-enhanced chemical vapor deposition (PECVD) can prepare... passivation film thickness Performance will be affected. Studies have found that when As the film thickness increases, the tensile stress rises, stress-induced polarization charge increases, the channel two-dimensional electron gas (2DEG) concentration increases, and the device output characteristics improve. However, when the passivation layer thickness reaches more than 100 nm, the 2DEG concentration tends to saturate, and the mobility also reaches its maximum value.

[0035] For example, existing technologies, under the premise of fixing the passivation material and silicon-nitrogen ratio, temperature, pressure and other process parameters, only adjust the deposition time to change the film thickness. The total internal stress, density, parasitic capacitance, and water vapor barrier capacity of the medium all change monotonically with thickness, thus regulating the... Surface states, 2DEG concentration and device performance.

[0036] However, simply changing the thickness results in a narrow stress control window for the passivation layer, allowing only minor adjustments to the stress within a small range, thus limiting the improvement in device performance. Furthermore, changing the passivation layer thickness only alters the magnitude of stress, not its nature, making it difficult to achieve comprehensive performance enhancements. When the passivation layer is too thin, current collapse is not significantly improved, moisture barrier performance is poor, and long-term device reliability deteriorates. When it is too thick, gate leakage current increases, and excessive stress can lead to wafer warping. Therefore, simply changing the passivation thickness is not an effective passivation improvement method; it requires combining other approaches to synergistically optimize the passivation effect.

[0037] Different research directions lead to variations in the optimal passivation layer thickness for device adaptation. Even with passivation layers of the same thickness, differences in fabrication processes significantly impact passivation quality and effectiveness, primarily due to variations in passivation process parameters. In another existing technology, optimization is achieved by adjusting deposition parameters such as silane, nitrogen, and ammonia flow rates, RF power, and chamber pressure. Passivation process effectively improves The 2DEG concentration at the interface reduces the sheet resistance of the device and improves its mobility.

[0038] For example, existing technologies typically do not change the passivation material and structure, but optimize the passivation film density, chemical composition, intrinsic stress, and interface defects by adjusting the RF power, deposition temperature, cavity gas pressure, gas flow rate, and plasma atmosphere of equipment such as PECVD / LPCVD / ICP-CVD, while simultaneously reducing the influence of the plasma on the passivation film. The most common cause of bombardment damage to the surface of a potential barrier is alteration of the silicon-nitrogen ratio.

[0039] However, when adjusting the process parameters of passivation equipment, different parameters are coupled and influence each other, rather than acting independently. Adjusting a single parameter can simultaneously change multiple indicators such as stress, composition, and defect density, making comprehensive control difficult. Furthermore, low-frequency passivation processes cause significant damage, directly damaging the barrier layer and drastically degrading device performance. In addition, passivation layers prepared with different process parameters exhibit varying density, requiring subsequent etching processes to be reconfigured to avoid incomplete etching or etching damage.

[0040] In addition, existing technologies have made further innovations in passivation structures. In another existing technology, while keeping the total thickness of the passivation layer constant, a comprehensive comparison was made between single-layer passivation and multi-layer passivation structures. The impact of HEMT devices, which employ rich of As the bottom layer, the upper layer adopts the conventional approach. Passivation effectively reduces the sheet resistance and current collapse of the device at room temperature, as well as the leakage current at high temperatures, successfully achieving a significant improvement in the small-signal and power performance of the device.

[0041] For example, existing technologies employ stacked layers of two or more dielectric thin films to form a composite passivation structure, utilizing the complementary stress of different film layers to offset the overall stress. Different layers have different functions: the inner layer, closer to the semiconductor, focuses on repairing interfaces, neutralizing traps, and regulating local stress to enhance 2DEG density; the outer layer focuses on mechanical protection, isolating moisture and external interference, and playing a role in stress neutralization and protection. The mainstream forms are divided into two categories: stacked layers of the same material but different components (such as silicon-rich layers). +Nitrogen-rich ), heterogeneous media stacks (such as , ).

[0042] However, stacked passivation significantly increases the number of deposition and photolithography steps, raising process complexity, lengthening production cycles, and impacting yield and manufacturing costs. More importantly, new interlayer interface channels are easily generated between stacked films. If process control is inadequate, additional interface states can be introduced, causing leakage and increased dynamic resistance, which contradicts the purpose of stacked passivation. Furthermore, the different coefficients of thermal expansion of various media can lead to interlayer delamination and film cracking under high and low temperature cycling.

[0043] In addition, existing technologies also improve the passivation layer through atomic layer passivation (ALD) and in-situ passivation techniques.

[0044] For example, in ALD (Atomic Layer Deposition), atomic layer deposition relies on self-limiting surface adsorption reactions to grow dielectric films layer by layer at the unit of single atom or monomolecular layer. It possesses nanoscale or even atomic-level thickness precision, excellent step coverage capability, and the deposition process is free from high-energy plasma bombardment, enabling the fabrication of ultra-high purity, low-defect passivation layers. ALD offers a wide selection of dielectric materials, and the interfacial band structure and polarization characteristics can be controlled by selecting different materials to suppress surface traps.

[0045] However, ALD deposition rates are slow, and equipment procurement and operating costs are high, making it difficult to meet the demands of large-scale mass production. It is currently mostly used in laboratory research and development and for small-batch high-end products. Furthermore, the dielectric constant of ALD-deposited dielectrics is generally high, and the increased film thickness significantly increases parasitic capacitance, which limits the high-frequency performance of devices. In addition, ALD requires stringent wafer surface cleanliness; even tiny particles and contaminants can cause pinholes and defects in the film.

[0046] In in-situ passivation technology, after the AlGaN barrier or GaN channel is grown in the epitaxial cavity (MOCVD / MBE, etc.), the wafer is not removed from the cavity, does not come into contact with the atmosphere, and does not undergo subsequent external processes such as photolithography, etching, and cleaning. The passivation dielectric layer is directly and continuously grown in the same atmosphere. Its thickness is thinner than that of conventional passivation layers, generally less than 10nm.

[0047] However, in-situ passivation technology has extremely poor process flexibility. The passivation layer growth temperature and gas system must be matched with the front-end epitaxial process, and the adjustment of the passivation layer composition, thickness, and stress is very limited. Only the same passivation layer can be grown on the entire wafer; different passivation layers cannot be prepared for the gate region, source / drain region, and high-voltage field region, making local stress control impossible. Furthermore, under the high-temperature environment of mainstream MOCVD, , High-k media are difficult to grow stably, and most new passivation materials cannot be adapted to them.

[0048] In summary, in recent years, the academic community has already... The deposition thickness of the passivation layer, various deposition parameters, and stacked passivation structures have been thoroughly studied. These approaches aim to improve the passivation layer from different perspectives to enhance device performance, and their findings have gained widespread acceptance. Passivation layers are an indispensable structure in current radio frequency GaN HEMT devices. However, passivation layers are not without their drawbacks; the introduction of interlayer interfaces can sometimes increase leakage current and compromise the device's breakdown characteristics.

[0049] Meanwhile, current innovations in passivation layers are nearing a bottleneck: First, through systematic experimental exploration, the deposition thickness and deposition parameters of the passivation layer have reached a mature process, which can realize the device performance has reached the bottleneck. Secondly, while multilayer passivation is stronger than single-layer passivation, it introduces interface states at the interlayer interfaces, forming new leakage channels and increasing gate leakage current. This limits the device's breakdown voltage to a lower level, restricting its power output capability to low-voltage operation. Furthermore, the bottom passivation layer is relatively thinner, resulting in weaker stress, while the top passivation layer is thicker, leading to stronger stress. Even with the same thickness, the stress from the two passivation layers cannot be perfectly offset, as this is also affected by process parameters, barrier layer materials, and other factors. Under the combined effect of the two passivation layers, the total stress is difficult to precisely control, making it impossible to achieve an ideal zero-stress passivation structure. Consequently, the increase in 2DEG concentration is difficult to control precisely, requiring a more precise modulation method. More importantly, once passivation is complete, the passivation layer cannot be further modified, nor can its stress be improved; its control effect becomes fixed, making it impossible to further adjust the passivation effect or improve device performance.

[0050] Therefore, there is a need for a passivation process that can overcome the leakage risk associated with multilayer passivation, and allows for precise stress control, based on a combination of mature passivation technology and multilayer passivation structure. The invention will be further described in detail below with reference to specific embodiments, but the implementation of the invention is not limited thereto.

[0051] In a first aspect, embodiments of the present invention provide a groove passivation layer structure.

[0052] Please see Figure 1 , Figure 1 This is a schematic diagram of a grooved passivation layer structure provided in an embodiment of the present invention. The grooved passivation layer structure includes an epitaxial substrate and further includes: A first passivation layer and a second passivation layer are stacked sequentially from top to bottom on an epitaxial substrate, and there is an interlayer interface between the first passivation layer and the second passivation layer. The first trench is formed in the first passivation layer and the second passivation layer. The depth of the first trench is greater than the thickness of the first passivation layer and less than the total thickness of the first passivation layer and the second passivation layer. The first trench intersects with the leakage path at the interlayer interface, which is used to block the leakage path.

[0053] Specifically, such as Figure 1 As shown, the first passivation layer is the upper layer. The second passivation layer is the bottom layer. .use This indicates the etching depth of the first trench.

[0054] In terms of process design, the etching depth of the first trench is... The thickness is set between the top passivation layer thickness and the total thickness of the stacked passivation layers. This design precisely cuts off leakage current paths between the passivation layers, effectively suppressing interface leakage current and significantly improving the device's off-state breakdown voltage. Higher withstand voltage characteristics enable stable operation at higher operating voltages, fully unlocking the device's output potential and achieving superior output power density.

[0055] In one possible implementation, there are multiple first trenches arranged in an array to release the total interlayer stress between the first passivation layer and the second passivation layer.

[0056] The total interlayer stress refers to the sum of internal stresses accumulated at the interface between the first and second passivation layers during the stacking process due to the difference in thermal expansion coefficients and lattice mismatch between the two materials.

[0057] Specifically, such as Figure 2 As shown, the first groove is an array of multiple identical shapes.

[0058] Indicates the width of the arrayed graphic, Indicates the length of the arrayed graphic, Indicates the etching depth of the arrayed pattern, The spacing of the arrayed pattern indicates the density of the arrayed pattern.

[0059] and The size of the array pattern is determined, representing the area where the passivation layer is removed by the array. This is a key factor in determining the degree of stress relaxation of the passivation layer. The etching depth determines the pattern of the array. The deeper the etching depth, the stronger the stress relaxation effect and the stronger the damage to the stability of the passivation layer structure. When the depth exceeds the thickness of the top passivation layer, it can cut off the leakage current channel between layers. This represents the spacing between the arrayed patterns. A larger spacing indicates a sparser array. This can be adjusted... The size can change the arrangement and sparsity of the arrayed pattern, and can also play a certain role in regulating the overall stress.

[0060] In one possible implementation, the first groove is a cuboid or a cylinder.

[0061] Specifically, such as Figure 2 Figure (c) in the middle and Figure 2 As shown in Figure (d), when the first groove is a cylinder, Used to represent diameter.

[0062] Optional, such as Figure 3 As shown, the first groove is an array of multiple different shapes, including cuboids and cylinders.

[0063] This invention effectively releases the intrinsic stress accumulated within the thick top passivation layer by setting an array pattern, achieving a stress relaxation effect. Through stress release, the overall total stress of the stacked passivation structure can be controlled to a near-zero stress state, significantly reducing the risk of lattice distortion, interface defects, and thin film cracking caused by stress at the passivation layer and barrier layer interface, and significantly improving the reliability and lifespan of the device. This invention also offers more flexible stress control; the size and type of the array pattern can vary, enabling more precise stress control.

[0064] In one possible implementation, the epitaxial substrate is further provided with a drain and a gate; a first trench is disposed between the gate and the drain, wherein the first trench intersects with the leakage path between the gate and the drain, and is used to block the leakage path between the gate and the drain.

[0065] Specifically, such as Figure 4 As shown, the first trench is only set in a portion of the passivation layer. Since gate leakage mainly originates from the leakage current between the gate and the drain, exposure and etching can be performed only on the passivation layer between the drain and the gate, cutting off the leakage current path between the gate and the drain while releasing some of the stress in the top passivation layer.

[0066] Although this approach cannot completely release the excess stress of the top passivation layer and cannot make the total stress of the stacked passivation layer completely zero, it can serve as a comparative experiment to visually demonstrate the stress influence of the first trench on the passivation structure.

[0067] The laser curvature method can be used to visually characterize the stress difference between two passivation structures: during testing, a laser is incident perpendicularly to the surface passivation film, and the wafer curvature is fitted by collecting the offset of the reflected beam. Then, the total stress of the film is quantitatively calculated using the Stoney formula. During laser scanning, the reflection angle of the arrayed stacked passivation layer is 0, and the incident and reflected lasers are parallel. This means that the wafer curvature radius approaches infinity, and the calculated total stress of the film is approximately zero.

[0068] When a laser beam is incident on an unarrayed stacked passivation layer, the reflected beam will be significantly deflected. This indicates that the stacked passivation layer still has warping. The curvature of the film can be calculated by the deflection angle, and then the magnitude of the residual stress inside the film can be deduced.

[0069] In one possible implementation, the number of first trenches is one.

[0070] Specifically, when the quality of the stacked passivation is good, not many array patterns are needed to eliminate the total stress, but the first trench is needed to cut off the leakage path, so the minimum number of the first trenches is one.

[0071] In one possible implementation, the total thickness of the first passivation layer and the second passivation layer is 120 nm, and the depth of the first trench is 95 nm to 115 nm.

[0072] Specifically, the thickness of the first passivation layer is 90 nm; the thickness of the second passivation layer is 30 nm.

[0073] In one possible implementation, the first passivation layer and the second passivation layer include: The first passivation layer and the second passivation layer are made of different materials; the first passivation layer uses nitrogen-rich materials. Fabrication, the first passivation layer uses silicon-rich materials. preparation.

[0074] Specifically, silicon-rich It mainly relies on its own silicon-rich components and intrinsic compressive stress to effectively saturate. Surface dangling bonds reduce interface state density, significantly suppressing current collapse, while simultaneously repairing minor surface lattice damage, weakening carrier scattering, and increasing 2DEG concentration. The layer's function is thickness-independent; therefore, only 30 nm is needed to achieve all its functions.

[0075] Current industry practice The conventional thickness of the passivation layer is 120 nm, therefore the total thickness of the stacked passivation layer in this invention is also 120 nm, resulting in a first passivation layer thickness of 90 nm. Nitrogen-rich The passivation layer has the characteristics of tensile stress, high density and strong insulation. On the one hand, it uses tensile stress to suppress short-channel effect, improve gate control capability, reduce off-state leakage current, reduce threshold voltage drift, improve device consistency and better ensure device RF performance. On the other hand, it acts as the main physical protection barrier, effectively isolating water vapor, oxygen and external pollutants, significantly improving breakdown voltage and long-term reliability. At the same time, it balances the compressive stress of the first silicon-rich layer to alleviate the overall film stress and reduce wafer warpage.

[0076] In one possible implementation, the first trench extends downward through the first passivation layer and into the interior of the second passivation layer to a depth of 5 nm to 25 nm.

[0077] Specifically, the passivation layer is removed according to the arrayed photolithography pattern to obtain the first trench, with an etching depth of 95nm~115nm, exceeding the 90nm thickness of the upper passivation layer. After removing the upper passivation layer, the second passivation layer is still etched downwards for 5nm~25nm.

[0078] Understandably, the purpose of the first trench is to cut off the leakage current path between the layers of the stacked passivation. Circular and square trenches can only partially cut off this path, while a longitudinally elongated array can completely cut off the path, reducing gate leakage current and increasing device breakdown voltage. Simultaneously, because the upper passivation layer is thicker, its stress effect is stronger; the arrayed pattern can release some of the stress in the upper passivation layer. By changing the diameter or width of the arrayed pattern and the etching depth, the degree of stress release can be altered, bringing the total stress of the stacked passivation to zero, improving device reliability, and extending device lifespan.

[0079] Optionally, the first passivation layer and the second passivation layer can be made of the same material.

[0080] Specifically, conventional single-layer or multi-layer passivation is used when preparing the passivation layer, rather than stacked passivation.

[0081] For single layer The layers are arrayed, and the first trench can release excess stress inside the thin film, which can regulate the overall stress level to a certain extent, alleviate wafer warping caused by thin film stress, and slightly improve device reliability.

[0082] Arraying multiple passivation layers can release the stress in the upper layer to achieve zero stress and cut off the leakage current channel between layers. However, the multilayer passivation process is more complex, and there are significant differences in the etching selectivity and etching rate of passivation films with different compositions and materials, which places higher demands on the etching process.

[0083] However, the fabrication of groove passivation layer structures using conventional single-layer passivation has inherent drawbacks that are difficult to overcome: First, it is impossible to completely release stress, making it impossible to achieve a zero-stress passivation layer. In addition, since high stress can cause reliability issues, the stress of a single-layer passivation layer is usually too low, making it impossible to introduce a high-pressure stress passivation layer to enhance the piezoelectric polarization effect of the AlGaN barrier layer, and its effect on improving the two-dimensional electron gas concentration in the channel is very limited.

[0084] Optionally, the etching depth of different pattern arrays is not consistent. This comparative scheme uses multiple rounds of EBL and etching processes to prepare array trench patterns with varying etching depths in batches. Only some etching depths reach over 90nm to cut off leakage channels between layers and suppress interlayer leakage. The remaining array patterns undergo only shallow etching, the core function of which is to release excess stress accumulated inside the upper film without damaging the layer interface structure. The advantage of this embodiment is that it reduces the overall etching degree of the passivation layer, which helps to ensure the stability of the passivation layer structure, avoids passivation layer collapse or side collapse, and still achieves a zero-stress passivation layer. At the same time, it reduces device leakage current and improves breakdown voltage.

[0085] Secondly, such as Figure 5 As shown, this embodiment of the invention provides a method for fabricating a GaN HEMT device structure, the method comprising: S1. Prepare an epitaxial substrate. The epitaxial substrate consists of a substrate layer, a buffer layer, a channel layer, and a barrier layer from bottom to top.

[0086] Specifically, such as Figure 6 As shown, the initial material used to fabricate arrayed passivated GaN HEMT devices is an epitaxial substrate, which is grown using an MOCVD system with triethylgallium (TG) as the substrate material. Trimethylaluminum ( ) as Ga source Ammonia ( ) serves as the Al source. As the nitrogen source, the carrier gas is high-purity hydrogen. The substrate consists of, from top to bottom, a SiC substrate, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer.

[0087] S2. Fabricate the source and drain electrodes on the barrier layer.

[0088] Specifically, source and drain electrodes are fabricated on the epitaxial substrate through steps S21-S23, resulting in an epitaxial substrate with source and drain electrodes, as shown in Figure 1. Figure 7 As shown.

[0089] S21. Photolithographically etch the source electrode region and drain electrode region on the AlGaN barrier layer, wherein S21 includes steps S211 to S215.

[0090] S211. Place the epitaxial substrate on a hot plate at 200 degrees Celsius and preheat for 5 minutes.

[0091] S212. Apply release adhesive (PMGI SF6) to the AlGaN barrier layer. The spin coater speed is 2000 rad / min, the spin coat time is 40 sec, and the spin coat thickness is 0.35 μm. Then, bake the sample on a hot plate at 200°C for 5 minutes.

[0092] S213. Apply photoresist (EPI621) to the release adhesive. The spin coater speed is 5000 rad / min, the spin coat time is 30 sec, and the spin coat thickness is 0.77 μm. Then, place the sample on a hot plate at 90°C and bake for 1 minute.

[0093] S214. Place the sample that has been coated and spin-coated into the photolithography machine to expose the coated surface for 230ms. Then, place the exposed sample on a hot plate at 110°C and bake for 1 minute.

[0094] S215. Immerse the sample in developer (EPD1000) to remove photoresist and stripper. The development time is 45 seconds. Then rinse with ultrapure water and dry with nitrogen to obtain the defined source electrode region and drain electrode region.

[0095] S22. Evaporate ohmic metal on the AlGaN barrier layer in the source and drain electrode regions and on the photoresist outside the source and drain electrode regions, wherein S22 includes steps S221 to S223.

[0096] S221. Place the sample with the photolithographic pattern of the active electrode and drain electrode into a plasma resist remover for underfilm treatment at a power of 200W. =100sccm, processing time 5 minutes.

[0097] S222. Place the sample into the electron beam evaporation stage and wait for the vacuum level in the reaction chamber of the electron beam evaporation stage to reach... Subsequently, ohmic metals were evaporated on the AlGaN barrier layers in the source and drain electrode regions and on the photoresist outside the source and drain electrode regions to form the source and drain electrodes. The ohmic metals were arranged from bottom to top as Ti / Al / Ni / Au = 200 / 1600 / 550 / 450 Å.

[0098] S223. After the ohmic metal evaporation is completed, the sample is stripped to remove the ohmic metal, photoresist and release adhesive outside the source electrode and drain electrode. The sample is then rinsed with ultrapure water and dried with nitrogen.

[0099] S23. The sample after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing treatment, so that the ohmic metal on the AlGaN barrier layer in the source and drain electrodes sinks to the GaN buffer layer, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel. The annealing process conditions are: annealing atmosphere... The annealing temperature is 840 degrees Celsius and the annealing time is 60 seconds.

[0100] S3. A passivation layer is grown on the source electrode, drain electrode, and barrier layer, and an array structure is fabricated.

[0101] In one possible implementation, a first passivation layer and a second passivation layer are grown on the barrier layer between the source electrode and the drain electrode, and an arrayed structure is fabricated, including: S31. Perform surface pretreatment on the device surface to remove particles and the natural oxide layer.

[0102] Specifically, such as Figure 8 As shown, deposition is required on the device surface. The passivation layer area is treated with ammonia water to thoroughly remove micron or nano-sized particles, organic residues, and metallic impurities, preventing impurities from becoming leakage channels and trap centers. At the same time, it moderately peels off the unstable natural oxide layer to obtain a chemically uniform surface and improve the uniformity of subsequent passivation film adhesion.

[0103] S32. Preparation of silicon-rich substrate by PECVD Passivation layer, silicon-rich The passivation layer thickness is 30nm.

[0104] Specifically, a silicon-rich layer is deposited on the surface of the AlGaN barrier layer using a PECVD device. The passivation layer has a thickness of 30nm.

[0105] First, the sample with the source and drain electrodes fabricated is cleaned in steps S321-326: S321. Clean the surface of the sample after the source electrode and drain electrode have been fabricated.

[0106] S322. Place the sample in acetone solution and ultrasonically clean it for 5 minutes with an ultrasonic intensity of 2.2.

[0107] S323. Place the sample in a 60°C stripping solution and heat in a water bath for 15 minutes.

[0108] S324. Place the sample in acetone solution and isopropanol solution in sequence and ultrasonically clean for 3 minutes with an ultrasonic intensity of 2.2.

[0109] S325. Rinse the sample with ultrapure water and dry it with nitrogen.

[0110] S326. Perform surface pretreatment within 30 minutes of the start of the passivation process.

[0111] Then, a 30 nm thick AlGaN barrier layer was grown on the source electrode, drain electrode, and active region using PECVD. The passivation layer is grown under the following process conditions: ( =1091sccm =10sccm, =1091sccm, =0 sccm, pressure = 600 mT, temperature = 350 degrees Celsius, power = 30 W, deposition time = 4 minutes; the resulting material possesses silicon-rich properties. Epitaxial substrates with passivation layers, such as Figure 9 middle As shown.

[0112] Silicon-rich Primarily relying on its own silicon-rich composition and intrinsic compressive stress, it effectively saturates the dangling bonds on the AlGaN / GaN surface, reduces the interface state density, significantly suppresses current collapse, and simultaneously repairs minor lattice damage on the surface, weakens carrier scattering, and increases 2DEG concentration. The effect of this layer is not thickness-dependent; therefore, only 30 nm is needed to achieve all its functions.

[0113] S33. Preparation of nitrogen-rich upper layer by PECVD passivation layer, nitrogen-rich The passivation layer thickness is 90 nm; the total thickness of the passivation layer is 120 nm.

[0114] Specifically, a silicon-rich substrate is grown on the AlGaN barrier layer of the source electrode, drain electrode, and active region using PECVD technology. Passivation layer. A first silicon-rich layer was applied using a PECVD device. A nitrogen-rich layer is deposited on the surface of the passivation layer. Its thickness is 90nm, and the total passivation layer is 120nm. The upper layer is nitrogen-rich. The effectiveness of the passivation layer is affected by its thickness; currently, the industry standard is... The conventional thickness of the passivation layer is 120 nm, therefore the total thickness of the stacked passivation layer in this invention is also 120 nm.

[0115] First, the sample with the source and drain electrodes fabricated is cleaned using steps S331-335: S331. Place the sample in acetone solution and ultrasonically clean it for 5 minutes with an ultrasonic intensity of 2.2.

[0116] S332. Place the sample in a 60°C stripping solution and heat in a water bath for 15 minutes.

[0117] S333. Place the sample in acetone solution and isopropanol solution in sequence and ultrasonically clean for 3 minutes. The ultrasonic intensity is 2.2.

[0118] S334. Rinse the sample with ultrapure water and dry it with nitrogen.

[0119] S335. Perform surface pretreatment within 30 minutes of the start of the passivation process.

[0120] Then, on the AlGaN barrier layer of the source electrode, drain electrode, and active region, a 90 nm thick layer was grown using PECVD. The passivation layer is grown under the following process conditions: (2%SiH4 / N2) = 1091 sccm, NH3 = 50 sccm, N2 = 1091 sccm, He = 0 sccm, pressure = 600 mT, temperature = 350 degrees Celsius, power = 30 W, deposition time = 15 minutes; the resulting product is nitrogen-rich. Epitaxial substrates with passivation layers, such as Figure 10 middle As shown.

[0121] Nitrogen enrichment The passivation layer has the characteristics of tensile stress, high density and strong insulation. On the one hand, it uses tensile stress to suppress short-channel effect, improve gate control capability, reduce off-state leakage current, reduce threshold voltage drift, improve device consistency and better ensure device RF performance. On the other hand, it acts as the main physical protection barrier, effectively isolating water vapor, oxygen and external pollutants, significantly improving breakdown voltage and long-term reliability. At the same time, it balances the compressive stress of the first silicon-rich layer to alleviate the overall film stress and reduce wafer warpage.

[0122] S34. Use EBL lithography to design an array pattern on the surface of the passivation layer.

[0123] Specifically, different array patterns (circular, square, rectangular, etc.) are designed on the surface of the stacked passivation layer using EBL. The diameter of the circular pattern is the same as the side length of the square, which is 200 nm. The rectangular pattern can be divided into those along the gate width direction and those along the gate length direction, or a combination of multiple patterns, with a width of 200 nm. The purpose is to remove the passivation layer in the exposed area through subsequent etching arraying, thereby relaxing the stress of the top passivation layer and cutting off the interlayer leakage current channels of the stacked passivation to varying degrees. First, through steps 341~344... Photolithographic arrayed regions on the passivation layer: S341. Place the sample on a hot plate at 200°C and preheat for 5 minutes.

[0124] S342. Perform EBL photoresist coating and spin-coating. The spin-coating speed is 3500 rad / min, the spin-coating time is 40 sec, the photoresist layer thickness is 450 nm, and the sample is baked on a hot plate at 150°C for 1 minute.

[0125] S343. Place the sample into the EBL lithography machine to expose the photoresist in the gate trench area.

[0126] S344. Place the exposed sample into the developer to remove the photoresist in the grid trench area and dry it with nitrogen.

[0127] S35. Etch the passivation layer to a depth of 95~115nm to transfer the arrayed pattern onto the passivation layer.

[0128] Specifically, the ICP-RIE process is used to analyze the arrayed region. The passivation layer is etched.

[0129] The etching conditions are: =60sccm, =2sccm, pressure=1Pa, upper electrode power=100W, lower electrode power=25W. Etching depth is 95~115nm. After ICP-RIE process... Epitaxial substrate after passivation layer etching, such as Figure 11 As shown.

[0130] S4. Photolithographically etch the gate region on the dielectric layer and evaporate the gate metal to prepare a T-shaped gate.

[0131] Specifically, in A photolithographically etched gate trench region is applied to the passivation layer, and the gate trench region is then processed using an ICP process. The passivation layer is etched. Using F-based etching, the passivation layer is removed according to an array of photolithographic patterns at a depth of 95nm~115nm, exceeding the thickness of the upper passivation layer. After removing the upper passivation layer, etching continues downwards for 5nm~25nm to cut off the leakage current channels between the stacked passivation layers. Circular and square patterns can only partially cut off these channels, while the vertically elongated array can completely cut them off, reducing gate leakage current and increasing device breakdown voltage. Simultaneously, because the upper passivation layer is thicker, its stress effect is stronger; the arrayed pattern can release some of the stress in the upper passivation layer. By changing the diameter or width of the arrayed pattern and the etching depth, the degree of stress release can be altered, bringing the total stress of the stacked passivation layer to zero, improving device reliability and extending device lifespan.

[0132] First, through steps S401~405... Photolithographic gate trench area on passivation layer: S401. Place the sample on a hot plate at 200°C and preheat for 5 minutes.

[0133] S402. Perform EBL photoresist coating and spin-coating. The spin-coating speed is 3500 rad / min, the spin-coating time is 40 sec, the photoresist layer thickness is 450 nm, and the sample is baked on a hot plate at 150°C for 1 minute.

[0134] S403. Place the sample into the EBL lithography machine to expose the photoresist in the gate trench area.

[0135] S404. Place the exposed sample into the developer to remove the photoresist in the grid area and dry it with nitrogen.

[0136] S405. Remove the gate trench area using ICP etching process. The etching conditions for the passivation layer are as follows: =60sccm, =2sccm, pressure=1Pa, upper electrode power=100W, lower electrode power=25W. Etching depth equals Total layer thickness.

[0137] The epitaxial substrate with photolithographic groove regions produced after steps S401-405 is as follows: Figure 12 As shown.

[0138] Then, through steps S406 to S410, the gate electrode region is photolithographically etched on the AlGaN barrier layer.

[0139] S406. Place the sample on a hot plate at 200°C and preheat for 5 minutes.

[0140] S407, in The passivation layer was coated with release adhesive (PMGI SF6) at a spin coater speed of 2000 rad / min for 40 seconds, resulting in a spin coat thickness of 0.35 μm. The sample was then baked on a hot plate at 200°C for 5 minutes.

[0141] S408. Apply photoresist (EPI621) to the release adhesive. The spin coater speed is 5000 rad / min, the spin coat time is 30 sec, and the spin coat thickness is 0.77 μm. Then, place the sample on a hot plate at 90°C and bake for 1 minute.

[0142] S409. Place the sample that has been coated and spin-coated into the photolithography machine to expose the coated surface for 280ms. Then, place the exposed sample on a hot plate at 110°C and bake for 1 minute.

[0143] S410, immerse in developer (EPD1000) to remove photoresist and stripper, develop for 60 seconds, then rinse with ultrapure water and dry with nitrogen.

[0144] Finally, through steps S411~413, the gate electrode is evaporated on the AlGaN barrier layer in the gate electrode region and on the photoresist outside the gate electrode region using an electron beam evaporation process.

[0145] S411. Place the sample with the photolithographic pattern of the gate electrode into a plasma resist remover for underfilm treatment, power 200W. =100sccm, processing time 5 minutes.

[0146] S412. Place the sample in the electron beam evaporation stage. After the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10-6 Torr, evaporate the gate metal on the AlGaN barrier layer in the gate electrode region and the photoresist outside the gate electrode region. The gate metal is in the order of Ni / Au=450 / 2700 Å from bottom to top.

[0147] S413. The sample after the gate metal evaporation is completed is stripped to remove the gate metal, photoresist and stripping adhesive outside the gate electrode area. The sample is rinsed with ultrapure water and dried with nitrogen to form the gate electrode.

[0148] Finally, the epitaxial substrate with T-type gate electrodes, such as Figure 13 As shown.

[0149] S5. Photolithographically pattern metal interconnect regions on the source electrode, drain electrode, and un-etched dielectric layer, and evaporate to form a metal interconnect layer.

[0150] Specifically, gate feet are formed through EBL and etching, followed by gate caps formed through stepper lithography, and finally, gate metal is evaporated. For example... Figure 3 As shown, the array pattern is not fixed and can be combined arbitrarily. The ultimate goal is to release the excess stress of the top passivation layer, so that the total stress is zero, and at the same time cut off the leakage current path between the gate and the drain.

[0151] First, through steps S501~505, in Photolithographically etched metal interconnect openings on the passivation layer: S501. Place the sample on a hot plate at 200°C and preheat for 5 minutes.

[0152] S502. Apply photoresist (EPI621) to the sample. The spin coater speed is 3000 rad / min and the spin coat time is 30 sec. Then place the sample on a hot plate at 90°C and bake for 1 minute.

[0153] S503. Place the sample that has been coated and spin-coated into the photolithography machine to expose the coated surface for 280ms. Then, place the exposed sample on a hot plate at 110°C and bake for 1 minute.

[0154] S504. Place the exposed sample into the developer (EPD1000) to remove the photoresist in the interconnect opening area. The development time is 75 seconds. Then rinse it with ultrapure water and dry it with nitrogen.

[0155] S505: Before etching the metal interconnect opening area, perform hard film etching and bake the sample on a hot plate at 100°C for 1 minute.

[0156] Then, in step S507, the interconnect opening areas are sequentially etched away using the ICP process. Passivation layer: S507, using ICP etching process, the reaction gas is... and , =60sccm, =2sccm, pressure=1Pa, upper electrode power=100W, lower electrode power=25W, remove 120nm thick material in the interconnect opening area. Passivation layer.

[0157] Next, through steps S508-511, the source and drain electrodes in the metal interconnect opening region and the un-opened area are etched. Photolithographic metal interconnect layer on passivation layer: S508. Place the sample with the completed metal interconnect opening etching on a hot plate at 200°C for 5 minutes for pre-baking.

[0158] S509. Apply release adhesive (PMGI SF6) to the AlGaN barrier layer. The spin coater speed is 2000 rad / min, the spin coat time is 40 sec, and the spin coat thickness is 0.35 μm. Then, bake the sample on a hot plate at 200°C for 5 minutes.

[0159] S508. Apply photoresist (EPI621) to the release adhesive. The spin coater speed is 5000 rad / min, the spin coat time is 30 sec, and the spin coat thickness is 0.77 μm. Then, place the sample on a hot plate at 90°C and bake for 1 minute.

[0160] S510. Place the sample that has been coated and spin-coated into the photolithography machine to expose the coated surface for 270ms. Then, place the exposed sample on a hot plate at 110°C and bake for 1 minute.

[0161] S511. Immerse the sample in developer (EPD1000) to remove photoresist and stripper in the metal interconnect area. The development time is 60 seconds. Then rinse with ultrapure water and dry with nitrogen.

[0162] Finally, through steps S512-514, electrodes and... The metal interconnect layer is evaporated on the photoresist outside the passivation layer and the metal interconnect region.

[0163] S512. Place the sample with the metal interconnect area into a plasma stripper for bottom film treatment (power 200W). =100sccm, processing time is 5 minutes.

[0164] S513. Place the sample in the electron beam evaporation stage. After the vacuum level in the reaction chamber of the electron beam evaporation stage reaches 2 × 10⁻⁶ Torr, then place the electrodes and... Interconnect metal is evaporated on the photoresist outside the passivation layer and the metal interconnect region to form a metal interconnect layer. This metal interconnect layer consists of Ti / Au = 450 / 2700 Å from bottom to top, to lead out electrodes.

[0165] S514. The sample after the interconnect metal evaporation is completed is stripped to remove the metal, photoresist and release adhesive outside the metal interconnect layer, and the sample is rinsed with ultrapure water and dried with nitrogen to complete the device fabrication.

[0166] Understandably, this invention, through the deposition of stacked passivation layers, can significantly increase the channel 2DEG concentration, improve mobility, reduce current collapse, and enhance the device's output current and transconductance characteristics. Furthermore, by precisely controlling the passivation layer stress through arraying, the total stress of the passivation layer is reduced to zero, preventing passivation film cracking and wafer warping, reducing internal stress defects, and improving process stability. In addition, the arrayed passivation structure can cut off interlayer leakage current channels, reducing the device's off-state leakage current and consequently increasing the breakdown voltage. A higher breakdown voltage means the device can operate safely at higher voltages, enhancing its power output capability in high-voltage applications.

[0167] The following section provides further explanation of the effects based on experimental data: First, this invention can significantly increase the 2DEG concentration in the channel, improving mobility and effectively suppressing current collapse. Because excessive stress can easily lead to negative issues such as film warping, interface relaxation, and barrier layer cracking, the stress level of traditional single compressive stress passivation layers is limited. However, in this invention, the subsequent upper passivation layer can offset the stress of the lower passivation layer, reducing the total stress and avoiding various problems caused by excessive stress. Based on this stress neutralization mechanism, this invention can use a lower passivation layer with higher pressure stress, more fully enhancing the piezoelectric polarization effect inside the AlGaN barrier layer, significantly increasing the interface polarization charge density, and thus simultaneously improving the 2DEG concentration and carrier mobility. Figure 14 As shown, thanks to the improved 2DEG characteristics, both the device's saturated output current and peak transconductance are significantly enhanced. Simultaneously, the high-density, high-stress thin film used in the underlying layer of this invention can effectively passivate surface traps, such as... Figure 15 As shown, the current collapse subsequently decreases.

[0168] Secondly, this invention enables precise control of the passivation layer stress, achieving a zero-stress passivation layer. The invention employs a stacked passivation structure, with a compressive stress passivation layer at the bottom and a tensile stress passivation layer at the top. These two layers cancel each other out, balancing the overall film stress. Based on this, the passivation layers are arrayed using photolithography. Etching releases residual excess stress in the upper passivation layer, further refining the overall stress level and achieving high-precision control of stress balance, ultimately reaching the ideal zero-stress passivation state. Therefore, the arrayed passivation layer can prevent passivation film cracking and wafer warping, reduce internal stress defects in the device, and improve process stability.

[0169] Meanwhile, this invention can effectively suppress off-state leakage current, significantly improve breakdown voltage, and fully exploit the power output potential of the device under high-voltage operating conditions. Conventional multilayer passivation processes are not stable and easily form interlayer interface states at the junction of two thin films. Defective channels at this point become leakage paths for carrier tunneling, resulting in high off-state leakage current and degraded withstand voltage. Arrayed passivation structures can suppress the interlayer interface state energy levels introduced by multilayer passivation, cut off interlayer leakage channels, and hinder electron tunneling transport. Figure 16 As shown, the off-state leakage current of the device is reduced, and the breakdown voltage is significantly improved. The higher breakdown voltage widens the voltage range in which the device can operate safely, allowing the device to operate stably at higher leakage voltages, outputting larger saturation current and output power density, ultimately comprehensively improving the overall power output performance of the device.

[0170] In addition, this invention possesses exceptional flexibility, effectively overcoming the inherent shortcomings of traditional passivation processes: after conventional passivation film deposition, the film stress and surface passivation effect are fixed, making it impossible to perform secondary optimization adjustments to device performance in subsequent processes, resulting in very limited performance control. However, this solution, while maintaining the unchanged stacked passivation structure, can differentiate the degree of stress release and interface trap suppression effect of the passivation layer simply by changing the arrayed patterns of different sizes and arrangement periods, achieving diverse performance optimization goals such as stress relaxation, leakage current suppression, and voltage withstand improvement as needed. It is important to emphasize that there is no limit to the number of arraying operations. During device fabrication, the passivation layer arraying process can be flexibly embedded into device fabrication process nodes, performing multiple arraying processes based on device performance feedback to fully improve device characteristics. Compared to the inherent defect of traditional passivation layers, which cannot be adjusted for performance after deposition and finalization, this invention can achieve iterative optimization of device performance through multiple arraying processes, significantly expanding the process debugging space and possessing a strong advantage in performance fine-tuning. This opens up a new technical path for precisely controlling the stress of the passivation layer through surface patterning, with significant advantages in process adaptability, flexibility and compatibility.

[0171] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A grooved passivation layer structure, comprising an epitaxial substrate, characterized in that, Also includes: A first passivation layer and a second passivation layer are stacked sequentially from top to bottom on an epitaxial substrate, and an interlayer interface is provided between the first passivation layer and the second passivation layer. The first trench is formed in the first passivation layer and the second passivation layer. The depth of the first trench is greater than the thickness of the first passivation layer and less than the total thickness of the first passivation layer and the second passivation layer. The first trench intersects with the leakage path at the interlayer interface, thereby blocking the leakage path.

2. The groove passivation layer structure according to claim 1, characterized in that, There are multiple first trenches, and the multiple first trenches are arranged in an array to release the total interlayer stress between the first passivation layer and the second passivation layer.

3. The groove passivation layer structure according to claim 2, characterized in that, The first groove is a cuboid or a cylinder.

4. The groove passivation layer structure according to claim 1, characterized in that, The epitaxial substrate is also provided with a drain and a gate; The first trench is disposed between the gate and the drain, wherein the first trench intersects with the leakage path between the gate and the drain, and is used to block the leakage path between the gate and the drain.

5. The groove passivation layer structure according to claim 4, characterized in that, The number of the first trenches is one.

6. The groove passivation layer structure according to claim 1, characterized in that, The total thickness of the first passivation layer and the second passivation layer is 120 nm, and the depth of the first trench is 95 nm to 115 nm.

7. The groove passivation layer structure according to claim 1, characterized in that, The first trench extends downward through the first passivation layer and into the interior of the second passivation layer to a depth of 5 nm to 25 nm.

8. The groove passivation layer structure according to claim 1, characterized in that, The first passivation layer and the second passivation layer include: The first passivation layer and the second passivation layer are made of different materials; the first passivation layer uses nitrogen-rich materials. The second passivation layer is prepared using silicon-rich materials. preparation.

9. A method for fabricating a GaN HEMT device structure, characterized in that, The method includes: S1. Prepare an epitaxial substrate, wherein the epitaxial substrate comprises, from bottom to top, a substrate layer, a buffer layer, a channel layer and a barrier layer; S2. Fabricate source and drain electrodes on the barrier layer; S3. A first passivation layer and a second passivation layer are grown on the barrier layer between the source electrode and the drain electrode, and an array structure is prepared. The first passivation layer and the second passivation layer are stacked sequentially from top to bottom on the barrier layer, and there is an interlayer interface between the first passivation layer and the second passivation layer. S4. Photolithographically etch the gate region on the passivation layer and evaporate the gate metal to prepare a T-shaped gate; S5. Photolithographically etch metal interconnect regions on the source electrode, drain electrode, and second passivation layer, and evaporate to form a metal interconnect layer.

10. A method for fabricating a GaN HEMT device structure according to claim 9, characterized in that, The process of growing a first passivation layer and a second passivation layer on the barrier layer between the source electrode and the drain electrode and fabricating an arrayed structure includes: S31. Perform surface pretreatment on the device surface to remove particles and the natural oxide layer; S32. Preparation of silicon-rich substrate by PECVD The passivation layer serves as the second passivation layer, and the silicon-rich layer... The passivation layer thickness is 30nm; S33. Preparation of nitrogen-rich upper layer by PECVD The passivation layer serves as the first passivation layer, and the nitrogen-rich layer... The passivation layer thickness is 90 nm; the total thickness of the passivation layer is 120 nm. S34. Use EBL lithography to design an array pattern on the surface of the passivation layer; S35. Etch the passivation layer to a depth of 95~115nm to transfer the arrayed pattern onto the passivation layer.

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