Packaged electronic device comprising horizontally and vertically contacting configuration components

Abstract

Packaged electronic devices are disclosed that have horizontally and vertically contacting configuration components. The devices have first and second dies disposed between first and second support elements formed of multiple layers. The first die has first and second contact areas on a first major face thereof. The second die has a first contact area on a first major face thereof and a second contact area on a second major face thereof. The dies are bonded with their first faces to the second support element and with their second faces to the first support element. The first support element forms a conductive interconnect region electrically coupled to the first contact area of the second die. The second support element forms a plurality of islands: a first island coupled to the first contact area of the first die by an inner portion of a first connection element; a second island coupled to the first contact area of the second die by an inner portion of a second connection element. A third connection element couples the second contact area of the first die to the interconnect region.

Description

Technical Field

[0001] This disclosure relates to a packaged electronic device including horizontal contact configuration components and vertical direct contact configuration components.

[0002] For example, packaged electronic devices may include power components (such as gallium nitride (GaN)-based devices) with horizontal conduction capable of switching at high frequencies (100 kHz to 400 kHz) with high load current (up to 10 A to 15 A) or contact pads arranged on a single main surface in any case, and low-voltage components (such as silicon-based MOSFETs) with vertical conduction.

[0003] In particular, in the following description, reference will be made to packaged electronic devices in which horizontal contact configuration components and vertical direct contact configuration components are coupled to each other in a common source, common gate configuration. Background Technology

[0004] Electronic devices are known to include power components coupled in a common-source, common-gate configuration and low-voltage silicon MOSFET devices.

[0005] For example, a solution described in “GaNHEMT Improves Overall Performance in ZVS Totem Pole PFC Converters” presented by Marco Torrisi, Sebastiano Messina, Daniele Giovanni Sfilio, Giuseppina Fiore, Giuseppe Di Stefano, and Mario Cacciato at the 2023 IEEE Applied Power Conference and Exhibition (APEC) 978-1-6654-7539-6 / 23, held March 19-23, 2023, discusses the advantages achievable by using GaN transistors with wide bandgap and high switching frequency, which allows for reduced switching losses compared to individual components and other solutions using superjunction MOSFETs.

[0006] In this solution, the two devices are each integrated into their respective dies and encapsulated in a housing with through-holes.

[0007] While this solution has its advantages, there is still room for improvement in order to achieve the correct creepage distance (safe distance) under high-power operation conditions.

[0008] The purpose of this disclosure is to improve the performance of known devices. Summary of the Invention

[0009] According to this disclosure, a packaged electronic device and a packaging method are provided.

[0010] According to a first aspect, a packaged electronic device is provided, comprising: a first support element; a second support element, each of the first and second support elements comprising multiple layers, the multiple layers including a corresponding first conductive layer facing the interior of the packaged electronic device, a second conductive layer disposed facing the exterior of the packaged electronic device, and an insulating layer between the first and second conductive layers, the first conductive layer of the first support element forming an interconnect region; the first conductive layer of the second support element forming a plurality of mutually insulated islands, and including first islands and second islands; the second conductive layers of the first and second support elements forming a heat sink; a first die integrating a first electronic component and having a first main surface, a second main surface, a first contact area on the first main surface of the first die, and a second contact area on the first main surface of the first die; a second die integrating a second electronic component and having a first main surface, a second main surface, a first contact area on the first main surface of the second die, and a second contact area on the second main surface of the second die, the first die and the second... The die is coupled to a second support element with a corresponding first surface and to a first support element with a corresponding second surface, and the second contact area of ​​the second die is in electrical contact with the interconnection area of ​​the first support element; a first connecting element including its own internal portion and its own pins, a second connecting element having its own internal portion and its own pins, and a third connecting element having its own internal portion; and a housing, embedded with a first conductive layer of the first die, the second die, the first support element, and the second support element, an insulating layer of the first support element and the second support element, and the internal portions of the first connecting element, the second connecting element, and the third connecting element, the first pin and the second pin protruding from the housing, wherein the internal portion of the first connecting element is arranged between the first contact area of ​​the first die and the first island, the internal portion of the second connecting element is arranged between the first contact area of ​​the second die and the second island; and the internal portion of the third connecting element has a first segment coupled to the second contact area of ​​the first die and a second segment coupled to the interconnection area of ​​the first support element.

[0011] According to a second aspect, a method for packaging an electronic device is provided, comprising: bonding a first die to an interconnect region formed by a first conductive layer of a first support member, the first conductive layer being formed by multiple layers, the multiple layers further including a second conductive layer and an insulating layer between the first conductive layer and the second conductive layer; the first die integrating a first electronic component and having a first main surface, a second main surface, a first contact region on the first main surface of the first die, and a second contact region on the first main surface of the first die; the first die being coupled to the interconnect region of the first support member via its second surface; bonding a second die to the interconnect region of the first support member, the second die integrating a second electronic component and having a first main surface, a second main surface, a first contact region on the first main surface of the second die, and a second contact region on the second main surface of the second die; the second die being coupled to the first support member via its second surface; the second contact region of the second die being in electrical contact with the interconnect region of the first support member; bonding an internal portion of a first connecting element to the first contact region of the first die, the first connecting element having its own pins; and bonding an internal portion of a second connecting element to the first contact region of the second die. The second connecting element has its own pins; a first segment of the internal portion of the third connecting element is bonded to a second contact area of ​​the first die and a second segment of the internal portion of the third connecting element is bonded to an interconnect area of ​​the first support; a second support element is bonded to a first surface of the first die and the second die, the second support element comprising multiple layers, the multiple layers including a first conductive layer, a second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer of the second support element, the first conductive layer of the second support element forming a plurality of mutually insulated islands and including a first island and a second island, the first island being bonded to the internal portion of the first connecting element and the second island being bonded to the internal portion of the second connecting element; and a housing is formed, the housing being embedded in the first die, the second die, the first conductive layer of the first support element and the second support element, the insulating layer of the first support element and the second support element, and the internal portions of the first connecting element, the second connecting element and the third connecting element, the pins of the first connecting element and the second connecting element protruding from the housing, the second conductive layer of the first support element and the second support element forming a heat sink.

[0012] According to a third aspect, an electronic device is provided, comprising: a housing including a first side and a second side opposite to the first side; a first multilayer support element located in the housing on the first side of the housing, the first multilayer support element including a first plate exposed on the first side of the housing, and the first plate including first fins projecting laterally from the housing; a second multilayer support element located in the housing on the second side, the second multilayer housing including a second plate exposed on the second side of the housing, the second multilayer support element opposite to the first multilayer support element, and the second plate including second fins projecting laterally from the housing; a first cooling structure coupled to the first plate, the first cooling structure including a plurality of columns of first cooling channels extending from the first side of the housing into the first cooling structure; and a second cooling structure coupled to the second plate, the second cooling structure including second cooling channels and a plurality of protrusions extending outwardly from the housing, and the second cooling channels being in fluid communication with the first cooling channels. Attached Figure Description

[0014] To better understand this disclosure, embodiments thereof will now be described by way of non-limiting example with reference to the accompanying drawings, in which: Figure 1 A circuit diagram of an embodiment of this power device is shown, which is formed by a common-source, common-gate connection of a GaN transistor and a low-voltage MOSFET. Figure 2 The cross-section shows the integration within the respective die. Figure 1 A portion of GaN transistors and low-voltage MOSFETs, and their associated electrical connections; Figure 3 This is a top perspective view of the power device; Figure 4 This is a bottom perspective view of the power device; Figure 5 It is integrated Figure 2 The GaN transistor is shown, and a top view of the die with its contact area is also shown; Figure 6 It is integrated Figure 2 The low-voltage MOSFET is shown, and a top view of the die with its contact pads is shown. Figure 7A This is along the power device Figure 4 The cross section intercepted by line VIIA-VIIA; Figure 7B This is along the power device Figure 4 The cross section intercepted by line VIIB-VIIB; Figure 8 This is along the power device Figure 4 The cross section intercepted by line VIII-VIII; Figure 9 This is a bottom perspective view of a portion of this power device during an intermediate installation step; Figure 10 Shown in bottom perspective Figure 9 Details; Figure 11 This is another part of the power device in relation to Figure 9 Top perspective view before the parts are assembled; and Figures 12 to 14 A cooling system including a cooling plate and this power device is shown. Detailed Implementation

[0015] The following description refers to the arrangement shown; therefore, expressions such as “above,” “below,” “upper,” “lower,” “right,” “left,” etc. refer to the accompanying drawings and should not be interpreted in a restrictive manner.

[0016] Figure 1 An electronic device 1 is shown, consisting of a first transistor 2, a high-power transistor (here, a GaN MOSFET), a second transistor 3, and a low-voltage transistor (with a voltage lower than that of the first transistor 2), which are coupled in a common-source, common-gate configuration.

[0017] In detail, the first transistor 2 and the second transistor 3 each have a first conductive terminal 6, namely 7 (drain terminal); a second conductive terminal 8, namely 9 (source terminal); and a control terminal 10, namely 11 (gate terminal).

[0018] The second conductive terminal 8 of the first transistor 2 is coupled to the first conductive terminal 7 of the second transistor 3; and the control terminal 10 of the first transistor 2 is coupled to the second conductive terminal 9 of the second transistor 3 through an external voltage generator 15.

[0019] Furthermore, the first conductive terminal 6 of the first transistor 2 is coupled to the first output conductive terminal 16 of the electronic device 1; the second conductive terminal 9 of the second transistor 3 is coupled to the second output conductive terminal 17 of the electronic device 1; the control terminal 10 of the first transistor 2 is coupled to the first output control terminal 18 of the electronic device 1; and the control terminal 11 of the second transistor 3 is coupled to the second output control terminal 19 of the electronic device 1.

[0020] In addition, Figure 1 In the electronic device 1, the second conductive terminal 8 of the first transistor 2 and the first conductive terminal 7 of the second transistor 3 are coupled to the intermediate output terminal 23 of the electronic device 1; and the second conductive terminal 8 of the first transistor 2 is also coupled to the output verification terminal 24 (auxiliary terminal or "Kelvin" source terminal) of the electronic device 1.

[0021] also, Figure 1 The parasitic diode 25, which is anti-series coupled to the second transistor 3, is shown.

[0022] exist Figure 1 In the electronic device 1, the first transistor 2 is a horizontally contacted component, and the second transistor 3 is a vertically contacted component; they can be, for example, as follows: Figure 2 The implementation is shown.

[0023] For details, refer to Figure 2 The first transistor 2 is formed in the first die 26, which has a first surface 26A and a second surface 26B, and includes a substrate 27, a buffer layer 28, a first semiconductor layer 29 and a second semiconductor layer 30 that are stacked on each other.

[0024] The substrate 27 may be made of, for example, single-crystal silicon; the buffer layer 28 directly superimposed on and in contact with the substrate 27 may be made of, for example, one or more AlGaN / GaN / AlN alloys; for example, the first semiconductor layer 29 directly superimposed on and in contact with the buffer layer 28 may be made of a first semiconductor alloy of elements from Group III and Group V of the periodic table, such as gallium nitride (GaN); and for example, the second semiconductor layer 30 directly superimposed on and in contact with the first semiconductor layer 28 may be made of a second semiconductor alloy of elements from Group III and Group V of the periodic table that are different from the first semiconductor alloy, such as aluminum gallium nitride (AlGaN).

[0025] A substrate metallization layer 31 extends on the substrate 27. The substrate metallization layer 31 defines a second surface 26B of the die 26.

[0026] The first semiconductor layer 29 forms a channel layer on its upper part, and the second semiconductor layer 30 forms a barrier layer.

[0027] The first semiconductor layer 29 and the second semiconductor layer 30 are, for example, N-type.

[0028] The GaN gate region 33 extends over the second semiconductor layer 30. The GaN gate region 33 is made of a conductive material, such as a third semiconductor alloy different from the first and second semiconductor alloys, and is made of elements from Group III and V of the periodic table, such as p-type gallium nitride (p-GaN).

[0029] The metal gate electrode 34 is disposed above and in direct electrical contact with the GaN gate region 33, forming Figure 1 The first transistor 2 is connected to the control terminal 10 and is coupled to the first output control terminal 18 of the electronic device 1.

[0030] The drain electrode 35 and the source electrode 36 are disposed above and in contact with the second semiconductor layer 30 on opposite sides of the GaN gate region 33, and form a... Figure 1 The conductive terminals 6 and 8 of the first transistor 2 are coupled to the first output conductive terminal 16 and the intermediate output terminal 23 of the electronic device 1, respectively.

[0031] Here, all electrodes 34 to 36 of the first transistor 2 face the first surface 26A of the first die 26 and are electrically insulated from each other, for example, through the first dielectric layer 37.

[0032] The second transistor 3 is formed in the second die 38 ( Figure 2 (shown only partially in the image) The second die has a first surface 38A and a second surface 38B, and includes a substrate 40 and an epitaxial layer 41 superimposed on the substrate 40 of the second die 38.

[0033] The body region 42 extends in the epitaxial layer 41; the source region 43 is surrounded by the body region 42; the MOSFET gate region 44 is superimposed on the epitaxial layer 41; and the oxide layer 45 surrounds the MOSFET gate region 44.

[0034] The second die 38 also includes a source metallization layer 47 superimposed on the epitaxial layer 41 and the oxide layer 45 and surrounded by the second dielectric layer 46; and a drain metallization layer 48 below the substrate 40.

[0035] Here, the MOSFET gate region 44 is coupled to the corresponding gate metallization, schematically represented only by the second output control terminal 19. Furthermore, the source metallization 47 is coupled to... Figure 1 The second output conductive terminal 17 of the electronic device 1.

[0036] For example, source metallization 47 faces the first surface 38A of the second die 38; drain metallization 48 forms the second surface 38B of the second die 38.

[0037] Figure 2 The first connection 49A between the substrate 27 of the first transistor 2 and the substrate 40 of the second transistor 3, and the second connection 49B between the source electrode 36 of the first transistor 2 and the substrates 27 and 40 (via the first connection 49A) are also schematically shown. Figure 2 The external connection 49C between the gate electrode 34 of the first transistor 2 and the source metallization 47 of the second transistor 3 via the voltage generator 15 is also shown in dashed lines.

[0038] The following text refers to Figures 3 to 11 The connection between 49A and 49B is described, showing a packaged electronic device 50 with dual cooling sides, suitable for surface mounting, and featuring high creepage and electrical insulation.

[0039] Specifically, the packaged electronic device 50 includes a housing 51 that is generally parallelepiped in shape, having a first main surface 51A, a second main surface 51B, two front surfaces 51C, and two side surfaces, which are also referred to below as the first side surface 51D and the second side surface 51E.

[0040] In the example shown, the side surfaces 51D and 51E are longer than the front surface 51C; however, the housing 51 may have a generally parallelepiped shape with a square base, wherein the front surface 51C and the side surfaces 51D and 51E are of equal length.

[0041] The pins (simply indicated here by the number 54, but referred to below as pins 54A to 54G for the purpose of distinguishing them) protrude from the side surfaces 51D and 51E.

[0042] The housing 51 is made of an insulating material (such as resin), which exposes the first plate 52 and the second plate 53 on the first main surface 51A and the second main surface 51B, respectively.

[0043] The first plate 52 and the second plate 53 protrude slightly relative to the shell 51 at this point, as... Figure 8 They are visible in the cross-section; alternatively, they can be flush with the corresponding main surfaces 51A, 51B.

[0044] In addition, plates 52 and 53 have fins or tabs 55 protruding from the front surface 51C; pins 54 are folded to form wettable side wings.

[0045] The housing 51 is fully embedded with the first component (specifically the first transistor 58, which has a contact area on only one main surface) and the second component (specifically the second transistor 59, which has contact areas on both main surfaces, such as...). Figure 5 , Figure 6 (As shown).

[0046] The first transistor 58 and the second transistor 59 are respectively formed in the first die 60 and the second die 61, which have a generally parallelepiped shape.

[0047] For example, the first transistor 58 and the second transistor 59 can be like Figure 2 The first transistor 2 is formed in the same way as the second transistor 3.

[0048] In detail, Figure 5 The first face 60A of the first die 60 is shown (e.g. Figure 2 The first die 26 has a first surface 26A). The first die 60 also has Figure 7A , Figure 7B and Figure 8 The second visible side is 60B.

[0049] In particular, Figure 5 The control contact area 63 of the first transistor 58 is shown (e.g., Figure 2 The gate electrode 34 of the first transistor 2), and the first current-conducting contact region 64 of the first transistor 58 (e.g., Figure 2 The drain electrode 35 of the first transistor 2 and the second current-conducting contact region 65 of the first transistor 58 (e.g., the drain electrode 35 of the first transistor 2) .... Figure 2 The source electrode 36 of the first transistor 2), they are passivated by a passivation layer 66 (e.g., Figure 2 Surrounded by the first dielectric layer 37).

[0050] The contact areas 63 to 65 of the first transistor 58 can be, for example, as follows: Figure 5 As shown, the second current conduction contact region 65 and the control contact region 63 of the first transistor 58 can be arranged side by side along the first side of the first die 60, and the first current conduction contact region 64 of the first transistor 58 can be arranged along the opposite side of the first die 60.

[0051] exist Figure 5 In order to make this clear, Figure 4 The cross-sectional lines VIIA-VIIA, VIIB-VIIB and VIII-VIII are shown in the regions where they pass through the first core 60.

[0052] Figure 6 The first surface 61A of the second die 61 is shown (e.g. Figure 2 The second die 38 has a first surface 38A). The second die 61 also has Figure 7A and Figure 7B The second surface 61B is visible in the image.

[0053] In particular, Figure 6 The control contact area 68 of the second transistor 59 is shown (e.g., coupled to...). Figure 2 The MOSFET gate region 44 of the second transistor 3 and the first current-conducting contact region 69 of the second transistor 59 (e.g., the MOSFET gate region 44 of the second transistor 3 and the first current-conducting contact region 69 of the second transistor 59) Figure 2 The source metallization 47 of the second transistor 3). The control contact region 68 and the first current conduction contact region 69 of the second transistor 59 are separated by the second dielectric layer 46 (e.g., the second dielectric layer 46). Figure 2 The second dielectric layer 46) is electrically separated.

[0054] The second transistor 59 also includes its own second current-conducting contact region (e.g. Figure 2 The drain metallization 48 of the second transistor 3), in Figures 6 to 8 Invisible in the middle, extending on the opposite side of the second die 61, but... Figure 7A and Figure 7BIt is indicated schematically by a dashed line and marked by 71.

[0055] It should be noted that the shape of the first current-conducting contact region 69 of the second transistor 59 is complex, but it can have other shapes depending on the designer's needs.

[0056] In the following text, reference will be made to Figures 7A to 11 The connection of dies 60 and 61 in packaged electronic device 50 is described. For ease of understanding, the first current conducting contact region 64 of the first transistor 58 is also referred to as the drain contact region 64 of the first transistor 58; the second current conducting contact region 65 of the first transistor 58 is also referred to as the source contact region of the first transistor 58; the first current conducting contact region 69 of the second transistor 59 is also referred to as the source contact region 69 of the second transistor 59; and the second current conducting contact region of the second transistor 59 is also referred to as the drain contact region 71 of the second transistor 59.

[0057] Reference Figure 7A , Figure 7B and Figure 8 The first plate 52 and the second plate 53 are respectively part of the first support member 75 and the second support member 76, and are embedded in the material of the housing 51 except for the exposed surfaces of the plates 52 and 53.

[0058] In detail, the first support 75 is formed of a multilayer, electrically insulating and thermally conductive substrate, such as a DBC (direct bonded copper) substrate, including a first conductive layer 80 (e.g., copper); an intermediate insulating layer 81 (e.g., ceramic); and a second conductive layer (e.g., copper) formed by the first plate 52.

[0059] In fact, the first support member 75 has an outward-facing surface that mainly forms the first main surface 51A of the housing 51 (as shown above). Figure 3 and Figure 4 (as indicated) and the inward-facing surface 75A formed by its first conductive layer 80.

[0060] The inward-facing surface 75A of the first support member 75 defines a support surface (also indicated by 75A below), which is bonded by a first adhesive layer 82 (e.g., solder paste) to the second surfaces 60B of the first die 60 and the second die 61, which are spaced apart from each other.

[0061] The first conductive layer 80 of the first support 75 is continuous, or in any case forms an interconnecting region (also indicated by 80 below), such as the lower metallization of the dies 60, 61 to which it is electrically connected (in this example, Figure 2 The substrate metallization layer 31 of the first transistor 2 and Figure 2The drain metallization layer 48 of the second transistor 3). For example, in this way, Figure 2 The substrates 27 and 40 are coupled to each other, and a first conductive layer 80 is formed. Figure 2 The first connection is 49A.

[0062] In other words, in Figure 2 In this example, the substrate 27 of the first die 26 and the substrate 40 of the second die 38 are both arranged to face and be in electrical contact with the support surface 75A of the first support 75.

[0063] The second support 76 is also formed of a multilayer electrically insulating and thermally conductive substrate, such as a DBC substrate, including a first conductive layer 84 (e.g., copper); an intermediate insulating layer 85 (e.g., ceramic); and a second conductive layer (e.g., copper) formed by the second plate 53.

[0064] In fact, the second support member 76 has an outward-facing surface that mainly forms the second main surface 51B of the housing 51 (as shown above). Figure 3 and Figure 4 (as indicated) and the inward-facing surface 76A formed by the first conductive layer 84.

[0065] The inward-facing surface 76A of the second support 76 defines the thermal connection surface (and is still indicated by 76A below).

[0066] The first die 60 and the second die 61 are coupled to the thermal connection surface 76A of the second support 76 by means of the internal portions 87A to 87F of the connecting elements 88A to 88F and the adhesive regions (e.g., solder) formed in the second adhesive layer 90A and the third adhesive layer 90B.

[0067] Connecting elements 88A to 88G (their internal portions 87A to 87G are also referred to as clamps below, and are usually indicated by the number 87 when there is no need to distinguish them) are as follows Figure 9 and 10 As shown, and described in detail below.

[0068] like Figure 11 As shown and described in detail below, the first conductive layer 84 of the second support 76 is shaped to form a plurality of islands 89A, 89B to 89C, 89D, 89E, 89F and 89G (which are generally referred to as islands 89 below when it is not necessary to distinguish them) for electrical and thermal connections of the contact areas 64, 65, 68, 69 of the dies 60, 61. Figure 5 and Figure 6 ).

[0069] In other words, the contact areas 64, 65, 68, and 69 of the first transistor 58 and the second transistor 59 are electrically coupled to the clamp 87 and the island 89 through the adhesive areas 90A and 90B.

[0070] The first core 60, the second core 61, the connecting elements 88A to 88G, and the first support member 75 are arranged in a mutually... Figure 9 and Figure 10 As can be seen, when dies 60 and 61 have been bonded to the first support 75 and connecting elements 88A to 88G have been bonded to dies 60 and 61, Figure 9 The intermediate installation steps are shown in the bottom perspective view, but Figure 11 The second support member 76 shown does not yet exist. Figure 10 It shows Figure 9 Zoomed-in details.

[0071] For details, refer to Figure 9 The connecting elements 88A to 88G here include seven connecting elements, identified as first control connecting element 88A, first Kelvin connecting element 88B, first conductive connecting element 88C, second conductive connecting element 88D, second control connecting element 88EF, second Kelvin connecting element 88FG, and second conductive connecting element 88G.

[0072] Specifically, when die 60 and 61 are integrated Figure 2 When the first transistor 2 and the second transistor 3 are in operation, the first control connection element 88A corresponds to... Figure 1 and Figure 2 The first output control terminal 18 (gate terminal 10 of the GaN transistor); the first Kelvin connection element 88B corresponds to Figure 1 and Figure 2 Output verification terminal 24; first conductive connection element 88C corresponds to Figure 1 and Figure 2 The intermediate output terminal 23 (source terminal 8 of the first transistor 2); the second conductive connection element 88D corresponds to Figure 1 and Figure 2 The second output conductive terminal 17 (the source terminal of the second transistor 2); the second control connection element 88E corresponds to Figure 1 and Figure 2 The second output control terminal 19 (coupled to the control terminal 11 of the second transistor 3); the second Kelvin connection element 88F is coupled to Figure 1 and Figure 2 The source terminal of the second transistor 3 ( Figure 1 (not shown in the image); and the second conductive connection element 88G corresponds to Figure 1 and Figure 2 The first output conductive terminal 16 is coupled to the drain terminal of the first transistor 2.

[0073] Each connecting element 88A to 88G is formed from a shaped flat metal area, as indicated above, which includes corresponding clamps 87A to 87G and at least one corresponding pin 54A to 54G, wherein the letters A to G in the clamps 87A to 87G and the pins 54A to 54G refer to the corresponding connecting elements 88A to 88G having the same letters A to G.

[0074] Specifically, the shape and arrangement of the clamps 87A to 87G enable them to contact the upper surfaces of the dies 60 and 61 in a manner described in detail below. Figures 7A to 10 Therefore, at a certain distance from the first support 75 (in these figures, indicated below the second support 76), they extend in height (parallel to the vertical axis Z of the Cartesian coordinate system XYZ), particularly at a certain distance from the support surface 75A of the first support 75. However, as indicated, they are bonded to the first conductive layer 84 of the second support 76, and thus bonded to the islands 89A, 89B to 89C, 89D to 89G.

[0075] For details, refer to Figure 5 , Figures 7A to 9 : The first control connection element 88A has a corresponding clamp 87A (in the case of a control contact region 63 coupled to the first transistor 58, and thus, in this example, coupled to the gate terminal 10 of the GaN transistor 2) Figure 7A (See image) and corresponding pin 54A, after the second support 76 is attached and the resin of the molded housing 51 is molded, pin 54A is designed to protrude from the second side surface 51E of the housing 51. Figure 4 ); The first Kelvin connection element 88B and the first conductive connection element 88C have a second current-conducting contact region 65 coupled to the first transistor 58 (therefore, in this example, coupled to...). Figure 2 The corresponding clamps 87B and 87C (in the source electrode 36 of the first GaN transistor 2) Figure 7A As can be seen in, and in Figure 9 (The middle part is visible) and corresponding pins 54B, 54C designed to protrude from the second side surface 51E of the housing 51; The second conductive connection element 88D has a first current-conducting contact region 69 that is coupled to the second transistor 59 (therefore, in this example, coupled to...). Figure 2 The corresponding fixture 87D (in the source metallization 47) of the second transistor 3 Figure 7A (as can be seen in the image) and its corresponding pin 54D which is designed to protrude from the second side surface 51E of the housing 51; Second control connection element 88E (in) Figure 7B(As can be seen in the image) has a control contact region 68 coupled to the second transistor 59 (therefore, in the example, coupled to...). Figure 2 The corresponding clamp 87E of the gate terminal 11 of the second transistor 3 and its corresponding pin 54E which are intended to protrude from the first side surface 51D of the housing 51; The second Kelvin connection element 88F has a corresponding clamp 87F that is coupled to the first current-conducting contact region 69 of the second transistor 59 (in Figure 7B (as seen in the image) (and the clamp 87D of the second conductive connection element 88D) and the corresponding pin 54F designed to protrude from the first side surface 51D of the housing 51; and The second conductive connection element 88G has a first current-conducting contact region 64 coupled to the first transistor 58 (therefore, in this example, coupled to...). Figure 2 The corresponding fixture 87G (in the drain electrode 35 of the first GaN transistor 2) Figure 7B and 9 (as can be seen in the image) and its corresponding pin 54G, which is designed to protrude from the first side surface 51D of the housing 51.

[0076] like Figure 10 As shown in the magnified details, besides the portion that contacts the second current-conducting contact region 65 of the first transistor 58 and thus extends to the same level as the other clamps 87A, 87B, 87D to 87F (upper segment 87C1), the clamp 87C of the first conductive connection element 88C also has a lower segment 87C2 bonded to the first conductive layer 80 of the first support 75. Therefore, it is connected to the source electrode 36 of the first transistor 2. Figure 2 A second connection 49B is formed between substrates 27 and 40.

[0077] As indicated above, in Figure 3 , Figure 4 In the electronic device 50, islands 89 of the second support 76 are bonded to clamps 87 such that each island 89A, 89B to 89C, 89D, 89E, 89F and 89G is coupled to clamps 87A to 87G having the same letters A to G. In particular, clamps 87B and 87C of the first Kelvin connection element 88B and the first conductive connection element 88C are coupled to individual islands, as indicated by 89B to 89C.

[0078] Alternative sites, islands 89B to 89C, may be designated.

[0079] In this way, islands 89A, 89B to 89C, 89D, 89E, 89F and 89G together with the second plate 53 form a first thermal via, which can effectively dissipate the heat generated by the current passing through the second main surface 51B of the housing 51 in the contact areas 63 to 65, 68, 69 of the first transistor 58 and the second transistor 59. Figure 4 ).

[0080] Conversely, except for the electrical connection elements (as indicated above) Figure 2 In addition to the first connection 49A, it is bonded to the second side of the die 60, 61 (in Figure 7A , Figure 7B and Figure 8 The first conductive layer 80 of the first support member 75 (at the bottom) also forms a second thermal via, which can effectively dissipate heat from the first transistor 58 and the second transistor 59 (in the bottom). Figure 2 In the example (27, 40), the current in the substrate generates heat through the first main surface 51A of the housing 51.

[0081] The electronic device 50 is realized by providing corresponding first conductive layers 80, 84 on the first support 75 and the second supports 75, 76, the shapes of which, if necessary, are as explained above.

[0082] Then, the second surfaces 60B and 61B of the dies 60 and 61 are bonded to the first conductive layer 80 of the first support member 75 through the first adhesive layer 82.

[0083] Next, a second adhesive layer 90A is selectively deposited to ensure electrical separation of the terminals of dies 60 and 61; then the connecting element 88 is placed and bonded (possibly connected and supported in the manner described above via a lead frame not shown).

[0084] After selectively depositing the third adhesive layer 90B, the second support 76 is placed on the fixture 87, so that it surrounds... Figure 11 The second horizontal axis Y of the Cartesian coordinate system XYZ is rotated and bonded.

[0085] The housing 51 is then molded and the usual final operations are performed, including cutting the lead frame (if envisioned).

[0086] As indicated above, packaged electronic device 50 is a dual-cooled (DC) device and can be coupled to an external cooling system 150, such as, for example... Figures 12 to 14 As shown.

[0087] Here, the lower cooling structure 165 is in contact with the second plate 53 of the second substrate 76, and the upper cooling structure 166 is in contact with the first plate 52 of the second substrate 75.

[0088] In the illustrated example, cooling structures 165 and 166 are of the coolant type; however, any type of cooling system suitable for the intended application can be used.

[0089] In the example shown, the upper cooling structure 166 has an upper channel 191 for the passage of cooling fluid; the lower cooling structure 65 has a lower channel 192 for the passage of cooling fluid.

[0090] Channels 191 and 192 are also connected to each other upstream and downstream of packaged electronic device 50.

[0091] In the illustrated embodiment, the upper cooling structure 166 has protrusions 199 for increasing heat dissipation, and the lower cooling structure 165 has pillars 194 extending between the packaged electronics 50 and the lower channel 192 to facilitate heat transfer.

[0092] Highly efficient heat dissipation is achieved due to the direct contact between cooling structures 165 and 166 and substrates 75 and 76.

[0093] Finally, it will be apparent that modifications and variations may be made to the packaged electronic devices and packaging methods described and illustrated herein without departing from the scope of this disclosure, as defined in the appended claims.

[0094] For example, if not needed, the Kelvin pins 54B, 54F and 54C of the first conductive connection element 88C may be absent.

[0095] An encapsulated electronic device is generally defined as including: a first support element (75); a second support element (76), each of the first and second support elements (75, 76) comprising multiple layers, the multiple layers including corresponding first conductive layers (80, 84) facing the interior of the encapsulated electronic device (50), second conductive layers (52, 53) arranged facing the exterior of the encapsulated electronic device (50), and insulating layers (81, 85) between the first and second conductive layers, the first conductive layer (80) of the first support element forming interconnect regions; the first conductive layer (84) of the second support element (76) forming a plurality of mutually insulated islands (89), and including first islands and second islands (89G, 89D); the first... A second conductive layer of a support element and a second support element (52, 53) forms a heat sink; a first die (60) integrates a first electronic component (58) and has a first main surface (60A), a second main surface (60B), a first contact area (64) on the first main surface (60A) of the first die, and a second contact area (65) on the first main surface (60A) of the first die; a second die (61) integrates a second electronic component (59) and has a first main surface (61A), a second main surface (61B), a first contact area (69) on the first main surface (61A) of the second die, and a second contact area (71) on the second main surface (61B) of the second die (61), the first die and the second die Coupled to the second support element (76) with corresponding first surfaces (60A, 61A) and coupled to the first support element (75) with corresponding second surfaces (60B, 61B), the second contact area (71) of the second die (61) is electrically in contact with the interconnection area (80) of the first support element (75); including a first connecting element (88G) having its own internal portion (87G) and its own pins (54G), a second connecting element (88D) having its own internal portion (87D) and its own pins (87D), and a third connecting element (88C) having its own internal portion (87C); and a housing (51) into which the first die (60), the second die (61), the first support element and the second support element (75) are embedded. The first conductive layer (80, 84), the insulating layer (81, 85) of the first support element and the second support element (75, 76), and the internal portions (87G, 87D, 87C) of the first connecting element, the second connecting element and the third connecting element (88G, 88D, 88C), the first pin and the second pin (54G, 54D) protrude from the housing (51), wherein the internal portion (87G) of the first connecting element (88G) is arranged between the first contact area (64) of the first die (60) and the first island (89G), and the internal portion (87D) of the second connecting element (88D) is arranged between the first contact area (69) of the second die (61) and the second island (89D);Furthermore, the internal portion (87C) of the third connecting element (88C) has a first segment (87C1) of a second contact region (65) coupled to the first die (60) and a second segment (87C2) of an interconnecting region (80) coupled to the first support element (75).

[0096] The first conductive layer (84) of the second support element (76) includes a plurality of islands (89) including a third island (89B to 89C), and a first section (87C1) of the inner portion (87C) of the third connecting element (88C) is arranged between the second contact area (65) of the first die (60) and the third island (89B to 89C).

[0097] The third connecting element (88C) includes a third pin (54C) protruding from the housing (88C).

[0098] The first component (58) includes a first transistor (2), and the second component (59) includes a second transistor (3); the first transistor and the second transistor (2, 3) are coupled in series.

[0099] The first transistor (2) is a GaN power transistor.

[0100] The second transistor (3) is a low-voltage MOSFET.

[0101] The first transistor and the second transistor (2, 3) are coupled in a common source and common gate configuration. The first contact area (64) of the first die (60) is the drain pad; the second contact area (65) of the first die (60) is the source pad; the first contact area (69) of the second die (61) is the source pad and the second contact area (71) of the second die (61) is the drain pad.

[0102] The first transistor (58) includes a self-control contact area (63) disposed on a first main surface (60A) of the first die (60), and the second transistor (59) includes a self-control contact area (68) disposed on a first main surface (61A) of the second die (61). The plurality of islands include a fourth island (89A) and a fifth island (89E). The packaged electronic device (50) also includes a fourth connecting element (88A) and a fifth connecting element (88E). The fourth connecting element (88A) has a self-internal portion (87A) disposed between the control contact area (63) of the first transistor (58) and a self-pin (54A) protruding from the housing (51), and the fifth connecting element (88E) has a self-internal portion (87E) disposed between the control contact area (68) of the second transistor (59) and a self-pin (54E) protruding from the housing (51).

[0103] The packaged electronic device also includes a fifth connecting element and a sixth connecting element (88B, 88F), the fifth connecting element and the sixth connecting element including their own internal portions (87B, 87F) and their own pins (54B, 54F), the internal portion (87B) of the fifth connecting element (88B) being coupled to the second contact area (65) of the first die (60) and forming a first Kelvin contact, and the internal portion (87F) of the fifth connecting element (88F) being coupled to the second contact area (69) of the second die (61) and forming a second Kelvin contact.

[0104] The second conductive layer (52, 53) of at least one of the first support element and the second support element (75, 76) has a tab (55) that protrudes laterally from the housing (51).

[0105] The first and second support elements (75, 76) are DBC direct-bonded copper elements.

[0106] The first conductive layer (80, 84) and the second conductive layer (52, 53) of the first support element and the second support element (75, 76) form a thermal via.

[0107] The first die (60) has a substrate (71) that is in electrical contact with the first conductive layer (80) of the first support element (75).

[0108] The packaged electronic device includes a first adhesive layer (82) between a first conductive layer (80) of a first support (75) and a second main surface (60B, 61B) of a first die and a second die (60, 61); a second adhesive layer (90A) between a first main surface (60A, 61A) of the first die and the second die (60, 61) and an inner portion (87G, 87D) of a first connecting element and a second connecting element (88G, 88D); and a third adhesive layer (90B) between an inner portion (88G, 87D) of the first connecting element and the second connecting element (88G, 88D) and a first conductive layer (84) of a second substrate (76).

[0109] A method of packaging an electronic device is summarized as including: bonding a first die (60) to an interconnect region (80) formed by a first conductive layer (80) of a first support (75), the first conductive layer being formed by multiple layers, the multiple layers further including a second conductive layer (52) and an insulating layer (81) between the first conductive layer and the second conductive layer, the first die (60) integrating a first electronic component (58) and having a first main surface (60A), a second main surface (60B), a first contact region (64) on the first main surface (60A) of the first die, and a second contact region (65) on the first main surface (60A) of the first die, the first die (60) being coupled to the first support (75) with its second surface (60B). The interconnection region (80) of the first support element (75); the second die (61) is bonded to the interconnection region (80) of the first support element (75), the second die (61) integrates the second electronic component (59) and has a first main surface (61A), a second main surface (61B), a first contact region (69) on the first main surface (61A) of the second die and a second contact region (71) on the second main surface (61B) of the second die (61), the second die is coupled to the first support element (75) with its second surface (61B), and the second contact region (71) of the second die (61) is in electrical contact with the interconnection region (80) of the first support element (75); the internal portion (87G) of the first connecting element (88G) is connected. A first contact area (64) is bonded to a first die (60), and a first connecting element (88G) has its own pins (54G); an internal portion (87D) of a second connecting element (88D) is bonded to a first contact area (69) of a second die (61), and the second connecting element (88D) has its own pins (87D); a first segment (87C1) of an internal portion (87C) of a third connecting element (88C) is bonded to a second contact area (65) of the first die 60, and a second segment (87C2) of an internal portion (87C) of the third connecting element (88C) is bonded to an interconnect area (80) of a first support member (75); a second support element (76) is bonded to a first die 60. The first surfaces (60A, 61A) of the core and the second dies (60, 61), the second support element (76) includes multiple layers, the multiple layers include a self-conductive first conductive layer (84), a self-conductive second conductive layer (53) and a self-insulating layer (85) between the first conductive layer and the second conductive layer of the second support element (76), the first conductive layer (84) of the second support element (76) forms a plurality of mutually insulated islands (89) and includes a first island and a second island (89G, 89D), the first island (89G) is bonded to the inner portion (87G) of the first connecting element (88G) and the second island (89D) is bonded to the inner portion (87D) of the second connecting element (88D);A housing (51) is formed, which is embedded in the first conductive layer (80, 84) of the first die (60), the second die (61), the first support element and the second support element (75, 76), the insulating layer (81, 85) of the first support element and the second support element (75, 76), and the internal portion (87G, 87D, 87C) of the first connecting element, the second connecting element and the third connecting element (88G, 88D). The pins (54G, 54D) of the first connecting element and the second connecting element (88G, 88D) protrude from the housing (51). The second conductive layer of the first support element and the second support element (52, 53) forms a heat sink.

[0110] The various embodiments described above can be combined to provide other embodiments. If it is necessary to employ concepts from various patents, applications, and publications to provide other embodiments, aspects of the embodiments can be modified.

[0111] In view of the detailed description above, these and other changes may be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and the claims, but should be construed as including all possible embodiments and the full scope of equivalents to which such claims are conferred. Therefore, the claims are not limited to this disclosure.

Claims

1. A packaged electronic device, comprising: First supporting element; The second support element, the first support element and the second support element each include multiple layers, the multiple layers including a corresponding first conductive layer facing the interior of the packaged electronic device, a second conductive layer arranged facing the exterior of the packaged electronic device, and an insulating layer between the first conductive layer and the second conductive layer, wherein the first conductive layer of the first support element forms an interconnect region. The first conductive layer of the second support element forms a plurality of mutually insulated islands, including a first island and a second island; the second conductive layer of the first support element and the second support element form a heat sink. The first die integrates a first electronic component and has a first main surface, a second main surface, a first contact area on the first main surface of the first die, and a second contact area on the first main surface of the first die. The second die integrates a second electronic component and has a first main surface, a second main surface, a first contact area on the first main surface of the second die, and a second contact area on the second main surface of the second die. The first die and the second die are coupled to the second support element with their respective first surfaces and to the first support element with their respective second surfaces. The second contact area of ​​the second die is in electrical contact with the interconnection area of ​​the first support element. A first connecting element including its own internal portion and its own pins, a second connecting element having its own internal portion and its own pins, and a third connecting element having its own internal portion; as well as The housing contains the first conductive layer of the first die, the second die, the first support element, and the second support element, the insulating layer of the first support element and the second support element, and the internal portions of the first connecting element, the second connecting element, and the third connecting element, with the first pin and the second pin protruding from the housing. The internal portion of the first connecting element is disposed between the first contact area of ​​the first die and the first island, the internal portion of the second connecting element is disposed between the first contact area of ​​the second die and the second island, and the internal portion of the third connecting element has a first segment coupled to the second contact area of ​​the first die and a second segment coupled to the interconnection area of ​​the first support element.

2. The packaged electronic device of claim 1, wherein the plurality of islands of the first conductive layer of the second support element includes a third island, and the first segment of the internal portion of the third connecting element is disposed between the second contact area of ​​the first die and the third island.

3. The packaged electronic device of claim 1, wherein the third connection element includes a third pin protruding from the housing.

4. The packaged electronic device of claim 1, wherein the first electronic component includes a first transistor, and the second electronic component includes a second transistor; the first transistor and the second transistor are coupled in series.

5. The packaged electronic device according to claim 4, wherein the first transistor is a GaN power transistor.

6. The packaged electronic device of claim 4, wherein the second transistor is a low-voltage MOSFET.

7. The packaged electronic device of claim 4, wherein the first transistor and the second transistor are coupled in a cascode configuration, the first contact region of the first die is a drain pad; the second contact region of the first die is a source pad; the first contact region of the second die is a source pad and the second contact region of the second die is a drain pad.

8. The packaged electronic device according to claim 4, wherein: The first transistor includes a self-controlling contact region disposed on the first main surface of the first die, and the second transistor includes a self-controlling contact region disposed on the first main surface of the second die. The plurality of islands includes a fourth island and a fifth island. The packaged electronic device further includes a fourth connecting element and a fifth connecting element. The fourth connection element has an internal portion disposed between the control contact area of ​​the first transistor and its own pin protruding from the housing, and The fifth connecting element has an internal portion disposed between the control contact area of ​​the second transistor and its own pin protruding from the housing.

9. The packaged electronic device of claim 4, further comprising a fifth connecting element and a sixth connecting element, the fifth connecting element and the sixth connecting element comprising an internal portion and a pin, the internal portion of the fifth connecting element being coupled to the second contact area of ​​the first die to form a first Kelvin contact, and the internal portion of the fifth connecting element being coupled to the second contact area of ​​the second die to form a second Kelvin contact.

10. The packaged electronic device of claim 1, wherein the second conductive layer of at least one of the first support element and the second support element has tabs that project laterally from the housing.

11. The packaged electronic device according to claim 1, wherein the first support element and the second support element are DBC direct-bonded copper elements.

12. The packaged electronic device according to claim 1, wherein the first conductive layer and the second conductive layer of the first support element and the second support element form thermal vias.

13. The packaged electronic device of claim 1, wherein the first die has a substrate in electrical contact with the first conductive layer of the first support element.

14. The packaged electronic device of claim 1, comprising a first adhesive layer between the first conductive layer of the first support and the second main surfaces of the first die and the second die; A second adhesive layer between the first main surface of the first die and the second die and the inner portion of the first connecting element and the second connecting element; And a third adhesive layer between the inner portions of the first connecting element and the second connecting element and the first conductive layer of the second substrate.

15. A method for packaging an electronic device, comprising: A first die is bonded to an interconnect region formed by a first conductive layer of a first support member, the first conductive layer being formed by multiple layers, the multiple layers further including a second conductive layer and an insulating layer between the first conductive layer and the second conductive layer, the first die integrating a first electronic component and having a first main surface, a second main surface, a first contact region on the first main surface of the first die and a second contact region on the first main surface of the first die, the first die being coupled to the interconnect region of the first support member with its second surface; The second die is bonded to the interconnect region of the first support member. The second die integrates a second electronic component and has a first main surface, a second main surface, a first contact region on the first main surface of the second die, and a second contact region on the second main surface of the second die. The second die is coupled to the first support member with its second surface, and the second contact region of the second die is in electrical contact with the interconnect region of the first support member. The internal portion of the first connecting element is bonded to the first contact area of ​​the first die, and the first connecting element has its own pins; The internal portion of the second connecting element is bonded to the first contact area of ​​the second die, and the second connecting element has its own pins; A first segment of the internal portion of the third connecting element is bonded to the second contact area of ​​the first die, and a second segment of the internal portion of the third connecting element is bonded to the interconnect area of ​​the first support. A second support element is bonded to the first surface of the first die and the second die. The second support element comprises multiple layers, including a first conductive layer, a second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer of the second support element. The first conductive layer of the second support element forms a plurality of mutually insulating islands and includes a first island and a second island. The first island is bonded to the internal portion of the first connecting element, and the second island is bonded to the internal portion of the second connecting element. as well as A housing is formed, the housing being embedded within the first die, the second die, the first support element, the second support element, the first conductive layer of the second support element, the insulating layer of the first support element, the second support element, and the internal portions of the first connecting element, the second connecting element, and the third connecting element, wherein the pins of the first connecting element and the second connecting element protrude from the housing. The first support element and the second support element form a heat sink.

16. The method of claim 15, further comprising contacting the second conductive layer itself with a first cooling structure on a first side of the housing.

17. The method of claim 16, further comprising contacting the second conductive layer with a second cooling structure on a second side of the housing.

18. A device comprising: The housing includes a first side and a second side opposite to the first side. A first multi-layer support element is located on the first side of the housing, the first multi-layer support element including a first plate exposed on the first side of the housing, and the first plate including a first fin projecting laterally from the housing; A second multi-layer support element is located on the second side of the housing, the second multi-layer housing includes a second plate exposed on the second side of the housing, the second multi-layer support element is opposite to the first multi-layer support element, and the second plate includes a second fin projecting laterally from the housing; A first cooling structure is coupled to the first plate, the first cooling structure comprising a plurality of columns of first cooling channels extending from the first side of the housing into the first cooling structure; as well as A second cooling structure is coupled to the second plate. The second cooling structure includes a second cooling channel and a plurality of protrusions extending outward from the housing. The second cooling channel is in fluid communication with the first cooling channel.

19. The device of claim 18, further comprising a first die within the housing, the first die including a first side coupled to a first inner surface of the first multilayer support element.

20. The device of claim 19, further comprising a connecting element extending from a second side of the first die to a second inner surface of the second multilayer support structure, the second inner surface of the second multilayer support structure facing the first inner surface of the first multilayer support structure, and the connecting element comprising a plurality of pins extending laterally from the housing.

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