Hybrid intelligent power module dual-face cavity packaging method and packaging structure thereof

Abstract

The application relates to a hybrid intelligent power module double-face cavity packaging method and a packaging structure thereof, and belongs to the technical field of microelectronic packaging. Based on a heterogeneous integrated packaging technology, an active integrated area and a passive integrated area are arranged on the front face and the back face of a ceramic base respectively to form double-face cavities. High-density and high-power integration of driving chips and power chips is carried out on the front face of the ceramic base, and back-face integration of passive elements is realized on the back face of the ceramic base, vertical space of packaging is maximally utilized, and the space limitation of traditional planar integration is broken. A multilayer stepped bonding structure with high and low interlacing and annular distribution is arranged on the periphery of the driving chip, bonding wiring density is doubled through vertical space dislocation, and high-density lead arrangement is realized without expanding the packaging size. The problems of poor plastic packaging reliability, low single-face layout density of traditional ceramic packaging, large parasitic parameters, uneven heat dissipation and the like are solved, and the application is suitable for high-demand scenes such as motor driving, new energy inversion, industrial control and the like.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic packaging technology, and more specifically to the field of power electronic packaging technology. In particular, it relates to a hybrid intelligent power module double-cavity packaging method and its packaging structure. Background Technology

[0002] Hybrid intelligent power modules are core power devices in motor drives, new energy inverters, and industrial control scenarios. They integrate drive, power switch, protection, and auxiliary passive components into a single unit. The integration level, power density, thermal reliability, and electrical performance directly determine the efficiency, size, and lifespan of the entire device. Currently, the industry has an urgent need for power modules that are miniaturized, have low parasitic emissions, high heat dissipation, and high reliability.

[0003] Existing hybrid smart power modules mostly adopt two types of packaging forms: (1) Plastic encapsulation: using organic materials such as epoxy resin as the encapsulation shell, it is low in cost and easy to mass-produce, but it has poor heat resistance, low thermal conductivity and insufficient air tightness; under high temperature, high humidity and high vibration conditions, it is easy to delamination, aging and failure, and large parasitic parameters, making it difficult to meet the requirements of high reliability and high power application scenarios. (2) Traditional ceramic packaging: It uses a ceramic substrate and shell, which has significantly better heat dissipation and reliability than plastic packaging. However, it is generally a single-sided planar layout. The driver chip, power transistor, protection and auxiliary passive components are all arranged in the inner cavity of the ceramic base, resulting in crowded top space and long wiring. Passive components occupy the layout and heat dissipation channel of the power chip, resulting in low space utilization, large module size, and difficulty in optimizing parasitic inductance / resistance, which cannot give full play to the integration advantages of SiP heterogeneous integration.

[0004] In summary, existing packaging technologies struggle to simultaneously meet the demands for high integration, small size, low parasitics, excellent heat dissipation, and high reliability. Therefore, there is an urgent need to propose a novel hybrid intelligent power module packaging structure to address these shortcomings.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The technical problem to be solved by this invention is to address the problems of poor heat resistance, poor heat dissipation, low space utilization, limited integration and power density, large parasitic parameters, large package size, poor anti-interference, poor current sharing, and low reliability of existing packaging technologies, and to achieve integrated heterogeneous integration of drive, power, and passive components, thereby improving the overall performance and consistency of the module.

[0007] The inventive concept of this invention is to achieve full-function system-level packaging integration using heterogeneous integrated packaging technology, improving integration density, power density, reliability, heat dissipation performance, and electromagnetic compatibility. The overall design is divided into an active integration area within the base cavity and a passive integration area on the back of the base. High-density, high-power integration of a three-phase bridge driver chip, a high-power transistor chip, and a bootstrap diode chip is achieved on the front side of the ceramic base, while heterogeneous back-side integration of passive components is realized on the back side of the ceramic base, maximizing the use of vertical space and breaking through the spatial limitations of traditional planar integration. Specifically, the three-phase bridge driver chip is used for gate driving, signal isolation, and protection of the three-phase bridge arms; the high-power transistor chip constitutes a three-phase full-bridge arm circuit, with each phase including upper and lower bridge arm switching transistors; and the bootstrap diode chip, in conjunction with the bootstrap circuit, provides high-voltage side drive power supply. A multi-layered stepped bonding structure with alternating high and low heights and a ring-shaped distribution is set around the driver chip, doubling the bonding wiring density through vertical spatial misalignment, achieving high-density lead layout without increasing the package size. Full-function SiP integration is achieved based on heterogeneous integrated packaging technology, which takes into account high integration, high power density, high reliability, high heat dissipation and high electromagnetic compatibility.

[0008] Therefore, this invention provides a method for packaging a hybrid smart power module with two-sided cavities. The method includes the following steps: (1) Using heterogeneous integrated packaging technology, the ceramic shell is used as the packaging carrier, and multiple sunken pits are provided in the inner cavity of the ceramic base for assembling three-phase bridge drive chips and high-power transistor chips. (2) The three-phase bridge arms are designed with symmetrical and equal-length wiring to ensure consistent electrical performance of the three phases and improve the uniformity of current sharing and heat dissipation; (3) A bootstrap diode chip assembly area and bonding area metal layer are provided on the non-recessed bottom surface of the inner cavity of the ceramic housing base; (4) The high bonding platform and the low bonding plane are arranged alternately around the three-phase bridge driver chip. The high platform protrudes from the bottom surface of the ceramic base cavity, and the low plane is the bottom surface of the inner cavity itself. This staggered spatial layout makes the adjacent bonding areas staggered in the vertical direction. Compared with the traditional single-layer planar layout, the effective wiring length of the bonding area is increased by more than double under the same perimeter. Thus, high-density lead pads can be accommodated without increasing the package size, ensuring the compactness of the layout while avoiding bonding line crossing, shortening the interconnect length, and reducing parasitic parameters. (5) A recessed pit is added to the back of the base for assembling passive components such as resistors and capacitors; (6) Through double-sided three-dimensional integration, active and passive devices are partitioned and interconnected in a short distance, maximizing the use of package space; (7) The multi-cavity structure design provides high-voltage insulation and isolation between high-power transistors and other chip areas to meet higher withstand voltage insulation requirements; (8) The high-power transistor chip is directly soldered onto the surface of the heat sink substrate CMC (copper molybdenum copper), which not only increases the heat capacity of the chip, but also reduces the influence of parasitic parameters caused by complex packaging and reduces the integrated volume. (9) A multi-layer metal layer is provided in the chip assembly area or bonding area, which consists of a printed tungsten or molybdenum manganese paste layer, an electroplated nickel or nickel cobalt or nickel phosphorus layer, and an electroplated gold layer.

[0009] The packaging structure of the hybrid intelligent power module double-cavity packaging method is as follows: Figure 1-10 As shown. Includes: 1. Ceramic housing base; 2. Circular frame; 3. Sealing ring; 4. High-power transistor chip assembly recess; 5. Metal heat sink; 6. Three-phase bridge driver chip assembly recess; 7. External electrode metal sheet; 8. External electrode side metal layer; 9. Driver chip boss bonding area; 10. Passive component assembly recess; 11. External electrode back pin positioning mark; 12. Cover plate.

[0010] The ceramic base has a flat-bottomed inner cavity on its top surface, which together with the surrounding annular frame forms the assembly cavity.

[0011] The inner cavity of the top surface of the ceramic base is divided into physically isolated chip assembly areas, as detailed below:

[0012] (1) High power transistor chip: placed in a recessed pit in the inner cavity of the top surface of the base. The surface of the pit is covered with a metal layer, and a metal heat sink is brazed on the metal layer. The chip is then soldered onto the heat sink.

[0013] (2) Three-phase bridge drive chip: placed in another recessed pit, the chip is directly soldered to the metal layer on the surface of the pit.

[0014] (3) Bootstrap diode chip: directly mounted on the non-recessed bottom surface of the inner cavity, with a metal layer at the corresponding position.

[0015] The ceramic base has a recessed groove on the back, and a metal layer on the surface of the groove for welding matching passive components such as resistors and capacitors.

[0016] Several bonding area metal layers are provided on the non-recessed bottom surface of the inner cavity of the base. Electrical connections are achieved between the chip and the bonding area, and between different bonding areas, through bonding wires or embedded metal circuits inside the base. Passive components on the back side are connected to the corresponding chip or bonding area on the top surface through metal traces inside the base.

[0017] External electrode metal layers are provided on the back and sides of the base, and the two are perpendicular to each other. A metal sheet is welded to the metal layer on the back, and a pin positioning mark is attached for identification; a sealing ring is fixed to the annular frame, and a cover plate is welded to the sealing ring to complete the airtight seal.

[0018] The beneficial effects of this invention are as follows:

[0019] Significantly improves space utilization and power density: Power transistor chips, three-phase bridge driver chips, and bootstrap diode chips are arranged in the inner cavity of the ceramic housing base, while passive components are arranged on the back. The double-sided heterogeneous inner cavity makes full use of vertical space, reduces module volume, and achieves high-density SiP integration.

[0020] Optimized heat dissipation path: Passive components are placed on the back of the base, which does not occupy the power area on the front. The heat dissipation channel of power devices is smoother, the module temperature rise and thermal stress are reduced, and the lifespan and stability are improved.

[0021] Doubled bonding and wiring capabilities: The bonding area around the three-phase bridge driver chip is not a single plane, but a multi-layered stepped structure with alternating heights and rings. Compared with the traditional single-layer planar layout, the effective wiring length of the bonding area with the same perimeter is increased by more than double. This allows for high-density wire bonding without increasing the package size, while avoiding bonding wire interference and short circuit problems caused by compact layout, shortening the interconnect path, reducing parasitic inductance and resistance, and reducing switching losses and EMI interference.

[0022] With high integration and strong versatility, a single module can fully realize three-phase full-bridge drive and power output, simplifying the peripheral circuit and adapting to three-phase motor drive and inverter systems in multiple scenarios.

[0023] This invention relates to a full-bridge intelligent power SiP module based on heterogeneous integrated packaging, employing a ceramic housing and a highly integrated power module packaging structure with double-sided sunken recesses. It features miniaturization, surface-mount design, high integration, and high reliability through integrated technology.

[0024] It is widely used in various scenarios requiring three-phase full-bridge power conversion, including but not limited to: main and auxiliary electric drive systems for new energy vehicles, industrial frequency converters, servo drives, energy storage converters, and aerospace airborne power supplies. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the planar structure of the inner cavity on the top surface of the ceramic outer shell base.

[0026] Figure 2 This is a cross-sectional view of the inner cavity of the top surface of the ceramic shell base.

[0027] Figure 3 This is a cross-sectional view of the planar structure of the inner cavity on the top surface of the ceramic shell base.

[0028] Figure 4 This is a schematic diagram of the inner cavity of the bottom surface of the ceramic outer shell base.

[0029] Figure 5 A frontal view of the ceramic encapsulation shell structure.

[0030] Figure 6 This is a top view of the ceramic encapsulation shell.

[0031] Figure 7 This is a schematic diagram of the bottom view of the ceramic encapsulation shell.

[0032] Figure 8 This is a schematic diagram of the ceramic encapsulation shell from the left side.

[0033] Figure 9 This is a schematic diagram of the right-side structure of the ceramic encapsulation shell.

[0034] Figure 10 This is a schematic diagram of the rear view of the ceramic encapsulation shell.

[0035] In the figure: 1. Ceramic housing base; 2. Circular frame; 3. Sealing ring; 4. High-power transistor chip assembly recess; 5. Metal heat sink; 6. Three-phase bridge driver chip assembly recess; 7. External electrode metal sheet; 8. External electrode side metal layer; 9. Driver chip boss bonding area; 10. Passive component assembly recess; 11. External electrode back pin positioning mark; 12. Cover plate.

[0036] Areas D1-D6 are power transistor chip assembly areas; areas F1-F3, E1-E3, H11, H22, H33, L11, L22, and L33 are power transistor chip bonding areas; area G5 is a three-phase bridge driver chip assembly area; areas A41, A51, A61, A71, A81, A91, B1-B3, G1-G4, H1-H3, W1-W3, L1-L3, and V1 are three-phase bridge driver chip bonding areas; areas B11, B22, and B33 are bootstrap diode chip assembly areas; area C1-C3 is a bootstrap diode chip bonding area; and areas J1-J3, J6, K1-K3, V2-V4, and W1-W3 are passive electronic component assembly areas. Detailed Implementation

[0037] like Figure 1-10 As shown, the specific implementation method and packaging structure of the hybrid intelligent power module double-sided cavity packaging method are as follows: The multilayer composite metal layer is a gold (1.3μm~5.7μm)-nickel / nickel-cobalt / nickel-phosphorus (1.3μm~8.9μm)-tungsten / molybdenum-manganese (5μm~30μm) composite layer.

[0038] The frame, sealing ring, external electrode metal sheet, and cover plate are made of 4J42 or 4J29 material. The sealing ring and cover plate are welded in parallel.

[0039] The substrate bonding area around the three-phase bridge driver chip includes two height layers, which are arranged alternately along the circumference of the chip to form a ring-shaped staggered topology, with a horizontal metallization gap of only 0.1 mm.

[0040] A right-angle interconnect is formed at pins 19 (A19) and 20 (A20) of the back metal layer of the outer electrode of the ceramic base to facilitate the positioning of the package module pins.

[0041] The ceramic shell has external dimensions of 18mm×16mm×5.5mm, internal cavity dimensions of 14.5mm×12.8mm, and a bottom surface height of 2.00mm.

[0042] To facilitate wire bonding between the chip and the metal layer of the bonding area after sintering, the depth of the recess in the base cavity is adapted to the chip thickness: 0.3mm for three-phase bridge driver chips and 0.5mm for high-power transistor chips. The non-recessed bottom surface is provided with a bootstrap diode chip assembly area and a bonding area. The chip areas are physically isolated from each other and interconnected through bonding wires or embedded metal lines inside the base.

[0043] The recess on the back of the base is 1mm deep. Passive components are fixed by surface mount technology and connected to the front circuitry through embedded metal lines inside the base.

[0044] The height of the outer electrode metal layer on the side of the base is 1.5mm.

[0045] Tungsten copper or copper-molybdenum-copper heat sinks are brazed onto the metal layer on the surface of the high-power transistor chip's recess to reduce the chip's heat capacity;

[0046] The specific structure is as follows:

[0047] Regions D1-D6 are used as the power transistor chip assembly area, while regions F1-F3, E1-E3, H11, H22, H33, L11, L22, and L33 are used as the power transistor chip bonding area.

[0048] Area G5 is the assembly area for the three-phase bridge driver chip, while areas A41, A51, A61, A71, B1-B3, G1-G4, H1-H3, W1-W3, L1-L3, and V1 are the bonding areas for the three-phase bridge driver chip.

[0049] Regions B11, B22, and B33 are used as the assembly areas for bootstrap diode chips, while regions C1-C3 are used as the bonding areas for bootstrap diode chips.

[0050] Areas J1-J3, J6, K1-K3, V2-V4, and W1-W3 are passive component assembly areas.

[0051] The following interconnections exist between the aforementioned regions: A1-A19-A20-F1-W1, A2-B1-B11-J1, A3-C1-K1, A4-A41, A5-A51, A6-A61, A7-A71, A8-A81, A9-A91, A10-E1, A11-E2, A12-E3, A13-A23-G1-G2-G3-G4-G5-G6, A14-A17 -F3-W3, A15-B3-B33-J2, A16-C3-K3, A18-A24-F2-W2, A21-D1-D2-D3, A22-V1-V2-V3-V4, A25-B2-B22-J3, A26-C2-K2, H1-H11, H2-H22, H3-H33, L1-L11, L2-L22, L33-L33, the sealing ring area is an island. "-" indicates a metal connection.

[0052] This implementation achieves heterogeneous integration of passive electronic components such as drivers, power switches, protection, and auxiliary components into a single SiP. Based on the high reliability of ceramics, it utilizes three-dimensional space and stepped bonding structures to achieve the packaging goals of miniaturization, high density, and high wiring capacity.

[0053] Finally, it should be noted that the above embodiments are merely examples for clear illustration. This invention includes, but is not limited to, the above embodiments, and it is neither necessary nor possible to exhaustively describe all possible implementations. Those skilled in the art can make other variations or modifications based on the above description. All implementation schemes that meet the requirements of this invention are within the protection scope of this invention.

Claims

1. A method for packaging a hybrid intelligent power module with a double-sided cavity, characterized in that, Including the following methods: (1) A ceramic shell is used as the packaging carrier, and a recessed pit is set in the inner cavity of the top surface of its base, which is used to assemble a three-phase bridge drive chip and a high-power transistor chip respectively. (2) The three-phase bridge arms are designed with symmetrical and equal-length wiring to ensure consistent electrical performance of the three phases and improve the uniformity of current sharing and heat dissipation; (3) On the non-recessed bottom surface of the ceramic base cavity, a metal layer for the bootstrap diode chip assembly area and bonding area is provided; (4) The high bonding platform and the low bonding plane are arranged alternately around the three-phase bridge driver chip. The high platform protrudes from the bottom surface of the ceramic base cavity, and the low plane is the bottom surface of the inner cavity itself. This staggered spatial layout makes the adjacent bonding areas staggered in the vertical direction. Compared with the traditional single-layer planar layout, the effective wiring length of the bonding area is increased by more than double under the same perimeter. Thus, high-density lead pads can be accommodated without increasing the package size, ensuring the compactness of the layout while avoiding bonding line crossing, shortening the interconnect length, and reducing parasitic parameters. (5) A recessed pit is provided on the back of the ceramic base for assembling passive components such as resistors and capacitors; (6) By integrating the double-sided recessed three-dimensional components, active and passive devices are partitioned and interconnected in a short distance, maximizing the utilization of the package space and optimizing heat dissipation and electrical performance. (7) Through the multi-cavity structure design, high-power transistors are isolated from other chip areas under high voltage to achieve higher withstand voltage insulation requirements; (8) The high-power transistor chip is directly soldered to the surface of copper-molybdenum copper (CMC) heat sink substrate, which not only increases the heat capacity of the chip, but also reduces the influence of parasitic parameters and reduces the integrated volume; (9) A multilayer composite metal layer is provided in the chip assembly area or bonding area.

2. The packaging structure of the hybrid intelligent power module double-sided cavity packaging method as described in claim 1, characterized in that: The encapsulation shell consists of a ceramic base, an annular frame, a sealing ring, and a cover plate; the top surface of the ceramic base has a flat-bottomed inner cavity, which together with the surrounding annular frame forms the assembly cavity; The inner cavity of the top surface of the ceramic base is divided into physically isolated chip assembly areas, as detailed below: (1) High power transistor chip: placed in a recessed pit in the inner cavity of the top surface of the base, the surface of the pit is covered with a metal layer, a metal heat sink is soldered on the metal layer, and the chip is then soldered onto the heat sink. (2) Three-phase bridge drive chip: placed in another recessed pit, the chip is directly soldered to the metal layer on the surface of the pit; (3) Bootstrap diode chip: directly mounted on the non-recessed bottom surface of the inner cavity, with a metal layer at the corresponding position; The ceramic base has a recessed groove on the back, and a metal layer on the surface of the groove for welding matching passive components such as resistors and capacitors. Several bonding area metal layers are provided on the non-recessed bottom surface of the inner cavity of the base top surface; the chip and the bonding area, and different bonding areas are electrically connected through bonding wires or embedded metal lines inside the base; the passive components on the back are connected to the corresponding chip or bonding area on the top surface through metal lines inside the base. The base has external electrode metal layers on the back and sides, which are perpendicular to each other; a metal sheet is welded on the metal layer on the back, and a pin positioning mark is attached for identification; a sealing ring is fixed to the annular frame, and a cover plate is welded on the sealing ring to complete the airtight seal.

3. The packaging structure of the hybrid intelligent power module double-sided cavity packaging method as described in claim 2, characterized in that: The ceramic housing base has a recessed pit 1mm below the bottom surface on the back, and matching electronic components are soldered onto the metal layer on the surface of the pit.

4. The packaging structure of the hybrid intelligent power module double-sided cavity packaging method as described in claim 2, characterized in that: The substrate bonding area around the three-phase bridge driver chip has two forms: a boss and a flat bottom. The boss height is 0.2mm (relative to the flat bottom surface of the base cavity), forming a ring-shaped staggered topology. The horizontal metallization spacing is 0.1mm to avoid bonding line interference problems under compact layout.

5. The packaging structure of the hybrid intelligent power module double-sided cavity packaging method as described in claim 2, characterized in that: The chip / passive component assembly area and bonding area, external electrode metal layer, sealing ring, and cover plate surface are covered with a composite metal layer, which consists of printing a layer of tungsten or molybdenum-manganese paste with a thickness of 5μm to 30μm on its surface; then electroplating a layer of nickel, nickel-cobalt, or nickel-phosphorus with a thickness of 1.3μm to 8.9μm; and finally electroplating a layer of gold with a thickness of 1.3μm to 5.7μm.

6. The packaging structure of the hybrid intelligent power module double-sided cavity packaging method as described in claim 2, characterized in that: The sealing ring and the cover plate are welded together by parallel seam welding.

7. The packaging structure of the hybrid intelligent power module double-sided cavity packaging method as described in claim 2, characterized in that: The ceramic shell has external dimensions of 18mm×16mm×5.5mm, internal cavity dimensions of 14.5mm×12.8mm, and a bottom surface height of 2.00mm.

8. The packaging structure of the hybrid intelligent power module double-sided cavity packaging method as described in claim 2, characterized in that: The materials of the frame, sealing ring, external electrode metal sheet, and cover plate are 4J42 or 4J29.

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