A bonding method, a bonding apparatus, and a medium

Abstract

This invention provides a bonding method, a bonding apparatus, and a computer-readable storage medium. The bonding method includes the following steps: obtaining a first wafer, wherein the first wafer is a device wafer; obtaining a second wafer and performing a pre-deformation process on the second wafer to adapt to the surface shape of the first wafer, wherein the second wafer is a bare wafer; and bonding the first wafer and the second wafer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication, and more specifically to a bonding method, a bonding apparatus, and a computer-readable storage medium. Background Technology

[0002] Existing wafer bonding processes are mostly based on room temperature and pressure bonding. In this process, the lower wafer is fixed to the surface of the lower chuck by vacuum adsorption, and the upper wafer is fixed to the surface of the upper chuck by vacuum adsorption. During bonding, the ejector pins press down on the upper wafer to deform it, thereby completing the bonding with the lower wafer. Therefore, existing warpage correction is mostly based on the wafer's surface shape data, and temperature or force is applied to the wafer during bonding to temporarily correct wafer warpage. However, for carrier wafers with multi-layer device structures, warpage correction will inevitably damage the complex circuit structure integrated on it, thus affecting the yield of semiconductor devices. At the same time, the bonding correction process that continuously applies temperature or force to the wafer to temporarily correct wafer warpage during bonding places extremely high demands on the control precision and computing power of the wafer bonding equipment, thereby increasing the process cost.

[0003] To address the aforementioned problems of the prior art, the present invention provides a bonding method, a bonding apparatus, and a computer-readable storage medium, which balances bonding accuracy and semiconductor device yield while significantly reducing the control accuracy requirements and computing power demands on the bonding equipment. Summary of the Invention

[0004] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed descriptions that follow.

[0005] To address the aforementioned problems of prior art, this invention provides a bonding method, a bonding apparatus, and a computer-readable storage medium. By performing a pre-deformation treatment on the bare wafer to be bonded during the bonding process based on the surface shape data of the device wafer, the warpage of the bonded components is corrected, thereby balancing bonding accuracy and semiconductor device yield. Furthermore, by applying a permanent pre-deformation treatment to the bare wafer, this invention significantly reduces the control accuracy requirements and computing power demands on the bonding equipment.

[0006] A first aspect of the present invention provides a bonding method comprising the following steps: obtaining a first wafer, wherein the first wafer is a device wafer; obtaining a second wafer and performing a pre-deformation process on the second wafer to adapt to the surface shape of the first wafer, wherein the second wafer is a bare wafer; and bonding the first wafer and the second wafer.

[0007] Furthermore, in some embodiments of the present invention, after obtaining the first wafer and before performing pre-deformation processing on the second wafer, the bonding method further includes the following step: scanning the first wafer to determine the surface shape of the first wafer.

[0008] Furthermore, in some embodiments of the present invention, the step of performing the pre-deformation process of adapting the second wafer to the surface shape of the first wafer includes: scanning the second wafer to determine its second wafer surface shape; determining surface shape difference data of the first wafer and the second wafer based on the first wafer surface shape and the second wafer surface shape; determining stress compensation values ​​at multiple locations on the surface shape difference data of the second wafer; and performing the pre-deformation process of the second wafer based on the stress compensation values ​​at the multiple locations.

[0009] Furthermore, in some embodiments of the present invention, the above-mentioned pre-deformation treatment is selected from at least one of etching treatment, stress thin film deposition treatment, and ion implantation treatment.

[0010] Furthermore, in some embodiments of the present invention, the step of performing the above-mentioned etching process includes: when the stress compensation value at any of the above-mentioned locations is greater than 0, determining that there is positive warping at the location, and performing etching at the non-positive warping location of the second wafer, or at the location facing the first side of the first wafer; and / or when the stress compensation value at any of the above-mentioned locations is less than 0, determining that there is negative warping at the location, and performing etching at the non-negative warping location of the second wafer, or at the location facing away from the second side of the first wafer.

[0011] Furthermore, in some embodiments of the present invention, the step of performing the above-mentioned stress film deposition process includes: when the stress compensation value at any of the above-mentioned locations is greater than 0, determining that there is positive warping at that location, and depositing a negative stress film at the above-mentioned location on the first side of the second wafer facing the first wafer, and / or depositing a positive stress film at the above-mentioned location on the second side of the second wafer facing away from the first wafer, and / or when the stress compensation value at any of the above-mentioned locations is less than 0, determining that there is negative warping at that location, and depositing a positive stress film at the above-mentioned location on the first side of the second wafer facing the first wafer, and / or depositing a negative stress film at the above-mentioned location on the second side of the second wafer facing away from the first wafer.

[0012] Furthermore, in some embodiments of the present invention, the steps of performing the above-mentioned ion implantation process include: when the stress compensation value at any of the above-mentioned locations is greater than 0, determining that there is positive warping at that location, and performing a first ion implantation process with positive deformation at the above-mentioned location on the first side of the second wafer facing the first wafer, and / or performing a second ion implantation process with negative deformation at the above-mentioned location on the second side of the second wafer facing away from the first wafer, and / or when the stress compensation value at any of the above-mentioned locations is less than 0, determining that there is negative warping at that location, and performing a second ion implantation process with negative deformation at the first side of the second wafer facing the first wafer, and / or performing a first ion implantation process with positive deformation at the above-mentioned location on the second side of the second wafer facing away from the first wafer.

[0013] Furthermore, in some embodiments of the present invention, after bonding the first wafer and the second wafer, the bonding method further includes the following steps: performing an annealing process on the bonding components of the first wafer and the second wafer, and grinding the back side of the first wafer in the bonding components to a target thickness.

[0014] A second aspect of the present invention provides a bonding apparatus, comprising a pre-deformation module, a first bonding head, and a second bonding head. The pre-deformation module is used to perform a pre-deformation process on a second wafer to adapt to the surface shape of a first wafer, wherein the second wafer is a bare wafer, and the first wafer corresponding to the surface shape of the first wafer is a device wafer. The first bonding head is used to acquire and fix the first wafer. The second bonding head is used to acquire and fix the pre-deformed second wafer, and cooperates with the first bonding head to bond the first wafer and the second wafer.

[0015] Furthermore, in some embodiments of the present invention, the bonding apparatus further includes a surface shape scanning module and / or a post-processing module. The surface shape scanning module is used to scan the first wafer to determine the corresponding first wafer surface shape, and / or scan the second wafer to determine the corresponding second wafer surface shape. The post-processing module is used to perform an annealing process on the bonding assembly of the first wafer and the second wafer, and to grind the back side of the first wafer in the bonding assembly to a target thickness.

[0016] A third aspect of the present invention provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the bonding method as provided in the first aspect of the present invention. Attached Figure Description

[0017] The above-described features and advantages of the present invention will be better understood after reading the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings. In the drawings, components are not necessarily drawn to scale, and components having similar related characteristics or features may have the same or similar reference numerals.

[0018] Figure 1 A schematic flowchart of a bonding method provided according to some embodiments of the present invention is shown.

[0019] Figure 2 A schematic diagram of a first wafer surface shape provided according to some embodiments of the present invention is shown.

[0020] Figure 3 A schematic diagram of a second wafer surface shape provided according to some embodiments of the present invention is shown.

[0021] Figure 4 A thermal map showing the distribution of wafer bonding distortion results after bonding, according to a prior art reference example.

[0022] Figure 5 A thermal map showing the distribution of wafer bonding distortion results after bonding is provided according to another prior art reference example.

[0023] Figure 6 A thermal diagram showing the distribution of distortion results of a bonded wafer according to an embodiment of the present invention is shown. Detailed Implementation

[0024] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of the present invention. To provide a thorough understanding of the invention, many specific details will be included in the following description. The invention may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0026] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0027] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various components, regions, layers, and / or parts, these components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers, and / or parts. Therefore, the first components, regions, layers, and / or parts discussed below may be referred to as second components, regions, layers, and / or parts without departing from some embodiments of the present invention.

[0028] As mentioned above, with the continuous development of the integrated circuit industry, 3D integration technology, with its significant advantages such as low power consumption, high performance, and low cost, has become one of the core technological development directions in the integrated circuit field. Constrained by factors such as semiconductor material characteristics and process conditions, wafer bonding is an indispensable key process in 3D integration. In the ambient temperature and pressure bonding process, the lower wafer is fixed to the surface of the lower chuck by vacuum adsorption, and the upper wafer is fixed to the surface of the upper chuck by vacuum adsorption. During bonding, the ejector pins press down on the upper wafer to deform it, thereby completing the bonding with the lower wafer.

[0029] In the aforementioned wafer bonding process, for fusion bonding, the upper wafer is a single-layer carrier wafer with a relatively low internal stress level; while the lower wafer is a device wafer with a multi-layer device structure, exhibiting inherent deformation due to the tensile stress of the multiple film layers. During bonding, the lower wafer is forced flattened by the vacuum adsorption of the lower chuck to complete the bonding. After bonding, due to the high residual stress inside the lower wafer, the deformation generated after back-side grinding and chemical mechanical polishing (CMP) processes exceeds the process compensation range of the lithography machine and cannot be effectively corrected by the lithography process.

[0030] Existing wafer bonding processes are mostly based on room temperature and pressure bonding. In this process, the lower wafer is fixed to the surface of the lower chuck by vacuum adsorption, and the upper wafer is fixed to the surface of the upper chuck by vacuum adsorption. During bonding, the ejector pins press down on the upper wafer to deform it, thereby completing the bonding with the lower wafer. Therefore, existing warpage correction is mostly based on the wafer's surface shape data, and temperature or force is applied to the wafer during bonding to temporarily correct wafer warpage. However, for carrier wafers with multi-layer device structures, warpage correction will inevitably damage the complex circuit structure integrated on it, thus affecting the yield of semiconductor devices. At the same time, the bonding correction process that continuously applies temperature or force to the wafer to temporarily correct wafer warpage during bonding places extremely high demands on the control precision and computing power of the wafer bonding equipment, thereby increasing the process cost.

[0031] To address the aforementioned problems of prior art, this invention provides a bonding method, a bonding apparatus, and a computer-readable storage medium. By performing a pre-deformation treatment on the bare wafer to be bonded during the bonding process based on the surface shape data of the device wafer, the warpage of the bonded components is corrected, thereby balancing bonding accuracy and semiconductor device yield. Furthermore, by applying a permanent pre-deformation treatment to the bare wafer, this invention significantly reduces the control accuracy requirements and computing power demands on the bonding equipment.

[0032] Specifically, a bonding apparatus provided in the second aspect of the present invention includes a pre-deformation module, a first bonding head, and a second bonding head. The pre-deformation module is used to perform a pre-deformation process on a second wafer to adapt it to the surface shape of a first wafer, wherein the second wafer is a bare wafer, and the first wafer corresponding to the surface shape of the first wafer is a device wafer. The first bonding head is used to acquire and fix the first wafer. The second bonding head is used to acquire and fix the pre-deformed second wafer, and cooperates with the first bonding head to bond the first wafer and the second wafer.

[0033] Furthermore, in some embodiments of the present invention, the bonding apparatus further includes a surface shape scanning module and / or a post-processing module. The surface shape scanning module is used to scan the first wafer to determine the corresponding first wafer surface shape, and / or scan the second wafer to determine the corresponding second wafer surface shape. The post-processing module is used to perform an annealing process on the bonding assembly of the first wafer and the second wafer, and to grind the back side of the first wafer in the bonding assembly to a target thickness.

[0034] A third aspect of the present invention provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the bonding method as provided in the first aspect of the present invention.

[0035] In some non-limiting embodiments, when computer instructions in the computer-readable storage medium provided in the third aspect of the invention are executed by a processor, the bonding method provided in the first aspect of the invention is implemented via the bonding apparatus provided in the second aspect of the invention.

[0036] The following will combine Figure 1 The bonding method provided in the first aspect of this invention will be briefly described below. Figure 1 A schematic flowchart of a bonding method provided according to some embodiments of the present invention is shown.

[0037] like Figure 1 As shown, a first aspect of the present invention provides a bonding method, the bonding method comprising the following steps: obtaining a first wafer, wherein the first wafer is a device wafer; obtaining a second wafer and performing a pre-deformation process on the second wafer to adapt to the surface shape of the first wafer, wherein the second wafer is a bare wafer; and bonding the first wafer and the second wafer.

[0038] Please refer to Figures 1-2 , Figure 2 A schematic diagram of a first wafer surface shape provided according to some embodiments of the present invention is shown.

[0039] like Figure 1 As shown, further, in some embodiments of the present invention, after obtaining the first wafer and before performing pre-deformation processing on the second wafer, the bonding method further includes the following step: scanning the first wafer to determine the surface shape of the first wafer. In one embodiment, the surface shape of the first wafer is as follows: Figure 2 As shown in the image.

[0040] Please refer to Figures 2-3 , Figure 3 A schematic diagram of a second wafer surface shape provided according to some embodiments of the present invention is shown.

[0041] like Figures 2-3 As shown, further, in some embodiments of the present invention, the above-mentioned pre-deformation process of adapting the second wafer to the surface shape of the first wafer includes: scanning the second wafer to determine its second wafer surface shape; determining surface shape difference data of the first wafer and the second wafer based on the first wafer surface shape and the second wafer surface shape; determining stress compensation values ​​at multiple locations on the surface shape difference data of the second wafer; and performing the above-mentioned pre-deformation process on the second wafer based on the stress compensation values ​​at the multiple locations.

[0042] It should be noted that the aforementioned first wafer surface shape data and second wafer surface shape data include, but are not limited to, wafer warpage, warpage difference, and surface roughness.

[0043] Thus, by scanning and acquiring the surface shape data of the first and second wafers, and performing permanent pre-deformation treatment on the bare wafers without devices before bonding, in order to adjust and compensate the surface stress of the device wafers, this invention reduces the control accuracy and computing power requirements of wafer bonding equipment, while also taking into account bonding accuracy and semiconductor device yield.

[0044] Furthermore, in some embodiments of the present invention, the above-mentioned pre-deformation treatment is selected from at least one of etching treatment, stress thin film deposition treatment, and ion implantation treatment.

[0045] Furthermore, in some embodiments of the present invention, the step of performing the above-mentioned etching process includes: when the stress compensation value at any of the above-mentioned locations is greater than 0, determining that there is positive warping at the location, and performing etching at the non-positive warping location of the second wafer, or at the location facing the first side of the first wafer; and / or when the stress compensation value at any of the above-mentioned locations is less than 0, determining that there is negative warping at the location, and performing etching at the non-negative warping location of the second wafer, or at the location facing away from the second side of the first wafer.

[0046] It should be noted that the etching locations described above are only some non-limiting embodiments provided by this invention. This invention can also perform etching at other specific locations depending on the specific process requirements. This invention etches trenches of specific depth and width onto the wafer surface, causing specific deformation of the wafer and thereby altering the stress distribution on the wafer surface.

[0047] Furthermore, in some embodiments of the present invention, the step of performing the above-mentioned stress film deposition process includes: when the stress compensation value at any of the above-mentioned locations is greater than 0, determining that there is positive warping at the location, and depositing a negative stress film at the above-mentioned location on the first side of the second wafer facing the first wafer to generate compressive stress, and / or depositing a positive stress film at the above-mentioned location on the second side of the second wafer facing away from the first wafer to generate tensile stress.

[0048] In other embodiments of the present invention, when the stress compensation value at any of the above-mentioned locations is less than 0, it is determined that there is negative warping at that location, and a positive stress film is deposited at the above-mentioned location on the first side of the second wafer facing the first wafer to generate tensile stress, and / or a negative stress film is deposited at the above-mentioned location on the second side of the second wafer facing away from the first wafer to generate contractile stress.

[0049] It should be noted that, since the lattice coefficients of the film and the wafer are different, tensile stress or contractile stress will be generated. Therefore, this invention can generate specific deformation of the wafer by depositing and growing different thin films, thereby controlling the stress distribution on the wafer surface.

[0050] Further, in some embodiments of the present invention, the steps of performing the above-mentioned ion implantation process include: when the stress compensation value at any of the above-mentioned locations is greater than 0, determining that there is positive warping at that location, and performing a first ion implantation process of positive deformation (e.g., bowl-shaped deformation) at the above-mentioned location on the first side of the second wafer facing the first wafer, and / or performing a second ion implantation process of negative deformation (e.g., inverted bowl-shaped deformation) at the above-mentioned location on the second side of the second wafer facing away from the first wafer, and / or when the stress compensation value at any of the above-mentioned locations is less than 0, determining that there is negative warping at that location, and performing a second ion implantation process of negative deformation at the first side of the second wafer facing the first wafer, and / or performing a first ion implantation process of positive deformation at the above-mentioned location on the second side of the second wafer facing away from the first wafer.

[0051] It should be noted that the present invention implants certain ions into a specific process window of the wafer. After the ions are activated, the window position changes due to the lattice change, and the wafer surface shape also changes accordingly, thereby controlling the stress distribution on the wafer surface.

[0052] For the aforementioned pre-deformation treatment processes, the main advantage of stress film deposition is its ability to control large-scale positional deformation, such as deformation exceeding 200µm on a 300mm diameter wafer, and to control wafer bending (Bow) exceeding 800µm. However, stress film deposition struggles to control precise positional deformation of the surface profile, such as controlling deformation below 200µm at a specific location on a 300mm diameter wafer. Meanwhile, the main advantage of etching and ion implantation is their ability to control precise positional deformation within a small range, such as deformation less than 200µm in diameter on a 300mm diameter wafer, while their disadvantage is the difficulty in controlling larger surface deformations, such as Bow values ​​below 10µm.

[0053] Therefore, in some embodiments, the present invention may also use multiple of the following processes for pretreatment: etching, stress film deposition, and ion implantation. After large-scale coarse adjustment using stress film deposition, etching and ion implantation are then flexibly used for fine adjustment.

[0054] For example, in one embodiment of the present invention, after the lower wafer surface is detected and collected, a specific thin film is first grown on the surface of the upper wafer to control the surface of the upper wafer to the specific morphology required by the lower wafer, so as to complete the coarse adjustment. Then, a small process window (less than 200 μm) is opened on the surface of the upper wafer by a photolithography machine. The upper wafer surface is then processed by etching and ion implantation equipment to optimize the position and amount of deformation of the upper wafer, so as to complete the fine adjustment and enable the overall bonding distortion to be canceled when the upper and lower wafers are bonded.

[0055] Thus, this technical solution improves the stress distribution during bonding by using multiple process methods to permanently pre-deform the bare wafers to be bonded. This improves the bonding accuracy of the wafers to be bonded, reduces short circuits and open circuits in the metal interconnect layer, enhances the uniformity of bonding strength, reduces internal residual stress, improves the subsequent process window, and ultimately improves chip performance, increases yield, and reduces costs.

[0056] Furthermore, in some embodiments of the present invention, after bonding the first wafer and the second wafer, the bonding method further includes the following steps: performing an annealing process on the bonding components of the first wafer and the second wafer, and grinding the back side of the first wafer in the bonding components to a target thickness.

[0057] Please refer to the following: Figures 4-6 , Figure 4 A thermal map showing the distribution of wafer bonding distortion results after bonding, according to a prior art reference example. Figure 5 A thermal map showing the distribution of wafer bonding distortion results after bonding is provided according to another prior art reference example. Figure 6 A thermal diagram showing the distribution of distortion results of a bonded wafer according to an embodiment of the present invention is shown.

[0058] To verify the effect of the bonding method, equipment and medium provided in this application on the distortion elimination of the bonded wafer bond, the technician compared the distortion of the wafer bond obtained after bonding in the prior art with that of the wafer bond obtained after processing in this application.

[0059] like Figures 4-6 As shown, Figure 4 The image shows bonding distortion in upper and lower wafers that had no warpage before bonding. Figure 5 The image shows the bonding distortion between upper and lower wafers before bonding, where the upper wafer has no warpage and the lower wafer has warpage. Figure 6 This demonstrates the wafer bonding assembly obtained after processing according to this application, compared to... Figures 4-5 The distortion residual of the wafer bonding device is reduced after being processed by the method in this application.

[0060] Therefore, the wafer bonding obtained after processing in this application has a special stress on the upper and lower wafers, and the wafer distortion after bonding is reduced, resulting in a significant distortion elimination effect.

[0061] In summary, this invention provides a bonding method, a bonding apparatus, and a computer-readable storage medium. By performing a pre-deformation treatment on the bare wafer to be bonded during the bonding process based on the surface shape data of the device wafer, the warpage of the bonded components is corrected, thereby balancing bonding accuracy and semiconductor device yield. Furthermore, by applying a permanent pre-deformation treatment to the bare wafer, this invention significantly reduces the control accuracy requirements and computing power demands on the bonding equipment.

[0062] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments.

[0063] Those skilled in the art will understand that information, signals, and data can be represented using any of a variety of different techniques and skills. For example, the data, instructions, commands, information, signals, bits, symbols, and chips described throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0064] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps are described above in a generalized manner in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the invention.

[0065] Although the controller and / or processor described in the above embodiments can be implemented through a combination of software and hardware, it is understood that the controller and / or processor can also be implemented solely in software or hardware. For hardware implementation, the controller and / or processor can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, general-purpose controllers, microcontrollers, microprocessors, other electronic devices for performing the functions described above, or a selection of combinations of the above devices. For software implementation, the controller and / or processor can be implemented through independent software modules such as procedures and functions running on a general-purpose chip, each module performing one or more functions and operations described herein.

[0066] The various illustrative logic modules and circuits described in conjunction with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration.

[0067] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read and write information to / from the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and storage medium may reside as discrete components in the user terminal.

[0068] In one or more exemplary embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software as a computer program product, the functionality may be stored or transmitted as one or more instructions or code on or through a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, encompassing any medium that facilitates the transfer of a computer program from one location to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such a computer-readable medium may include non-transitory storage devices such as RAM, ROM, EEPROM, CD-ROM, or other optical disc storage, disk storage, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Any connection is also legitimately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. As used in this article, disk and disc include compact discs (CDs), laser discs, optical discs, digital multi-purpose discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0069] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bonding method, characterized in that, Includes the following steps: Obtain a first wafer, wherein the first wafer is a device wafer; Obtain a second wafer and perform a pre-deformation process on the second wafer to adapt it to the surface shape of the first wafer, wherein the second wafer is a bare wafer; and The first wafer and the second wafer are bonded together.

2. The bonding method as described in claim 1, characterized in that, After obtaining the first wafer and before performing the pre-deformation treatment on the second wafer, the bonding method further includes the following steps: The first wafer is scanned to determine its surface shape.

3. The bonding method as described in claim 1, characterized in that, The step of performing pre-deformation processing on the second wafer to adapt to the surface shape of the first wafer includes: The second wafer is scanned to determine its second wafer surface shape; Based on the first wafer surface shape and the second wafer surface shape, determine the surface shape difference data between the first wafer and the second wafer; Based on the surface shape difference data, stress compensation values ​​are determined at multiple locations on the surface of the second wafer; and The pre-deformation treatment is performed on the second wafer based on the stress compensation values ​​at the plurality of locations.

4. The bonding method as described in claim 3, characterized in that, The pre-deformation treatment is selected from at least one of etching treatment, stress thin film deposition treatment, and ion implantation treatment.

5. The bonding method as described in claim 4, characterized in that, The etching process includes the following steps: When the stress compensation value at any of the aforementioned locations is greater than 0, it is determined that there is positive warping at that location, and the etching process is performed at the non-positive warping location on the second wafer, or at the location facing the first side of the first wafer; and / or When the stress compensation value at any of the locations is less than 0, it is determined that there is negative warping at the location, and the etching process is performed at the non-negative warping location of the second wafer, or at the location on the second side opposite to the first wafer.

6. The bonding method as described in claim 4, characterized in that, The steps for performing the stress film deposition process include: When the stress compensation value at any of the aforementioned locations is greater than 0, it is determined that positive warping exists at that location, and a negative stress film is deposited at the location on the first side of the second wafer facing the first wafer, and / or a positive stress film is deposited at the location on the second side of the second wafer facing away from the first wafer; and / or When the stress compensation value at any of the locations is less than 0, it is determined that there is negative warping at the location, and a positive stress film is deposited at the location on the first side of the second wafer facing the first wafer, and / or a negative stress film is deposited at the location on the second side of the second wafer facing away from the first wafer.

7. The bonding method as described in claim 4, characterized in that, The steps for performing the ion implantation process include: When the stress compensation value at any of the aforementioned locations is greater than 0, it is determined that positive warping exists at that location. A first ion implantation process for positive deformation is then performed at the location on the first side of the second wafer facing the first wafer, and / or a second ion implantation process for negative deformation is performed at the location on the second side of the second wafer facing away from the first wafer; and / or When the stress compensation value at any of the locations is less than 0, it is determined that there is negative warping at the location, and a second ion implantation process with negative deformation is performed on the first side of the second wafer facing the first wafer, and / or a first ion implantation process with positive deformation is performed at the location on the second side of the second wafer facing away from the first wafer.

8. The bonding method as described in claim 1, characterized in that, After bonding the first wafer and the second wafer, the bonding method further includes the following steps: Annealing process is performed on the bonding components of the first wafer and the second wafer; and The back side of the first wafer in the bonding assembly is ground to the target thickness.

9. A bonding device, characterized in that, include: A pre-deformation module is used to perform pre-deformation processing on the second wafer to adapt to the surface shape of the first wafer, wherein the second wafer is a bare wafer and the first wafer corresponding to the surface shape of the first wafer is a device wafer; A first bonding head, used to acquire and fix the first wafer; and The second bonding head is used to acquire and fix the second wafer after the pre-deformation treatment, and to bond the first wafer and the second wafer together with the first bonding head.

10. The bonding apparatus as claimed in claim 9, characterized in that, Also includes: A surface shape scanning module is used to scan the first wafer to determine the corresponding first wafer surface shape, and / or scan the second wafer to determine the corresponding second wafer surface shape; and / or The post-processing module is used to perform an annealing process on the bonding components of the first wafer and the second wafer, and to grind the back side of the first wafer in the bonding components to the target thickness.

11. A computer-readable storage medium storing computer instructions thereon, characterized in that, When the computer instructions are executed by the processor, the bonding method as described in any one of claims 1 to 8 is implemented.

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