Chip, electronic device, and electronic apparatus
Patent Information
- Application Number
- CN202610661104.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-13
- Publication Date
- 2026-09-22
AI Technical Summary
[0003]然而，在现有的3D IC技术中，芯片的制造成本高昂
[0004]本申请提供一种芯片、电子器件以及电子设备，以期降低芯片的制造成本。
Smart Images
Figure CN122803768A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a chip, electronic device, and electronic device. Background Technology
[0002] With the rapid development of technologies such as artificial intelligence (AI) and high-performance computing (HPC), the industry has placed higher demands on the computing power and data transmission rate of chips, which has driven continuous innovation in chip design technology. Three-dimensional integrated circuit (3D IC) technology is one of the achievements of this continuous innovation. By employing technologies such as through silicon vias (TSVs) or hybrid bonding (HB), it shortens the interconnect distance between dies, reduces signal transmission delay and power consumption, and expands integration density in the vertical direction. This can improve chip performance, reduce chip package size, and integrate dies from different process technologies to meet multifunctional needs.
[0003] However, in existing 3D IC technology, chip manufacturing costs are high. Therefore, how to reduce chip manufacturing costs is a pressing technical problem that needs to be solved. Summary of the Invention
[0004] This application provides a chip, electronic device, and electronic device in order to reduce the manufacturing cost of the chip.
[0005] In a first aspect, a chip is provided, the chip including a first substrate, a first die, a second die, and a second power management unit (PMU), the first die being stacked on the surface of the first substrate, the second die being stacked on the surface of the first die, and the second PMU being stacked on the surface of the second die, the first substrate being provided with the first PMU, the first PMU supplying power to the first die, and the second PMU supplying power to the second die.
[0006] With the above architecture, the first and second dies are powered by different PMUs. The first die does not need to be configured as a TSV for transmitting power to the second die, which reduces the manufacturing cost of the first die and consequently the overall chip manufacturing cost. Furthermore, this also improves the area utilization of the first die. Since the second PMU is stacked on top of the second die, the second die directly draws power from the second PMU, meeting the requirements for power response speed and adjustment accuracy. Because the power supply path of the second die does not pass through the first die but directly draws power from the second PMU, the power supply path of the second die can be shortened. Since the parasitic resistance and inductance of the die are positively correlated with the length of the power supply path, shortening the power supply path of the second die reduces these parasitic resistance and inductance, improving the power supply quality and efficiency from the second PMU to the second die. Because the fabrication process of the second die is more advanced, compared with the solution of integrating the second PMU in the second die, stacking the second PMU on top of the second die can reduce the fabrication cost of the second die, thereby further reducing the manufacturing cost of the chip.
[0007] In some implementations of the first aspect, the chip further includes a second substrate stacked on the surface of the second die, and the second substrate has a second PMU disposed thereon. In mass production scenarios, by integrating the second PMU into the second substrate, the packaging and mounting steps of the second PMU can be eliminated, reducing assembly costs and thus reducing the cost of the chip.
[0008] In some implementations of the first aspect, the chip further includes an interposer layer located between the second die and the second substrate. The power distribution network (PDN) of the second die is disposed within the second die and the interposer layer. The PDN of the second die being disposed within the second die and the interposer layer means that a portion of the complete PDN of the second die is fabricated in the interposer layer, and the remaining portion of the complete PDN of the second die is fabricated within the second die itself; or, in other words, only a portion of the complete PDN is fabricated within the second die, not the entire complete PDN. By placing an interposer layer between the second die and the second substrate, the interposer layer can provide additional metal layer resources for constructing the PDN of the second die, thereby simplifying the PDN design within the second die. This allows some of the metal layer resources of the second die to be freed up for other functions, or reduces the metal layer resource requirements of the second die, further improving the chip's design flexibility and area utilization.
[0009] In some implementations of the first aspect, the chip further includes a power transmission structure for power transmission between the first substrate and the second substrate. Through this power transmission structure, the power source for the first PMU and the power source for the second PMU can be the same. This simplifies the power supply design complexity; that is, one power supply powers the multiple dies, and the power supply path of the top die does not pass through other dies, thus achieving the aforementioned advantages.
[0010] In some implementations of the first aspect, the power transmission structure includes one or more of the following: copper pillars, power transfer dies, or molded through-holes. Through one or more of the above, embodiments of this application can achieve power transmission between the first substrate and the second substrate.
[0011] In some implementations of the first aspect, the chip further includes a third die located between the first and second dies; the first PMU supplies power to the third die, and / or, the second PMU supplies power to the third die. For scenarios with multiple dies stacked, the above architecture allows the embodiments of this application to supply power to the top die and the bottom die respectively. The power supply path of the top die does not pass through the middle die, which improves the area utilization of the middle die and reduces its manufacturing cost. Simultaneously, this also increases the diversity of power supply methods for the middle die, thereby improving the power supply stability for the middle die. For example, when the first PMU cannot supply power to the third die, the third die can obtain power from the second PMU and thus operate normally.
[0012] In some implementations of the first aspect, the second substrate is stacked on the surface of the second die, including: the second substrate is stacked on the front side of the second die, where the front side of the second die is the surface for forming active transistors; or, the second substrate is stacked on the back side of the second die, where the back side of the second die is opposite to the front side of the second die. When the second substrate is stacked on the front side of the second die, this application can fabricate a PDN on the front side of the second die, which can reduce the manufacturing complexity of the PDN, and at the same time, reduce the manufacturing cost of the chip and ensure yield. When the second substrate is stacked on the back side of the second die, this application can fabricate a PDN on the back side of the second die, which can free up the wiring space of the metal layer on the front side of the second die, reduce interference between power and signal, and optimize power supply quality.
[0013] In some implementations of the first aspect, the interposer is located between the second die and the second substrate, including: the interposer is stacked on the front side of the second die, which is the surface for forming active transistors; or, the interposer is stacked on the back side of the second die, with the back side of the second die facing the front side. When the interposer is stacked on the front side of the second die, this application can fabricate a PDN on the front side of the second die, which can reduce the manufacturing complexity of the PDN, and at the same time, reduce the manufacturing cost of the chip and ensure yield. When the interposer is stacked on the back side of the second die, this application can fabricate a PDN on the back side of the second die, which can free up the wiring space of the metal layer on the front side of the second die, reduce interference between power and signal, and optimize power supply quality.
[0014] In a second aspect, an electronic device is provided, comprising the chip described in the first aspect and any possible implementation thereof.
[0015] Thirdly, an electronic device is provided, which includes the electronic components described in the second aspect. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the power supply scheme in a 3D IC.
[0017] Figure 2 This is a schematic diagram of the architecture of chip 200 according to an embodiment of this application.
[0018] Figure 3 yes Figure 2 A schematic diagram of the power supply scheme for the chip 200.
[0019] Figure 4 This is another schematic diagram of the architecture of chip 200 according to an embodiment of this application.
[0020] Figure 5 This is another schematic diagram of the architecture of chip 200 according to an embodiment of this application.
[0021] Figure 6 yes Figure 5 A schematic diagram of the power supply scheme for the chip 200.
[0022] Figure 7 This is another schematic diagram of the architecture of chip 200 according to an embodiment of this application.
[0023] Figure 8 This is another schematic diagram of the architecture of chip 200 according to an embodiment of this application.
[0024] Figure 9 yes Figure 8 A schematic diagram of the power supply scheme for the chip 200.
[0025] Figure 10 yes Figure 2 A schematic diagram of the manufacturing process of the chip 200. Detailed Implementation
[0026] To facilitate understanding of the embodiments of this application, the following points will be explained first.
[0027] 1. Unless otherwise stated, “multiple” means two or more.
[0028] 2. Unless otherwise specified or in case of logical conflict, the terms and / or descriptions in different embodiments of this application are consistent and can be referenced in each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.
[0029] III. The various numerical designations used in this application are merely for descriptive convenience and do not limit the scope of protection of this application. The order of the serial numbers used in this application does not imply the sequence of execution; the execution order of each process should be determined by its function and internal logic. For example, the terms "first (e.g., first blank)," "second (e.g., second blank)," "third (e.g., third blank)," and other various terminology (if present) in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0030] Furthermore, any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner for ease of understanding.
[0031] IV. The terms “comprising” and “having” and any variations thereof are intended to cover non-exclusive inclusion, for example, a product or device that includes a series of units is not necessarily limited to those units that are clearly listed, but may include other units that are not clearly listed or that are inherent to such product or device.
[0032] V. In this application, directional terms such as “upper,” “lower,” “top,” and “bottom” are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.
[0033] VI. In this application, the term "electrical connection" refers to a conductive path for current or signals established between different components (such as transistors, resistors, dies, printed circuit boards, etc.) in a power system via a conductor. Furthermore, the term "electrical connection" includes direct electrical connections and / or indirect electrical connections. For example, die A is directly electrically connected to die B, or die A is directly electrically connected to die C, die C is directly electrically connected to die B, and die A and die B are electrically connected via die C.
[0034] In this application, by way of example, electrical connections between dies can be achieved in one or more of the following ways: Microbump interconnect: Electrical connection between bare dies is achieved through copper pillars and solder microbump arrays; HB: Metal-to-metal direct bonding (such as Cu-Cu bonding) combined with dielectric bonding; TSV+redistribution layer (RDL) interconnect: TSVs penetrate the wafer, and RDLs are used to bring out pads, achieving vertical electrical connections in a three-dimensional structure; or Direct metal bonding: Achieving atomic-level direct bonding of metal contact surfaces under high temperature and high pressure.
[0035] The following section will first describe the technical terms related to this application.
[0036] 1. Nude film A bare die is a single functional unit obtained after dicing a wafer; it is essentially an unpackaged semiconductor circuit. Each bare die is an independent microcircuit portion obtained from a wafer through photolithography and subsequent manufacturing processes.
[0037] 2. Chip: A chip is a bare die that has been packaged, allowing it to be used directly as a standalone module. The package protects the internal circuitry of the die and provides pins or contacts for connection to external devices. Common packages include ball grid arrays (BGAs), quad flat packages (QFPs), and dual in-line packages (DIPs). A chip can be a microprocessor, memory, sensor, or other functional module. Chips serve as various functional units in electronic devices, such as processor chips and memory chips in mobile phones.
[0038] 3. RDL Relay-Depth Interconnect (RDD) is an interconnect technology used in chip packaging. It redistributes the chip's original input / output (IO) pads to more ideal locations by building a metal wiring layer on the chip surface. The principle of RDL is to use metal wires and vias to achieve a rearrangement of electrical connections, thereby adapting to high-density packaging requirements. RDL typically consists of a copper metal layer and a polymer dielectric layer (such as polyimide), and is built layer by layer through semiconductor processes such as photolithography and electroplating.
[0039] 4. PDN PDN refers to the collective term for all interconnect structures used for power transmission between the external power supply and the internal transistors of the chip. Its core objective is to provide a stable, low-noise, and low-impedance power supply path for the chip, ensuring that the chip receives the required voltage under various operating conditions. PDN mainly includes voltage regulator modules (VRMs), decoupling capacitors, power / ground planes, and interconnect structures.
[0040] PDNs include back-side PDNs (BSPDNs) and front-side PDNs (FSPDNs). A BSPDN is a PDN located on the back side of the die, while an FSPDN is a PDN located on the front side. The front side of the die is the surface where active transistors are formed; alternatively, the front side of the die can be understood as the active surface, where functional devices are fabricated.
[0041] 5. PMU A Power Management Unit (PMU) is a power management module that can be integrated into a chip or set up independently. It generates, distributes, regulates, and manages the chip's operating voltage, providing a stable and adaptable power supply environment for various functional circuits within the chip. In advanced chip architectures, the PMU can integrate multiple voltage conversion circuits, power switches, timing control logic, and monitoring and protection circuits. It can output multiple independently adjustable operating voltages according to the operational requirements of different functional modules within the chip, and perform fine-grained power control for each module. The PMU supports dynamic voltage and frequency regulation, adjusting the supply voltage and operating frequency in real time according to the computational load, reducing system power consumption while ensuring performance. Simultaneously, the PMU can strictly control the power-on and power-off sequences of each power supply, avoiding inrush current and circuit logic disorder. It also provides overvoltage, undervoltage, overcurrent, and overheat protection by monitoring voltage, current, and temperature parameters in real time, improving the chip's reliability and stability.
[0042] In 3D IC technology, current power supply schemes for dies require power to be output from the chip substrate, sequentially powering each die. However, this approach increases chip manufacturing costs. Furthermore, it reduces die area utilization and fails to meet the requirements for die response speed and adjustment precision. The following section describes power supply schemes for 3D ICs.
[0043] refer to Figure 1 For example, chip 100 includes substrate 101, die 102 and die 103, with die 102 stacked on the surface of substrate 101 and die 103 stacked on the surface of die 102. PMU 104 is disposed in substrate 101, and PMU 104 supplies power to both die 102 and die 103.
[0044] The bare die 102 passes through one or more uBumps ( Figure 1 Only one uBump is shown in the diagram, electrically connected to the surface of substrate 101. Die 102 and die 103 are bonded together via HB (or ubump), and one or more HB metal structure contact interfaces exist between die 102 and die 103. Figure 1 Only one HB metal structure contact interface is shown (only one is shown in the diagram). The HB metal structure contact interface refers to the interface where the copper pads between the bare dies in the HB are directly attached to form an atomic-level conductive connection. This HB metal structure contact interface is made of metallic material to enable power and signal transmission. The bare die 102 contains an RDL, TSV, PDN, and devices. The RDL is electrically connected to the uBump, TSV, and PDN, respectively. The devices in the bare die 102 obtain power from the PMU 104 through the PDN and RDL. The bare die 103 contains a PDN and devices. The devices in the bare die 103 obtain power from the PMU 104 through the PDN in the bare die 103, the HB metal structure contact interface between the bare dies 102 and 103, the TSV in the bare die 102, and the RDL. Alternatively, the power supply path of the bare die 103 passes through the bare die 102. The device can be an active device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), or a passive device, such as a resistor or capacitor. It can also be a special-purpose device, such as a storage device or an electrostatic discharge (ESD) protection device.
[0045] Die 102 includes a TSV (Transmission Switch) for power transfer between die 102 and die 103, enabling PMU 104 to supply power to die 103. However, this TSV not only occupies valuable internal space in die 102, reducing the area available for logic functions and ultimately lowering its area utilization, but also increases manufacturing costs, thereby raising the overall manufacturing cost of chip 100. Furthermore, die 103 is typically a high-performance die, demanding higher response speed and adjustment accuracy from the PMU. Since die 103 receives power from PMU 104 via die 102, the PMU 104's response speed and adjustment accuracy for die 103 may not meet its requirements.
[0046] In view of this, this application provides a chip that reduces manufacturing costs by providing independent power supply paths for different dies. Furthermore, it can improve die area utilization and meet the requirements for die power response speed and regulation accuracy. For a description of this chip, please refer to [link to relevant documentation]. Figure 2 .
[0047] Figure 2 This is a schematic diagram of the architecture of chip 200 according to an embodiment of this application. (Reference) Figure 2 The chip 200 includes: a first substrate 201, a first die 202, a second die 203, and a second PMU 205. The first substrate 201 is provided with a first PMU 204. The first die 202 is stacked on the surface of the first substrate 201, the second die 203 is stacked on the surface of the first die 202, and the second PMU 205 is stacked on the surface of the second die 203. The second PMU 205 supplies power to the second die 203, and the first PMU 204 supplies power to the first die 202.
[0048] The first substrate 201, also known as a packaging substrate, can support the die and provide it with mechanical support, electrical interconnection, and heat dissipation path. The first substrate 201 internally uses wiring and vias to distribute signals and power between the die pins and external package pins, while also providing physical protection and heat conduction channels for the chip. In this embodiment, the first substrate 201 provides mechanical support for the first die 202 and is electrically connected to the first die 202.
[0049] The power source for the second PMU205 can be the same as or different from the power source for the first PMU204; this is not limited. When the power source for the second PMU205 is the same as the power source for the first PMU204, this application provides a power supply that is electrically connected to both the first PMU204 and the second PMU205. Alternatively, the first substrate 201 can output power to the second PMU205 directly without passing through the first die 202. For example, a conductive structure is provided between the first substrate 201 and the second PMU205 to realize power transmission between them. This application does not limit the specific form of the conductive structure; for example, it can be a metal wire, with one end electrically connected to the first substrate 201 and the other end electrically connected to the second PMU205. When the power source of the second PMU205 is different from that of the first PMU204, this application can set two power sources, each of which is connected to a PMU. The power source can be electrically connected to the first substrate 201 to achieve electrical connection with the first PMU204.
[0050] One possible example is that the second PMU205 is a standalone die or module. In this case, the second PMU205 can be directly mounted or disposed on the surface of the second die 203 and electrically connected to the surface of the second die 203. Another possible example is that the second PMU205 is integrated into another module, which can be mounted or disposed on the surface of the second die 203 and electrically connected to the surface of the second die 203, as described below.
[0051] A first die 202 is stacked on the surface of the first substrate 201, meaning that the first die 202 is electrically connected to the first substrate 201. Since a first PMU 204 is disposed in the first substrate 201, the first die 202 is electrically connected to the first PMU 204, and the first die 202 draws power from the first PMU 204. A second die 203 is stacked on the surface of the first die 202, meaning that the second die 203 is electrically connected to the first die 202, and signal transmission can occur between the second die 203 and the first die 202. A second PMU 205 is stacked on the surface of the second die 203, meaning that the second PMU 205 is electrically connected to the second die 203, and the second die 203 draws power from the second PMU 205.
[0052] With the above architecture, the first die 202 and the second die 203 are powered by different PMUs. The first die 202 does not need to be configured as a TSV for transmitting power to the second die 203, which reduces the manufacturing cost of the first die 202 and consequently the overall chip manufacturing cost. Furthermore, this also improves the area utilization of the first die 202. Since the second PMU 205 is stacked on top of the second die 203, the second die 203 directly obtains power from the second PMU 205, which meets the requirements of the second die 203 for response speed and adjustment accuracy to the second PMU 205. Since the power supply path of the second die 203 does not need to pass through the first die 202, but instead draws power directly from the second PMU 205, the power supply path of the second die 203 can be shortened. Because the parasitic resistance and inductance of the die are positively correlated with the length of the power supply path, shortening the power supply path of the second die 203 reduces its parasitic resistance and inductance, improving the power supply quality and efficiency from the PMU to the second die 203. Furthermore, due to the more advanced fabrication process of the second die 203, compared to integrating the second PMU 205 into the second die 203, the manufacturing cost of the second die 203 can be reduced, thereby further reducing the manufacturing cost of the chip 200.
[0053] For a description of the power supply scheme for chip 200, please refer to [link / reference]. Figure 3 . refer to Figure 3 For example, the first die 202 is electrically connected to the upper surface of the first substrate 201 via a uBump. The first die 202 and the second die 203 are bonded together via HB (helical bonding), and three HB metal structure contact interfaces exist between them. The first die 202 contains an RDL (Receptor Drilling Array), a PDN (Programmable Node Network), and devices. The RDL is electrically connected to the uBump and the PDN, respectively. The devices in the first die 202 obtain power from the PMU 204 through the PDN and the RDL. The second die 203 contains a PDN, a nano-through-silicon via (nTSV), and devices. The devices in the second die 203 obtain power from the PMU 205 through the nTSV and the PDN. Here, nTSV refers to a TSV with a diameter on the nanometer scale, used to penetrate the substrate to achieve vertical electrical connections. Compared to traditional micron-scale TSVs, nTSVs have smaller linewidths, higher integration density, and lower parasitic capacitance, enabling high-density, low-power vertical interconnects within the chip.
[0054] One possible example is that the first die 202 and the second die 203 can be bonded together by a face-to-face (F2F) HB process or by a face-to-back (F2B) HB process, without limitation.
[0055] Figure 2 The first die 202 and the second die 203 are stacked using the HB process. Alternatively, the first die 202 and the second die 203 can be stacked using the ubump process. As a possible example, the first die 202 and the second die 203 can also be stacked using the F2F ubump process or the F2B ubump process; there is no limitation on this.
[0056] As mentioned earlier, the PMU205 can be integrated into other modules, and a description of such modules can be found below.
[0057] In one possible implementation, the chip 200 also includes a second substrate 206, which is stacked on the surface of the second die 203, and the second substrate 206 is provided with a second PMU 205.
[0058] The second substrate 206 is stacked on the surface of the second die 203, meaning that the second die 203 is electrically connected to the second substrate 206. Since the second substrate 206 contains the second PMU 205, the second die 203 is electrically connected to the second PMU 205, and the second die 203 draws power from the second PMU 205. The second substrate 206 can also be referred to as the packaging substrate; for a detailed description, please refer to the preceding description of the first substrate 201, which will not be repeated here. The second substrate 206 can be stacked on the surface of the second die 203 using either HB (bump) technology or micro-bump technology, which can be selected according to process requirements.
[0059] In mass production scenarios, by integrating the second PMU205 into the second substrate 206, the packaging and mounting of the second PMU205 can be eliminated, reducing assembly costs and thus reducing the cost of the chip 200.
[0060] For a description of the second substrate 206, please refer to [link / reference]. Figure 4 . refer to Figure 4 Compared to Figure 2 The chip 200 further includes a second substrate 206, which is stacked on the surface of the second die 203, and a second PMU 205 is disposed on the second substrate 206. Specifically, regarding... Figure 4 The power supply scheme for the chip 200 shown is similar to that for... Figure 3 The power supply scheme for chip 200 is basically the same and will not be described in detail here.
[0061] The second substrate 206 can be stacked on the surface of the second die 203 in various ways, as described below.
[0062] One possible implementation is that the second substrate 206 is stacked on the surface of the second die 203, including: The second substrate 206 is stacked on the front side of the second die 203, and the front side of the second die 203 is the surface on which the active transistor is formed; or, The second substrate 206 is stacked on the back side of the second die 203, with the back side of the second die 203 facing the front side of the second die 203.
[0063] When the second substrate 206 is stacked on the front side of the second die 203, this application can fabricate a PDN on the front side of the second die 203. This reduces the manufacturing complexity of the PDN, while also reducing the manufacturing cost of the chip 200 and ensuring yield. When the second substrate 206 is stacked on the back side of the second die 203, this application can fabricate a PDN on the back side of the second die 203. This frees up wiring space in the metal layer on the front side of the second die 203, reduces interference between power and signals, and optimizes power supply quality.
[0064] The above description is based on the example of the second PMU205 being disposed on the second substrate 206. Other layers may also be disposed between the second substrate 206 and the second die 203, as described below.
[0065] In one possible implementation, the chip 200 also includes an interposer 207 located between the second die 203 and the second substrate 206, with the PDN of the second die 203 disposed in the second die 203 and the interposer 207.
[0066] Interposer 207 is a carrier disposed between a die and a package substrate or between multiple dies. It integrates high-density wiring and vertical vias to enable pin transitions, signal fan-out, and interconnect wiring for chips of different sizes, pin numbers, and pitches, thereby completing the interconnection and integration of multiple dies. Interposer 207 can be a silicon interposer or a silicon carbide interposer, and there is no limitation on the latter.
[0067] Interposer 207 is located between the second die 203 and the second substrate 206, meaning that interposer 207 is stacked on the surface of the second die 203, and the second substrate 206 is stacked on the surface of interposer 207. Interposer 207 is stacked on the surface of the second die 203 by either HB process or microbump process, which can be selected according to process requirements.
[0068] The PDN of the second die 203 is disposed in the second die 203 and the interposer 207. This means that a portion of the complete PDN of the second die 203 is fabricated in the interposer 207, and the remaining portion of the complete PDN of the second die 203 is fabricated in the second die 203. In other words, only a portion of the complete PDN is fabricated in the second die 203, rather than the entire complete PDN.
[0069] By providing an interposer between the second die 203 and the second substrate 206, the interposer can provide additional metal layer resources for constructing the PDN of the second die 203, thereby simplifying the PDN design inside the second die 203. This can free up some of the metal layer resources of the second die 203 for other functions, or reduce the demand for metal layer resources of the second die 203, further improving the design flexibility and area utilization of the chip.
[0070] For a description of the intermediary layer 207, please refer to [link / reference]. Figure 5 . refer to Figure 5 Compared to Figure 4 The chip 200 also includes an interposer 207, which is located between the second die 203 and the second substrate 206. The length of the interposer 207 is less than the length of the second substrate 206.
[0071] The following text combines Figure 6 right Figure 5 The power supply scheme for the chip 200 is described below. (Refer to...) Figure 6 For example, the first die 202 is electrically connected to the upper surface of the first substrate 201 via a uBump. The first die 202 and the second die 203 are bonded together via HB (helical interface), and there are three HB metal structure contact interfaces between the first die 202 and the second die 203. The first die 202 contains an RDL (Receptor Layer), a PDN (Power Distribution Network), and devices. The RDL is electrically connected to the uBump and the PDN, respectively. The devices in the first die 202 obtain power from the PMU 204 through the PDN and the RDL. The second die 203 and the interposer 207 are bonded together via HB, wherein there are three HB metal structure contact interfaces between the second die 203 and the interposer 207. The interposer 207 contains a PDN, which is electrically connected to the PMU 205. The second die 203 is provided with a PDN, an nTSV and a device. The PDN is electrically connected to the HB metal structure contact interface between the second die 203 and the interposer 207. The device in the second die 203 obtains power from the PMU 205 through the nTSV and the PDN.
[0072] Intermediate layer 207 can be stacked on the surface of second die 203 in a variety of ways, as described below.
[0073] One possible implementation is that the interposer 207 is located between the second die 203 and the substrate 206, and includes: Intermediate layer 207 is stacked on the front side of second die 203; or, Intermediate layer 207 is stacked on the back side of second die 203.
[0074] When the interposer layer 207 is stacked on the front side of the second die 203, this application can fabricate a PDN on the front side of the second die 203. This reduces the manufacturing complexity of the PDN, while also reducing the manufacturing cost of the chip 200 and ensuring yield. When the interposer layer 207 is stacked on the back side of the second die 203, this application can fabricate a PDN on the back side of the second die 203. This frees up wiring space on the front side of the second die 203, reduces interference between power and signals, and optimizes power supply quality.
[0075] Figures 2 to 6 This is an overall description of chip 200. The following text describes the power source of chip 200.
[0076] In one possible implementation, the chip 200 also includes a power transmission structure 208 for power transmission between the first substrate 201 and the second substrate 206.
[0077] The power transmission structure 208 is a structure capable of power transmission. The power transmission structure 208 is independent of the die, or the power transmission structure 208 does not pass through the die. The first substrate 201 can output power to the second substrate 206 through the power transmission structure 208, or the second substrate 206 can output power to the first substrate 201 through the power transmission structure 208. Through the power transmission structure 208, the power source for the first PMU 204 and the power source for the second PMU 205 can be the same. This simplifies the power supply design complexity; that is, one power supply powers multiple dies, and the power supply path of the top die does not pass through other dies, thus achieving the aforementioned advantages.
[0078] For a description of the power transmission structure 208, please refer to [link / reference needed]. Figure 7 . Figure 7 In (a), compared to Figure 5 The chip 200 also includes a power transmission structure 208, which is used to connect the second substrate 206 and the first substrate 201 to realize power transmission between the second substrate 206 and the first substrate 201. Figure 7 In (b), compared to Figure 2The chip 200 also includes a power transmission structure 208, which is used to connect the second substrate 206 and the first substrate 201 to realize power transmission between the second substrate 206 and the first substrate 201.
[0079] In this embodiment of the application, the power transmission structure 208 may include various forms, as described below.
[0080] One possible implementation is that the power transmission structure 208 includes one or more of the following: copper pillars, power transfer die, or through-mold via (TMV).
[0081] A TMV (Through-Mount Virtual Machine) is a vertical conductive via fabricated in the mold compound layer of a chip package. It is used to penetrate the mold compound and achieve electrical interconnection between the interior of the package (such as the substrate / RDL) and the outside. When the power transmission structure 208 is a TMV, the TMV is disposed between the second substrate 206 and the first substrate 201 to achieve power transmission between the first substrate 201 and the second substrate 206.
[0082] When the power transmission structure 208 is a copper pillar, the copper pillar is disposed between the second substrate 206 and the first substrate 201 to realize power transmission between the first substrate 201 and the second substrate 206.
[0083] A power transfer die is a functional device that does not require transistors or other components to perform logic operations. Instead, it consists of a substrate with conductive interconnect structures such as metal interconnect layers, vertical vias, and metal contact interfaces. When the power transmission structure 208 is a power transfer die, it is positioned between the second substrate 206 and the first substrate 201. Its interconnect structure forms a continuous conductive path, enabling power transmission between the two substrates.
[0084] Figures 2 to 7 The description is based on the example of chip 200 including a first die 202 and a second die 203. Chip 200 may also include more dies, as detailed in the following description.
[0085] In one possible implementation, chip 200 further includes a third die 209 located between the first die 202 and the second die 203. A first PMU 204 supplies power to the third die 209, and / or a second PMU 205 supplies power to the third die 209.
[0086] The third bare film 209 can represent one bare film or multiple bare films. For ease of description, the following description will take the example of the third bare film 209 representing one bare film.
[0087] The third die 209 is located between the first die 202 and the second die 203, meaning that the third die 209 is stacked on the surface of the first die 202, and the second die 203 is stacked on the surface of the third die 209. The process for stacking the third die 209 on the surface of the first die 202 can be found in the foregoing description and will not be repeated here.
[0088] The third die 209 can draw power from the first PMU 204, the second PMU 205, or both simultaneously; there is no limitation on this. When the third die 209 draws power from the first PMU 204, the power supply path of the third die 209 and... Figure 1 The power supply path of die 103 is the same. When the third die 209 draws power from the second PMU 205, the power supply path of the third die 209 can be referenced. Figure 1 The power supply path of the bare die 103 in the middle.
[0089] For a description of the third nude film 209, please refer to [link / reference]. Figure 8 . refer to Figure 8 Compared to Figure 2 The chip 200 also includes a third die 209, which is stacked on the surface of the first die 202, and a second die 203 is stacked on the surface of the third die 209.
[0090] The following text combines Figure 9 right Figure 8 The power supply scheme for the chip 200 is described below. (Refer to...) Figure 9Taking the third die 209 obtaining power from the second PMU 205 as an example, exemplarily, the first die 202 is electrically connected to the upper surface of the first substrate 201 via a uBump. The first die 202 and the third die 209 are bonded together via HB, and there are three HB metal structure contact interfaces between the first die 202 and the third die 209. The second die 203 and the third die 209 are bonded together via HB, and there are three HB metal structure contact interfaces between the second die 203 and the third die 209. The first die 202 is provided with an RDL, a PDN, and a device. The RDL is electrically connected to the uBump and the PDN, respectively. The device obtains power from the first PMU 204 through the PDN and the RDL. The second die 203 is provided with a TSV, an RDL, a PDN, an nTSV, and a device. The RDL is electrically connected to the uBump, the PDN, and the TSV, respectively. The device is electrically connected to the PDN through the nTSV and obtains power from the second PMU 205 through the RDL. The third die 209 contains a PDN and a device. The PDN is electrically connected to the HB metal structure contact interface between the third die 209 and the second die 203. The device obtains power from the second PMU 205 through the PDN, the HB metal structure contact interface between the second die 203 and the third die 209, the TSV in the second die 203, and the RDL in the second die 203.
[0091] When chip 200 includes both a third die 209 and an interposer 207, the power supply scheme of chip 200 can be described in [reference needed]. Figure 9 and Figure 6 The description will not be repeated here.
[0092] The following text combines Figure 10 The fabrication process of chip 200 is described exemplarily below. For ease of description, the following mainly focuses on... Figure 2 The manufacturing process of the chip 200 is described exemplarily, and the content can also be applied to... Figure 4 The manufacturing process of the chip 200 and Figure 5 The manufacturing process of the chip 200.
[0093] refer to Figure 10 (a) First die 202 is fabricated. Specifically, a dielectric layer 2022 and a device layer 2024 are first fabricated on a substrate 2021 made of silicon wafer. Next, a TSV 2023 is fabricated, with one end electrically connected to the device layer 2024 and the other end extending into the substrate 2021. Finally, a passivation layer 2025 and metal pads 2026 are fabricated. The device layer 2024 contains RDL, PDN, and other devices. The TSV 2023 is used to realize signal transmission between the first die 202 and the dies stacked on top of the first die 202.
[0094] refer to Figure 10 (b) The first die 202 is stacked with the first substrate 201. Specifically, bumps are formed on the surface of the metal pads 2026, and then the first substrate 201 and the first die 202 are electrically connected to achieve stacking of the first die 202 on the surface of the first substrate 201. The first substrate 201 integrates a first PMU 204. Then, the substrate 2021 is thinned to expose one end of the TSV 2023.
[0095] refer to Figure 10 (c) The first die 202 and the second die 203 are stacked. Specifically, metal pads are prepared on the surface of the first die 202 and bumps are prepared on the metal pads of the second die 203. The second die 203 and the first die 202 are electrically connected through the bumps so that the second die 203 is stacked on the surface of the first die 202. The structure of the second die 203 is basically the same as the structure of the first die 202.
[0096] refer to Figure 10 (d) The substrate of the second die 203 is thinned to expose one end of the TSV in the second die 203. The TSV in the second die 203 is used to realize power transmission.
[0097] refer to Figure 10 (e) The second die 203 is stacked with the second PMU 205. Specifically, a metal pad is prepared on the surface of the substrate of the second die 203, and bumps are prepared on the metal pad. The second die 203 and the second PMU 205 are electrically connected through the bumps, and finally the second PMU 205 is stacked on the surface of the second die 203.
[0098] Figure 10 The manufacturing process of chip 200 described above is for illustrative purposes only. Anyone skilled in the art can prepare the chip based on existing processes. Figures 2 to 9 The aforementioned chip 200.
[0099] This application also provides an electronic device, which includes a chip 200. Optionally, the electronic device may further include one or more of the following: a power supply circuit, a clock oscillation circuit, a communication interface circuit, and a drive circuit. The aforementioned circuits are electrically connected to the chip 200 to meet one or more of the chip 200's power supply, timing, data interaction, and signal processing requirements. The above-mentioned electronic device can be applied to devices that require charging, such as mobile phones, tablets, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, and augmented reality (AR) terminal devices. The above-mentioned electronic device can also be applied to rechargeable electric vehicles, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, and other electronic devices. This application does not impose any special limitations on the specific form of the above-mentioned electronic device.
[0100] This application also provides an electronic device that includes the aforementioned electronic components. This electronic device can be a mobile phone, tablet computer, smart wearable product, VR terminal device, AR terminal device, etc. It can also be a rechargeable electric vehicle, a rechargeable small household appliance, a drone, etc.
[0101] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A chip, characterized in that, include: A first substrate, wherein a first power management unit is disposed on the first substrate; A first die, the first die is stacked on the surface of the first substrate, and the first power management unit supplies power to the first die; A second die, which is stacked on the surface of the first die; A second power management unit is stacked on the surface of the second die, and the second power management unit supplies power to the second die.
2. The chip according to claim 1, characterized in that, The chip also includes: The second substrate is stacked on the surface of the second die, and the second substrate is provided with the second power management unit.
3. The chip according to claim 2, characterized in that, The chip also includes: An interposer layer is located between the second die and the second substrate, and a power distribution network for the second die is disposed in the second die and the interposer layer.
4. The chip according to claim 2 or 3, characterized in that, The chip also includes: A power transmission structure for power transmission between the first substrate and the second substrate.
5. The chip according to claim 4, characterized in that, The power transmission structure includes one or more of the following: Copper pillars, power adapter bare plates, or molded through holes.
6. The chip according to any one of claims 1 to 5, characterized in that, The chip also includes: A third die, wherein the third die is located between the first die and the second die; The first power management unit supplies power to the third die, and / or the second power management unit supplies power to the third die.
7. The chip according to claim 2, characterized in that, The second substrate is stacked on the surface of the second bare die, including: The second substrate is stacked on the front side of the second die, and the front side of the second die is the surface for forming active transistors; or, The second substrate is stacked on the back side of the second die, and the back side of the second die is opposite to the front side of the second die.
8. The chip according to any one of claims 3 to 6, characterized in that, The interposer layer is located between the second die and the second substrate, and includes: The interposer layer is stacked on the front side of the second die, and the front side of the second die is the surface for forming the active transistor; or, The interposer layer is stacked on the back side of the second die, with the back side of the second die facing the front side of the second die.
9. An electronic device, characterized in that, The electronic device includes the chip according to any one of claims 1 to 8.
10. An electronic device, characterized in that, The electronic device includes the electronic device as described in claim 9.