Packaging structure and packaging method

Abstract

The application provides a packaging structure and a packaging method. The packaging structure comprises: a substrate, the substrate has opposite first and second surfaces in a thickness direction; a first core particle, the first core particle has opposite first and second surfaces in the thickness direction, and the first core particle is located in the substrate; a first auxiliary core particle, the first auxiliary core particle is coupled with the first surface of the substrate and the first surface of the first core particle through a hybrid bonding structure; a second auxiliary core particle, the second auxiliary core particle is coupled with the second surface of the substrate and the second surface of the first core particle through a hybrid bonding structure; the first auxiliary core particle covers the first surface of the first core particle and covers part of the first surface of the substrate; and the second auxiliary core particle covers the second surface of the first core particle and covers part of the second surface of the substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a packaging structure and packaging method. Background Technology

[0002] In traditional chip-to-substrate interconnect solutions, the chip typically only physically and electrically connects to the substrate through microbumps or solder balls arranged on its edge regions. The central region of the chip does not participate in external interconnection and only serves internal circuit functions. This interconnection method, which relies solely on chip edge bumps, results in the number of available input / output channels being physically limited by the chip's perimeter, making it difficult to effectively expand as chip functional complexity and data transmission requirements increase. Limited edge interconnect resources simultaneously carry multiple functional traces, including signal lines, power lines, ground lines, and control signals. Signal networks and power distribution networks must share these scarce edge bandwidths, causing crosstalk and resource contention between signals and power. With the increasing computing power of chips and the trend towards multi-chip integration, interconnect bandwidth demands are surging. Traditional edge bump interconnection methods have become a major bottleneck restricting system performance and integration density, failing to meet the advanced packaging requirements of high bandwidth, low latency, and high power integrity. Therefore, there is still much room for improvement in packaging structures and methods. Summary of the Invention

[0003] According to some aspects of embodiments of this application, a packaging structure is provided, comprising: a substrate having opposing first and second surfaces in a thickness direction; a first core having opposing first and second surfaces in the thickness direction, the first core being located in the substrate; a first auxiliary core coupled to the first surface of the substrate and the first surface of the first core via a hybrid bonding structure; a second auxiliary core coupled to the second surface of the substrate and the second surface of the first core via a hybrid bonding structure; the first auxiliary core covering the first surface of the first core and a portion of the first surface of the substrate; and the second auxiliary core covering the second surface of the first core and a portion of the second surface of the substrate.

[0004] In some embodiments, the first surface of the first auxiliary core is provided with a plurality of first bonding contacts, the first surface of the substrate is provided with a plurality of second bonding contacts, and the first surface of the first core is provided with a plurality of third bonding contacts; wherein, the first bonding contacts include a first type of contact and a second type of contact, the first type of contact is bonded to the second bonding contact, and the second type of contact is bonded to the third bonding contact; the first type of contact is distributed at intervals around the plurality of second type of contact.

[0005] In some embodiments, the first chip includes a plurality of first sub-chips, which are sequentially bonded together, and adjacent first sub-chips are coupled by a hybrid bonding structure; the first sub-chip includes: a first semiconductor layer; a first device structure, at least partially located on the first semiconductor layer; and a first connection structure, which at least penetrates the first semiconductor layer and is coupled to the first device structure.

[0006] In some embodiments, the packaging structure further includes a second core located in the substrate, the second core having opposing first and second surfaces in the thickness direction.

[0007] In some embodiments, the first surface of the first auxiliary core is also coupled to the first surface of the second core through a hybrid bonding structure; the first surface of the second auxiliary core is also coupled to the second surface of the second core through a hybrid bonding structure.

[0008] In some embodiments, the packaging structure further includes: a third auxiliary core, the first surface of which is coupled to the substrate and the first surface of the second core via a hybrid bonding structure; a fourth auxiliary core, the first surface of which is coupled to the substrate and the second surface of the second core via a hybrid bonding structure; the first surface of the third auxiliary core covers the first surface of the second core and a portion of the first surface of the substrate; the first surface of the fourth auxiliary core covers the second surface of the second core and a portion of the second surface of the substrate.

[0009] In some embodiments, the packaging structure further includes: a fifth auxiliary core located in the substrate, the fifth auxiliary core being located between the first core and the second core; a first surface of the first auxiliary core being coupled to the first surface of the fifth auxiliary core via a hybrid bonding structure; a first surface of the second auxiliary core being coupled to the second surface of the fifth auxiliary core via a hybrid bonding structure; a first surface of the third auxiliary core being coupled to the first surface of the fifth auxiliary core via a hybrid bonding structure; and a first surface of the fourth auxiliary core being coupled to the second surface of the fifth auxiliary core via a hybrid bonding structure.

[0010] In some embodiments, the packaging structure further includes a first heat dissipation structure, which covers the outer periphery of the first auxiliary core and the second auxiliary core.

[0011] In some embodiments, the packaging structure further includes a second heat dissipation structure located in the substrate, the second heat dissipation structure being located at least on both sides of the first core.

[0012] In some embodiments, the packaging structure further includes a filler layer located between the first core and the substrate, the filler layer surrounding the outer periphery of the first core.

[0013] According to some aspects of embodiments of this application, a packaging method is provided, comprising: providing a substrate; etching the substrate to form a first groove, the first groove penetrating the substrate along a thickness direction; providing a first core particle; disposing the first core particle within the first groove; hybrid bonding a first auxiliary core particle to a first surface of the substrate and a first surface of the first core particle, the first auxiliary core particle covering the first surface of the first core particle and a portion of the first surface of the substrate, the first auxiliary core particle being coupled to the first surface of the substrate and the first surface of the first core particle via a hybrid bonding structure; and hybrid bonding a second auxiliary core particle to a second surface of the substrate and a second surface of the first core particle, the second auxiliary core particle covering the second surface of the first core particle and a portion of the second surface of the substrate, the second auxiliary core particle being coupled to the second surface of the substrate and the second surface of the first core particle via a hybrid bonding structure.

[0014] In some embodiments, the packaging method includes: forming a plurality of first bonding contacts on a first surface of the first auxiliary core, wherein the first bonding contacts include first type contacts and second type contacts, and the first type contacts are spaced apart around the plurality of second type contacts; forming a plurality of second bonding contacts on a first surface of the substrate; forming a plurality of third bonding contacts on a first surface of the first core; bonding the first type contacts and the second bonding contacts, and bonding the second type contacts and the third bonding contacts.

[0015] In some embodiments, providing a first chip includes: sequentially bonding a plurality of first sub-chips, adjacent first sub-chips being coupled by a hybrid bonding structure; the first sub-chip includes: a first semiconductor layer; a first device structure at least partially located on the first semiconductor layer; and a first connection structure at least penetrating the first semiconductor layer and coupled to the first device structure.

[0016] In some embodiments, the packaging method further includes: etching the substrate to form a second groove, the second groove penetrating the substrate along the thickness direction; and providing a second core, wherein the second core is disposed within the second groove.

[0017] In some embodiments, the packaging method further includes: the first auxiliary core is further mixed-bonded with a first surface of the second core; and the second auxiliary core is further mixed-bonded with a second surface of the second core.

[0018] In some embodiments, the packaging method further includes: co-bonding a third auxiliary core to the substrate and a first surface of the second core, wherein the third auxiliary core covers the first surface of the second core and a portion of the first surface of the substrate; and co-bonding a fourth auxiliary core to the substrate and a second surface of the second core, wherein the fourth auxiliary core covers the second surface of the second core and a portion of the second surface of the substrate.

[0019] In some embodiments, the packaging method further includes: etching the substrate to form a third groove, the third groove penetrating the substrate along the thickness direction and located between the first groove and the second groove; disposing the fifth auxiliary core in the third groove; the first auxiliary core is also mixed-bonded with a first surface of the fifth auxiliary core, the second auxiliary core is also mixed-bonded with a second surface of the fifth auxiliary core; the third auxiliary core is also mixed-bonded with the first surface of the fifth auxiliary core, and the fourth auxiliary core is also mixed-bonded with the second surface of the fifth auxiliary core.

[0020] In some embodiments, the packaging method further includes: forming a first heat dissipation structure covering the outer periphery of the first auxiliary core and the second auxiliary core.

[0021] In some embodiments, the packaging method further includes: etching the substrate to form a fourth groove and a fifth groove, the fourth groove and the fifth groove being located on both sides of the first groove; and forming a second heat dissipation structure within the fourth groove and the fifth groove.

[0022] In some embodiments, the step of disposing the first core in the first groove includes: placing the first core in the first groove and filling the space between the first core and the substrate with a dielectric material to form a filler layer.

[0023] This application provides a packaging structure, including: a substrate having opposing first and second surfaces in the thickness direction; a first core having opposing first and second surfaces in the thickness direction, the first core being located within the substrate; a first auxiliary core, the first surface of the first auxiliary core being coupled to the substrate and the first surface of the first core via a hybrid bonding structure; and a second auxiliary core, the first surface of the second auxiliary core being coupled to the substrate and the second surface of the first core via a hybrid bonding structure; the first surface of the first auxiliary core covers the first surface of the first core and a portion of the first surface of the substrate; the first surface of the second auxiliary core covers the second surface of the first core and a portion of the second surface of the substrate. The first core is encapsulated within the substrate and is covered and electrically interconnected from both sides by the first and second auxiliary cores. The input / output signals and power of the first core can be directly input and output via the first and second auxiliary cores using double-sided hybrid bonding. This improves the interaction bandwidth between the core and external systems, allows signal and power networks to be naturally separated and led out on the top and bottom sides, resulting in shorter interconnection paths and significantly reduced parasitic effects. Attached Figure Description

[0024] Figures 1 to 2 This is a schematic diagram of an exemplary packaging structure provided in an embodiment of this application; Figures 3 to 12 This is a schematic diagram of the packaging structure provided in an embodiment of this application; Figure 13 This is a schematic diagram of the encapsulation method provided in the embodiments of this application; Figure 14 This is a schematic diagram of etching the first groove provided in an embodiment of this application; Figure 15 This is a schematic diagram of graphic alignment provided in the embodiments of this application. Detailed Implementation

[0025] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0026] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0027] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0030] This application provides a packaging structure. The thickness mentioned below can be the z-direction as illustrated in the figures. The z-direction is the thickness direction of the device or the vertical direction. The x-direction and y-direction can intersect or be perpendicular. The xoy plane intersects or is perpendicular to the z-direction. The x and y directions can be interchanged.

[0031] According to some aspects of the embodiments of this application, Figure 1 An exemplary packaging structure is provided, including a substrate 11, and a first chip 12 and a second chip 13 stacked on the substrate 11. The first chip 12 and the second chip 13 are bonded together. A redistribution layer is provided on the substrate 11 and is bonded together with the substrate 11. The side of the first chip 12 facing away from the second chip 13 is bonded together with the side of the redistribution layer facing away from the substrate 11. (Refer to...) Figure 2 As shown, in this packaging structure, the bonding contacts on the first chip 12 are divided into two functional areas: only the chip edge contacts are used for physical and electrical interconnection with the substrate 11, while the middle area contacts 122 are dedicated to the three-dimensional stacking bonding between multiple chips. This design results in the entire system relying solely on a limited number of edge contacts 121 or pad substrates 11 for communication, thus severely limiting the number of input / output channels; simultaneously, signal traces and power networks have to share these edge bandwidths, further exacerbating the strain on interconnect resources. When the second chip 13 stacked on top needs to interact with the substrate 11, data and control signals pass vertically through the first chip 12 via through-silicon vias (TSVs), and then indirectly complete communication with the substrate 11 via the edge path of the first chip 12. In view of this, embodiments of this application provide a packaging structure that constructs a double-sided signal and power lead-out and interconnect architecture for a system-on-a-chip (SoC), so that signal traces and power networks are no longer limited to a single edge of the chip, but can be led out from both the front and back main surfaces of the chip simultaneously.

[0032] According to some aspects of the embodiments of this application, Figure 3 A packaging structure is provided, comprising: Substrate 11, substrate 11 has opposing first and second surfaces in the thickness direction; The first core 20 has a first surface and a second surface opposite each other in the thickness direction, and the first core 20 is located in the substrate 11. The first auxiliary core 30, the first surface of the first auxiliary core 30 is coupled to the first surface of the substrate 11 and the first surface of the first core 20 through a hybrid bonding structure; The second auxiliary core 40, the first surface of the second auxiliary core 40 is coupled to the first surface of the substrate 11 and the second surface of the first core 20 through a hybrid bonding structure; The first auxiliary core 30 covers the first surface of the first core 20 and a portion of the first surface of the substrate 11; The second auxiliary core 40 covers the second surface of the first core 20 and a portion of the second surface of the substrate 11.

[0033] The packaging structure includes a substrate 11, a first chip 20, a first auxiliary chip 30, and a second auxiliary chip 40. The first chip 20 is embedded in the substrate 11, with its first and second surfaces in the thickness direction substantially flush with the first and second surfaces of the substrate 11, respectively. A redistribution structure for signal and power redistribution is constructed within the substrate 11 to work in conjunction with the first and second auxiliary chips 30 and 40 to achieve high-density interconnection. The substrate 11 may include, but is not limited to, a packaging substrate, a silicon interposer, a PCB board, or other packaging materials with a redistribution structure. The redistribution structure of the substrate may be located on the first surface, the second surface, or inside the substrate, and may include, but is not limited to, multi-layered wiring and conductive plugs between adjacent wiring layers, as well as through-substrate connection structures such as TSVs. The redistribution structure is used to realize electrical signal interconnection between the various chips coupled on the front and back surfaces of the substrate, including but not limited to control signal communication interconnection, data transmission, and relay power supply. In some examples, the substrate may include a silicon interposer, allowing the height difference between the substrate and the chips on the substrate to be filled by a dielectric material. A redistribution layer is provided on an auxiliary chip on either side to bring out the electrical signals of the package structure. Furthermore, a redistribution structure can be provided on the dielectric material to bring out the electrical signals of the substrate, thus completing the global electrical signal outsourcing of the package structure. The dielectric material may include a material with high thermal conductivity to facilitate heat dissipation.

[0034] Reference Figure 3 As shown, on one side of the first surface of the substrate 11, the first surface of the first auxiliary core 30 is simultaneously bonded and coupled to a portion of the first surface of the substrate 11 and the first surface of the first core 20 via a hybrid bonding structure. (Refer to...) Figure 4As shown, the first surface of the first auxiliary core 30 covers the first surface of the first core 20 and a portion of the first surface of the substrate 11. Similarly, on the second surface side of the substrate 11, the first surface of the second auxiliary core 40 is bonded and coupled to both a portion of the second surface of the substrate 11 and the second surface of the first core 20 via a hybrid bonding structure. The first surface of the second auxiliary core 40 covers the second surface of the first core 20 and a portion of the second surface of the substrate 11. The first core 20 is encapsulated within the substrate 11 and is covered from both the front and back surfaces by the first auxiliary core 30 and the second auxiliary core 40. The input / output signals and power supply of the first core 20 can be interconnected via the first auxiliary core 30 and the second auxiliary core 40 through the double-sided hybrid bonding structure. The communication, data transmission, and power supply of the first auxiliary core 30 and the second auxiliary core 40 can be electrically interconnected with external integrated circuit structures or systems such as PCB boards via substrate relay. When interconnection is achieved solely through chip edge bumps, the number of I / O channels is limited. The first auxiliary chip 30 and the second auxiliary chip 40 increase the interaction bandwidth between the first chip 20 and the external system. Signal and power networks can be separated and brought out on the top and bottom sides, shortening the interconnection path and reducing parasitic effects.

[0035] The first auxiliary core 30 and the second auxiliary core 40 can be selected as passive or active designs according to the actual needs of the first core 20, so as to realize differentiated functional carrying in the double-sided 3D packaging architecture of the substrate or core. The first auxiliary core 30 and the second auxiliary core 40 can be selected as passive designs at the same time, or they can be selected as active designs at the same time, or they can be selected separately. This application does not impose any restrictions.

[0036] In this embodiment, a passive design is adopted. The auxiliary chip can include or be configured as an interconnected bidirectional redistribution area (passive IOD), undertaking the electrical signal output function of the first chip 20 interface. By rearranging and redistributing the signals and power on the upper and lower surfaces of the first chip 20, the auxiliary chip defines and outputs the I / O interface of the first chip 20 to a more optimized circuit distribution area, reducing circuit distribution pressure and interference. Simultaneously, it can also connect external input signals and power supplies to the first chip 20, realizing a bidirectional interconnection path. At this time, the power distribution network in the original substrate 11 can also be transferred to the passive auxiliary chip, utilizing the advantage of bidirectional input to shorten the power supply path.

[0037] This embodiment employs an active design, where the auxiliary chip is an active interconnect chip (active IOD) with circuit processing capabilities. Based on system requirements, external communication IPs (excluding core logic) within the first chip 20 are migrated to the auxiliary chip, achieving heterogeneous decoupling of logic computation and I / O functions. For example, when the first chip 20 is a processor such as a CPU or GPU, or a chip with logic functions, various high-speed protocol interface IPs (including but not limited to PCIe, CXL, etc.), memory controllers, and interface controllers originally integrated within the first chip 20 can be separately designed and placed within the active auxiliary chip. These migrated IP modules have electrical signal output links, enabling the first chip 20 to perform bidirectional, efficient interaction with DRAM or other peripherals through the auxiliary chip. Furthermore, the auxiliary chip can further integrate some last-level cache, power distribution network (PDN), and decoupling capacitors, effectively freeing up the area of ​​the first chip 20 while expanding bidirectional interface capabilities and shortening the interconnect path.

[0038] In some embodiments, the first surface of the first auxiliary core 30 is provided with a plurality of first bonding contacts 31, the first surface of the substrate 11 is provided with a plurality of second bonding contacts 111, and the first surface of the first core 20 is provided with a plurality of third bonding contacts 21; wherein, the first bonding contacts 31 include first type contacts 311 and second type contacts 312, the first type contacts 311 are bonded to the second bonding contacts 111, and the second type contacts 312 are bonded to the third bonding contacts 21; the first type contacts 311 are distributed at intervals around the plurality of second type contacts 312.

[0039] The connection method of the second auxiliary core 40 is the same as that of the first auxiliary core 30. The following description will focus on the first auxiliary core 30.

[0040] The first auxiliary core 30, the substrate 11, and the first core 20 are coupled together by a hybrid bonding method. A plurality of first bonding contacts 31 are provided on the first surface of the first auxiliary core 30, and a plurality of second bonding contacts 111 are provided on the first surface of the substrate 11, as shown in the figure. Figure 5 As shown, a plurality of third bonding contacts 21 are disposed on the first surface of the first core 20. The first bonding contacts 31 on the first auxiliary core 30 are further divided into first type contacts 311 and second type contacts 312: the first type contacts 311 correspond one-to-one with and are bonded to the second bonding contacts 111 on the substrate 11, and the second type contacts 312 correspond one-to-one with and are bonded to the third bonding contacts 21 on the first core 20. In terms of spatial arrangement, the first type contacts 311 are distributed at intervals around the plurality of second type contacts 312, forming a surrounding layout with the corresponding area of ​​the first core 20 as the center and the corresponding area of ​​the substrate 11 as the periphery.

[0041] Through this structure of classified and spaced bonding contacts, the first auxiliary core 30 simultaneously covers and couples the substrate 11 and the first core 20. The input and output signals of the first core 20 are transmitted to the first auxiliary core 30 via the bonding of the second type of contact 312 and the third bonding contact 21, and then transmitted to the substrate via the bonding of the first type of contact 311 and the second bonding contact 111. Electrical signals within the substrate 11 are connected to the first auxiliary core 30 via the bonding of the first type of contact 311 and the second bonding contact 111, and then transmitted to the first core 20 via the bonding of the second type of contact 312 and the third bonding contact 21. The first core 20 can achieve high-density double-sided interconnection without needing to penetrate the substrate 11 using through-silicon vias; the first core 20 can complete the signal extraction through the first auxiliary core 30, shortening the interconnection path and helping to reduce parasitic effects and improve signal integrity.

[0042] In some embodiments, the first chip 20 includes a plurality of first sub-chips 22, which are bonded sequentially, and adjacent first sub-chips 22 are coupled by a hybrid bonding structure; the first sub-chip 22 includes: a first semiconductor layer 221; a first device structure 222, which is at least partially located on the first semiconductor layer 221; and a first connection structure 223, which at least penetrates the first semiconductor layer 221 and is coupled to the first device structure 222.

[0043] Reference Figure 6 As shown, the first core 20 is formed by sequentially stacking and bonding multiple first sub-cores 22 in the thickness direction. Adjacent first sub-cores 22 are face-to-face coupled through a hybrid bonding structure. The multiple first sub-cores 22 can respectively carry computing logic, cache, memory array, or specific acceleration units. With the help of the short-pitch interconnection provided by hybrid bonding, low-latency, high-bandwidth data transmission between cores is achieved. Different first sub-cores 22 may include cores of the same type or cores of different types.

[0044] The first sub-core 22 includes a first semiconductor layer 221, which may be a substrate of the first sub-core 22 or a semiconductor film epitaxially grown on the substrate. The first semiconductor layer 221 may include, but is not limited to, elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. For example, silicon, germanium, or silicon carbide. It may also include materials such as indium gallium zinc oxide (IGZO), where IGZO materials may be composed of oxides of elements such as indium, gallium, and zinc. The first device structure 222 may include, but is not limited to, transistors, memory devices, capacitors, inductors, resonant devices, radio frequency devices, and interconnect layers connected to the devices, as well as conductive plugs connecting the interconnect layers. The source and channel of the transistor may be located in the first semiconductor layer 221, and shallow trench isolation structures such as isolation between different transistors may be located in the first semiconductor layer 221. This application embodiment does not impose specific limitations on the electrical functions of the core, the physical structure of the internal devices, etc. Figure 6 A first connection structure 223 is provided that penetrates the first semiconductor layer 221 along the z-direction. The first connection structure 223 may include, but is not limited to, conductive structures such as through-silicon vias (TSVs), conductive plugs, and conductive pillars. The first connection structure 223 is coupled to the first device structure 222.

[0045] In some embodiments, the packaging structure further includes a second core 50 located in the substrate 11, the second core 50 having opposing first and second surfaces in the thickness direction.

[0046] Reference Figure 7 As shown, the substrate 11 not only contains a first core 20, but also a second core 50, or more cores, embedded within the substrate 11. The second core 50 has opposing first and second surfaces in the thickness direction, with both surfaces substantially flush with the first and second surfaces of the substrate 11, respectively. By integrating multiple parallel embedded cores horizontally within the substrate 11, tight coupling of multiple functional cores can be achieved within the same package. The first core 20 and the second core 50 can respectively support different computing, storage, or I / O functional modules.

[0047] In some embodiments, refer to Figure 7 As shown, the first surface of the first auxiliary core 30 is also coupled to the first surface of the second core 50 through a hybrid bonding structure; the first surface of the second auxiliary core 40 is also coupled to the second surface of the second core 50 through a hybrid bonding structure.

[0048] The first surface of the first auxiliary core 30, through a hybrid bonding structure, simultaneously covers and couples the first surface of the first core 20, the first surface of the second core 50, and a portion of the first surface of the substrate 11. Similarly, the first surface of the second auxiliary core 40, through a hybrid bonding structure, simultaneously covers and couples the second surface of the first core 20, the second surface of the second core 50, and a portion of the second surface of the substrate 11. When the interconnect bandwidth requirement between the first core 20 and the second core 50 is high, they do not need to communicate via the substrate 11 or external pins. Instead, they can directly achieve high-speed interconnection using the redistribution layer or active circuitry within the auxiliary core. Signals in the first core 20 and the second core 50 can be transmitted and interacted through the cooperation of the first auxiliary core 30 and the second auxiliary core 40.

[0049] In some embodiments, the packaging structure further includes: a third auxiliary core 60, the first surface of which is coupled to the first surface of the substrate 11 and the second core 50 via a hybrid bonding structure; a fourth auxiliary core 70, the first surface of which is coupled to the second surface of the substrate 11 and the second core 50 via a hybrid bonding structure; the first surface of the third auxiliary core 60 covers the first surface of the second core 50 and covers a portion of the first surface of the substrate 11; the first surface of the fourth auxiliary core 70 covers the second surface of the second core 50 and covers a portion of the second surface of the substrate 11.

[0050] Reference Figure 8 As shown, when the interconnect bandwidth requirement between the first core 20 and the second core 50 is not high, an independent auxiliary core scheme can be adopted to achieve horizontal partitioning integration of the two cores within the substrate 11. The second core 50 is embedded in the substrate 11, and its first and second surfaces in the thickness direction are substantially flush with the first and second surfaces of the substrate 11, respectively. The first surface of the third auxiliary core 60 is bonded and coupled to a portion of the first surface of the substrate 11 and the first surface of the second core 50 through a hybrid bonding structure, and the first surface of the third auxiliary core 60 covers the first surface of the second core 50 and a portion of the first surface of the substrate 11; the first surface of the fourth auxiliary core 70 is bonded and coupled to a portion of the second surface of the substrate 11 and the second surface of the second core 50 through a hybrid bonding structure, and the first surface of the fourth auxiliary core 70 covers the second surface of the second core 50 and a portion of the second surface of the substrate 11. The first core 20 completes the double-sided electrical signal lead-out by the first auxiliary core 30 and the second auxiliary core 40, and the second core 50 completes the double-sided electrical signal lead-out by the third auxiliary core 60 and the fourth auxiliary core 70. Each of the two cores has an independent auxiliary core group.

[0051] The first core 20 and the second core 50 use the auxiliary cores on their upper and lower sides to lead the electrical signals to the substrate 11. The four independent auxiliary cores can be flexibly designed as passive or active as needed, and each can independently complete interface rewiring, power distribution or protocol IP integration, thereby realizing horizontal heterogeneous splicing of multiple cores and providing a highly flexible architecture solution.

[0052] In some embodiments, refer to Figure 9 As shown, the packaging structure further includes: a fifth auxiliary core 80 located in the substrate 11, the fifth auxiliary core 80 being located between the first core 20 and the second core 50; the first surface of the first auxiliary core 30 being coupled to the first surface of the fifth auxiliary core 80 via a hybrid bonding structure; the first surface of the second auxiliary core 40 being coupled to the second surface of the fifth auxiliary core 80 via a hybrid bonding structure; the first surface of the third auxiliary core 60 being coupled to the first surface of the fifth auxiliary core 80 via a hybrid bonding structure; and the first surface of the fourth auxiliary core 70 being coupled to the second surface of the fifth auxiliary core 80 via a hybrid bonding structure.

[0053] When there is a high interconnect bandwidth requirement between the first core 20 and the second core 50, and the area of ​​the upper and lower surface auxiliary cores (IODs) is limited, a fifth auxiliary core 80 can be directly embedded inside the substrate 11 as a high-speed interconnect channel between the first core 20 and the second core 50. The fifth auxiliary core 80 is located between the first core 20 and the second core 50, and is embedded in the substrate 11. Its first and second surfaces in the thickness direction are substantially flush with the first and second surfaces of the substrate 11, respectively.

[0054] The first surface of the first auxiliary core 30 is not only bonded to the substrate 11 and the first surface of the first core 20, but also extends to cover and is coupled to the first surface of the fifth auxiliary core 80 through a hybrid bonding structure; the first surface of the second auxiliary core 40 is coupled to the second surface of the fifth auxiliary core 80 through a hybrid bonding structure. Similarly, the first surface of the third auxiliary core 60 is coupled to the first surface of the fifth auxiliary core 80 through a hybrid bonding structure; the first surface of the fourth auxiliary core 70 is coupled to the second surface of the fifth auxiliary core 80 through a hybrid bonding structure. The fifth auxiliary core 80 forms an interconnect bridge inside the substrate 11, completing the electrical signal interconnection of the four auxiliary cores on the upper and lower sides, and the interconnection path between the first core 20 and the second core 50 is shorter.

[0055] When the first chip 20 and the second chip 50 need to exchange data, this can be done directly through the fifth auxiliary chip 80, eliminating the need to bypass the redistribution layer on the substrate 11, or rely on a large-area silicon interposer or external bridging chip. The fifth auxiliary chip 80 can be designed as a passive, high-density redistribution channel, or it can integrate active routing, protocol conversion, or caching functions as needed, providing ultra-high bandwidth and ultra-low latency bidirectional interconnection within a limited embedded area. This solution sinks high-speed interconnect resources into the substrate 11, reducing the cost and size limitations of large-area interposers, while freeing up the area resources of the top and bottom surface IODs, allowing them to focus on electrical signal interconnection with external chips or system-level integration with the PCB. This provides a compact and scalable architectural path for realizing multi-chip, high-bandwidth, high-density heterogeneous system packaging.

[0056] In some embodiments, refer to Figure 10 As shown, the packaging structure also includes a first heat dissipation structure 90, which covers the outer periphery of the first auxiliary core 30 and the second auxiliary core 40.

[0057] The first heat dissipation structure 90 is configured to cover the outer peripheral regions of the first auxiliary core 30 and the second auxiliary core 40. The first heat dissipation structure 90 can cover the portions of the first auxiliary core 30 and the second auxiliary core 40 that are not bonded to the substrate 11, forming a large-area, low-thermal-resistance physical contact. At the same time, the first heat dissipation structure 90 is in contact with the edge regions of the upper and lower surfaces of the substrate 11.

[0058] For the first auxiliary core 30 and the second auxiliary core 40, which adopt an active design and integrate high-speed interface IP, cache or power management circuits, the heat generated can be efficiently conducted laterally and dissipated through the peripheral heat dissipation structure, effectively avoiding local hot spots and performance degradation caused by heat accumulation.

[0059] In some embodiments, refer to Figure 11 As shown, the packaging structure also includes a second heat dissipation structure 100 located in the substrate 11, the second heat dissipation structure 100 being located at least on both sides of the first core 20.

[0060] The second heat dissipation structure 100 is disposed at least on both sides of the first core 20 and embedded in the substrate 11 dielectric. The large amount of heat generated when the first core 20 is working can be laterally expanded through the second heat dissipation structure 100 on both sides, increasing the effective heat dissipation area and reducing thermal resistance.

[0061] In some embodiments, the packaging structure includes a first heat dissipation structure 90 and a second heat dissipation structure 100.

[0062] The first heat dissipation structure 90 covers the outer periphery of the first auxiliary core 30 and the second auxiliary core 40, and is responsible for laterally dissipating the heat generated by the upper and lower auxiliary cores; the second heat dissipation structure 100 is embedded inside the substrate 11 and is arranged at least on both sides of the first core 20 to dissipate heat from the embedded core. Together, they constitute a low thermal resistance heat dissipation structure from the inside of the core to the periphery of the package.

[0063] In some embodiments, refer to Figure 3 As shown, the packaging structure also includes a filling layer 110 located between the first core 20 and the substrate 11, with the filling layer 110 surrounding the outer periphery of the first core 20.

[0064] A filler layer 110 is also provided between the first core particle 20 and the substrate 11. The filler layer 110 is distributed around the outer periphery of the first core particle 20, filling the gap between the sidewall of the first core particle 20 and the cavity sidewall of the substrate 11. The main function of the filler layer 110 is to fix and hold the first core particle 20 inside the substrate 11. At the same time, through material selection and process control, the first surface and the second surface of the first core particle 20 are kept flush with the first surface and the second surface of the substrate 11, respectively, thereby forming a continuous and flat splicing plane on both sides of the substrate 11.

[0065] The filler layer 110 provides a flat, step-free base plane for the subsequent double-sided hybrid bonding of the first auxiliary core 30 and the second auxiliary core 40. The bonding interface is free from voids or stress concentrations caused by the height difference between the first core 20 and the substrate 11, ensuring the yield and reliability of high-density hybrid bonding. Secondly, the filler layer 110 can be made of a material with a coefficient of thermal expansion matching that of the substrate 11 and the first core 20, absorbing and buffering the thermal mismatch stress between the core and the substrate 11 during temperature cycling, preventing interface cracking or bonding failure. The filler layer 110 can also act as a heat conduction medium, laterally transferring heat generated on the sidewalls of the first core 20 to the substrate 11 and the second heat dissipation structure 100, collaboratively forming the aforementioned hierarchical heat dissipation network. Finally, the filler layer 110's coating of the first core 20 provides physical protection and electrical isolation. The filler layer 110 may include a high thermal conductivity insulating material, including but not limited to an insulating substrate and heat dissipation particles doped within the insulating substrate.

[0066] In some embodiments, the substrate 11 is a PCB substrate 11, and the first chip 20 is integrated directly on the PCB substrate 11 without the need for soldering to the PCB.

[0067] In some embodiments, the side of the first auxiliary core 30 or the second auxiliary core 40 facing away from the first core 20 is provided with a contact 130 or a pad for soldering to the PCB.

[0068] In some embodiments, refer to Figure 12As shown, a dielectric layer 120 is provided at the top and bottom of the substrate 11, making the substrate 11 flush with the first auxiliary core 30 and the second auxiliary core 40. A conductive structure is provided within the dielectric layer 120 and connected to the substrate 11. One side of the dielectric layer 120 has a contact 130. When the package structure is soldered to the PCB, the contact 130 on the dielectric layer is soldered to the PCB. The dielectric layer 120 can serve as a heat conduction medium and may include an insulating material with high thermal conductivity.

[0069] According to some aspects of the embodiments of this application, Figure 13 Provide an encapsulation method, including: A substrate is provided, and a first groove 101 is formed by etching the substrate. The first groove 101 penetrates the substrate along the thickness direction. A first core is provided and disposed within the first groove 101; The first auxiliary core particle is hybrid bonded to the first surface of the substrate and the first surface of the first core particle. The first auxiliary core particle covers the first surface of the first core particle and a portion of the first surface of the substrate. The first auxiliary core particle is coupled to the first surface of the substrate and the first surface of the first core particle through a hybrid bonding structure. The second auxiliary core is mixed and bonded to the second surface of the substrate and the second surface of the first core. The second auxiliary core covers the second surface of the first core and the second surface of the substrate. The second auxiliary core is coupled to the second surface of the substrate and the second surface of the first core through a bonding structure.

[0070] Reference Figure 14 As shown, a first groove 101 extending through the thickness direction is first formed on the substrate 11. Other grooves described later can be etched in the same manner as the first groove 101, with only the location differing. (Refer to...) Figure 3 As shown, the first chip 20 is then embedded in the first groove 101. Subsequently, the first auxiliary chip 30 and the second auxiliary chip 40 are hybrid-bonded on the upper and lower sides of the substrate 11, respectively, to finally construct a double-sided embedded package structure with electrical signal leads. The first auxiliary chip 30 is bonded and coupled to a portion of the first surface of the substrate 11 and the first surface of the first chip 20 through the hybrid bonding structure, and covers the first surface of the first chip 20 and a portion of the first surface of the substrate 11. The second auxiliary chip 40 is bonded and coupled to a portion of the second surface of the substrate 11 and the second surface of the first chip 20 through the bonding structure, and covers the second surface of the first chip 20 and a portion of the second surface of the substrate 11.

[0071] Reference Figure 3As shown, the through-groove 101 in the substrate 11 provides an embedding space for the first chip 20. After the first chip 20 is embedded inside the substrate 11, its first and second surfaces form a continuous splicing plane that can be bonded to both sides of the substrate 11. Subsequently, the first auxiliary chip 30 and the second auxiliary chip 40 are bonded to this splicing plane using a hybrid bonding process. This allows the input / output signals and power channels of the first chip 20 to be directly led out from both sides via the auxiliary chips without the need for through-silicon vias or edge bumps, thus shortening the interconnection path. In addition, the double-sided auxiliary chips can be designed with passive redistribution to achieve high-density interface redistribution, or with active design to integrate protocol interface IP, power distribution network, or buffer.

[0072] In some embodiments, refer to Figure 14 As shown, before etching the substrate 11, the substrate 11 is patterned under 4x illumination. Detection patterns, test circuits, etc., can be placed in the subsequent slotted area for subsequent testing and alignment. The embedded substrate 11 structure is compatible with existing interposer fabrication processes and can integrate more fabrication auxiliary patterns in the slotted area for alignment and testing, improving production line yield and efficiency.

[0073] In some embodiments, the mixed bonding of the first auxiliary core 30 with the first surface of the substrate 11 and the first surface of the first core 20 includes: forming a plurality of first bonding contacts 31 on the first surface of the first auxiliary core 30, wherein the first bonding contacts 31 include first type contacts 311 and second type contacts 312, and the first type contacts 311 are spaced apart around the plurality of second type contacts 312; forming a plurality of second bonding contacts 111 on the first surface of the substrate 11; forming a plurality of third bonding contacts 21 on the first surface of the first core 20; bonding the first type contacts 311 and the second bonding contacts 111, and bonding the second type contacts 312 and the third bonding contacts 21.

[0074] Reference Figure 3 As shown, a plurality of first bonding contacts 31 are formed on the first surface of the first auxiliary core 30. These contacts are divided into first type contacts 311 and second type contacts 312 with different functions. The first type contacts 311 are arranged in the peripheral area, surrounding the second type contacts 312 located in the central area, and the first bonding contacts 31 are spaced apart. A plurality of second bonding contacts 111 are formed on the first surface of the substrate 11, and a plurality of third bonding contacts 21 are formed on the first surface of the first core 20. Subsequently, through a hybrid bonding process, the first type contacts 311 on the first auxiliary core 30 are aligned and bonded one by one with the second bonding contacts 111 on the substrate 11, and the second type contacts 312 are aligned and bonded one by one with the third bonding contacts 21 on the first core 20. The first auxiliary core 30 can simultaneously complete the connection with the substrate 11 and the first core 20 with a single, continuous bonding interface.

[0075] The input / output signals and power channels of the first core 20 directly enter the first auxiliary core 30, while the redistribution network, power distribution network, or external signals inside the substrate 11 are synchronously connected to the same auxiliary core. This interconnection structure makes the first auxiliary core 30 an interconnect hub integrating convergence, conversion, and redistribution functions, eliminating the need for bumps on the core edge and enabling high-density bidirectional signal output. The same contact partitioning and bonding method can also be symmetrically applied to the bonding of the second auxiliary core 40 on the second surface, thereby forming a symmetrical double-sided signal output architecture in the package thickness direction.

[0076] In some embodiments, providing a first chip 20 includes: sequentially bonding a plurality of first sub-chips 22, with adjacent first sub-chips 22 coupled by a hybrid bonding structure; the first sub-chip 22 includes: a first semiconductor layer 221; a first device structure 222, at least partially located on the first semiconductor layer 221; and a first connection structure 223, at least penetrating the first semiconductor layer 221 and coupled to the first device structure 222.

[0077] Reference Figure 6 As shown, the first core 20 is further formed by stacking and bonding multiple first sub-cores 22 sequentially in the thickness direction. Adjacent first sub-cores 22 are coupled face-to-face through a hybrid bonding structure. The multiple first sub-cores 22 can respectively carry computing logic, cache, memory array or specific acceleration unit, and achieve low-latency, high-bandwidth data transmission between cores by means of the short-pitch interconnection provided by hybrid bonding.

[0078] The first sub-core 22 includes a first semiconductor layer 221, which may be a substrate of the first sub-core 22 or a semiconductor film epitaxially grown on the substrate. The first semiconductor layer 221 may include, but is not limited to, elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. For example, silicon, germanium, or silicon carbide. It may also include materials such as indium gallium zinc oxide (IGZO), where IGZO materials may be composed of oxides of elements such as indium, gallium, and zinc. The first device structure 222 may include, but is not limited to, transistors, memory devices, capacitors, inductors, resonant devices, radio frequency devices, and interconnect layers connected to the devices, as well as conductive plugs connecting the interconnect layers. The source and channel of the transistor may be located in the first semiconductor layer 221, and shallow trench isolation structures such as isolation between different transistors may be located in the first semiconductor layer 221. This application embodiment does not impose specific limitations on the electrical functions of the core, the physical structure of the internal devices, etc. Figure 5A first connection structure 223 is provided that penetrates the first semiconductor layer 221 along the z-direction. The first connection structure 223 may include, but is not limited to, conductive structures such as through-silicon vias (TSVs), conductive plugs, and conductive pillars. The first connection structure 223 is coupled to the first device structure 222.

[0079] In some embodiments, the packaging method further includes: etching a substrate 11 to form a second groove, the second groove penetrating the substrate 11 along the thickness direction; and providing a second core 50, wherein the second core 50 is disposed in the second groove.

[0080] Reference Figure 7 As shown, the substrate 11 is etched to form a second groove penetrating the substrate 11 along the thickness direction. This second groove is arranged horizontally at intervals from the first groove 101 that accommodates the first core 20. A second core 50 is provided and disposed in the second groove, such that its first and second surfaces in the thickness direction are substantially flush with the first and second surfaces of the substrate 11, respectively.

[0081] Two functional cores, a first core 20 and a second core 50, are embedded inside the substrate 11. They are arranged side by side in the horizontal direction, and their first and second surfaces together with the corresponding surfaces of the substrate 11 form a continuous splicing plane.

[0082] In some embodiments, the encapsulation method further includes: Figure 7 The first auxiliary core 30 is also mixed-bonded with the first surface of the second core 50; the second auxiliary core 40 is also mixed-bonded with the second surface of the second core 50.

[0083] Reference Figure 7 As shown, the first surface of the first auxiliary core 30 is simultaneously coupled to a portion of the first surface of the substrate 11, the first surface of the first core 20, and the first surface of the second core 50 through a hybrid bonding structure; correspondingly, the first surface of the second auxiliary core 40 is simultaneously coupled to a portion of the second surface of the substrate 11, the second surface of the first core 20, and the second surface of the second core 50 through a hybrid bonding structure.

[0084] The first auxiliary chip 30 and the second auxiliary chip 40 become a unified interconnect platform for the first chip 20 and the second chip 50, respectively, and no longer serve a single chip. The input / output signals and power channels of the first chip 20 and the second chip 50 are all converged within the same pair of auxiliary chips. Interconnection can be directly completed through the redistribution layer or active circuitry within the auxiliary chips, improving interconnection bandwidth and energy efficiency, and providing an efficient integration path for heterogeneous system-in-packages with multiple chips working collaboratively.

[0085] In some embodiments, the packaging method further includes: providing a third auxiliary core 60 and a fourth auxiliary core 70; mixing and bonding the third auxiliary core 60 with the first surface of the substrate 11 and the second core 50, wherein the third auxiliary core 60 covers the first surface of the second core 50 and a portion of the first surface of the substrate 11; mixing and bonding the fourth auxiliary core 70 with the second surface of the substrate 11 and the second surface of the second core 50, wherein the fourth auxiliary core 70 covers the second surface of the second core 50 and a portion of the second surface of the substrate 11.

[0086] Reference Figure 8 As shown, the third auxiliary core 60 is bonded and coupled to a portion of the first surface of the substrate 11 and the first surface of the second core 50 through a hybrid bonding structure, and the third auxiliary core 60 covers the first surface of the second core 50 and a portion of the first surface of the substrate 11; at the same time, the first surface of the fourth auxiliary core 70 is bonded and coupled to a portion of the second surface of the substrate 11 and the second surface of the second core 50 through a hybrid bonding structure, and the fourth auxiliary core 70 covers the second surface of the second core 50 and a portion of the second surface of the substrate 11.

[0087] The first core 20 has a first auxiliary core 30 and a second auxiliary core 40 as its upper and lower interconnect platforms, while the second core 50 independently has a third auxiliary core 60 and a fourth auxiliary core 70 as its upper and lower interconnect platforms. Each of the two cores is equipped with a set of double-sided auxiliary core groups. The I / O electrical signal output paths of the two cores are physically separated within the package and do not interfere with each other. The area, number of layers, and active / passive design of each auxiliary core can be independently optimized according to the specific needs of the corresponding core, realizing customized heterogeneous integration. At the same time, the interconnection between the two cores can be led out to the substrate 11 through their respective auxiliary cores, and then completed through the redistribution layer in the substrate 11 or PCB-level routing. This is suitable for multi-core systems with low interconnect bandwidth requirements but diverse functional combinations, effectively reducing the internal interconnection complexity and process cost of the package while ensuring integration density.

[0088] In some embodiments, the packaging method further includes: etching a substrate 11 to form a third groove, the third groove penetrating the substrate 11 along the thickness direction and located between the first groove 101 and the second groove; providing a fifth auxiliary core 80 and disposing the fifth auxiliary core 80 within the third groove; the first auxiliary core 30 is also mixed-bonded with the first surface of the fifth auxiliary core 80, the second auxiliary core 40 is also mixed-bonded with the second surface of the fifth auxiliary core 80; the third auxiliary core 60 is also mixed-bonded with the first surface of the fifth auxiliary core 80, and the fourth auxiliary core 70 is also mixed-bonded with the second surface of the fifth auxiliary core 80.

[0089] Reference Figure 9As shown, based on the first core 20 and the second core 50 already embedded in the substrate 11, a third groove is further etched to form between the first groove 101 and the second groove, and the third groove penetrates the substrate 11 along the thickness direction. A fifth auxiliary core 80 is disposed in the third groove, with its first surface and second surface flush with the first surface and second surface of the substrate 11, respectively. The first auxiliary core 30 and the third auxiliary core 60 cover and bond to a portion of the first surface of the fifth auxiliary core 80 from one side of the first surface, and the second auxiliary core 40 and the fourth auxiliary core 70 cover and bond to a portion of the second surface of the fifth auxiliary core 80 from one side of the second surface, respectively. The fifth auxiliary core 80 is contacted and penetrated by the four auxiliary cores above and below, forming an embedded interconnect channel connecting the first core 20 and the second core 50.

[0090] When ultra-high bandwidth interconnection is required between the first chip 20 and the second chip 50, signals can be directly transmitted through the fifth auxiliary chip 80 without bypassing the redistribution layer of the substrate 11 or relying on external bridging chips. The fifth auxiliary chip 80 can be designed as a passive high-density redistribution channel or integrate active routing or protocol conversion functions, achieving high-bandwidth, low-latency bidirectional communication within a shorter physical path. Simultaneously, by recessing the fifth auxiliary chip 80 into the third groove inside the substrate 11, the area resources of the upper and lower surface auxiliary chips are effectively freed up, allowing them to focus on electrical signal interconnection of more external interfaces and system-level integration of the PCB. This method provides a compact and scalable process path for high-bandwidth, multi-chip collaborative packaging.

[0091] In some embodiments, the packaging method further includes forming a first heat dissipation structure 90 covering the outer periphery of the first auxiliary core 30 and the second auxiliary core 40.

[0092] Reference Figure 10 As shown, this step involves depositing, filling, or bonding a high thermal conductivity material (such as a metal thermally conductive layer, thermally conductive adhesive, or micro heat pipe array) to the peripheral regions of the sidewalls of the first auxiliary core 30 and the second auxiliary core 40, so that the heat dissipation structure surrounds and closely contacts the unbonded portion of the substrate 11 of the two auxiliary cores along the thickness direction, and can further extend to form a continuous thermally conductive interface with the sidewall or edge region of the substrate 11.

[0093] The first auxiliary core 30 and the second auxiliary core 40 generate considerable heat. The peripheral heat dissipation structure provides a low thermal resistance heat conduction path for them. The heat does not need to rely solely on vertical dissipation through the core stack to the outside, but can be directly conducted to the periphery of the package via the sidewall, effectively preventing heat from accumulating at the interface between the auxiliary core and the substrate 11 and the core stack.

[0094] In some embodiments, the packaging method further includes: etching the substrate 11 to form a fourth groove and a fifth groove, the fourth groove and the fifth groove being located on both sides of the first groove 101; and forming a second heat dissipation structure 100 in the fourth groove and the fifth groove.

[0095] Reference Figure 11 As shown, the substrate 11 is etched to form a fourth groove and a fifth groove on both sides of the first groove 101. These two grooves can partially or completely penetrate the substrate 11 along the thickness direction. The fourth and fifth grooves are filled or deposited with a high thermal conductivity material, such as metallic copper, thermally conductive adhesive, micro heat pipe array, or phase change heat dissipation medium, to form a second heat dissipation structure 100.

[0096] The fourth and fifth grooves are located on both sides of the first core 20. The large amount of heat generated during the operation of the first core 20 can be conducted vertically through the auxiliary cores on the upper and lower surfaces, and can also be extended laterally through the second heat dissipation structure 100 on both sides and conducted to the edge of the substrate 11, thereby increasing the effective heat dissipation area.

[0097] The first heat dissipation structure 90 covers the outer periphery of the first auxiliary core 30 and the second auxiliary core 40, and is responsible for laterally dissipating the heat generated by the upper and lower auxiliary cores; the second heat dissipation structure 100 is embedded inside the substrate 11 and is arranged at least on both sides of the first core 20 to dissipate heat from the embedded core. Together, they constitute a low thermal resistance heat dissipation structure from the inside of the core to the periphery of the package.

[0098] In some embodiments, disposing the first core 20 in the first groove 101 includes: placing the first core 20 in the first groove 101 and filling the space between the first core 20 and the substrate 11 with dielectric material to form a filling layer 110.

[0099] Reference Figure 3 As shown, a first core 20 is placed within an etched first groove 101, and then a dielectric material is filled into the gap between the core sidewall and the groove sidewall to form a filling layer 110. This filling layer 110 is distributed around the outer periphery of the first core 20, filling the gap between the sidewall of the first core 20 and the cavity sidewall of the substrate 11. The main function of the filling layer 110 is to fix and hold the first core 20 inside the substrate 11, while through material selection and process control, ensuring that the first and second surfaces of the first core 20 are highly flush with the first and second surfaces of the substrate 11, respectively, thereby forming a continuous and flat splicing plane on both sides of the substrate 11. The dielectric material may include an insulating material with high thermal conductivity, and may include, but is not limited to, an insulating substrate and heat dissipation particles doped within the insulating substrate.

[0100] In some embodiments, the substrate 11 is a PCB substrate 11, and the first chip 20 is integrated directly on the PCB substrate 11 without the need for soldering to the PCB.

[0101] In some embodiments, a contact 130 is formed on the side of the first auxiliary core 30 or the second auxiliary core 40 facing away from the first core 20 for soldering to the PCB.

[0102] In some embodiments, refer to Figure 12 As shown, dielectric layers 120 are deposited on the top and bottom of substrate 11, making substrate 11 flush with the first auxiliary core 30 and the second auxiliary core 40. Conductive structures are provided within dielectric layers 120 to connect with substrate 11, and contacts 130 are formed on one side of dielectric layers 120. When the package structure is soldered to the PCB, the contacts 130 on dielectric layers 120 are soldered to the PCB. Dielectric layers 120 can serve as a heat conduction medium and may include insulating materials with high thermal conductivity.

[0103] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A packaging structure, characterized in that, include: A substrate having opposing first and second surfaces in the thickness direction; A first core particle, having opposing first and second surfaces in the thickness direction, is located in the substrate; The first auxiliary core particle is coupled to the first surface of the substrate and the first surface of the first core particle through a hybrid bonding structure. The second auxiliary core is coupled to the second surface of the substrate and the second surface of the first core through a hybrid bonding structure. The first auxiliary core particle covers a first surface of the first core particle and a portion of the first surface of the substrate; The second auxiliary core particle covers the second surface of the first core particle and a portion of the second surface of the substrate.

2. The packaging structure according to claim 1, characterized in that, The first surface of the first auxiliary core is provided with a plurality of first bonding contacts, the first surface of the substrate is provided with a plurality of second bonding contacts, and the first surface of the first core is provided with a plurality of third bonding contacts; The first bonding contact includes a first type of contact and a second type of contact, wherein the first type of contact is bonded to the second bonding contact, and the second type of contact is bonded to the third bonding contact; The first type of contact is distributed at intervals around a plurality of the second type of contact.

3. The packaging structure according to claim 1, characterized in that, The first core particle includes multiple first sub-core particles, which are bonded sequentially, and adjacent first sub-core particles are coupled by a hybrid bonding structure. The first sub-core includes: First semiconductor layer; A first device structure, at least partially located on the first semiconductor layer; The first connection structure extends at least through the first semiconductor layer and is coupled to the first device structure.

4. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: The second core located in the substrate has a first surface and a second surface opposite each other in the thickness direction.

5. The packaging structure according to claim 4, characterized in that, The first surface of the first auxiliary core is also coupled to the first surface of the second core through a hybrid bonding structure; The first surface of the second auxiliary core is also coupled to the second surface of the second core through a hybrid bonding structure.

6. The packaging structure according to claim 4, characterized in that, The packaging structure further includes: The third auxiliary core particle, the first surface of the third auxiliary core particle is coupled to the substrate and the first surface of the second core particle through a hybrid bonding structure; The fourth auxiliary core, the first surface of which is coupled to the substrate and the second surface of the second core through a hybrid bonding structure; The first surface of the third auxiliary core particle covers the first surface of the second core particle and covers a portion of the first surface of the substrate. The first surface of the fourth auxiliary core particle covers the second surface of the second core particle and a portion of the second surface of the substrate.

7. The packaging structure according to claim 6, characterized in that, The packaging structure further includes: A fifth auxiliary core located in the substrate, the fifth auxiliary core being situated between the first core and the second core; The first surface of the first auxiliary core particle and the first surface of the fifth auxiliary core particle are coupled by a hybrid bonding structure; The first surface of the second auxiliary core particle is coupled to the second surface of the fifth auxiliary core particle through a hybrid bonding structure; The first surface of the third auxiliary core particle is coupled to the first surface of the fifth auxiliary core particle through a hybrid bonding structure; The first surface of the fourth auxiliary core is coupled to the second surface of the fifth auxiliary core through a hybrid bonding structure.

8. The packaging structure according to claim 1, characterized in that, The packaging structure also includes a first heat dissipation structure. The first heat dissipation structure covers the outer periphery of the first auxiliary core and the second auxiliary core.

9. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: A second heat dissipation structure is located in the substrate, and the second heat dissipation structure is located at least on both sides of the first core.

10. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: A filler layer is located between the first core and the substrate, and the filler layer surrounds the outer periphery of the first core.

11. A packaging method, characterized in that, include: A substrate is provided, and a first groove is formed by etching the substrate, the first groove penetrating the substrate along the thickness direction; A first core is provided, and the first core is disposed in the first groove; The first auxiliary core particle is hybrid bonded to the first surface of the substrate and the first surface of the first core particle. The first auxiliary core particle covers the first surface of the first core particle and a portion of the first surface of the substrate. The first auxiliary core particle is coupled to the first surface of the substrate and the first surface of the first core particle through a hybrid bonding structure. The second auxiliary core is hybrid-bonded to the second surface of the substrate and the second surface of the first core, the second auxiliary core covering the second surface of the first core and a portion of the second surface of the substrate, and the second auxiliary core is coupled to the second surface of the substrate and the second surface of the first core through a hybrid bonding structure.

12. The packaging method according to claim 11, characterized in that, The encapsulation method includes: A plurality of first bonding contacts are formed on the first surface of the first auxiliary core, wherein the first bonding contacts include a first type of contact and a second type of contact, and the first type of contact is distributed at intervals around the plurality of second type of contact; A plurality of second bonding contacts are formed on the first surface of the substrate; Multiple third bonding contacts are formed on the first surface of the first core particle; Bond the first type of contact and the second type of bonded contact, and bond the second type of contact and the third type of bonded contact.

13. The packaging method according to claim 11, characterized in that, Providing a first core particle includes: sequentially bonding a plurality of first sub-core particles, wherein adjacent first sub-core particles are coupled by a hybrid bonding structure; The first sub-core includes: First semiconductor layer; A first device structure, at least partially located on the first semiconductor layer; The first connection structure extends at least through the first semiconductor layer and is coupled to the first device structure.

14. The packaging method according to claim 11, characterized in that, The encapsulation method further includes: The substrate is etched to form a second groove, which penetrates the substrate along the thickness direction. A second core is provided and disposed within the second groove.

15. The packaging method according to claim 14, characterized in that, The encapsulation method further includes: The first auxiliary core particle is also mixed-bonded with the first surface of the second core particle; The second auxiliary core is also mixed-bonded with the second surface of the second core.

16. The packaging method according to claim 14, characterized in that, The encapsulation method further includes: The third auxiliary core is mixed and bonded to the substrate and the first surface of the second core, wherein the third auxiliary core covers the first surface of the second core and covers a portion of the first surface of the substrate; The fourth auxiliary core is mixed and bonded to the substrate and the second surface of the second core, wherein the fourth auxiliary core covers the second surface of the second core and a portion of the second surface of the substrate.

17. The packaging method according to claim 16, characterized in that, The encapsulation method further includes: The substrate is etched to form a third groove, which penetrates the substrate along the thickness direction and is located between the first groove and the second groove. The fifth auxiliary core is placed in the third groove; The first auxiliary core particle is also mixed-bonded with the first surface of the fifth auxiliary core particle, and the second auxiliary core particle is also mixed-bonded with the second surface of the fifth auxiliary core particle; The third auxiliary core particle is also mixed-bonded with the first surface of the fifth auxiliary core particle, and the fourth auxiliary core particle is also mixed-bonded with the second surface of the fifth auxiliary core particle.

18. The packaging method according to claim 11, characterized in that, The encapsulation method further includes: A first heat dissipation structure is formed to cover the outer periphery of the first auxiliary core and the second auxiliary core.

19. The packaging method according to claim 11, characterized in that, The encapsulation method further includes: The substrate is etched to form a fourth groove and a fifth groove, the fourth groove and the fifth groove being located on both sides of the first groove; A second heat dissipation structure is formed within the fourth and fifth grooves.

20. The packaging method according to claim 11, characterized in that, The step of placing the first core particle in the first groove includes: The first core is placed in the first groove, and a dielectric material is filled between the first core and the substrate to form a filler layer.

Images