3D packaging structure and method

Abstract

The application discloses a 3D packaging structure and method, which comprises a computing unit, the surface of the computing unit is provided with a redistribution layer one, the middle part of the surface of the redistribution layer one away from the computing unit is electrically connected with a storage unit, and a plurality of conductive columns are electrically connected on the same side of the redistribution layer one located outside the storage unit; the conductive column and the storage unit are packaged in a plastic package body, and the conductive column penetrates through the plastic package body in the length direction; the surface of the plastic package body away from the redistribution layer one is provided with a redistribution layer two, and the surface of the redistribution layer two is provided with tin balls; the redistribution mode of the computing unit, the interconnection mode between the storage unit and the computing unit and the external interconnection mode of packaging are redesigned, so that the storage unit and the computing unit can be directly interconnected at a short distance in the packaging, the transmission path is greatly shortened, the parasitic resistance, the parasitic capacitance and the parasitic inductance are effectively reduced, the high-speed signal transmission performance is improved, and meanwhile, the heat generated by the computing unit can be more efficiently dissipated to the outside of the packaging.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip packaging technology, and in particular to a 3D packaging structure and method. Background Technology

[0002] As electronic products develop towards miniaturization, high performance, and high integration, fan-out packaging and package stacking technologies are widely used in multi-chip system integration.

[0003] There is a 3D stacked fan-out package-on-package (FOPOP) structure, such as Figure 1 As shown, a typical structure includes an upper package structure, a lower package structure, a redistribution layer, a molding compound, a vertical interconnect structure, and external solder balls. The upper and lower packages are stacked in the thickness direction and interconnected via the interconnect structure shown in the figure to achieve electrical signal interconnection between them. In this existing structure, the upper memory chip 20 region can transmit electrical signals downwards through the wire bond line structure 30, substrate pads (SBT Pads) 40, and dynamic random access memory substrate (DRAM SBT) 50 shown in the figure. Subsequently, the electrical signals need to be further connected to the computing unit 70 through the molding compound vertical via (TMV) connection structure 60 and the redistribution layer 90 in the lower package, and finally connected to the external circuit board via solder balls 80.

[0004] Because the upper and lower layers are stacked vertically, electrical signals typically need to pass through multiple structural layers during transmission. Compared to planar packaging or close-pitch interconnects between chips, the electrical signal transmission path in this type of stacked packaging is longer, and there are more material interfaces and connection transition regions along the path. Especially in high-speed signal transmission scenarios, longer electrical connection paths can easily introduce larger parasitic resistance, parasitic inductance, and parasitic capacitance. Long-distance transmission can easily cause problems such as impedance discontinuities, signal reflection, increased transmission delay, and increased insertion loss. As chip operating frequencies increase, the number of input / output (I / O) pins increases, and the signal density within the package increases, these problems will be further exacerbated, thus affecting the communication speed between chips and the overall electrical performance of the package.

[0005] Furthermore, existing 3D stacked fan-out package-on-package (FOPOP) still suffers from insufficient heat dissipation. Because the upper and lower layers are stacked vertically, the heat generated by the lower computing units must pass through multiple layers of the package structure before it can be dissipated to the outside.

[0006] The thermal conductivity of the aforementioned dielectric and encapsulation materials is generally lower than that of metallic materials, resulting in higher internal thermal resistance. This is particularly true for structural areas located inside the package or far from external heat dissipation surfaces, such as the computing unit 70 area in the figure and its surrounding encapsulation material. The heat generated in these areas is difficult to conduct to the outside of the package in a timely manner, easily leading to localized heat accumulation.

[0007] Therefore, although existing 3D stacked fan-out top-package (FOPOP) packaging can improve package integration and reduce package planar size by stacking top and bottom, it still has problems such as long electrical signal transmission paths, more interconnect nodes, larger parasitic parameters, poor high-speed signal integrity, limited heat dissipation paths, easy accumulation of internal heat, and decreased package reliability. It is difficult to meet the requirements of high-performance, high-speed and high-power chip systems for package electrical and thermal performance.

[0008] There is an urgent need for a 3D stacked fan-out package-on-package (FOPOP) structure that can shorten the signal transmission path and improve heat dissipation. Summary of the Invention

[0009] To address the aforementioned issues, this application provides a rationally structured 3D packaging structure and method, which significantly shortens the transmission path, effectively reduces parasitic resistance, capacitance, and inductance, and improves high-speed signal transmission performance. Simultaneously, the heat generated by the computing unit can be dissipated to the outside of the package more efficiently.

[0010] The technical solution adopted in this invention is as follows: A 3D packaging structure includes a computing unit, a redistribution layer one disposed on the surface of the computing unit, a storage unit electrically connected to the center of the redistribution layer one surface opposite to the computing unit, and a plurality of conductive pillars electrically connected to one side surface of the redistribution layer one located outside the storage unit; the conductive pillars and the storage unit are encapsulated in a plastic package, the conductive pillars penetrating the plastic package in the length direction; a second redistribution layer is disposed on the surface of the plastic package opposite to the first redistribution layer, and solder balls are disposed on the surface of the second redistribution layer.

[0011] As a further improvement to the above technical solution: The central region of the rewiring layer constitutes the interconnection area for computing and storage units located on both sides.

[0012] Vertical interconnect channels are formed in the plastic package located outside the memory cell via conductive pillars, directly connecting the computing cells on both sides to the solder balls.

[0013] The rewiring layer is laid on the active layer surface of the computing unit.

[0014] Multiple metal pads are provided on the surface of the redistribution layer away from the computing unit, and the storage unit is soldered to the multiple metal pads located in the middle of the redistribution layer via solder.

[0015] The redistribution layer located on the outside of the storage cell is electrically connected to the conductive pillars via metal pads.

[0016] The number of conductive posts on both sides of the memory cell is the same.

[0017] A plastic encapsulation is provided between the surface of the storage cell that is away from the first redistribution layer and the second redistribution layer to form a gap.

[0018] A packaging method for a 3D packaging structure as described above includes the following steps: A redistribution layer 1 is prepared on the surface of the computing unit, and metal pads are grown on the redistribution layer 1. Conductive pillars are grown on one surface of the redistribution layer corresponding to the outer metal pads. The memory cells are soldered to a metal pad located in the middle of a surface of the redistribution layer using solder. The molding compound is filled, and the conductive pillars and storage cells are encapsulated in the molding compound. The surface of the molding compound away from the redistribution layer is ground to expose the ends of the conductive pillars. A second redistribution layer is prepared on the surface of the encapsulation layer opposite to the first redistribution layer, and solder balls are grown on the surface of the second redistribution layer.

[0019] As a further improvement to the above technical solution: The redistribution layer is fabricated on the surface of the active layer of the computing unit; the storage unit is vertically interconnected with the computing unit.

[0020] Compared with the prior art, the present invention has the following beneficial effects: This invention redesigns the rewiring method of the computing unit, the interconnection method between the storage unit and the computing unit, and the external interconnection method of the package, enabling the storage unit and the computing unit to achieve short-distance direct interconnection inside the package. This greatly shortens the transmission path, effectively reduces parasitic resistance, parasitic capacitance and parasitic inductance, and improves high-speed signal transmission performance. At the same time, the heat generated by the computing unit can be dissipated to the outside of the package more efficiently. The present invention also includes the following advantages: A redistribution layer 1 is formed on the surface of the computing unit wafer, and conductive pillars serving as external interconnect pins are fanned out to the outer region of the package, so that the external interconnects and chip interconnects are separated from each other, reducing signal winding length and wiring complexity. Forming through-hole (TMV) conductive pillars in the outer region of the package creates vertical interconnect channels, making the connection path between the computing unit and the ball grid array (BGA) solder balls more direct, which helps to reduce interconnect impedance and improve power integrity. The reverse packaging structure exposes the silicon side of the computing unit or brings it close to the outer surface of the package, which facilitates the rapid conduction of heat outward, reduces the thermal resistance of the package, and improves heat dissipation performance. The computing unit is directly used as the packaging substrate during packaging, replacing the glass, silicon substrate and bonding and debonding complex processes in the traditional stacked fan-out packaging process, reducing production costs and improving product market competitiveness. Attached Figure Description

[0021] Figure 1 This is an existing 3D packaging structure.

[0022] Figure 2 This is a schematic diagram of the packaging structure of the present invention.

[0023] Figure 3 This is a schematic diagram of the redistribution layer 1 and metal pads fabricated on the computing unit according to the present invention.

[0024] Figure 4 This is a schematic diagram of the conductive pillars fabricated on the redistribution layer 1 according to the present invention.

[0025] Figure 5 This is a schematic diagram of the storage units arranged on the redistribution layer 1 according to the present invention.

[0026] Figure 6 This is a schematic diagram of the encapsulated body prepared according to the present invention.

[0027] Figure 7 This is a schematic diagram of the second redistribution layer after the present invention has been prepared.

[0028] Among them: 20, memory chip; 30, bonding wire circuit structure; 40, substrate pad; 50, dynamic random access memory substrate; 60, plastic-encapsulated vertical through-hole connection structure; 70, computing unit; 80, solder ball; 90, redistribution layer; 100, Computing unit; 200, Redistribution layer 1; 300, Metal pad; 400, Conductive pillar; 500, Storage unit; 600, Solder; 700, Molded enclosure; 800, Redistribution layer 2; 900, Solder ball. Detailed Implementation

[0029] The specific embodiments of the present invention will now be described with reference to the accompanying drawings.

[0030] like Figure 2As shown, a 3D packaging structure of this embodiment includes a computing unit 100. A redistribution layer 200 is disposed on the surface of the computing unit 100. A storage unit 500 is electrically connected to the center of the redistribution layer 200 away from the computing unit 100. A plurality of conductive pillars 400 are electrically connected to the same side of the redistribution layer 200 located outside the storage unit 500. The conductive pillars 400 and the storage unit 500 are encapsulated in a plastic package 700. The conductive pillars 400 penetrate the plastic package 700 in the length direction. A second redistribution layer 800 is disposed on the surface of the plastic package 700 away from the first redistribution layer 200. Solder balls 900 are disposed on the surface of the second redistribution layer 800.

[0031] In this embodiment, by redesigning the rewiring method of the computing unit 100, the interconnection method between the storage unit 500 and the computing unit 100, and the external interconnection method of the package, the storage unit 500 and the computing unit 100 can achieve short-distance direct interconnection inside the package.

[0032] In this embodiment, a reverse packaging structure is adopted, which exposes the silicon side of the computing unit 100 or brings it close to the outer surface of the package. This facilitates the rapid outward conduction of heat, reduces the thermal resistance of the package, and improves the heat dissipation performance.

[0033] In this embodiment, the computing unit 100 is directly used as the packaging substrate during packaging, replacing the glass, silicon substrate and complex bonding and debonding processes in the traditional stacked fan-out packaging process, thereby reducing production costs and improving product market competitiveness.

[0034] The central region of the redistribution layer 200 forms the interconnection area between the computing unit 100 and the storage unit 500 located on both sides, enabling the storage unit 500 and the computing unit 100 to be directly interconnected over a short distance, thereby reducing parasitic resistance, parasitic capacitance and parasitic inductance, and improving high-speed signal transmission performance.

[0035] A vertical interconnect channel is formed in the plastic package 700 located outside the storage cell 500 via conductive pillars 400, directly connecting the computing cells 100 on both sides to the solder balls 900.

[0036] In this embodiment, a redistribution layer 200 is formed on the wafer surface of the computing unit 100, and conductive pillars 400, which serve as external interconnect pins, are fanned out to the outer region of the package, thereby separating the external interconnect from the chip interconnect and reducing the signal winding length and wiring complexity.

[0037] In this embodiment, a through-hole (TMV) conductive pillar 400 vertical interconnect channel is formed in the outer region of the package, making the connection path between the computing unit 100 and the ball grid array (BGA) solder balls more direct, which helps to reduce interconnect impedance and improve power integrity.

[0038] The redistribution layer 200 is disposed on the active layer surface of the computing unit 100, which helps to realize short-distance direct connection between the computing unit 100 and the redistribution layer 200 and the storage unit 500.

[0039] Multiple metal pads 300 are provided on the surface of the redistribution layer 200 away from the computing unit 100. The storage unit 500 is soldered to the multiple metal pads 300 located in the middle of the redistribution layer 200 by solder 600, which effectively ensures a reliable and effective electrical connection.

[0040] The redistribution layer 200 located outside the storage cell 500 is electrically connected to the conductive post 400 via the metal pad 300, thereby realizing and ensuring direct chip interconnection between the computing unit 100 and the storage cell 500, and interconnection between the computing unit 100 and the outside world. While being connected at short distances, they are separated from each other, effectively reducing the winding length and reducing the wiring complexity.

[0041] The number of conductive posts 400 located on both sides of the storage cell 500 is the same.

[0042] A plastic encapsulation 700 is provided between the surface of the storage cell 500 facing away from the redistribution layer 200 and the redistribution layer 800 to form a gap.

[0043] This embodiment also proposes a packaging method for a 3D packaging structure, including the following steps: Step 1: As Figure 3 As shown, a redistribution layer 200 is prepared on the surface of the computing unit 100, and metal pads 300 are grown on the redistribution layer 200.

[0044] In this embodiment, the redistribution layer 200 is fabricated on the surface of the active layer of the computing unit 100.

[0045] In practice, plasma cleaning is required on the surface of the active layer of computing unit 100 to remove photoresist residue, organic contaminants and metal oxide layer to ensure interface adhesion. Low-temperature PVD deposition of silicon nitride passivation protective layer is used to cover the non-pad area around the active area, exposing only the chip's native I / O and power supply metal contacts.

[0046] In practice, organic dry film photoresist can be spin-coated onto the surface of the silicon oxide passivation layer, and ultraviolet exposure and development using a mask can be used to etch redistribution trenches, memory chip bonding windows, and TMV copper pillar substrate contact windows. The redistribution layer 200 pattern can be fabricated by combining magnetron sputtering deposition with electroplating of copper metal.

[0047] In the window area of ​​redistribution layer 200, metal pads 300 are grown using an electroless nickel-gold process.

[0048] Step 2: As Figure 4 As shown, conductive pillars 400 are grown on the surface of the redistribution layer 200 corresponding to the outer metal pads 300.

[0049] In practice, a dry film can be directly pressed onto the surface of the redistribution layer 200, and conductive pillars 400 can be grown through processes such as exposure, seed layer evaporation, and electroplating.

[0050] On the upper surface of the computing unit 100 wafer with the redistribution layer 200 already prepared, a thick photosensitive dry film insulating layer is vacuum hot-pressed to eliminate air bubbles between the dry film and the redistribution layer, ensuring insulation density. Using a laser direct exposure process, vertical through-holes are fabricated in the redistribution window area corresponding to the dry film layer, with the depth of the blind holes penetrating the dry film layer to the metal surface of the redistribution layer 200 below. Wet development is used to remove residual dry film inside the holes, and plasma roughening treatment is applied to the inner wall of the through-holes to improve metal adhesion. An electron beam evaporation seed layer is deposited on the inner wall of the through-holes, and the entire wafer is immersed in an acidic copper sulfate electroplating solution for constant current electroplating to grow conductive pillars 400.

[0051] In practice, chemical mechanical polishing can be used to lightly polish the top of the conductive post 400 to ensure that the top surface is flat and burr-free. The conductive post 400 serves as a vertical fan-out channel for the package, undertaking high current power supply and low-speed global signal transmission.

[0052] In this embodiment, the conductive post 400 can be a copper post.

[0053] Step 3: As Figure 5 As shown, the memory cell 500 is soldered to the metal pad 300 located in the middle of the surface of the redistribution layer 200 using solder 600.

[0054] In this embodiment, the storage unit 500 and the computing unit 100 are vertically interconnected.

[0055] In actual operation, microbumps can be formed by pre-placing solder 600 on the IO contact array on the lower surface of the storage unit 500; the solder 600 can be low-temperature lead-free tin-silver-copper solder, and the microbumps correspond one-to-one with the array of metal pads 300 of the computing unit 100.

[0056] In actual operation, the storage unit 500 is precisely aligned and pressed onto the metal pad 300 array of the computing unit 100. The bonding cavity is protected by a nitrogen atmosphere. The temperature is raised to the point where the solder 600 melts and wets the substrate. After cooling, the solder 600 solidifies to form vertical metal interconnect pillars, realizing micron-level high-density vertical electrical connection between computing and storage.

[0057] Step 4: As Figure 6 As shown, the molding compound is filled, and the conductive pillar 400 and the storage unit 500 are encapsulated in the molding compound 700. The surface of the molding compound 700 away from the redistribution layer 200 is ground to expose the end of the conductive pillar 400.

[0058] In practice, the entire computing wafer with completed storage bonding and copper pillar preparation is placed into a compression molding die and injected with epoxy molding compound. Using the C-Molding compression molding process, the molding compound flows uniformly under pressure, completely covering the entire structure of computing unit 100, storage unit 500, redistribution layer 200, solder 600, and conductive pillar 400, forming the molding compound 700.

[0059] After encapsulating material 700 is applied, the upper surface of the encapsulant is mechanically ground to fully expose the top metal arc end face of the conductive post 400, ensuring reliable conduction between the conductive post 400 and the subsequent rewiring layer 800. After grinding, the surface grinding debris is cleaned with plasma to avoid insulation short circuit.

[0060] Step 5: As Figure 7 As shown, a second redistribution layer 800 is prepared on the surface of the encapsulant 700 opposite to the first redistribution layer 200, and solder balls 900 are grown on the surface of the second redistribution layer 800.

[0061] In practice, a redistribution layer 800 is prepared on the surface of the molding compound 700 by combining magnetron sputtering deposition with electroplating of copper metal. The surface of the redistribution layer 800 is covered with a top PI passivation protective layer, and the bottom solder ball pad window array is etched by photolithography. The window area corresponds to the subsequent growth position of the external solder balls 900.

[0062] This invention enables direct short-distance interconnection between the storage unit and the computing unit within the package, greatly shortening the transmission path, effectively reducing parasitic resistance, parasitic capacitance and parasitic inductance, and improving high-speed signal transmission performance. At the same time, the heat generated by the computing unit can be dissipated to the outside of the package more efficiently.

[0063] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0064] The above description is an explanation of the present invention and not a limitation thereof. The scope of the present invention is defined by the claims. Within the scope of protection of the present invention, any form of modification may be made.

Claims

1. A 3D packaging structure, characterized in that: The device includes a computing unit (100), a redistribution layer 1 (200) is provided on the surface of the computing unit (100), a storage unit (500) is electrically connected to the middle of the redistribution layer 1 (200) away from the computing unit (100), and a plurality of conductive pillars (400) are electrically connected to the same side of the redistribution layer 1 (200) located outside the storage unit (500); the conductive pillars (400) and the storage unit (500) are encapsulated in a plastic package (700), and the conductive pillars (400) penetrate the plastic package (700) in the length direction; a redistribution layer 2 (800) is provided on the surface of the plastic package (700) away from the redistribution layer 1 (200), and solder balls (900) are provided on the surface of the redistribution layer 2 (800).

2. The 3D packaging structure as described in claim 1, characterized in that: The central region of the rewiring layer 1 (200) constitutes the interconnection area of ​​the computing unit (100) and storage unit (500) located on both sides.

3. The 3D packaging structure as described in claim 1, characterized in that: A vertical interconnect channel is formed in the plastic package (700) located outside the storage cell (500) via conductive pillars (400), directly connecting the computing cells (100) on both sides to the solder balls (900).

4. The 3D packaging structure as described in claim 1, characterized in that: The redistribution layer 1 (200) is disposed on the active layer surface of the computing unit (100).

5. A 3D packaging structure as described in claim 1, characterized in that: Multiple metal pads (300) are provided on the surface of the redistribution layer 1 (200) away from the computing unit (100), and the storage unit (500) is soldered to the multiple metal pads (300) located in the middle of the redistribution layer 1 (200) by solder (600).

6. A 3D packaging structure as described in claim 5, characterized in that: The redistribution layer 1 (200) located outside the storage cell (500) is electrically connected to the conductive post (400) via a metal pad (300).

7. A 3D packaging structure as described in claim 1, characterized in that: The number of conductive posts (400) on both sides of the storage cell (500) is the same.

8. A 3D packaging structure as described in claim 1, characterized in that: A plastic encapsulation (700) is provided between the surface of the storage cell (500) facing away from the redistribution layer 1 (200) and the redistribution layer 2 (800) to form a gap.

9. A packaging method for a 3D packaging structure according to any one of claims 1-8, characterized in that: Includes the following steps: A redistribution layer 1 (200) is prepared on the surface of the computing unit (100), and metal pads (300) are grown on the redistribution layer 1 (200). Conductive pillars (400) are grown on the surface of redistribution layer 1 (200) corresponding to the outer metal pads (300). The memory cell (500) is soldered to the metal pad (300) located in the middle of the surface of the redistribution layer (200) using solder (600); The molding compound is filled, and the conductive pillar (400) and the memory cell (500) are encapsulated in the molding compound (700). The surface of the molding compound (700) away from the redistribution layer (200) is ground to expose the end of the conductive pillar (400). A second redistribution layer (800) is prepared on the surface of a molding compound (700) facing away from the first redistribution layer (200), and solder balls (900) are grown on the surface of the second redistribution layer (800).

10. A 3D packaging method as described in claim 9, characterized in that: The redistribution layer 1 (200) is fabricated on the active layer surface of the computing unit (100); the storage unit (500) is vertically interconnected with the computing unit (100).

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