A chip package structure using wire bonding and a manufacturing method thereof

Abstract

The application relates to a chip packaging structure and a manufacturing method adopting wire bonding, the chip packaging structure comprising a substrate and at least one stacked chip group, the top of the substrate being provided with at least one first bonding pad; one stacked chip group is arranged on the substrate, the stacked chip group comprising a plurality of chips, and each chip being provided with a second bonding pad; wherein the plurality of chips of one stacked chip group are arranged in sequence, the second bonding pad of one chip in one stacked chip group being bonded with the second bonding pad of one adjacent chip below through a wire, and the second bonding pad of the lowermost chip in one stacked chip group being bonded with the first bonding pad through a wire. The chip packaging structure adopting wire bonding replaces a TSV structure, effectively reduces the process difficulty and design cycle of products, and the effect is obvious especially in the mass production of middle and low-end chips, the cost of the product can be reduced, and the yield can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and manufacturing method using wire bonding. Background Technology

[0002] Currently, most 2.5D and 3D chip stacking in the industry adopts TSV structure chips. TSV stands for "Through Silicon Via," which means "through silicon via." It is achieved by etching vertical channels on the chip, which can penetrate the chip vertically to realize electrical connection between different chips or different layers of the chip. Most existing 3D stacked chips use a TSV structure to achieve vertical interconnection between chips. This requires deep silicon etching, insulating layer deposition, barrier layer, electroplated copper filling, CMP planarization, and back-side thinning, making the manufacturing process complex and resulting in unresolved issues of high cost and low yield. The TSV structure has obvious defects: complex process, expensive equipment, low yield (high risk of voids / cracks) and high cost, making it unsuitable for mass production of low-end and mid-range chips; concentrated thermal stress and high reliability risk; requires additional TSV pads and metal layers, resulting in a long design cycle; 3D stacking of multiple chips requires the use of solder balls or copper pillars to connect the chips, resulting in excessive overall thickness.

[0003] Therefore, we propose a chip packaging structure and manufacturing method using wire bonding. Summary of the Invention

[0004] To address the shortcomings of existing manufacturing technologies, the applicant provides a chip packaging structure and manufacturing method using wire bonding. This replaces the TSV structure with a wire-bonded chip packaging structure, effectively reducing the product's process difficulty and design cycle. The effect is particularly noticeable in the mass production of low- to mid-range chips, which can reduce production costs and improve yield.

[0005] The technical solution adopted in this application is as follows: This application discloses a chip packaging structure using wire bonding, comprising: A substrate having at least one first pad on its top; At least one stacked chipset is disposed on a substrate, the stacked chipset includes multiple chips, each chip having a second pad; In this stacked chipset, multiple chips are stacked sequentially. The second pad of one chip in the stacked chipset is bonded to the second pad of the adjacent chip below it via a lead wire. The second pad of the bottommost chip in the stacked chipset is bonded to the first pad via a lead wire.

[0006] Its further features are: The bottom chip is connected to the substrate via a connection layer, and adjacent chips are connected to each other via a connection layer.

[0007] The connecting layer is made of insulating adhesive.

[0008] The connecting layer is made of DAF die bond material.

[0009] There are two stacked chipsets, one stacked on top of the other, with the lower stacked chipset mounted on the substrate. The two stacked chipsets are stacked in opposite directions.

[0010] In the lower stacked chipset, the second pad of one chip is bonded to the second pad of the adjacent chip below it via a wire, and the second pad of the bottommost chip in the lower stacked chipset is bonded to the first pad via a wire; in the upper stacked chipset, the second pad of one chip is bonded to the second pad of the adjacent chip below it via a wire, and the second pad of the bottommost chip in the upper stacked chipset is bonded to the first pad via a wire.

[0011] There are three stacked chipsets, which are stacked sequentially. The bottom stacked chipets are placed on the substrate and have the opposite stacking direction to the middle stacked chipets. The bottom stacked chipets have the same stacking direction as the top stacked chipets.

[0012] In the lower stacked chipset, the second pad of one chip is bonded to the second pad of the adjacent chip below it via a wire, and the second pad of the bottommost chip in the lower stacked chipset is bonded to the first pad via a wire. In the upper stacked chipset, the second pad of one chip is bonded to the second pad of the adjacent chip below it via a wire, and the second pad of the bottommost chip in the upper stacked chipset is bonded to the first pad via a wire. In the middle stacked chipset, the second pad of one chip is bonded to the second pad of the adjacent chip below it via a wire, and the second pad of the bottommost chip in the middle stacked chipset is bonded to the first pad via a wire.

[0013] The chip does not have a TSV structure.

[0014] This application also discloses a method for manufacturing a chip package structure using wire bonding, comprising the following steps: Assemble at least one stacked chipset, and stack multiple chips in a stacked chipset sequentially. The second pad of one chip in the stacked chipset is bonded to the second pad of the adjacent chip below it via a lead wire. Multiple stacked chipsets are stacked sequentially, with the bottom chip in one stacked chipset connected to the top chip in the adjacent stacked chipset below it. The bottommost chip in the stacked chipset is connected to the substrate; The second pad of the bottommost chip in each stacked chipset is bonded to the first pad via a wire.

[0015] The beneficial effects of this application are as follows: This application features a compact and rational structure, convenient operation, and uses a wire-bonded chip packaging structure to replace the TSV chip structure. This simplifies the process, eliminating TSV structure processing steps including etching, insulation, filling, CMP, and thinning, reducing processing steps by 40% and significantly shortening the production cycle. Costs are reduced by eliminating TSV structure process equipment and materials, lowering the manufacturing cost per chip. Yield is improved by avoiding abnormalities such as deep vias, cracks, and leakage caused by TSV structures. It offers strong compatibility, using wire bonding equipment without requiring additional production lines. Reliability is enhanced by eliminating thermal stress concentration in TSV structures and improving high and low temperature cycle reliability. While ensuring the interconnect performance of stacked chips, it simplifies the process flow, reduces costs, and improves product yield. Attached Figure Description

[0016] Figure 1 A schematic diagram of a stacked chipset for this application.

[0017] Figure 2 A schematic diagram showing two stacked chipsets for this application.

[0018] Figure 3 A schematic diagram showing the arrangement of three stacked chipsets for this application.

[0019] Wherein: 100, substrate; 200, stacked chipset; 300, interconnect layer; 400, lead wire; 101. First pad; 201, Chip; 202, Second Pad. Detailed Implementation

[0020] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0021] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0022] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0023] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0025] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0026] like Figures 1-3 As shown, a chip packaging structure employing wire bonding includes a substrate 100 and at least one stacked chipset 200.

[0027] At least one first pad 101 is provided on the top of the substrate 100.

[0028] A stacked chipset 200 is disposed on a substrate 100; the stacked chipset 200 includes a plurality of chips 201, each chip 201 having a second pad 202.

[0029] Multiple chips 201 in a stacked chipset 200 are stacked sequentially. The second pad 202 of one chip 201 in the stacked chipset 200 is bonded to the second pad 202 of the adjacent chip 201 below it via a lead wire 400. The second pad 202 of the bottommost chip 201 in the stacked chipset 200 is bonded to the first pad 101 via a lead wire 400.

[0030] The bottom chip 201 is connected to the substrate 100 through the connection layer 300, and adjacent chips 201 are connected through the connection layer 300.

[0031] Chip 201 does not have a TSV structure.

[0032] In other embodiments, the connecting layer 300 is made of insulating adhesive.

[0033] In other embodiments, the bonding layer 300 is made of DAF die bond material.

[0034] In other embodiments, such as Figure 2 As shown, there are two stacked chip groups 200, one stacked chip group 200 is disposed on the other stacked chip group 200, and the lower stacked chip group 200 is disposed on the substrate 100. The stacking directions of the two stacked chip groups 200 are opposite.

[0035] In the lower stacked chipset 200, the second pad 202 of one chip 201 is bonded to the second pad 202 of the adjacent chip 201 below it via a lead 400. The second pad 202 of the bottommost chip 201 in the lower stacked chipset 200 is bonded to the first pad 101 via a lead 400. In the upper stacked chipset 200, the second pad 202 of one chip 201 is bonded to the second pad 202 of the adjacent chip 201 below it via a lead 400. The second pad 202 of the bottommost chip 201 in the upper stacked chipset 200 is bonded to the first pad 101 via a lead 400.

[0036] In other embodiments, such as Figure 3 As shown, there are three stacked chip groups 200, which are stacked sequentially. The lower stacked chip group 200 is disposed on the substrate 100. The stacking direction of the lower stacked chip group 200 is opposite to that of the middle stacked chip group 200. The stacking direction of the lower stacked chip group 200 is the same as that of the upper stacked chip group 200.

[0037] In the lower stacked chipset 200, the second pad 202 of one chip 201 is bonded to the second pad 202 of the adjacent chip 201 below it via a lead 400. The second pad 202 of the bottommost chip 201 in the lower stacked chipset 200 is bonded to the first pad 101 via a lead 400. In the upper stacked chipset 200, the second pad 202 of one chip 201 is bonded to the second pad 202 of the adjacent chip 201 below it via a lead 400. The second pad 202 of the bottommost chip 201 in the upper stacked chipset 200 is bonded to the first pad 101 via a lead 400. In the middle stacked chipset 200, the second pad 202 of one chip 201 is bonded to the second pad 202 of the adjacent chip 201 below it via a lead 400. The second pad 202 of the bottommost chip 201 in the middle stacked chipset 200 is bonded to the first pad 101 via a lead 400.

[0038] A method for manufacturing a chip package structure using wire bonding includes the following steps: At least one stacked chipset 200 is assembled, and multiple chips 201 in the stacked chipset 200 are stacked sequentially. The second pad 202 of one chip 201 in the stacked chipset 200 is bonded to the second pad 202 of the adjacent chip 201 below it through a lead 400. Multiple stacked chipsets 200 are stacked sequentially, and the bottom chip 201 of a stacked chipset 200 is connected to the top chip 201 of the adjacent stacked chipset 200 below it. In the bottommost stacked chipset 200, the bottommost chip 201 is connected to the substrate 100. The second pad 202 of the bottommost chip 201 in each stacked chipset 200 is bonded to the first pad 101 via a lead 400.

[0039] Replacing the TSV chip structure with a wire-bonded chip packaging structure simplifies the process, eliminating TSV structure processing steps including etching, insulation, filling, CMP, and thinning, reducing processing steps by 40% and significantly shortening the production cycle; it reduces costs by eliminating TSV structure process equipment and materials, lowering the manufacturing cost per chip; it improves yield by avoiding abnormalities such as deep vias, cracks, and leakage caused by TSV structures; it offers strong compatibility, as wire bonding equipment is used, eliminating the need for additional production lines; and it improves reliability by eliminating thermal stress concentration in TSV structures and improving high and low temperature cycle reliability. While ensuring the interconnect performance of stacked chips, it simplifies the process flow, reduces costs, and improves product yield.

[0040] The above description is an explanation of this application and not a limitation thereof. The scope of this application is defined by the claims. Within the scope of protection of this application, any form of modification may be made.

Claims

1. A chip packaging structure employing wire bonding, characterized in that, include: A substrate (100) having at least one first pad (101) on its top. At least one stacked chipset (200) is disposed on a substrate (100). The stacked chipset (200) includes a plurality of chips (201), each chip (201) having a second pad (202). In this stacked chip group (200), multiple chips (201) are stacked sequentially. The second pad (202) of one chip (201) in the stacked chip group (200) is bonded to the second pad (202) of the adjacent chip (201) below it through a lead (400). The second pad (202) of the bottommost chip (201) in the stacked chip group (200) is bonded to the first pad (101) through a lead (400).

2. The chip packaging structure using wire bonding as described in claim 1, characterized in that: The bottom chip (201) is connected to the substrate (100) through the connection layer (300), and adjacent chips (201) are connected through the connection layer (300).

3. The chip packaging structure using wire bonding as described in claim 2, characterized in that: The connecting layer (300) is made of insulating adhesive.

4. A chip packaging structure employing wire bonding as described in claim 2, characterized in that: The connecting layer (300) is made of DAF die bond material.

5. A chip packaging structure employing wire bonding as described in claim 2, characterized in that: There are two stacked chip groups (200), one stacked chip group (200) is disposed on the other stacked chip group (200), and the lower stacked chip group (200) is disposed on the substrate (100). The stacking directions of the two stacked chip groups (200) are opposite.

6. A chip packaging structure employing wire bonding as described in claim 5, characterized in that: In the lower stacked chipset (200), the second pad (202) of one chip (201) is bonded to the second pad (202) of the adjacent chip (201) below it via a lead (400). The second pad (202) of the bottommost chip (201) in the lower stacked chipset (200) is bonded to the first pad (101) via a lead (400). In the upper stacked chipset (200), the second pad (202) of one chip (201) is bonded to the second pad (202) of the adjacent chip (201) below it via a lead (400). The second pad (202) of the bottommost chip (201) in the upper stacked chipset (200) is bonded to the first pad (101) via a lead (400).

7. A chip packaging structure employing wire bonding as described in claim 2, characterized in that: There are three stacked chipsets (200), which are stacked sequentially. The lower stacked chipet (200) is disposed on the substrate (100). The stacking direction of the lower stacked chipet (200) is opposite to that of the middle stacked chipet (200). The stacking direction of the lower stacked chipet (200) is the same as that of the upper stacked chipet (200).

8. A chip packaging structure employing wire bonding as described in claim 1, characterized in that: In the lower stacked chipset (200), the second pad (202) of one chip (201) is bonded to the second pad (202) of the adjacent chip (201) below it via a lead (400). The second pad (202) of the bottommost chip (201) in the lower stacked chipset (200) is bonded to the first pad (101) via a lead (400). In the upper stacked chipset (200), the second pad (202) of one chip (201) is bonded to the second pad (202) of the adjacent chip (201) below it via a lead (400). The second pad (202) of the bottommost chip (201) in the upper stacked chipset (200) is bonded to the first pad (101) via a lead (400). In the middle stacked chipset (200), the second pad (202) of one chip (201) is bonded to the second pad (202) of the adjacent chip (201) below it via a lead (400), and the second pad (202) of the bottommost chip (201) in the middle stacked chipset (200) is bonded to the first pad (101) via a lead (400).

9. A chip packaging structure employing wire bonding as described in claim 1, characterized in that: The chip (201) does not have a TSV structure.

10. A method for manufacturing a chip package structure using wire bonding, characterized in that, The steps include the following: Assemble at least one stacked chipset (200), and stack multiple chips (201) in a stacked chipset (200) sequentially. The second pad (202) of one chip (201) in the stacked chipset (200) is bonded to the second pad (202) of the adjacent chip (201) below it via a lead (400). Multiple stacked chipsets (200) are stacked sequentially, and the bottom chip (201) of a stacked chipset (200) is connected to the top chip (201) of the adjacent stacked chipset (200) below it; The bottommost chip (201) in the bottommost stacked chipset (200) is connected to the substrate (100); The second pad (202) of the bottommost chip (201) in each stacked chipset (200) is bonded to the first pad (101) via a lead (400).

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