Packaging structure and packaging method

Abstract

The application provides a packaging structure and a packaging method, and relates to the technical field of semiconductor packaging. The packaging structure comprises a first substrate, a second substrate, a first chip and a second chip. The second substrate is arranged in a stack with the first substrate and is electrically connected with the first substrate. The first chip is embedded in the first substrate. The first chip has a first active surface. The first active surface is arranged towards the second substrate. The first active surface has a first electrical connection area and a second electrical connection area. The first electrical connection area is electrically connected with the second substrate. The second chip is embedded in the second substrate. The second chip has a second active surface. The second active surface has a third electrical connection area and a fourth electrical connection area. The third electrical connection area is connected with the second electrical connection area through a hybrid bonding layer. The fourth electrical connection area is electrically connected with the second substrate. The application solves the problems of complex process, high cost and large packaging thickness caused by the dependence on silicon interposer and TSV in the related art, and realizes low-cost, low-profile and high-density stacked packaging without interposer and TSV.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging structure and packaging method. Background Technology

[0002] With the increasing demands for electronic system integration, signal transmission efficiency, and packaging height from fields such as mobile terminals, wearable devices, and high-performance computing, how to achieve high-density chip integration within a limited space has become an important issue in the semiconductor packaging field.

[0003] In related technologies, stacked packaging technology is typically used to package semiconductors. The upper and lower packages are stacked through peripheral solder balls, and signal redistribution and vertical interconnection are achieved by relying on silicon interposers and TSVs (Through-Silicon Vias).

[0004] However, this solution introduces silicon interposers and TSV processes, which leads to problems such as complex processes, high equipment requirements, yield loss, and stress warping. At the same time, the overall package thickness is difficult to reduce further. Summary of the Invention

[0005] This application provides a packaging structure and packaging method to solve the problems of complex processes, high costs and large packaging thickness caused by reliance on silicon interposers and TSVs in related technologies, and to achieve low-cost, low-profile, high-density stacked packaging without interposers and TSVs.

[0006] In a first aspect, embodiments of this application provide a packaging structure, including: a first substrate, a second substrate, a first chip, and a second chip. The second substrate is stacked and electrically connected to the first substrate. The first chip is embedded in the first substrate and has a first active surface facing the second substrate. The first active surface has a first electrical connection region and a second electrical connection region, and the first electrical connection region is electrically connected to the second substrate. The second chip is embedded in the second substrate and has a second active surface. The second active surface has a third electrical connection region and a fourth electrical connection region. The third electrical connection region is connected to the second electrical connection region through a hybrid bonding layer, and the fourth electrical connection region is electrically connected to the second substrate.

[0007] In one possible implementation, the first electrical connection region and the fourth electrical connection region are offset from each other; both the first electrical connection region and the fourth electrical connection region are provided with controllable collapse chip connection bumps; both the first electrical connection region and the fourth electrical connection region are electrically connected to the second substrate through corresponding controllable collapse chip connection bumps.

[0008] In one possible implementation, the controllable collapse chip connection bump on the first electrical connection region is located between the first electrical connection region and the second substrate.

[0009] In one possible implementation, a first interconnect solder ball is provided between the first substrate and the second substrate, and the first interconnect solder ball is electrically connected to the second substrate; a wire is provided inside the first substrate, one end of the wire is electrically connected to the controllable collapse chip connection bump on the fourth electrical connection area, and the other end is electrically connected to the first interconnect solder ball.

[0010] In one possible implementation, a second interconnecting ball is provided between the first substrate and the second substrate, with one side of the second interconnecting ball electrically connected to the first substrate and the other side of the second interconnecting ball electrically connected to the second substrate.

[0011] In one possible implementation, a first mating groove is provided on the side of the first substrate facing the second substrate, and the first chip is mated in the first mating groove; a second mating groove is provided on the side of the second substrate facing the first substrate, and the second chip is mated in the second mating groove.

[0012] In one possible implementation, the inner walls of the first and second fitting grooves are provided with a heat-conducting layer; and / or, the inner walls of the first and second fitting grooves are provided with an electromagnetic shielding layer.

[0013] In one possible implementation, a third chip is electrically connected to the side of the first substrate opposite to the second substrate.

[0014] In one possible implementation, the thickness of the hybrid bonding layer is 1 μm-10 μm.

[0015] Secondly, embodiments of this application also provide a packaging method based on the packaging structure in any of the above embodiments, comprising: S1, embedding a second chip on a second substrate such that the second active surface faces away from the second substrate; S2, inverting a first chip on the second chip, connecting the first chip and the second chip by hybrid bonding, and electrically connecting the first chip and the second substrate; S3, stacking the first substrate on the second substrate such that the first chip is embedded in the first substrate, and electrically connecting the first substrate and the second substrate; S4, electrically connecting the second chip and the second substrate.

[0016] The packaging structure and method provided in this application utilize a face-to-face staggered arrangement of a first chip and a second chip. The first electrical connection area of ​​the first chip is electrically connected to the second substrate, and the fourth electrical connection area of ​​the second chip is also electrically connected to the second substrate. Simultaneously, the second and third electrical connection areas are directly bonded through a hybrid bonding layer. This allows signal transmission between the first and second chips to pass only through the hybrid bonding layer, which has a thickness on the micrometer level. Within this thickness range, the signal transmission time reaches the picosecond level. In contrast, in traditional stacked packaging, signals between the upper and lower chips need to pass through multiple segments such as internal chip circuitry, substrate circuitry, and peripheral solder balls, resulting in a transmission distance on the millimeter level and a signal delay on the nanosecond level. Therefore, the signal delay in this embodiment is significantly reduced. Furthermore, since there is no need to set up a silicon interposer for signal redistribution, and there is no need to fabricate TSVs in the first or second chip for vertical interconnection, complex processes such as photolithography, etching, and electroplating in interposer fabrication, as well as deep silicon etching, insulating layer deposition, and copper filling processes in TSV fabrication, are avoided, thereby simplifying the process and reducing manufacturing costs. Furthermore, the structure in which the first chip is embedded in the first substrate and the second chip is embedded in the second substrate allows the space in the chip thickness direction to be accommodated by the substrate groove. The overall cross-sectional thickness of the package is determined by the substrate thickness and the interlayer gap height, and the chip thickness no longer adds to the overall height. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] Figure 1 A cross-sectional view of a packaging structure provided in an embodiment of this application;

[0019] Figure 2 A diagram showing the connection relationship between the first chip and the second chip in a packaging structure provided in an embodiment of this application;

[0020] Figure 3 A cross-sectional view of the first substrate of a packaging structure provided in an embodiment of this application;

[0021] Figure 4 A cross-sectional view of the second substrate of the packaging structure provided in an embodiment of this application;

[0022] Figure 5 A flowchart illustrating an embodiment of the encapsulation method provided in this application;

[0023] Figure 6 One of the structural diagrams of the packaging process of the packaging method provided in an embodiment of this application;

[0024] Figure 7This is a second structural diagram of the packaging structure provided in an embodiment of the present application during the packaging process;

[0025] Figure 8 The third structural diagram of the packaging structure provided in an embodiment of this application is shown in the packaging process.

[0026] Figure label:

[0027] 100: First substrate; 110: First fitting groove;

[0028] 200: Second substrate; 210: Second mating groove;

[0029] 300: First chip; 310: First active surface; 311: First electrical connection region; 312: Second electrical connection region;

[0030] 400: Second chip; 410: Second active surface; 411: Third electrical connection region; 412: Fourth electrical connection region;

[0031] 510: Hybrid bonding layer; 520: Controlled collapse chip connection bump; 530: Third interconnect solder ball;

[0032] 600: First interconnect solder ball;

[0033] 700: Wire;

[0034] 800: Second interconnect solder ball;

[0035] 900: The third chip. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0037] In existing packaging solutions, stacked packaging typically achieves electrical connection through solder balls between the upper and lower packages, and the chip is then connected to the substrate to complete the device-level stacking. Direct bonding-type three-dimensional stacking achieves a shorter transmission path through high-density connections between the active surfaces of the chip, but the output of related signals still often relies on additional vertical interconnect structures or intermediate carrier structures.

[0038] The aforementioned solutions rely on through-silicon vias (TSVs) or interposers to achieve signal extraction and interlayer connectivity, which increases manufacturing complexity, cost, and assembly / testing difficulty. Furthermore, they are not suitable for widespread application in low-profile, miniaturized packaging scenarios. Therefore, achieving high-density interconnects, short signal paths, and low structural complexity within a limited packaging space has become a pressing technical challenge in the field of 3D packaging.

[0039] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0040] Reference Figure 1 and Figure 2 The present application provides a packaging structure including: a first substrate 100, a second substrate 200, a first chip 300, and a second chip 400. The second substrate 200 is stacked with and electrically connected to the first substrate 100. The first chip 300 is embedded in the first substrate 100 and has a first active surface 310 facing the second substrate 200. The first active surface 310 has a first electrical connection region 311 and a second electrical connection region 312. The first electrical connection region 311 is electrically connected to the second substrate 200. The second chip 400 is embedded in the second substrate 200 and has a second active surface 410. The second active surface 410 has a third electrical connection region 411 and a fourth electrical connection region 412. The third electrical connection region 411 and the second electrical connection region 312 are connected by a hybrid bonding layer 510, and the fourth electrical connection region 412 is electrically connected to the second substrate 200.

[0041] Specifically, both the first substrate 100 and the second substrate 200 are organic substrates, with multiple layers of metal circuitry arranged inside. The metal circuitry layers are isolated by dielectric layers and interconnected through conductive vias. Both the first chip 300 and the second chip 400 are semiconductor dies. The first active surface 310 is the device surface of the first chip 300, and the second active surface 410 is the device surface of the second chip 400. The device surface is the top surface after the chip fabrication is completed, and it includes transistors, interconnect layers, and input / output pads.

[0042] The first electrical connection region 311, the second electrical connection region 312, the third electrical connection region 411, and the fourth electrical connection region 412 are all pad areas arranged on the active surface of the chip. The pad areas contain multiple metal pads arranged in an array. The material of the pads can be aluminum, copper, or a copper-nickel-gold stacked structure. The hybrid bonding layer 510 refers to the bonding interface achieved simultaneously through dielectric layer bonding and metal diffusion bonding. Its formation process includes surface activation treatment, plasma cleaning, room temperature pre-bonding, and high temperature annealing treatment. During the annealing process, copper atoms diffuse into each other to form metal connections, while covalent bonds are formed between dielectric layers, thereby achieving direct interconnection without solder or bumps.

[0043] Furthermore, the first substrate 100 and the second substrate 200 are stacked vertically, and are electrically connected through a conductive structure. The first substrate 100 serves as the upper packaging substrate, with its lower surface facing the second substrate 200. The first chip 300 is embedded on the lower surface of the first substrate 100, and its first active surface 310 faces the second substrate 200, i.e., the active surface is arranged downwards. The first active surface 310 is divided into two functional regions: a first electrical connection region 311 and a second electrical connection region 312. The first electrical connection region 311 is located in the non-overlapping area of ​​the first chip 300 and is used to achieve electrical connection with the second substrate 200; the second electrical connection region 312 is located in the overlapping area of ​​the first chip 300 and the second chip 400 and is used to achieve hybrid bonding connection with the second chip 400.

[0044] The second substrate 200 serves as the lower packaging substrate, with its upper surface facing the first substrate 100. The second chip 400 is embedded on the upper surface of the second substrate 200, with its second active surface 410 facing the first substrate 100, i.e., the active surface is arranged upwards, so that the second active surface 410 and the first active surface 310 are face-to-face. The second active surface 410 is divided into a third electrical connection region 411 and a fourth electrical connection region 412. The third electrical connection region 411 is located in the overlapping region and is directly bonded to the second electrical connection region 312 face-to-face through a hybrid bonding layer 510. The fourth electrical connection region 412 is located in the non-overlapping region of the second chip 400 and is electrically connected to the second substrate 200. By horizontally staggering the first chip 300 and the second chip 400, the first electrical connection region 311 and the fourth electrical connection region 412 are offset from each other in the horizontal projection direction, providing space for each to independently lead out signals.

[0045] The electrical signal transmission path of the package structure is as follows: Data signals requiring high-speed exchange between the first chip 300 and the second chip 400 are transmitted directly downwards from the second electrical connection area 312 to the hybrid bonding layer 510. After passing through the hybrid bonding layer 510, they directly enter the third electrical connection area 411, completing the signal transmission between the first chip 300 and the second chip 400. Signals requiring communication between the first chip 300 and the outside of the package are transmitted downwards from the first electrical connection area 311 of the first chip 300 to the second substrate 200, and then through the internal circuit layer of the second substrate 200 to the third interconnect solder ball 530 on the back of the second substrate 200. The third interconnect solder ball 530 is used to transmit signals to the printed circuit board outside the package. Signals requiring communication between the second chip 400 and the outside of the package are transmitted from the fourth electrical connection area 412 of the second chip 400 to the second substrate 200 via another set of circuits, and similarly through the internal circuit layer of the second substrate 200 to the third interconnect solder ball 530 on the back of the second substrate 200. The electrical connection between the first substrate 100 and the second substrate 200 is achieved directly through the circuit between them.

[0046] In this embodiment, the first chip 300 and the second chip 400 are arranged face-to-face with a staggered arrangement. The first electrical connection area 311 of the first chip 300 is electrically connected to the second substrate 200, and the fourth electrical connection area 412 of the second chip 400 is also electrically connected to the second substrate 200. At the same time, the second electrical connection area 312 and the third electrical connection area 411 are directly bonded through a hybrid bonding layer 510, so that the signal transmission between the first chip 300 and the second chip 400 only needs to pass through the hybrid bonding layer 510. The thickness of the hybrid bonding layer 510 is on the micrometer level, and the signal transmission time within this thickness range reaches the picosecond level. In contrast, in traditional stacked packaging, the signal between the upper chip and the lower chip needs to pass through multiple structures such as the chip's internal circuitry, substrate circuitry, and peripheral solder balls, with a transmission distance on the millimeter level and a signal delay on the nanosecond level. Therefore, the signal delay in this embodiment is significantly reduced.

[0047] Meanwhile, since there is no need to set up a silicon interposer for signal redistribution, and no need to fabricate TSVs in the first chip 300 or the second chip 400 for vertical interconnection, complex processes such as photolithography, etching, and electroplating in interposer fabrication, as well as deep silicon etching, insulating layer deposition, and copper filling in TSV fabrication are avoided, thereby simplifying the process and reducing manufacturing costs. In addition, the structure in which the first chip 300 is embedded in the first substrate 100 and the second chip 400 is embedded in the second substrate 200 allows the space in the chip thickness direction to be accommodated by the substrate groove. The overall cross-sectional thickness of the package is determined by the substrate thickness and the interlayer gap height, and the chip thickness no longer adds to the overall height.

[0048] Reference Figure 2In some embodiments of this application, the first electrical connection region 311 and the fourth electrical connection region 412 are staggered; both the first electrical connection region 311 and the fourth electrical connection region 412 are provided with controllable collapse chip connection bumps 520; both the first electrical connection region 311 and the fourth electrical connection region 412 are electrically connected to the second substrate 200 through the corresponding controllable collapse chip connection bumps 520.

[0049] Specifically, the misalignment of the first electrical connection area 311 and the fourth electrical connection area 412 means that, in the horizontal projection direction, the positions of the first electrical connection area 311 of the first chip 300 and the fourth electrical connection area 412 of the second chip 400 do not overlap, and their projections in the horizontal plane are separate. There are overlapping and non-overlapping areas between the first chip 300 and the second chip 400. The overlapping area is the part where the two chips coincide in the horizontal projection, and the non-overlapping area is the part where only a single chip exists in the horizontal projection. The first electrical connection area 311 is disposed on the active surface of the first chip 300 located in the non-overlapping area, and the fourth electrical connection area 412 is disposed on the active surface of the second chip 400 located in the non-overlapping area. Due to the misalignment of the two chips in the horizontal direction, the non-overlapping areas of the first chip 300 and the second chip 400 are located at different positions in the horizontal projection, thus naturally forming a misaligned relationship between the first electrical connection area 311 and the fourth electrical connection area 412.

[0050] The controllable collapse chip connection bump 520 is a solder bump fabricated on the active surface pad of the chip. Its fabrication process includes forming a solder layer on the chip pad through electroplating or printing, followed by reflow to spheroidize the solder and form a bump. The controllable collapse chip connection bump 520 on the first electrical connection region 311 is located between the first chip 300 and the second substrate 200. The upper end of the bump is connected to the pad of the first electrical connection region 311 of the first chip 300, and the lower end is connected to the first pad at the corresponding position on the upper surface of the second substrate 200. The controllable collapse chip connection bump 520 on the fourth electrical connection region 412 is located between the second chip 400 and the second substrate 200. The lower end of the bump is connected to the pad of the fourth electrical connection region 412 of the second chip 400, and the upper end is connected to the second pad at the corresponding position on the upper surface of the second substrate 200.

[0051] In this embodiment, the staggered arrangement of the first electrical connection area 311 and the fourth electrical connection area 412 ensures that the connection positions of the first chip 300 and the second substrate 200, and the second chip 400 and the second substrate 200, are horizontally separated. Since the first electrical connection area 311 is located in the non-overlapping area of ​​the first chip 300, and the fourth electrical connection area 412 is located in the non-overlapping area of ​​the second chip 400, the two areas are separated in horizontal projection. Therefore, the spaces above and below each area are independent, avoiding spatial interference between the two connections. During reflow soldering, the controllable collapse chip connection bump 520 will collapse and expand laterally. If the distance between the two electrical connection areas is too close, the collapsed solder may bridge each other, causing a short circuit. In this embodiment, the staggered arrangement of the first electrical connection area 311 and the fourth electrical connection area 412, with a horizontal distance greater than twice the lateral expansion size of the controllable collapse chip connection bump 520 after collapse, provides sufficient space for the arrangement of the bumps and reflow soldering, effectively preventing bridging and short circuit defects.

[0052] Meanwhile, the controllable collapse chip connection bump 520 on the first electrical connection area 311 is located between the first electrical connection area 311 and the second substrate 200, so that the signal of the first chip 300 can be directly transmitted downward to the second substrate 200 without having to go through the upper substrate and then detour downward, thus shortening the signal path length; the controllable collapse chip connection bump 520 on the fourth electrical connection area 412 also enables the signal of the second chip 400 to be directly connected to the second substrate 200, realizing the convergence and extraction of signals from the upper and lower chips on the same substrate, which is beneficial to simplifying the substrate wiring design.

[0053] Reference Figure 1 and Figure 2 In some embodiments of this application, the controllable collapse chip connection bump 520 on the first electrical connection region 311 is located between the first electrical connection region 311 and the second substrate 200.

[0054] Specifically, the controllable collapse chip connection bump 520 on the first electrical connection area 311 is located between the first electrical connection area 311 and the second substrate 200. This means that the upper and lower ends of the controllable collapse chip connection bump 520 are respectively connected to the pads on the upper surfaces of the first electrical connection area 311 and the second substrate 200 on the first active surface 310. Spatially, the first chip 300 is located on the lower surface of the first substrate 100, the first electrical connection area 311 is located on the lower surface of the first chip 300, and the second substrate 200 is located below the first substrate 100. Therefore, the controllable collapse chip connection bump 520 on the first electrical connection area 311 extends vertically into the gap between the first chip 300 and the second substrate 200. The height of this gap is determined by the diameters of the first interconnect solder ball 600 and the second interconnect solder ball 800, and the height of the controllable collapse chip connection bump 520 needs to match the height of this gap.

[0055] Furthermore, the connection between the controllable collapse chip connection bumps 520 on the first electrical connection area 311 and the upper surface of the second substrate 200 can be achieved by thermocompression welding or reflow soldering. When using thermocompression welding, after aligning the first chip 300 with the second substrate 200, pressure and heat are applied to the chip using a heating head, causing the controllable collapse chip connection bumps 520 to melt and form a metallurgical bond with the pads on the second substrate 200. When using reflow soldering, the assembled chip and substrate are placed in a reflow oven and heated according to the reflow temperature profile, causing all controllable collapse chip connection bumps 520 to melt simultaneously and connect with their corresponding pads.

[0056] In this embodiment, by placing the controllable collapse chip connection bump 520 on the first electrical connection area 311 between the first electrical connection area 311 and the second substrate 200, the first chip 300 is directly electrically connected downwards to the second substrate 200. Since the first chip 300 is embedded on the lower surface of the first substrate 100, with its first active surface 310 facing downwards and close to the upper surface of the second substrate 200, the controllable collapse chip connection bump 520 directly bridges this short gap to achieve connection. In this connection path, the signal originates from the pad of the first electrical connection area 311 of the first chip 300, passes through the solder body of the controllable collapse chip connection bump 520, and reaches the pad on the upper surface of the second substrate 200; the total transmission distance is the height of the bump.

[0057] If a path is adopted where the signal first connects upwards to the first substrate 100 and then downwards through interlayer solder balls, the signal needs to travel upwards from the first chip 300, through the connection structure between the first chip 300 and the first substrate 100 to reach the lower surface of the first substrate 100, then through the internal circuit layer of the first substrate 100, and then downwards through the first interconnect solder balls 600 to reach the second substrate 200. This path is much longer than the direct connection path length of the controllable collapse chip connection bump 520. Therefore, in this embodiment, the path length of the signal from the first chip 300 to the second substrate 200 is shortened compared to the traditional solution. The signal transmission delay is proportional to the path length, and the delay is reduced accordingly. At the same time, it avoids the additional parasitic capacitance and parasitic inductance introduced by the internal circuit layer of the first substrate 100.

[0058] Reference Figure 1 In some embodiments of this application, a first interconnect solder ball 600 is provided between the first substrate 100 and the second substrate 200, and the first interconnect solder ball 600 is electrically connected to the second substrate 200; a wire 700 is provided inside the first substrate 100, one end of the wire 700 is electrically connected to the controllable collapse chip connection bump 520 on the fourth electrical connection area 412, and the other end is electrically connected to the first interconnect solder ball 600.

[0059] Specifically, a first interconnect solder ball 600 is disposed between the first substrate 100 and the second substrate 200 to achieve electrical and mechanical connections between the first substrate 100 and the second substrate 200. The upper end of the first interconnect solder ball 600 is connected to a pad on the lower surface of the first substrate 100, and the lower end is connected to a pad on the upper surface of the second substrate 200. A conductor 700 is disposed inside the first substrate 100. The conductor 700 is a conductive trace formed in a metal circuit layer inside the first substrate 100, and its material is copper. One end of the conductor 700 is electrically connected to the controllable collapse chip connection bump 520 on the fourth electrical connection area 412 through a pad on the lower surface of the first substrate 100, and the other end of the conductor 700 is electrically connected to the first interconnect solder ball 600 through another pad on the lower surface of the first substrate 100.

[0060] Furthermore, the conductor 700 can be a multi-layer structure, meaning that different metal layers within the first substrate 100 are connected through conductive vias, thereby forming a complete conductive path from the connection point of the controllable collapse chip connection bump 520 on the fourth electrical connection region 412 to the connection point of the first interconnect solder ball 600. For example, when the connection position of the controllable collapse chip connection bump 520 on the fourth electrical connection region 412 and the projection position of the connection position of the first interconnect solder ball 600 on the lower surface of the first substrate 100 need to cross other wiring areas, the conductor 700 can rise from the starting pad on the lower surface of the first substrate 100 through the first conductive via to the first metal layer inside the first substrate 100, extend horizontally in the first metal layer to avoid obstacle areas, and then descend through the second conductive via to the target pad on the lower surface of the first substrate 100, thereby achieving circuitous wiring.

[0061] In this embodiment, by setting a wire 700 inside the first substrate 100, and electrically connecting one end of the wire 700 to the controllable collapse chip connection bump 520 on the fourth electrical connection area 412 and the other end to the first interconnect solder ball 600, the signal of the second chip 400 can be redistributed through the circuit layer inside the first substrate 100 and then transmitted to the second substrate 200 through the first interconnect solder ball 600.

[0062] Specifically, after the signal from the second chip 400 is emitted from the fourth electrical connection area 412, it enters the first substrate 100 upwards through the controllable collapsed chip connection bump 520. Since the conductors 700 inside the first substrate 100 can be arranged to any horizontal position as needed, the signal from the second chip 400 can be redistributed to any solder joint position on the lower surface of the first substrate 100, and then transmitted downwards to the corresponding position on the second substrate 200 through the first interconnect solder ball 600. This signal redistribution function makes the pad layout of the second substrate 200 no longer restricted by the position of the fourth electrical connection area 412 of the second chip 400. Even if the fourth electrical connection area 412 of the second chip 400 is located in the internal area of ​​the package, its signal can first enter the first substrate 100 upwards, be redistributed to the pads in the peripheral area through the conductors 700, and then return downwards to the second substrate 200, thereby realizing the connection with the pads in the peripheral area of ​​the second substrate 200. In traditional solutions, signal redistribution requires the addition of a silicon interposer. However, this embodiment achieves the same function using the wires 700 inside the first substrate 100 without the need for a silicon interposer, thus achieving flexibility in signal redistribution while avoiding the cost of an interposer.

[0063] Reference Figure 1 In some embodiments of this application, a second interconnect solder ball 800 is provided between the first substrate 100 and the second substrate 200. One side of the second interconnect solder ball 800 is electrically connected to the first substrate 100, and the other side of the second interconnect solder ball 800 is electrically connected to the second substrate 200.

[0064] Specifically, the second interconnect solder ball 800 is disposed between the first substrate 100 and the second substrate 200. The upper side of the second interconnect solder ball 800 is connected to the pad on the lower surface of the first substrate 100, and the lower side of the second interconnect solder ball 800 is connected to the pad on the upper surface of the second substrate 200, thereby realizing the electrical and mechanical connection between the first substrate 100 and the second substrate 200. Both the second interconnect solder ball 800 and the first interconnect solder ball 600 are disposed in the gap between the first substrate 100 and the second substrate 200, and together they form a stacked interlayer interconnect structure. However, the second interconnect solder ball 800 directly connects the first substrate 100 and the second substrate 200 without the transition through the wire 700 or the controllable collapse chip connection bump 520.

[0065] In this embodiment, the first substrate 100 and the second substrate 200 are directly connected by a second interconnect solder ball 800, providing the main structural support and electrical connection channel for the packaging structure. During thermal cycling, there is a difference in the coefficient of thermal expansion between the organic substrate materials of the first substrate 100 and the second substrate 200 and the silicon materials of the first chip 300 and the second chip 400. The coefficient of thermal expansion of the organic substrate is approximately 15ppm / ℃ to 20ppm / ℃, while that of silicon is approximately 3ppm / ℃. When the temperature changes, the expansion of the substrate is greater than that of the chip, thus generating thermal stress at the interface between the substrate and the chip.

[0066] The second interconnect solder balls 800 are arranged around the periphery of the chip mating area, forming a support ring surrounding the chip area. During thermal cycling, the solder material of the second interconnect solder balls 800 has plastic deformation capability, which can absorb part of the thermal stress through its own creep and stress relaxation. At the same time, multiple second interconnect solder balls 800 are evenly distributed in the peripheral area, dispersing the expansion deformation of the substrate to multiple solder joints to share the burden, avoiding stress concentration at individual solder joints. If only the bumps in the chip area are relied upon to bear the thermal stress, the bump diameter is small and the amount of solder is limited, resulting in weak creep resistance and easy fatigue cracks during thermal cycling. However, the second interconnect solder balls 800 have a larger diameter and larger solder volume, resulting in stronger creep resistance and effective resistance to thermal stress. Therefore, in this embodiment, the arrangement of the second interconnect solder balls 800 improves the thermal fatigue resistance reliability of the packaging structure.

[0067] Reference Figure 3 and Figure 4 In some embodiments of this application, the first substrate 100 is provided with a first fitting groove 110 on the side facing the second substrate 200, and the first chip 300 is fitted into the first fitting groove 110; the second substrate 200 is provided with a second fitting groove 210 on the side facing the first substrate 100, and the second chip 400 is fitted into the second fitting groove 210.

[0068] Specifically, the first fitting groove 110 is disposed on the side surface of the first substrate 100 facing the second substrate 200, i.e., the lower surface of the first substrate 100. The first fitting groove 110 is a cavity structure formed by recessing inward from the lower surface of the first substrate 100, and its recess depth can be set according to actual conditions. This ensures that after the first chip 300 is completely accommodated in the groove, the first active surface 310 does not protrude from the lower surface of the first substrate 100, or only slightly protrudes but the amount of protrusion is less than the height of the controllable collapse chip connection bump 520. The shape of the first fitting groove 110 on the horizontal plane matches the planar shape of the first chip 300. For example, if the first chip 300 is a rectangular chip, the opening shape of the first fitting groove 110 is a corresponding rectangle, and the dimensions of each side of the rectangle are larger than the corresponding dimensions of the first chip 300, so as to provide alignment allowance during mounting and filling space for the bottom filler adhesive. A second fitting groove 210 is provided on the upper surface of the second substrate 200 facing the first substrate 100. The second fitting groove 210 is a cavity structure formed by recessing inward from the upper surface of the second substrate 200 to accommodate the second chip 400. The shape of the second fitting groove 210 on the horizontal plane matches the planar shape of the second chip 400, and its size is larger than that of the second chip 400.

[0069] Furthermore, the bottom wall and side walls of the first fitting groove 110 are the substrate exposed surfaces of the first substrate 100. When the first chip 300 is embedded in the first fitting groove 110, the back side of the first chip 300 faces the bottom wall of the first fitting groove 110, and the two are fixed together by an adhesive material. The adhesive material can be a chip mounting film, a thermally conductive adhesive, or an underfill adhesive. The chip mounting film is a thermosetting epoxy resin film. During the mounting process, the film is softened by heating and pressurizing to bond the chip to the bottom wall of the first fitting groove 110, and provides a fixing effect after curing. When a thermally conductive adhesive is used as the adhesive material, the thermally conductive adhesive is an organosilicon resin filled with alumina or boron nitride particles, which can transfer the heat generated by the chip during operation to the substrate for heat dissipation. The bonding method of the second chip 400 embedded in the second fitting groove 210 is the same as that of the first chip 300. The gap between the sidewall of the first mating groove 110 and the edge of the first chip 300 can be filled with bottom filler adhesive. The bottom filler adhesive seeps from the chip edge into the gap between the bottom wall of the first mating groove 110 and the first chip 300, as well as the gap between the sidewall and the first chip 300, through capillary action. After thermosetting, it forms a filling layer. The filling layer can alleviate the thermal stress caused by the difference in thermal expansion coefficient between the chip and the substrate, and prevent the chip from cracking during temperature cycling.

[0070] In this embodiment, a first fitting groove 110 is provided on the first substrate 100, and a second fitting groove 210 is provided on the second substrate 200, so that the first chip 300 and the second chip 400 are respectively accommodated inside the grooves of the upper and lower substrates. In the packaging structure, the total thickness of the package consists of three parts: the thickness of the first substrate 100, the gap height between the first substrate 100 and the second substrate 200, and the thickness of the second substrate 200. When the first chip 300 is accommodated in the first fitting groove 110 of the first substrate 100, the thickness of the first chip 300 is absorbed by the thickness of the first substrate 100, and the first chip 300 does not occupy any additional space other than the lower surface of the first substrate 100; when the second chip 400 is accommodated in the second fitting groove 210 of the second substrate 200, the thickness of the second chip 400 is absorbed by the thickness of the second substrate 200, and the second chip 400 does not occupy any additional space other than the upper surface of the second substrate 200. Since both chips are housed within the thickness range of the substrate, the gap between the first substrate 100 and the second substrate 200 only needs to meet the space requirements of the hybrid bonding layer 510 between the active surfaces of the two chips and the space requirements of the controllable collapse chip connection bump 520, without reserving space for chip thickness.

[0071] In contrast, in traditional stacked packaging, the chip is mounted on the substrate surface, and the chip thickness contributes entirely to the total package thickness. The total package thickness needs to be increased by the chip thickness and the height of the interconnect structure on top of the substrate thickness. In this embodiment, the chip thickness overlaps with the substrate thickness by setting the interlocking slot, compressing the overall package cross-sectional thickness to the substrate thickness plus a small interlayer gap. The chip thickness no longer increases the overall height, thus achieving a significant reduction in package height.

[0072] In some embodiments of this application, the inner walls of the first fitting groove 110 and the second fitting groove 210 are provided with a heat-conducting layer; and / or, the inner walls of the first fitting groove 110 and the second fitting groove 210 are provided with an electromagnetic shielding layer.

[0073] Specifically, a thermally conductive layer is disposed on the inner wall surfaces of the first interlocking groove 110 and the second interlocking groove 210. The thermally conductive layer is a layer of highly thermally conductive material covering the bottom and side walls of the first interlocking groove 110 and the bottom and side walls of the second interlocking groove 210. The thermally conductive layer can be selected from metal thin films, diamond-like carbon (DLC) thin films, graphene layers, or thermally conductive ceramic layers. When the thermally conductive layer is a metal thin film, its material can be copper, aluminum, or silver, and it is formed on the inner wall surfaces of the first interlocking groove 110 and the second interlocking groove 210 by electroplating, chemical plating, or sputtering. When the thermally conductive layer is a DLC thin film, it is formed by chemical vapor deposition, and DLC thin films have extremely high thermal conductivity. When the thermally conductive layer is a graphene layer, its thickness is from a single layer to tens of atomic layers, and it is formed on the inner wall surfaces of the first interlocking groove 110 and the second interlocking groove 210 by transfer methods or in-situ growth methods.

[0074] An electromagnetic shielding layer is disposed on the inner wall surface of the first fitting groove 110 and the second fitting groove 210. The electromagnetic shielding layer is a conductive material layer, and its material can be selected from copper foil, silver paste layer or nickel-chromium alloy layer. It is formed on the inner wall surface of the first fitting groove 110 and the second fitting groove 210 by electroplating, chemical plating or printing. The inner wall of the first fitting groove 110 and the second fitting groove 210 can also be provided with a heat-conducting layer and an electromagnetic shielding layer at the same time. In this case, the heat-conducting layer and the electromagnetic shielding layer can be the same material layer. For example, the copper layer has both heat-conducting function and electromagnetic shielding function. It can also be a layered structure of different materials. For example, the inner layer is a copper heat-conducting layer and the outer layer is a nickel-chromium electromagnetic shielding layer, or the inner layer is an electromagnetic shielding layer and the outer layer is a heat-conducting insulating layer.

[0075] Furthermore, when both the thermal conductive layer and the electromagnetic shielding layer are disposed simultaneously, their stacking order can be determined according to functional requirements. For scenarios where heat dissipation is the primary requirement, the thermal conductive layer is disposed on the side closest to the chip, and the electromagnetic shielding layer is disposed between the thermal conductive layer and the substrate material. In this way, the heat generated by the chip is first conducted through the thermal conductive layer to the inner walls of the entire first mating groove 110 and the second mating groove 210, and then dissipated through the substrate material. The electromagnetic shielding layer is located outside the thermal conductive layer, serving the dual purpose of reflecting external electromagnetic waves and preventing internal electromagnetic leakage.

[0076] For scenarios where electromagnetic shielding is the primary requirement, the electromagnetic shielding layer is placed on the side closest to the chip, and the thermally conductive layer is placed between the electromagnetic shielding layer and the substrate material. The electromagnetic shielding layer directly faces the chip and the bonding interface, which can more effectively shield the electromagnetic radiation generated during chip operation. The thermally conductive layer and the electromagnetic shielding layer can be bonded together through an adhesive layer or direct deposition. When using the direct deposition method, the bonding interface between the two layers is achieved through atomic diffusion or chemical bonding, resulting in high bonding strength and preventing delamination during thermal cycling.

[0077] In this embodiment, a thermally conductive layer is provided on the inner walls of the first mating groove 110 and the second mating groove 210, allowing the heat generated by the chip to be conducted through a large-area heat diffusion surface. The heat-generating areas of the first chip 300 and the second chip 400 are mainly concentrated on the active surface area of ​​the chip, with the active surface facing the opening direction of the mating groove, while the back side of the chip faces the bottom wall of the mating groove. Since the thermally conductive layer covers the entire inner wall surface of the first mating groove 110 and the second mating groove 210, including the bottom wall and the four side walls, the heat from the back side of the chip is conducted to the thermally conductive layer on the bottom wall through the adhesive material, diffuses along the planar direction to the side wall area within the thermally conductive layer, and then is conducted to the interior of the substrate through the thermally conductive layer on the side walls, and finally dissipates heat through the outer surface of the substrate. In this three-dimensional heat dissipation path, after the heat is conducted out from the back side of the chip, it can be dissipated not only through the bottom wall area but also through the four side wall areas. The total heat dissipation area is the sum of the bottom wall area and the four side wall areas, which is much larger than the heat dissipation area (bottom wall area only) in the scheme that only dissipates heat through point contact on the back side of the chip.

[0078] Meanwhile, by setting an electromagnetic shielding layer on the inner wall of the first fitting groove 110 and the second fitting groove 210, the electromagnetic shielding layer surrounds the first chip 300 and the second chip 400 to form a Faraday cage structure. The electromagnetic radiation generated when the chip switches at high speed is absorbed and reflected by the shielding layer and cannot penetrate the shielding layer to reach the outside of the package. At the same time, it also prevents external electromagnetic waves from entering the interior of the shielding layer and affecting the chip operation, thereby improving the electromagnetic compatibility of the packaging system.

[0079] Reference Figure 1 In some embodiments of this application, a third chip 900 is electrically connected to the side of the first substrate 100 opposite to the second substrate 200.

[0080] Specifically, the side of the first substrate 100 facing away from the second substrate 200, i.e., the upper surface of the first substrate 100, is considered. The third chip 900 can be a memory chip, an RF front-end chip, a power management chip, or a sensor chip. The lower surface of the third chip 900 has a third active surface, on which pads are provided. The third active surface of the third chip 900 faces the upper surface of the first substrate 100 and is electrically connected to the corresponding pads on the upper surface of the first substrate 100 through a mounting interconnect structure. The gap between the third chip 900 and the upper surface of the first substrate 100 can be filled with underfill adhesive to alleviate thermal stress. There can be multiple third chips 900, which can be arranged side-by-side on the upper surface of the first substrate 100, for example, two memory chips mounted side-by-side, or one memory chip and one RF chip mounted side-by-side. The multiple third chips 900 can be interconnected through the circuit layers inside the first substrate 100.

[0081] During use, the third chip 900 acts as a functional expansion chip, working in conjunction with the first chip 300 and the second chip 400. Taking the third chip 900 as a memory chip, the first chip 300 as an application processor chip, and the second chip 400 as a baseband processor chip as an example, the application processor chip and the baseband processor chip exchange data at high speed through a hybrid bonding layer 510. When the application processor chip needs to store data, it transfers the data from the first chip 300 to the pads on the upper surface of the first substrate 100 through the circuit layer inside the first substrate 100, and then through the mounting interconnect structure of the third chip 900 for storage. When reading data, the data is transferred from the third chip 900 to the first chip 300 in the opposite direction. The signal path between the third chip 900 and the first chip 300 is as follows: the first electrical connection area 311 of the first chip 300 is connected to the second substrate 200 via the controllable collapse chip connection bump 520, then to the first substrate 100 via the first interconnect solder ball 600 or the second interconnect solder ball 800, then to the pad on the upper surface of the first substrate 100 via the internal circuit layer of the first substrate 100, and finally to the third chip 900 via the mounting interconnect structure. The signal path achieves vertical crossing through the substrate circuit.

[0082] In some embodiments of this application, the thickness of the hybrid bonding layer 510 is 1 μm-10 μm.

[0083] Specifically, the thickness of the hybrid bonding layer 510 is 1 μm to 10 μm. The hybrid bonding layer 510 refers to the bonding interface layer between the second electrical connection region 312 and the third electrical connection region 411. This layer consists of two parts: one part is the bonding interface between dielectric layers, and the other part is the bonding interface between metal pads. The dielectric layer is a dielectric material layer covering the top layer of the first active surface 310 and the second active surface 410, and can be silicon oxide, silicon nitride, or silicon carbonitride, with a thickness of 0.5 μm to 3 μm. The metal pads are metal electrodes embedded in the dielectric layer, made of copper, with a thickness of 0.5 μm to 5 μm. The upper surface of the metal pads is coplanar with or slightly recessed from the upper surface of the dielectric layer.

[0084] During the hybrid bonding process, the surfaces of the dielectric layers of the two chips are contacted and covalently bonded after plasma activation treatment. During high-temperature annealing, copper atoms diffuse into the metal pads to form metallic bonds. The resulting hybrid bonding layer 510 comprises both the dielectric layer bonding interface and the metallic bonding interface, together forming a complete bonding interface layer with a total thickness of 1 μm to 10 μm. The thickness of the hybrid bonding layer 510 can be controlled as the sum of the dielectric layer thickness at the second electrical connection region 312 and the metal pad thickness, and the dielectric layer thickness at the third electrical connection region 411 and the metal pad thickness, minus the thinning caused by the fusion of the two dielectric layers during annealing. Furthermore, the thickness of the hybrid bonding layer 510 can also be 3 μm to 7 μm.

[0085] This embodiment achieves ultra-short-distance vertical interconnection between the first chip 300 and the second chip 400 by controlling the thickness of the hybrid bonding layer 510 within the range of 1μm to 10μm. During signal transmission, the signal originates from the copper pad of the second electrical connection region 312, passes through the metal bonding interface of the hybrid bonding layer 510, and enters the copper pad of the third electrical connection region 411. The transmission distance is equal to the thickness of the hybrid bonding layer 510. Since the thickness of the hybrid bonding layer 510 is 1μm to 10μm, the signal transmission distance within this thickness range is only on the micrometer level. The signal propagation time is proportional to the transmission distance, and the propagation time corresponding to a micrometer-level transmission distance is on the picosecond level.

[0086] In traditional solder ball interconnects, the height of the solder balls is typically above 100 μm. The signal transmission distance through the solder balls is ten to a hundred times the thickness of the hybrid bonding layer 510, corresponding to a propagation delay on the order of nanoseconds. Therefore, this embodiment reduces the signal transmission delay between chips by one to two orders of magnitude through the ultra-thin design of the hybrid bonding layer 510, significantly improving the speed of data exchange between chips. Simultaneously, the short-distance interconnect reduces the parasitic capacitance and inductance values ​​of the signal path, decreases the distortion of the rising and falling edges of the signal during transmission, and improves signal integrity and power integrity. This allows the first chip 300 and the second chip 400 to operate stably at higher operating frequencies. Furthermore, the thickness uniformity of the hybrid bonding layer 510 directly affects the bonding quality. By controlling the thickness within this range, the integrity and consistency of the dielectric layer bonding and the metal bonding can be ensured.

[0087] Reference Figure 5 This application also provides a packaging method based on the packaging structure of any of the above embodiments, comprising the following steps: S1, embedding a second chip 400 on a second substrate 200 such that the second active surface 410 faces away from the second substrate 200; S2, placing a first chip 300 upside down on the second chip 400, connecting the first chip 300 and the second chip 400 by hybrid bonding, and electrically connecting the first chip 300 and the second substrate 200; S3, stacking a first substrate 100 on the second substrate 200 such that the first chip 300 is embedded in the first substrate 100, and electrically connecting the first substrate 100 and the second substrate 200; S4, electrically connecting the second chip 400 and the second substrate 200.

[0088] Specifically, during the embedding process, the second chip 400 is placed in the second fitting groove 210 of the second substrate 200 with its second active surface 410 facing away from the second substrate 200. The second active surface 410 facing away from the second substrate 200 means that the second active surface 410 faces upward, while the back of the second chip 400 faces the bottom wall of the second fitting groove 210.

[0089] Before performing step S1, a first fitting groove 110 and a second fitting groove 210 are etched on the first substrate 100 and the second substrate 200 respectively (e.g. Figure 3 and Figure 4 (As shown). Then, an adhesive material is applied to the bottom wall of the second mating groove 210. The adhesive material can be a chip mounting film or a liquid thermally conductive adhesive, and the application method can be dispensing, printing, or film application.

[0090] Then, the second chip 400 is picked up from the wafer and transferred to the second fitting slot 210 using a pick-and-place device. The planar position of the second chip 400 is aligned with the opening position of the second fitting slot 210 using a vision alignment system, so that the second chip 400 is placed in the second fitting slot 210 of the second substrate 200 with the second active surface 410 facing away from the second substrate 200, and the back side of the second chip 400 faces the bottom wall of the second fitting slot 210.

[0091] Then, the placement head is lowered so that the second chip 400 falls into the second fitting groove 210. The back of the second chip 400 comes into contact with the adhesive material. The adhesive material is cured by heating and pressurizing, and the second chip 400 is fixed in the second fitting groove 210.

[0092] Reference Figure 6 In step S2, a controllable collapse chip connection bump 520 is first prepared in the first electrical connection region 311 of the first chip 300, and a corresponding pad is prepared at the corresponding position on the upper surface of the second substrate 200. Then, the first chip 300 is picked up and moved above the second chip 400 using a pick-and-place device, and the second electrical connection region 312 and the third electrical connection region 411 are precisely aligned horizontally using a high-precision vision alignment system. After alignment, the first chip 300 is lowered to contact the second chip 400, and pre-bonding pressure is applied at room temperature to pre-bond the dielectric layer surfaces of the second electrical connection region 312 and the third electrical connection region 411, forming a mechanical connection between the first chip 300 and the second chip 400. Simultaneously, the controllable collapse chip connection bump 520 on the first electrical connection region 311 of the first chip 300 contacts the pad on the upper surface of the second substrate 200. After pre-bonding is completed, high-temperature annealing is performed to achieve copper-copper diffusion bonding of the metal pads of the hybrid bonding layer 510. At the same time, the controllable collapse chip connection bumps 520 are reflow soldered to achieve electrical connection between the first chip 300 and the second substrate 200.

[0093] Reference Figure 7Before step S3, the mounting and interconnection of the third chip 900 need to be completed on the upper surface, and then the first interconnect solder ball 600 and the second interconnect solder ball 800 are fabricated on the pads on the lower surface. At the same time, the first substrate 100 is provided with a wire 700, the first interconnect solder ball 600 is disposed at one end of the wire 700, and the other end of the wire 700 is exposed to the outside for connection with the controllable collapse chip connection bump 520 on the second chip 400.

[0094] Reference Figure 8 Then, the first substrate 100 is picked up and flipped so that its lower surface faces down, and moved above the second substrate 200. A visual alignment system is used to align the lower surface pads of the first substrate 100 with the upper surface pads of the second substrate 200 horizontally. After alignment, the first substrate 100 is lowered until it contacts the second substrate 200. At this point, the first chip 300 enters the first mating groove 110 of the first substrate 100. An adhesive material can be pre-coated between the back surface of the first chip 300 and the bottom wall of the first mating groove 110. During the descent, the adhesive material is pressurized and flows, filling the space between the back surface of the first chip 300 and the bottom wall of the first mating groove 110. Then, reflow soldering melts the first interconnect solder balls 600 and the second interconnect solder balls 800, electrically and mechanically connecting the first substrate 100 and the second substrate 200.

[0095] In step S4, the controllable collapse chip connection bump 520 on the second chip 400 can be melted to electrically connect the second chip 400 and the second substrate 200. After step S4, a third interconnect solder ball 530 (e.g., ...) can be implanted into the bottom of the second substrate 200. Figure 1 (as shown), and then apply adhesive.

[0096] In this embodiment, by first embedding the second chip 400 on the second substrate 200 with its active side facing upwards, a stable mounting foundation is provided for subsequent face-to-face high-density interconnection with the first chip 300. After the first chip 300 is inverted, it is connected to the second chip 400 using hybrid bonding, forming a shorter signal transmission path between the chips, thereby reducing parasitic parameters and transmission delay. The electrical connection between the first chip 300 and the second substrate 200, as well as the electrical connection between the second chip 400 and the second substrate 200, can achieve a synergistic balance between inter-chip communication and external signal output. Then, the first substrate 100 is stacked on the second substrate 200 and electrically connected to it, so that the first chip 300 is embedded in the first substrate 100, thereby improving the overall package compactness and structural stability. Therefore, high-density interconnection, high I / O integration, and better electrical performance can be achieved in a limited space.

[0097] Finally, it should be noted that other embodiments of this application will readily conceive of by those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope.

Claims

1. A packaging structure, characterized in that, include: First substrate (100); The second substrate (200) is stacked on top of the first substrate (100) and electrically connected to it; A first chip (300) is embedded in the first substrate (100). The first chip (300) has a first active surface (310) facing the second substrate (200). The first active surface (310) has a first electrical connection area (311) and a second electrical connection area (312). The first electrical connection area (311) is electrically connected to the second substrate (200). The second chip (400) is embedded in the second substrate (200). The second chip (400) has a second active surface (410). The second active surface (410) has a third electrical connection region (411) and a fourth electrical connection region (412). The third electrical connection region (411) and the second electrical connection region (312) are connected through a hybrid bonding layer (510). The fourth electrical connection region (412) is electrically connected to the second substrate (200).

2. The packaging structure according to claim 1, characterized in that, The first electrical connection region (311) and the fourth electrical connection region (412) are misaligned with each other; Both the first electrical connection area (311) and the fourth electrical connection area (412) are provided with controllable collapse chip connection bumps (520). The first electrical connection area (311) and the fourth electrical connection area (412) are both electrically connected to the second substrate (200) through the corresponding controllable collapse chip connection bump (520).

3. The packaging structure according to claim 2, characterized in that, The controllable collapse chip connection bump (520) on the first electrical connection area (311) is located between the first electrical connection area (311) and the second substrate (200).

4. The packaging structure according to claim 2, characterized in that, A first interconnect solder ball (600) is provided between the first substrate (100) and the second substrate (200), and the first interconnect solder ball (600) is electrically connected to the second substrate (200); The first substrate (100) has a wire (700) inside. One end of the wire (700) is electrically connected to the controllable collapse chip connection bump (520) on the fourth electrical connection area (412), and the other end is electrically connected to the first interconnect solder ball (600).

5. The packaging structure according to claim 1, characterized in that, A second interconnect solder ball (800) is provided between the first substrate (100) and the second substrate (200). One side of the second interconnect solder ball (800) is electrically connected to the first substrate (100), and the other side of the second interconnect solder ball (800) is electrically connected to the second substrate (200).

6. The packaging structure according to any one of claims 1-5, characterized in that, The first substrate (100) has a first fitting groove (110) on the side facing the second substrate (200), and the first chip (300) is fitted into the first fitting groove (110); The second substrate (200) has a second fitting groove (210) on the side facing the first substrate (100), and the second chip (400) is fitted into the second fitting groove (210).

7. The packaging structure according to claim 6, characterized in that, The inner walls of the first fitting groove (110) and the second fitting groove (210) are provided with a heat-conducting layer; And / or, the inner walls of the first fitting groove (110) and the second fitting groove (210) are provided with an electromagnetic shielding layer.

8. The packaging structure according to any one of claims 1-5, characterized in that, The first substrate (100) is electrically connected to a third chip (900) on the side opposite to the second substrate (200).

9. The packaging structure according to any one of claims 1-5, characterized in that, The thickness of the hybrid bonding layer (510) is 1μm-10μm.

10. A packaging method, characterized in that, Based on the packaging structure according to any one of claims 1-9, it includes: The second chip (400) is embedded in the second substrate (200), and the second active surface (410) is away from the second substrate (200). The first chip (300) is flipped onto the second chip (400), and the first chip (300) and the second chip (400) are connected by a hybrid bonding method, and the first chip (300) and the second substrate (200) are electrically connected. The first substrate (100) is stacked on the second substrate (200) so that the first chip (300) is embedded in the first substrate (100) and electrically connected to the first substrate (100) and the second substrate (200). The second chip (400) and the second substrate (200) are electrically connected.

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