Method for manufacturing a coupled wafer

Abstract

The invention relates to a method for producing a coupled wafer (100) having: providing a first MEMS wafer (110), wherein the first MEMS wafer (110) has a first functional layer (112) with first MEMS structures (112'); providing a TSV wafer (120) with silicon through holes (150) independently of this; and connecting a first side (110a) of the first MEMS wafer (110) with a first side (120a) of the TSV wafer (120) in such a way that a coupled wafer (100) is obtained.

Description

Technical Field

[0001] This invention relates to the field of wafer fabrication, and specifically to a method for manufacturing a coupled wafer, a coupled wafer, a method for manufacturing a MEMS chip, and a MEMS chip. Background Technology

[0002] Devices incorporating microelectromechanical systems (MEMS), such as micromirror arrays or micromirror actuators, are now used in a variety of devices, including smartphones, projectors, head-up displays, barcode readers, mask exposure machines in semiconductor manufacturing, and microscopes. Corresponding micromirror arrays are known, for example, from documents DE 10 2013 208 446A1, EP 0 877 272 A1, and WO 2010 / 049076 A2. DE 10 2006 032 195 A1 describes a method for fabricating microelectromechanical structures (MEMS structures). DE 10 2009 029 202 A1 discloses a micromechanical system and a method for fabricating a micromechanical system. The so-called EPyC process (EPyC: epitaxial polysilicon cycle) for fabricating microelectromechanical structures with large vertical extension scales is known from DE 10 2015 206 996 A1. It uses epitaxial polysilicon as the functional and sacrificial material and constructs a layer structure consisting of epitaxial polysilicon layers (EpiPoly layers) by means of repeated cycles.

[0003] Especially for components consisting of multiple arrayed MEMS elements, such as micromirror arrays, the challenge often lies in achieving high yields for fully functional MEMS elements. Summary of the Invention

[0004] The present invention provides a method for manufacturing a coupled wafer, a coupled wafer, a method for manufacturing a MEMS chip, and a MEMS chip.

[0005] According to a first aspect of the invention, a method for manufacturing a coupled wafer is provided. For this purpose, a first MEMS wafer is provided, wherein the first MEMS wafer has a first functional layer with a first MEMS structure, for example, for an actuator and / or sensor, and a first handling wafer. This handling wafer may be an SOI handling wafer / starting wafer (SOI: Silicon-on-isolator). Independently thereof, a TSV wafer having silicon vias (hereinafter also simply referred to as Si vias or TSVs, where TSV stands for Through-Silicon Via) is provided, and subsequently, a first side of the first MEMS wafer is connected to a first side of the TSV wafer such that a coupled wafer is obtained.

[0006] Preferably, the method further includes providing a second MEMS wafer, which is, for example, in the form of an SOI wafer and / or has a structure for a mirror plate, wherein the second MEMS wafer has a second functional layer with a second MEMS structure and a second operating wafer, and preferably has a silicon oxide layer disposed between the operating wafer and the functional layer, and connects a second side of the first MEMS wafer that is different from the first side and one side of the second MEMS wafer, preferably via a conductive bonding connection.

[0007] The first and / or second MEMS structures may include, or be for, structures of one or more MEMS elements to be manufactured, such as MEMS sensors and / or MEMS actuators. In particular, the first and / or second MEMS structures may be arranged such that the MEMS elements to be manufactured have an array-like, and especially rectangular or square, arrangement, such as a 2x2, 3x2, 3x3, 3x4, or 4x4 arrangement. MEMS elements may be, for example, MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors, and / or MEMS resonators. For example, the first MEMS structure includes structures for actuators and / or sensors, and the second MEMS structure includes structures for mirror plates.

[0008] The functional layers and operational wafers of the first and / or second MEMS wafers are made of or include silicon. Metals and / or semiconductor oxides may also be included in the first and / or second functional layers. Therefore, the first and / or second functional layers may include sacrificial regions made of semiconductors, such as silicon, and / or semiconductor oxides, such as silicon oxide. The first and / or second MEMS structures may, in addition to purely mechanical structures, include, for example, structures for actuators, sensors, mirrors, one or more electronic circuits, integrated circuits (ICs), electrodes, and / or vias, such as through-silicon vias (TSVs).

[0009] The TSV wafer can be provided as follows: First, a silicon wafer with a thickness of, for example, up to 100µm, 200µm, 300µm, 400µm, 500µm, or greater than 500µm is provided. The thickness of the silicon wafer is selected according to the desired thickness of the TSV wafer. Subsequently, the silicon wafer is oxidized, for example by thermal oxidation and / or LPCVD (low pressure chemical vapor deposition), to form a silicon oxide layer on the surface of the silicon wafer. Here and in the following, oxidation is understood not only as the induced oxidation of a portion of the wafer, for example by thermal oxidation, but also as the application of an oxide layer from the outside, for example by LPCVS. The surface of the wafer opposite to this surface is called the wafer back side. An etch mask is then generated by the structured silicon oxide layer. Now, when using the etch mask, through-holes for silicon vias are generated, for example by a Bosch process. These holes extend to the underside, i.e., to the silicon oxide layer serving as an etch stop layer on the back side of the wafer. The silicon oxide layer serving as an etch stop layer on the back side of the wafer is at least partially removed, for example, by means of HF vapor phase etching, plasma etching, and / or wet chemical etching, resulting in the exposure of the holes. Furthermore, to provide a TSV wafer, the holes, which are preferably already exposed, are oxidized, for example by means of thermal oxidation and / or LPCVD. Oxidation creates a passivation layer in the holes; that is, it is typically done so that all open silicon surfaces, both inside and preferably outside the holes, are passivated.

[0010] Alternatively, the TSV wafer can be provided by applying an etching mask, such as a photoresist layer and / or an oxide hard mask, to the surface of the silicon wafer after providing a silicon wafer preferably having a thickness of up to 1000 µm, particularly preferably up to 800 µm, and especially preferably up to 725 µm. An oxide hard mask is a variant of an etching mask used to structure trenches and / or holes. The oxide hard mask can be made of or comprise metal, for example. Following this step, the etching mask is structured, and then holes are etched in the silicon wafer using the thus structured etching mask. In this case, these holes are preferably formed as blind vias, so that they do not necessarily penetrate the wafer after this step. Finally, the silicon wafer is back-thinned, for example by back-grinding, so that the holes completely penetrate the silicon wafer. That is, the blind vias are opened. The target thickness of the TSV can be adjusted by the back-thinning, for example, grinding, to be between 50 µm and 700 µm. Finally, the holes are oxidized, for example by thermal oxidation and / or LPCVD (low pressure chemical vapor deposition), and preferably so that all open silicon surfaces are passivated, wherein cleaning of the TSV wafer can be performed prior to this step.

[0011] In both variants, the necessary alignment marks (Justagemarken) can be etched into the raw silicon before the vias are applied. In subsequent steps, the alignment marks are protected by passivation oxide. Alignment marks can be used to bond MEMS wafers to TSV wafers, aligning structures (e.g., contact surfaces) with each other. Alignment marks are used for aligned wafer-to-wafer bonding.

[0012] The method according to the invention preferably includes the following additional steps: at least partially, preferably completely, removing the first operating wafer and thereby exposing the surface of the first functional layer, and adding an additional first MEMS structure by growing one or more additional layers having an additional first MEMS structure on the exposed surface.

[0013] Furthermore, preferably, the connection between the first side of the first MEMS wafer and the first side of the TSV wafer is performed earlier in time than the connection between the second side of the first MEMS wafer and the side of the second MEMS wafer.

[0014] Preferably, providing the first MEMS wafer and the TSV wafer includes manufacturing the first MEMS wafer and the TSV wafer, wherein the manufacturing of the first MEMS wafer and the TSV wafer is carried out in an overlapping manner in time.

[0015] Furthermore, preferably, one or more connection portions, particularly bonding portions, are formed by connecting the first side of the first MEMS wafer to the first side of the TSV wafer. These connection portions are suitable for conducting electrical signals between at least a portion of the redistribution plane of the MEMS wafer and the silicon via of the TSV wafer.

[0016] According to a second aspect of the invention, a coupled wafer is provided, preferably manufactured according to one of the methods described above. The coupled wafer includes a first MEMS wafer, wherein the first MEMS wafer has a first functional layer with a first MEMS structure and a first operational wafer, which may be an SOI operational wafer / starting wafer. Furthermore, the coupled wafer includes a TSV wafer with silicon vias, wherein a first side of the first MEMS wafer is connected to a first side of the TSV wafer.

[0017] According to a third aspect of the invention, a method for manufacturing a MEMS chip having one or more MEMS elements is provided. The method includes manufacturing a coupling wafer comprising a coupling wafer according to the invention as described above, and dicing the coupling wafer into a plurality of MEMS chips, such as micromirror chips and / or MMA chips, wherein each MEMS chip may include a plurality of MEMS elements. Preferably, in this case, the coupling wafer is manufactured with a second MEMS wafer provided as described above, wherein the coupling wafer further comprises a second MEMS wafer.

[0018] After the coupled wafer is manufactured and before it is diced, the first MEMS structure and / or the second MEMS structure can be released.

[0019] According to a fourth aspect of the invention, a MEMS chip is manufactured according to one of the methods for manufacturing MEMS chips according to the invention.

[0020] Advantages of the invention This invention describes a scheme in which a TSV wafer is provided in parallel with the MEMS wafer during the manufacturing process of a MEMS chip, and used as an operational wafer for rewiring and subsequent processing. In this case, the TSV wafer replaces the classic layer growth used to manufacture the substrate. The process can thus be parallelized because classic layer growth is avoided. Therefore, turnaround time is shortened and the stability of the MEMS chip is improved. In summary, this also achieves higher yield and high-temperature compatibility, and increased flexibility.

[0021] Classical substrates for MEMS chips typically perform redistribution, stabilization, and signal steering functions. Constructing such a substrate from a single layer is extremely time-consuming. According to the present invention, the substrate is implemented as a TSV wafer. In the TSV wafer, as in the application according to the invention, a relatively thin EPyC layer can be configured for redistribution, for example. This enables a shorter overall process time. The thickness of the TSV wafer can be arbitrarily adjusted between 50µm and 700µm or larger by back-side thinning, for example by grinding. Attached Figure Description

[0022] Embodiments of the present invention will be explained in detail with reference to the accompanying drawings and the following description.

[0023] The attached diagram shows: Figures 1A to 1E : A schematic cross-sectional view for explaining the method for manufacturing a coupled wafer according to the present invention; Figure 2A , 2B : A schematic cross-sectional view for explaining the method for providing TSV wafers according to the present invention; Figure 3A , 3B : A schematic cross-sectional view for explaining the details of the method for manufacturing MEMS components according to the present invention; Figure 4 : A schematic cross-sectional view for explaining the details of the method for providing TSV wafers according to the present invention; Figure 5 : A schematic top view of the coupled wafer according to the invention and different TSV cross sections, also schematically shown; and Figure 6 The following is a schematic flowchart illustrating an exemplary method for manufacturing a coupled wafer and the MEMS chip produced by the method according to the present invention. Detailed Implementation

[0024] In the following description of embodiments of the invention, the same or similar elements are identified by the same reference numerals, and in some cases, repeated descriptions of these elements are omitted. The drawings are for illustrative purposes only, showing the subject matter of the invention.

[0025] Figures 1A to 1E A schematic cross-sectional view is shown to illustrate the method for manufacturing a coupled wafer according to the present invention.

[0026] Figure 1AA portion of a first MEMS wafer 110 is shown, wherein the first MEMS wafer 110 has a first functional layer 112 with a first MEMS structure 112' and a first operational wafer 114. In this case, in this figure and the following figures, the MEMS structure is schematically indicated by horizontally and vertically extending lines 113, for example, symbolizing passivation layers.

[0027] exist Figure 1B In this configuration, a first MEMS wafer 110 is now connected to a TSV wafer 120 having Si vias 150, which are filled, for example, with doped polysilicon, copper, tungsten, and / or metal silicides, which can be applied, for example, by means of LPCVD (low-pressure chemical vapor deposition). More specifically, a first side of the first MEMS wafer (110) is connected to a first side 120a of the TSV wafer 120 to obtain a coupled wafer 100. A material layer, such as a polysilicon layer 124, is formed on the TSV wafer 120 by LPCVD deposition. In the case of LPCVD polysilicon, the LPCVD polysilicon can be in situ doped with not only boron but also phosphorus.

[0028] Figure 1C The diagram shows the situation after the first operating wafer 114 is subsequently completely removed, thereby exposing the surface 112a of the first functional layer 112. Additional first MEMS structures 116' are added to the coupled wafer 100 by growing one or more additional layers 116 having additional first MEMS structures 116' on the exposed surface 112a.

[0029] Now, after providing the second MEMS wafer 130, it can be connected to the coupling wafer 100, wherein the second MEMS wafer 130 has a second functional layer 132 with a second MEMS structure 132' and a second operating wafer 134, and a second side 110b of the first MEMS wafer 110, different from the first side 110a, is connected to one side 130b of the second MEMS wafer 130 via a bonding connection portion 180. As a result... Figure 1D As shown in the image.

[0030] Finally, as Figure 1E As shown, metal contacts 190 that are electrically connected to Si vias 150 can be generated by selectively removing the polysilicon layer 124 and performing metallization.

[0031] Figure 2A , 2B Schematic cross-sectional views are now shown in two variations for explaining the method of providing a TSV wafer 120 according to the present invention, wherein the sequence of steps is indicated by arrows 280.

[0032] According to Figure 2A A first variant, as shown in subfigure (i), provides a silicon wafer 210 with a thickness 211, which is selected according to the desired target thickness of the TSV wafer 120. For example, in this case, the thickness 211 can be up to 100 µm, up to 200 µm, up to 300 µm, up to 400 µm, up to 500 µm, or greater than 500 µm. After, for example, thermally oxidizing the silicon wafer 210 to form a silicon oxide layer 220 on the surface of the silicon wafer 210 (subfigure (iii)), an etch mask 220' is generated on the upper sub-region of the silicon oxide layer 220 by structuring the silicon oxide layer 220.

[0033] When using an etch mask 220', as shown in subfigure (iii), holes 250 penetrating the silicon wafer 210 can be created for silicon vias 150. In this case, a sub-region of the silicon oxide layer 220 located below serves as an etch stop layer. This portion is now removed in the region of the holes 250 in subfigure (iv), thereby exposing these holes 250. These holes now penetrate the entire thickness 211 of the silicon wafer 210. Finally, the holes 250 are subjected to, for example, thermal oxidation to create a passivation layer 122 in the holes 250, wherein the result, i.e., the completed TSV wafer 120, is shown in subfigure (v).

[0034] Figure 2B Show Figure 2A An alternative to the method is provided. In this case, a silicon wafer 210 is re-provided (sub-figure (i)), this time having a thickness 211 of up to 1000 µm, preferably up to 800 µm, and particularly preferably up to 725 µm. Now, in sub-figure (ii), an etching mask 220', such as an oxide hard mask 221, is applied to the upper surface of the silicon wafer 210 and subsequently structured. Now, as shown in sub-figure (iii), holes 250 are etched in the silicon wafer 210 using the structured etching mask 220'. These holes 250 are connected to... Figure 2A The opposite topography of the holes 250 becomes blind vias, which do not penetrate the silicon wafer 210.

[0035] Subsequently, as shown in subfigure (iv), the silicon wafer 210 can be thinned, for example, by back-side grinding. This is done so that the vias 250 completely penetrate the silicon wafer 210. This creates blind vias. This back-side thinning sets the target thickness of the TSV wafer 120 to be manufactured. Finally, oxidation is performed, for example, by thermal oxidation of the thinned silicon wafer 210 or by using LPCVD, to passivate all open silicon surfaces. The result of this step is shown in subfigure (v) and represents the completed TSV wafer 120. Through oxidation, a passivation layer 122 is formed on the walls of the vias 250. Through this step, all remaining open surfaces of the silicon wafer 210 are passivated by oxidation, as shown by the additional passivation layer 222 drawn in subfigure (v). Prior to oxidation, it is preferable to perform cleaning of the silicon wafer 210.

[0036] Figure 3A , 3B A schematic cross-sectional view is now shown to explain the details of the method for manufacturing MEMS components according to the present invention. The chronological order of the method steps is indicated by arrows 280, as already shown. Figure 2A , 2B As shown in the image.

[0037] More precisely, Figure 3A and 3B Details of the steps for connecting the TSV wafer 120 to the MEMS wafer 110, such as an actuator wafer, are shown, including possibilities for a configuration redistribution plane 300 and filling vias 250. In this case, Figure 3A Subgraphs (i) to (iv) and Figure 3B Subgraphs (i) to (v) are shown respectively in Figure 3A , 3B The upper left of the image shows an enlarged view of the coupled wafer 100, in which the components and structures shown are further simplified relative to the sub-diagram. For example, the signal lines 330 of the MEMS wafer 110 are omitted from the drawing. The situation shown in the overall view is roughly closest to the sub-diagram (ii).

[0038] Typically, the first MEMS wafer 110 requires only a thin redistribution plane 300. The cap oxide layer 320 of the redistribution plane 300 of the MEMS wafer 110, facing the TSV wafer 120, is polished and structured such that the signal line 330 coincides with the via 250 of the TSV wafer 120. This is shown in subfigure (i), where other possible passivation layers 340, 350 of the MEMS wafer 110 are drawn in addition to the cap oxide layer 320. Bonding of the wafers 110 and 120 is then performed, for example, by hydrophilic SiO2-SiO2 bonding. The signal line 330 of the MEMS wafer 110 is free of oxide and is open and accessible to the back side of the coupled wafer 100 through the via 250 of the TSV wafer 120. In this case, the via 250 is provided with a passivation layer 122. At this point in time (sub-figure (ii)), no electrical contact has yet been established between the TSV wafer 120 and the MEMS wafer 110. A cleaning step removes any native oxides that may be present on the silicon contact surfaces. The electrical contact is now established in the next step (sub-figure (iii)) by depositing a conductive material 150, such as doped polysilicon deposited via LPCVD, which may also be copper, tungsten, and / or metal silicides. This filler material 150 is uniformly deposited in the passivated vias 250 during this process and establishes an electrical connection between the signal lines 330 of the first MEMS wafer 110 and the upper side of the TSV wafer 120. So much filler material 150 is deposited until the vias 250 are completely closed, to achieve a closed plane 124, such as a polysilicon layer 124, on the upper side of the TSV wafer 120, and to ensure continued processability.

[0039] To simplify and accelerate the complete sealing of the vias 250 with polycrystalline silicon, the vias 250 can be artificially narrowed by previously deposited PECVD oxide (PECVD: plasma-enhanced chemical vapor deposition). This method is used in... Figure 4 As shown in the figure. In this case, subfigure (ii) shows the narrowing portion 410 achieved accordingly by means of anisotropic growth via PECVD, wherein this method is shown in enlarged views in subfigures (iii) to (v). Figure 4 In the diagram, the time sequence of each method step is also indicated by arrow 280.

[0040] A combination of LPCVD polycrystalline silicon 124 (isotropic growth) and subsequent epitaxial steps (anisotropic growth), or a combination of both variations, is also possible. This variation... Figure 3BAs shown in Figure (iii), the aperture 250 is first lined with LPCVD polysilicon 124, but not completely filled (subfigure (iii)). Subsequently, the remaining opening is closed in the epitaxial step by an anisotropic passivation layer 360, but the remaining aperture 322, i.e., cavity, remains (subfigure (iv)).

[0041] Now, as Figure 3A subgraph (iii) and Figure 3B As shown in sub-figure (iv), hole 250 is closed and TSV wafer 120 can be used as an operating wafer for further processing of coupled wafer 100. (The last sentence appears to be incomplete and possibly contains errors.) Figure 3A Compared to fully filling the 250 hole, in accordance with Figure 3B In the variant, the closure of the hole 250 is achieved through a combination of partial filling and closure.

[0042] At an appropriate time, the Si vias 150, which have been short-circuited to each other in the process so far, are electrically isolated from each other. This can be done by metallization to create metal contacts 190 and subsequent passivation to create a passivation layer 350. Figure 3A Subgraph (iv)). The isotropic passivation layer 350 is replaced, as shown in the figure. Figure 3B As shown in sub-figure (v), the anisotropic polysilicon layer 360 can also be selectively removed to isolate the metal contact 190.

[0043] The process sequence described herein is exemplary and can be modularly embedded into any part of the process flow. The TSV can be fully fabricated before the first MEMS wafer 110 is completed. Alternatively, the first MEMS wafer 110 can be completed and then subsequently bonded to the TSV wafer 120.

[0044] The absolute resistance of the Si via 150, or the portion with filling material, can be adjusted via its cross-section (TSV cross-section). Specifically, the resistance of the Si via 150 is related not only to its cross-section but also to its length. Therefore, with a constant length, i.e., TSV depth, the resistance can be changed via the TSV cross-section. Here, the TSV cross-section should be chosen such that the TSV can be closed. In addition to the classic circular or rectangular shapes, more complex structures, such as cross-shaped, spiral, and / or meandering shapes, are conceivable for the shape of the TSV cross-section. The absolute resistance of the Si via 150 can be specifically adjusted by selecting the TSV cross-section. Corresponding exemplary variations of the TSV cross-section are described in... Figure 5 As shown in sub-figure A, and in sub-figure B, for example, the arrangement of Si vias 150 on the coupled wafer 100 is shown for multiple MEMS elements 510.

[0045] Figure 6An exemplary method for manufacturing a 600-coupled wafer 100 according to the present invention is illustrated schematically as a flowchart. Furthermore, Figure 6 A method for manufacturing a MEMS chip 500 according to the present invention is also shown.

[0046] Therefore, a first MEMS wafer 110 is first provided (610), wherein the first MEMS wafer 110 has a first functional layer 112 with a first MEMS structure 112' and a first operational wafer 114. Independently, a TSV wafer 120 with silicon vias 150 is provided (615). Subsequently, in step 620, a first side 110a of the first MEMS wafer 110 is connected to a first side 120a of the TSV wafer 120 to obtain a coupled wafer 100.

[0047] Furthermore, a second MEMS wafer 130 is provided (step 630), wherein the second MEMS wafer 130 has a second functional layer 132 with a second MEMS structure 132' and a second operational wafer 134. Now, a second side 110b of the first MEMS wafer 110, which is different from the first side 110a, is connected 640 to one side 130b of the second MEMS wafer 130, for example, via a bonding connection 180.

[0048] Now, the first operating wafer 114 can be removed 650, thereby exposing the surface 112a of the first functional layer 112, and an additional first MEMS structure 116' can be added 660 by growing one or more additional layers 116 having an additional first MEMS structure 116' on the exposed surface 112.

[0049] After fabricating the 600 coupled wafer 100, the first MEMS structures 112', 116' and / or the second MEMS structure 132' can be released. Finally, the coupled wafer 100 is diced 680 into multiple MEMS chips 500.

[0050] The invention is not limited to the embodiments described herein and the aspects highlighted therein. Rather, various modifications that are within the scope of the claims are possible and are of skill to those skilled in the art.

Claims

1. A method for manufacturing (600) coupled wafers (100), comprising the following steps: a. Provide (610) a first MEMS wafer (110), wherein, The first MEMS wafer (110) has a first functional layer (112) with a first MEMS structure (112') and a first operating wafer (114). b. Unrelated to this, provide (615) a TSV wafer (120) having silicon vias (150); and c. Connect the first side (110a) of the first MEMS wafer (110) to the first side (120a) of the TSV wafer (120) in such a way (620) to obtain a coupled wafer (100).

2. The method according to claim 1, wherein, The method includes the following further steps: d. Provide (630) a second MEMS wafer (130), wherein the second MEMS wafer (130) has a second functional layer (132) with a second MEMS structure (132') and a second operational wafer (134); and e. Connect (640) a second side (110b) of the first MEMS wafer (110) that is different from the first side (110a) to one side (130b) of the second MEMS wafer (130).

3. The method according to claim 1 or 2, wherein, Providing (615) the TSV wafer (120) includes the following steps: a. Provide silicon wafers (210); b. Oxidize the silicon wafer (210) to form a silicon oxide layer (220) on the surface of the silicon wafer (210). c. An etching mask (220') is generated by structuring the silicon oxide layer (220); d. Using the etching mask (220'), holes (250) are formed through the silicon wafer (210) for the silicon via (150); e. At least partially remove the silicon oxide layer (220) on the back side of the wafer to expose the via (250); and f. Oxidize the pores (250).

4. The method according to claim 1 or 2, wherein, Providing (615) the TSV wafer (120) includes the following steps: a. Provide silicon wafers (210); b. Apply an etching mask (220') to the surface of the silicon wafer (210); c. Structure the etch mask (220'); d. Etch holes (250) in the silicon wafer (210) using the structured etching mask (220'); e. Thin the back of the silicon wafer (210) such that the aperture (250) completely penetrates the silicon wafer (210); and f. Oxidize the pores (250).

5. The method according to any one of the preceding claims, wherein, The method includes the following further steps: At least partially remove (650) the first operating wafer (114) and thereby expose the surface (112a) of the first functional layer (112); and Additional first MEMS structure (116') is added (660) by growing one or more additional layers (116) having additional first MEMS structure (116') on the exposed surface (112a).

6. The method according to any one of the preceding claims, wherein, The connection (620) between the first side (110a) of the first MEMS wafer (110) and the first side (120a) of the TSV wafer (120) is performed earlier in time than the connection (640) between the second side (110b) of the first MEMS wafer (110) and the side (130b) of the second MEMS wafer (130).

7. The method according to any one of the preceding claims, wherein, Providing (610) the first MEMS wafer (110) and the TSV wafer (120) includes manufacturing the first MEMS wafer (110) and the TSV wafer (120), and the manufacturing of the first MEMS wafer (110) and the TSV wafer (120) is carried out in overlapping time.

8. The method according to any one of the preceding claims, wherein, One or more connection portions (180) are formed by connecting (620) the first side (110a) of the first MEMS wafer (110) to the first side (120a) of the TSV wafer (120), the connection portions being adapted to conduct electrical signals between at least a portion of the redistribution plane (300) of the MEMS wafer (110) and the silicon via (150) of the TSV wafer (120).

9. The method according to any one of claims 1 to 8, wherein, The first MEMS structure (112', 116') includes structures for actuators and / or sensors, and the second MEMS structure (132') includes structures for mirror plates.

10. A coupled wafer (100), preferably manufactured by the method according to any one of claims 1 to 9, comprising a first MEMS wafer (110) and a TSV wafer (120) having silicon vias (150), wherein, The first MEMS wafer (110) has a first functional layer (112) with a first MEMS structure (112') and a first operating wafer (114), wherein a first side (110a) of the first MEMS wafer (110) is connected to a first side (120a) of the TSV wafer (120).

11. A method for manufacturing a MEMS chip (500) having one or more MEMS elements (510), comprising the following steps: a. Manufacturing (600) a coupled wafer (100) comprising the coupled wafer (100) according to claim 10; and b. Divide (680) the coupled wafer (100) into multiple MEMS chips (500).

12. The method according to claim 11, wherein, The coupling wafer (100) is manufactured (600) according to claim 2 and preferably according to any one of claims 3 to 9, and the coupling wafer (100) further includes a second MEMS wafer (140).

13. The method according to claim 12, wherein, After manufacturing (600) the coupled wafer (100) and before dicing (680) the coupled wafer (100), release (670) the first MEMS structure (112', 116') and / or the second MEMS structure (132').

14. A MEMS chip (500) manufactured by the method according to any one of claims 11 to 13.

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