Semiconductor chip, instantaneous power failure countermeasure system, and control method for semiconductor chip

Abstract

This invention reduces inrush current in a system that writes data from volatile memory to non-volatile memory. The semiconductor chip includes volatile memory cells, non-volatile memory cells, a write processing unit, a read processing unit, and a save / restore processing unit. The write processing unit writes data to the same address in both the volatile and non-volatile memory cells. The read processing unit reads data from the address in the volatile memory cell as first read data and reads data from the address in the non-volatile memory cell as second read data. The save / restore processing unit performs a save process that writes the first read data to an address in the non-volatile memory cell where the corresponding second read data does not match the first read data.

Description

Technical Field

[0001] This technology relates to semiconductor chips. Specifically, this technology relates to semiconductor chips equipped with volatile and non-volatile memory cells, instantaneous power failure countermeasure systems, and control methods for semiconductor chips. Background Technology

[0002] Conventionally, in various systems and devices using semiconductor chips, data saving and recovery can be performed within the semiconductor chip in the event of a power supply voltage drop or interruption. For example, a system has been proposed in which, in the event of a power supply voltage drop, all data in volatile memory is written to non-volatile memory, and in the event of a power supply voltage rise, the data is written back to volatile memory (see, for example, Patent Document 1).

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent No. 5284142 Summary of the Invention

[0006] The problem to be solved by the present invention

[0007] In the aforementioned related technologies, data loss is prevented by storing data in non-volatile memory. However, in the above system, since all data is written to non-volatile memory, a larger inrush current is generated during the writing process compared to the case where only a portion of the data is written.

[0008] This technology was developed in view of this situation, and its purpose is to reduce inrush current in systems configured to write data from volatile memory cells to non-volatile memory.

[0009] Solution to the problem

[0010] This technology was developed to overcome the aforementioned problems, and its first aspect is a semiconductor chip comprising: a volatile memory cell; a non-volatile memory cell; a write processing unit configured to write write data to the same address of the volatile memory cell and the non-volatile memory cell; a read processing unit configured to read data from the address of the volatile memory cell as first read data, and configured to read data from the address of the non-volatile memory cell as second read data; and a save / restore processing unit configured to perform a save process, wherein the save process writes the first read data to an address in the non-volatile memory cell where the corresponding second read data does not match the first read data; and a control method thereof. Therefore, the effect of reducing inrush current is achieved.

[0011] Furthermore, in the first aspect, the write processing unit can use a first write pulse to write write data, and the save / restore processing unit can use a second write pulse having at least one of a pulse width and voltage greater than the first write pulse to write first read data. Therefore, the effect of minimizing write errors is achieved.

[0012] Furthermore, in the first aspect, the save / restore processing unit can also perform a restore process that writes newly read data from the non-volatile storage unit to the volatile storage unit after the save process. Therefore, the effect of restoring the saved data is achieved.

[0013] Furthermore, in the first aspect, the volatile storage unit can maintain an initial value for the tag bit at each address. The write processing unit can use a first write pulse to write the write data to the address and update the corresponding tag bit to a value different from the initial value. The read processing unit can update the corresponding tag bit to the initial value if the first read data and the second read data match each other. The save / restore processing unit can use a second write pulse to write the first read data to the address where the tag bit is different from the initial value among all addresses. Therefore, the effect of determining whether a mismatch exists based on the tag bit is achieved.

[0014] Furthermore, in the first aspect, the non-volatile memory cell may include multiple non-volatile memory banks. Therefore, the effect of reducing inrush current in a multi-bank configuration is achieved.

[0015] Furthermore, in the first aspect, the semiconductor chip may further include a memory bank switching control unit configured to switch between multiple non-volatile memory banks in operation. A save / restore processing unit can perform save and restore processes. The save process uses a second write pulse to write first read data to addresses in the operating memory bank whose corresponding tag bits differ from their initial values. The restore process writes read data from the restore target memory bank specified by the memory bank switching control unit after the save process to the volatile memory bank and updates the corresponding tag bits to their initial values. Therefore, the effect of determining whether a mismatch exists based on the tag bits in the multi-memory bank configuration is achieved.

[0016] Furthermore, in the first aspect, both volatile and non-volatile memory units can include at least one of a general-purpose register, a stack pointer register, a program counter register, a save program counter register, a processor status word register, a save status register, a procedure register, a multiplication register, a base address register, a vector base address register, a read data buffer register, and a write data buffer register. Therefore, the effect of reducing inrush current is achieved during writes to general-purpose registers, etc.

[0017] Furthermore, in the first aspect, the volatile storage unit may include volatile shared resources that hold shared data shared by multiple subjects and volatile non-shared resources that hold data that is not part of the shared data, and the non-volatile storage unit may include non-volatile shared resources that hold shared data and multiple non-volatile non-shared storage units that hold data that is not part of the shared data. Therefore, efficient memory utilization is achieved.

[0018] Furthermore, in the first aspect, the volatile memory cells may include a predetermined number of volatile registers, and the non-volatile memory cells may include a predetermined number of non-volatile registers. Therefore, the effect of reducing inrush current during writing to the non-volatile registers is achieved.

[0019] Furthermore, in the first aspect, the volatile memory cell may include a predetermined number of volatile memory circuits, and the non-volatile memory cell may include a predetermined number of non-volatile memory circuits, and the volatile and non-volatile memory circuits may be deployed within a single register. Therefore, the effect of integrating non-volatile registers and volatile registers is achieved.

[0020] Furthermore, a second aspect of this technology is a momentary power outage countermeasure system, comprising: a detection circuit configured to detect a power supply voltage drop below a second threshold value; and a semiconductor chip including volatile memory cells, non-volatile memory cells, a write processing unit, a read processing unit, and a save / restore processing unit. The write processing unit is configured to write write data to the same address in both the volatile and non-volatile memory cells. The read processing unit is configured to read data from the address of the volatile memory cell as first read data and to read data from the address of the non-volatile memory cell as second read data. The save / restore processing unit is configured to perform a save process when the power supply voltage drops below the second threshold value, wherein the save process writes the first read data to the address in the non-volatile memory cell where the corresponding second read data does not match the first read data. Therefore, the effect of reducing inrush current during save operations in response to a power supply drop is achieved.

[0021] Furthermore, in the second aspect, the instantaneous power failure countermeasure system may also include an energy harvester; and a power control unit configured to supply power from the energy harvester to the detection circuit when the power supply voltage drops below a first threshold higher than the second threshold. Thus, the need for rollback processing is eliminated.

[0022] Furthermore, in the second aspect, the momentary power outage countermeasure system may also include a battery, wherein the power control unit is configured to supply power to the semiconductor chip from at least one of the energy harvester and the battery when the power supply voltage drops below a first threshold. Thus, the effect of continuing power supply even in situations of insufficient ambient energy is achieved. Attached Figure Description

[0023] Figure 1 This is a block diagram illustrating an example configuration of a semiconductor chip according to a first embodiment of the present technology.

[0024] Figure 2 This is a block diagram illustrating an example configuration of a digital signal processing unit according to a first embodiment of the present technology.

[0025] Figure 3 This is a block diagram illustrating a configuration example of a non-volatile register file according to a first embodiment of the present technology.

[0026] Figure 4 This is a block diagram illustrating a configuration example of a volatile register file according to a first embodiment of the present technology.

[0027] Figure 5 This is a circuit diagram illustrating an example configuration of a non-volatile register according to a first embodiment of the present technology.

[0028] Figure 6 This is a circuit diagram illustrating an example configuration of a volatile register according to a first embodiment of the present technology.

[0029] Figure 7 This is a diagram illustrating an example of a signal list according to a first embodiment of the present technology.

[0030] Figure 8 This is a flowchart illustrating an example of a write process according to a first embodiment of the present technology.

[0031] Figure 9 This is a flowchart illustrating an example of a read process according to a first embodiment of the present technology.

[0032] Figure 10 This is a flowchart illustrating an example of a save / restore process according to a first embodiment of the present technology.

[0033] Figure 11 This is a flowchart illustrating another example of the save / restore process according to a first embodiment of the present technology.

[0034] Figure 12 This is a block diagram illustrating an example configuration of a storage unit in a variation of the first embodiment of the present technology.

[0035] Figure 13This is a block diagram illustrating an example of register configuration in a variation of the first embodiment of the present technology.

[0036] Figure 14 This is a block diagram illustrating an example configuration of an embedded register in a variation of the first embodiment of the present technology.

[0037] Figure 15 This is a diagram illustrating an example of control signal settings in a variation of the first embodiment of the present technology.

[0038] Figure 16 This is a diagram illustrating the conditions under which each signal becomes "1" in a variation of the first embodiment of the present technology.

[0039] Figure 17 This is a timing diagram illustrating an example of the clock signal waveform and the operation of the digital signal processing unit in a variation of the first embodiment of the present technology.

[0040] Figure 18 This is a block diagram illustrating an example configuration of a storage unit according to a second embodiment of the present technology.

[0041] Figure 19 This is a block diagram illustrating a configuration example of a power-off recovery compatible central processing unit (CPU) system according to a second embodiment of the present technology.

[0042] Figure 20 This is a diagram illustrating an example configuration of a BN register according to a second embodiment of the present technology, the BN register including a non-volatile register or non-volatile memory in which read verification is performed until a write is successful.

[0043] Figure 21 This is a diagram illustrating an example configuration of the BN register in a variation of a second embodiment of the present technology, the BN register including a non-volatile register or non-volatile memory in which read verification is performed until a write is successful.

[0044] Figure 22 This is a block diagram illustrating a configuration example of a power-off recovery compatible CPU system according to a third embodiment of the present technology.

[0045] Figure 23 This is a diagram illustrating a list of registers according to a third embodiment of the present technology.

[0046] Figure 24 This is a block diagram illustrating an example configuration of a storage unit according to a third embodiment of the present technology.

[0047] Figure 25 This is a block diagram illustrating an example configuration of a memory cell in the case where non-volatile registers and volatile registers are integrated, according to a third embodiment of the present technology.

[0048] Figure 26 This is a block diagram illustrating an example configuration of a storage unit in a variation of a third embodiment of the present technology.

[0049] Figure 27 This is a block diagram illustrating a configuration example of a power-off recovery compatible CPU system in a variation of the third embodiment of the present technology.

[0050] Figure 28 This is a block diagram illustrating an example configuration of a non-volatile memory according to a fourth embodiment of the present technology.

[0051] Figure 29 This is a block diagram illustrating an example configuration of a volatile memory according to a fourth embodiment of the present technology.

[0052] Figure 30 This is a block diagram illustrating a configuration example of a power-off recovery compatible CPU system according to a fourth embodiment of the present technology.

[0053] Figure 31 This is a block diagram illustrating a configuration example of a momentary power outage countermeasure system according to a fifth embodiment of the present technology.

[0054] Figure 32 This is a diagram illustrating an example of the implementation of a momentary power outage countermeasure system according to a fifth embodiment of the present technology.

[0055] Figure 33 This is a block diagram illustrating a configuration example of a momentary power outage countermeasure system in a variation of the fifth embodiment of the present technology.

[0056] Figure 34 This is a diagram illustrating an example of the implementation of a momentary power outage countermeasure system in a variation of the fifth embodiment of the present technology. Detailed Implementation

[0057] The following describes the methods used to implement this technology (hereinafter referred to as embodiments). The descriptions will be given in the following order.

[0058] 1. First embodiment (example of saving data to an address where the read data does not match)

[0059] 2. Second embodiment (example of saving data to an address in the execution memory where the data does not match)

[0060] 3. Third embodiment (example of saving data to an address in the CPU register file where the data does not match)

[0061] 4. Fourth embodiment (example of providing shared and non-shared resources and saving data to an address where the read data does not match)

[0062] 5. Fifth embodiment (example of saving data to an address where the read data does not match in response to a power drop)

[0063] <1. First Embodiment>

[0064] [Semiconductor chip configuration example]

[0065] Figure 1 This is a block diagram illustrating an example configuration of a semiconductor chip 200 according to a first embodiment of the present technology. The semiconductor chip 200 is a CMOS image sensor (CIS) and includes a vertical drive circuit 211, a timing control unit 212, a digital-to-analog converter (DAC) 213, and a pixel array unit 214. Furthermore, the semiconductor chip 200 includes a column signal processing unit 215, a horizontal transmission control unit 216, and a digital signal processing unit 220.

[0066] In pixel array unit 214, multiple pixels are arranged in a two-dimensional grid pattern. Vertical drive circuit 211 sequentially selects rows in pixel array unit 214, drives each pixel in the selected row, and causes an analog signal to be output to column signal processing unit 215.

[0067] The timing control unit 212 controls the operation timing of the vertical drive circuit 211, DAC 213, column signal processing unit 215 and horizontal transmission control unit 216 respectively.

[0068] DAC 213 generates a sawtooth ramp signal through digital-to-analog (DA) conversion and supplies the signal to column signal processing unit 215.

[0069] In the column signal processing unit 215, an analog-to-digital converter (ADC) is arranged for each column of the pixel array unit 214. The ADC converts the analog signal from the corresponding column into a digital signal and supplies the digital signal to the digital signal processing unit 220 in accordance with the control of the horizontal transmission control unit 216.

[0070] The horizontal transmission control unit 216 controls the column signal processing unit 215 to output digital signals for each column in sequence.

[0071] The digital signal processing unit 220 performs various signal processing operations, such as white balance correction and depixelation, on the digital signals from the column signal processing unit 215. This digital signal processing unit 220 outputs processed image data.

[0072] [Configuration example of a digital signal processing unit]

[0073] Figure 2This is a block diagram illustrating a configuration example of a digital signal processing unit 220 according to a first embodiment of the present technology. The digital signal processing unit 220 includes an external setting input / output interface 221, an external setting non-volatile register set 222, and a power-off recovery compatible CPU system 300.

[0074] The external setting input / output interface 221 receives data from the outside for performing initial settings or changing settings during operation, and maintains this data in the external setting non-volatile register group 222. Furthermore, the external setting input / output interface 221 transmits data read from the external setting non-volatile register group 222 to the outside.

[0075] The power-off recovery compatible CPU system 300 saves data when the power supply voltage drops and restores the data when the power supply voltage is restored. This power-off recovery compatible CPU system 300 includes an access control unit 310 and a storage unit 400. The storage unit 400 may include a frame memory, etc. Details regarding the provision of a frame memory will be described later in the fifth embodiment.

[0076] The access control unit 310 includes a write processing unit 311, a read processing unit 312, and a save / restore processing unit 313. The storage unit 400 includes a non-volatile register file 410 and a volatile register file 450.

[0077] Note that although non-volatile register file 410 and volatile register file 450 are used in the figure, volatile and non-volatile memory can also be used instead. For example, a combination of static random access memory (SRAM) and non-volatile RAM or a combination of dynamic random access memory (DRAM) and non-volatile RAM can be used. Furthermore, magnetic memory can be used as a non-volatile memory, for example. Spin-torque torque (STT)-magnetoresistive random access memory (MRAM) can be used as a magnetic memory, for example. Moreover, the memory is not limited to STT-MRAM, and other novel magnetic memories such as voltage-controlled magnetic anisotropy (VCMA)-MRAM and spin-orbit torque (SOT)-MRAM can be used.

[0078] Furthermore, non-volatile register file 410 is an example of a non-volatile memory unit as described in the claims, and volatile register file 450 is an example of a non-volatile memory unit as described in the claims.

[0079] The details of the individual processes performed by the write processing unit 311, the read processing unit 312, and the save / restore processing unit 313 will be described later.

[0080] Note that the power-off recovery compatible system, which has the same functions as the power-off recovery compatible CPU system 300, can be set independently in the automatic exposure (AE) control unit outside the digital signal processing unit 220. In this case, the power-off recovery compatible system in the AE control unit performs the recovery operation after a power failure independently of the power-off recovery compatible CPU system 300, corresponding to the user settings.

[0081] Furthermore, although the power-down recovery compatible CPU system 300 is deployed within the semiconductor chip 200 that acts as a CIS, the configuration is not limited to this. The power-down recovery compatible CPU system 300 can also be deployed within various semiconductor chips other than a CIS.

[0082] [Configuration example of a non-volatile register file]

[0083] Figure 3 This is a block diagram illustrating a configuration example of a non-volatile register file 410 according to a first embodiment of the present technology. The non-volatile register file 410 includes an address decoder 411, a non-volatile register group 412, and an output selector 413. In the non-volatile register group 412, K non-volatile registers 420 (where K is an integer greater than or equal to 2) are arranged. Each non-volatile register 420 is assigned an address ADDR. NV .

[0084] Address ADDR from access control unit 310 NV It is input into address decoder 411. Address decoder 411 inputs address ADDR. NV Decode and generate a K-bit one-hot signal DEC. Within the one-hot signal DEC, only the signal corresponding to address ADDR is included. NV The first bit is set to logic value "1", while the remaining bits are set to logic value "0". The address decoder 411 outputs the one-hot signal DEC to the non-volatile register group 412 and the output selector 413.

[0085] Note that the address ADDR from the access control unit 310... NV If the range is exceeded, the address decoder 411 can output a one-hot signal DEC in which all bits are set to the logic value "0".

[0086] Output selector 413 selects one of the non-volatile register output signals NVQ from each non-volatile register 420 based on the one-hot signal DEC. Output selector 413 selects the signal corresponding to the bit with a logic value of "1" in the one-hot signal DEC and outputs the selected signal to the volatile register file 450.

[0087] Note that when all bits of the hot-only signal DEC are set to logic value "0", the output selector 413 can output the previous value as is, perform some selections, or output a predetermined constant.

[0088] [Example of volatile register file configuration]

[0089] Figure 4 This is a block diagram illustrating a configuration example of a volatile register file 450 according to a first embodiment of the present technology. The volatile register file 450 includes an address decoder 451, a volatile register group 452, an output selector 453, and a comparator 454. K volatile registers 460 are arranged in the volatile register group 452. Each volatile register 460 is assigned the address ADDR. V .

[0090] In addition, the volatile register set 452 provides volatile registers for each address ADDR. V Keep one tag.

[0091] Address decoder 451 is configured to access address ADDR V Decode the signal to generate a K-bit one-hot signal DEC, and output the one-hot signal DEC to the volatile register group 452 and the output selector 453.

[0092] Output selector 413 selects one of the volatile register output signals VQ from each volatile register 460 based on the one-hot signal DEC. Output selector 413 selects the signal corresponding to the bit with a logic value of "1" in the one-hot signal DEC and outputs the selected signal to comparator 454.

[0093] Comparator 454 compares the non-volatile register output signal NVQ from non-volatile register file 410 with the volatile register output signal VQ from output selector 453. Comparator 454 supplies a comparison result signal CMP_OUT, indicating the comparison result, to volatile register group 452.

[0094] [Example of non-volatile register configuration]

[0095] Figure 5This is a circuit diagram illustrating a configuration example of a non-volatile register 420 according to a first embodiment of the present technology. DEC[k] from the address decoder 411, the access control signal R / W from the access control unit 310, the data input signal D, the register save enable signal REN, and the clock signal CK are input to the non-volatile register 420. Furthermore, the volatile register output signal VQ and the tag bit TAG from the volatile register file 450 are input to the non-volatile register 420. The non-volatile register 420 outputs the non-volatile register output signal NVQ to the volatile register file 450 and the output selector 413.

[0096] DEC[k] represents the k-th bit of the one-hot signal DEC (where k is an integer from 1 to K) and is input to the k-th non-volatile register 420.

[0097] The access control signal R / W is used to indicate whether there is no write or a write operation. For example, during a read-no-write period, the access control signal R / W is set to the logic value "0", while during a write operation, the access control signal R / W is set to the logic value "1".

[0098] The data input signal D indicates the data to be written to non-volatile register 420 and volatile register 460. The size of the data to be written is defined as J bits (where J is an integer).

[0099] The volatile register output signal VQ indicates the read data read from the volatile register 460 in the volatile register file 450. The size of this read data is also defined as J bits. Note that the volatile register output signal VQ is an example of the first read data described in the claims.

[0100] The tag bit TAG is a signal that indicates the write status of the corresponding non-volatile register 420. For example, when no write is performed on the non-volatile register 420 (in other words, the initial state) or when the write is completed, the logic value "0" is set to the initial value of the corresponding tag bit TAG, while when a temporary write is performed, the logic value "1" is set.

[0101] The register save enable signal REN is a signal that indicates whether the function of saving from volatile register 460 to non-volatile register 420 is enabled. For example, when disabled, the register save enable signal REN is set to the logical value "0", and when enabled, the register save enable signal REN is set to the logical value "1".

[0102] The non-volatile register output signal NVQ indicates the read data read from the non-volatile register 420. Note that the non-volatile register output signal NVQ is an example of the second read data described in the claims.

[0103] Here, the K addresses ADDR on the non-volatile side NV and the K addresses of the volatile side ADDR V They are linked one-to-one. The volatile register output signal VQ and the tag bit TAG from the k-th volatile register 460 are input to the k-th non-volatile register 420. The non-volatile register output signal NVQ from the k-th non-volatile register 420 is output to the k-th volatile register 460 and the output selector 413.

[0104] In addition, the nonvolatile register 420 includes logic product (AND) gates 421 and 422, selectors 423 and 424, and a nonvolatile multi-bit flip-flop 425.

[0105] AND gate 421 outputs the logical product of the access control signal R / W and the k-th bit DEC[k] of the hot-only signal to selector 423.

[0106] Selector 423 selects the output signal of AND gate 421 when the register save enable signal REN is set to logic value "0", and selects the tag bit TAG when the register save enable signal REN is set to logic value "1", and outputs the selected signal to AND gate 422.

[0107] AND gate 422 outputs the logical product of the output signal of selector 423 and the clock signal CK to the clock terminal of non-volatile multi-bit flip-flop 425.

[0108] Selector 423 selects the data input signal D when the register save enable signal REN is set to logic value "0", and selects the volatile register output signal NQ when the register save enable signal REN is set to logic value "1", and outputs the selected signal to the input terminal of the non-volatile multi-bit flip-flop 425.

[0109] The non-volatile multi-bit flip-flop 425 holds the output signal of the selector 424. The non-volatile multi-bit flip-flop 425 has a size of J bits. Furthermore, the signal held by the output of the non-volatile multi-bit flip-flop 425 serves as the non-volatile register output signal NVQ.

[0110] Using the configuration shown in the figure, the following operations are implemented. First, the description register stores the case where the enable signal REN is disabled. In this case, with R / W set to the logic value "1" indicating a write operation and DEC[k] set to the logic value "1" (i.e., the k-th address is selected), the non-volatile register 420 at that address writes the data input signal D to the non-volatile multi-bit flip-flop 425. The "1" R / W pulse during this write is called the write pulse P1. If the condition is not met, the non-volatile register 420 retains its previous value.

[0111] Next, the case where the register save enable signal REN is enabled will be described. In this case, with the tag bit TAG from the k-th volatile register 460 set to the logic value "1", the k-th non-volatile register 420 writes VQ from the volatile register 460 to the non-volatile multi-bit flip-flop 425. Referring to the write pulse during this write as P2, at least one of the pulse width and voltage of P2 is greater than P1. The pulse width and voltage of write pulse P2 are set to values ​​that result in a 100% successful write. Note that write pulses P1 and P2 are examples of the first and second write pulses described in the claims.

[0112] Furthermore, after a write operation during storage, the access control unit 310 reads data from the volatile register 460 and the non-volatile register 420, determines whether the data matches each other, and repeats the rewrite until the data matches each other. Note that the non-volatile multi-bit flip-flop 425 constantly outputs the stored value, and if the stored value is updated, the updated value is reflected in the output signal starting from the next cycle immediately following the write cycle.

[0113] [Example of volatile register configuration]

[0114] Figure 6 This is a circuit diagram illustrating a configuration example of a volatile register 460 according to a first embodiment of the present technology. DEC[k] from the address decoder 411, the access control signal R / W, the data input signal D, the register recovery signal REST from the access control unit 310, and the clock signal CK are input to the volatile register 460. Furthermore, the non-volatile register output signal NVQ from the non-volatile register file 410 and the comparison result signal CMP_OUT from the comparator 454 are input to the volatile register 460. The volatile register 460 then outputs the volatile register output signal VQ to the non-volatile register file 410 and the output selector 453. Additionally, the volatile register 460 outputs the tag bit TAG to the non-volatile register file 410.

[0115] The comparison result signal CMP_OUT is a signal indicating whether the read data of non-volatile register 420 and the read data of the corresponding volatile register 460 match each other. For example, if the read data match each other, the comparison result signal CMP_OUT is set to the logic value "1", and if the read data do not match each other, the comparison result signal CMP_OUT is set to the logic value "0".

[0116] The register restore signal REST is a signal indicating whether a write (in other words, a restore) should be performed from the non-volatile register 420 to the corresponding volatile register 460 after a save. For example, the register restore signal REST is set to the logic value "1" when a restore is performed, and to the logic value "0" when no restore is performed.

[0117] In addition, the volatile register 460 includes AND gates 461 to 464, logic gates 465 and 466, OR (logic AND) gate 467, selector 468, volatile multi-bit flip-flop 469 and 1-bit flip-flop 470.

[0118] AND gate 461 outputs the logical product of the access control signal R / W and the k-th bit DEC[k] of the hot-only signal to OR gate 467.

[0119] The OR gate 467 outputs the register recovery signal REST to the AND gate 462 and the output signal of the AND gate 461, which are logically summed.

[0120] AND gate 462 outputs the logic product of the output signal of OR gate 467 and the clock signal CK to the clock terminal of volatile multi-bit flip-flop 469.

[0121] Selector 468 selects the data input signal D when the register recovery signal REST has a logic value of "0", and selects the non-volatile register output signal NVQ when the register recovery signal REST has a logic value of "1", and outputs the selected signal to the input terminal of the volatile multi-bit flip-flop 469.

[0122] The volatile multi-bit flip-flop 469 holds the output signal of the selector 468. The volatile multi-bit flip-flop 469 has a size of J bits. Furthermore, the signal held by the volatile multi-bit flip-flop 469 is output as the volatile register output signal VQ.

[0123] Logic gate 466 outputs the inverted value of the access control signal R / W to logic gate 465 and the logical product of the k-th bit DEC[k] of the one-hot signal.

[0124] Logic gate 465 obtains the inverted value of clock signal CK, the logical product of comparison result signal CMP_OUT and output signal of logic gate 466, and outputs the logical product and the logical sum of register recovery signal REST to 1-bit flip-flop 470.

[0125] AND gate 464 outputs the logical product of the access control signal R / W and the k-th bit DEC[k] of the hot-only signal to AND gate 463.

[0126] AND gate 463 inputs the logic product of the output signal of AND gate 464 and the clock signal CK to the clock terminal of 1-bit flip-flop 470.

[0127] The 1-bit flip-flop 470 is volatile and holds the tag bit TAG. A high level (i.e., a logic value "1") is input to the set terminal S of the 1-bit flip-flop 470. Additionally, the inverted value of the output signal of logic gate 465 is input to the reset terminal R of the 1-bit flip-flop 470. Furthermore, in the 1-bit flip-flop 470, the input to the reset terminal R takes precedence in determining the output value. Furthermore, the 1-bit flip-flop 470 outputs the tag bit TAG to the non-volatile register file 410.

[0128] Using the configuration shown in the diagram, the following operations are implemented. First, the case where the register recovery signal REST is disabled will be described. In this case, with R / W having a logic value "1" indicating a write operation and DEC[k] having a logic value "1", the volatile register 460 writes the data input signal D to the volatile multi-bit flip-flop 469 and updates the 1-bit flip-flop 470 to the logic value "1". Furthermore, with R / W set to a logic value "0" indicating a read operation and DEC[k] set to a logic value "1", during the period when the clock signal CK is "0", the volatile register 460 initializes the 1-bit flip-flop 470 to the logic value "0", provided that the comparison result signal CMP_OUT is set to the logic value "1". If these conditions are not met, the volatile register 460 retains its previous value.

[0129] Next, the case where the register recovery signal REST is enabled will be described. In this case, volatile register 460 writes the non-volatile register output signal NVQ of non-volatile register 420 with the same DEC[k] to volatile multi-bit flip-flop 469, and initializes 1-bit flip-flop 470 to the logic value "0".

[0130] Figure 7 This is a diagram illustrating an example of a signal list according to a first embodiment of the present technology. In the diagram, reference is made to... Figure 5 and Figure 6 The signal names and descriptions of the above signals are summarized.

[0131] [Semiconductor chip operation example]

[0132] Next, we will refer to Figures 8 to 10 This describes the operation of a power-off recovery compatible CPU system 300. Write and read requests are generated by executing various programs within the power-off recovery compatible CPU system 300. The order of writes and reads, as well as the timing of the requests, are determined based on the program content and processing conditions. In the case of generating a write request, the following steps are executed: Figure 8 Write processing, and in the event of generating a read request without accompanying write, execute... Figure 9 The reading process. Furthermore, in situations requiring data saving, such as during interruptions, task switching, or power voltage drops, the process is executed. Figure 10 Save / restore process.

[0133] However, it is assumed that the device provided with semiconductor chip 200 is equipped with an auxiliary power supply, which will be described later, and that the power supply from the auxiliary power supply continues for a certain period of time even when the power supply voltage drops, and that the power supply is not interrupted during data storage.

[0134] Figure 8 This is a flowchart illustrating an example of a write process according to a first embodiment of the present technology. The write processing unit 311 within the power-off recovery compatible CPU system 300 uses a write pulse P1 to write write data to the same address in the volatile register file 450 and the non-volatile register file 410 (step S901).

[0135] For example, when setting the k-th volatile side address ADDR V When specified as the write destination, the same write data is written to this address and the corresponding k-th non-volatile side address ADDR. NV .

[0136] In addition, the write processing unit 311 updates the tag bit corresponding to the address of the access destination to the logical value "1" (step S902) and ends the write process.

[0137] Figure 9 This is a flowchart illustrating an example of a read process according to a first embodiment of the present technology. The read processing unit 312 within the power-off recovery compatible CPU system 300 reads data from the same address in the volatile register file 450 and the non-volatile register file 410 as read data (step S911).

[0138] For example, when setting the k-th volatile side address ADDR V When specified as the read source, from this address and the corresponding k-th non-volatile side address ADDR NVRead the data. The data read on the volatile side corresponds to the volatile register output signal VQ mentioned above, and the data read on the non-volatile side corresponds to the non-volatile register output signal NVQ mentioned above.

[0139] Comparator 454 in volatile register file 450 determines whether the read data (VQ) on the volatile side and the read data (NVQ) on the non-volatile side match each other (step S912).

[0140] If the read data matches each other (yes in step S912), the read processing unit 312 updates the tag bit of the access destination to the logical value "0" (step S913). If the read data does not match each other (no in step S912), or after step S913, the read processing unit 312 ends the read processing.

[0141] Note that, in addition to Figure 8 and Figure 9 In addition to the processes shown, the access control unit 310 can also perform the following processes. For example, the access control unit 310 checks the tag bits of the volatile register file 450 at regular intervals, and in cases where a tag bit has a logic value of "1", the access control unit 310 performs adjustments such as gradually increasing the voltage or extending the write pulse width up to the upper limit of the time period corresponding to the frequency. Then, the access control unit 310 uses the adjusted higher voltage or longer write pulse width to write the data at the address where the tag bit in the volatile register file 450 has a logic value of "1" to the non-volatile register file 410. Then, the access control unit 310 clears the tag bit that has been written to a logic value of "0".

[0142] Here, when all tag bits are set to logic value "0", the access control unit 310 can store the voltage and write pulse width in non-volatile memory and use them as default values ​​later. When a logic value "1" appears in the tag bit value, the access control unit 310 can perform an additional update. Therefore, this achieves the effect of appropriately selecting a low voltage and short write pulse width for stable writing based on the chip's operating state, rather than writing at a voltage or write pulse width that has already been successfully written to 100%.

[0143] Figure 10 This is a flowchart illustrating an example of save / restore processing according to a first embodiment of the present technology. The save / restore processing unit 313 within the power-off recovery compatible CPU system 300 specifies the address of the access destination (step S921) and determines whether the tag bit of that address is set to the logical value "1" (step S922).

[0144] When the tag bit is set to the logic value "1" (yes in step S922), the save / restore processing unit 313 writes the read data (VQ) from the volatile register 460 to the non-volatile register 420 via the write pulse P2 under high voltage (step S923).

[0145] For example, at the k-th address ADDR on the specified non-volatile side NV And if the corresponding k-th tag bit is a logic value "1", then the k-th address ADDR on the volatile side will be... V Read data (VQ) write address ADDR NV .

[0146] If the tag bit is set to a logic value "0" (No in step S922), or after step S923, the save / restore processing unit 313 determines whether all addresses have been specified (step S924). If not all addresses have been specified (No in step S924), the save / restore processing unit 313 repeats the processing from step S921 and subsequent steps. Furthermore, as described later, all data corresponding to the address group with a logic value "1" on the volatile side's tag bit can be written to the corresponding same address group on the non-volatile side in a single operation using a high voltage.

[0147] If all addresses have been specified (yes in step S924), the save / restore processing unit 313 determines whether it is a recovery timing, such as when the power supply voltage rises (step S925). If it is not a recovery timing (no in step S925), the save / restore processing unit 313 returns to step S925.

[0148] If the recovery timer is set (Yes in step S925), the save / recovery processing unit 313 specifies the access target address (step S926).

[0149] The save / restore processing unit 313 writes the read data (NVQ) from the non-volatile register 420 at the specified address into the corresponding volatile register 460 (step S927) and updates the tag bit of that address to the logical value "1" (step S928).

[0150] Then, the save / restore processing unit 313 determines whether all addresses have been specified (step S929). If not all addresses have been specified (no in step S929), the save / restore processing unit 313 repeats the processing from step S926 onwards and subsequent steps. Furthermore, as described later, all data corresponding to all address groups on the non-volatile side can be written to the corresponding same address groups on the volatile side in a single operation.

[0151] If all addresses have been specified (yes in step S929), the save / restore processing unit 313 ends the save / restore process.

[0152] Alternatively, the save / restore processing unit 313 can also perform this function. Figure 11 The save / restore process is shown below. The save / restore processing unit 313 determines whether the operation is a save operation (step S921) or a restore operation (step S922). If it is determined to be a save operation (yes in step S921), the save / restore processing unit 313 writes all data corresponding to the address group where the tag bit on the volatile side has a logic value "1" to the corresponding address group on the non-volatile side in a single operation with a high voltage (step S923). If it is determined to be a restore operation (yes in step S922), the save / restore processing unit 313 writes all data corresponding to all address groups on the non-volatile side to the corresponding address groups on the volatile side in a single operation (step S924). If neither condition applies (no in steps S921 and S922), the save / restore processing unit 313 neither performs a save operation nor a restore operation.

[0153] like Figure 10 and Figure 11 As shown, during the save period, VQ is written to addresses in the non-volatile register file 410 where the non-volatile side read data (NVQ) and volatile side read data (VQ) do not match. Therefore, compared to the case where data is written to all addresses on the non-volatile side during the save period, the inrush current during the save period is reduced.

[0154] Furthermore, by using a write pulse P2 with a voltage and pulse width greater than that of the write pulse P1 during the write period, write errors can be minimized compared to using P1 for the write operation. During the write period prior to the save, stable writing at voltages and pulse widths suitable for the chip's operating state is achieved by using P1 with a voltage or pulse width lower than that of P2 or a shorter pulse width, and power consumption can be reduced.

[0155] Furthermore, even when a write pulse P1 is used during storage, a method to minimize write errors by copying the non-volatile register file 410 can be considered, as described in Japanese Patent Application Publication No. 2018-021577. However, using this method, copying leads to an increase in the area and power consumption of the non-volatile register file 410. Conversely, in the first embodiment where data is written using a write pulse P2 during storage, copying is not required. Therefore, the effect of minimizing write errors while reducing the area and power consumption of the non-volatile register file 410 is achieved compared to Japanese Unexamined Patent Application Publication No. 2018-021577.

[0156] As described above, according to the first embodiment of this technology, the save / restore processing unit 313 writes data to addresses in the non-volatile register file 410 where the read data does not match during the save period. Therefore, the effect of reducing inrush current during the save period is achieved.

[0157] [Variation Example]

[0158] In the first embodiment described above, the non-volatile register 420 and the volatile register 460 are deployed separately; however, they can also be integrated. The semiconductor chip 200 in the variation of the first embodiment differs from that in the first embodiment in that both non-volatile and volatile memory circuitry are provided within a single register.

[0159] Figure 12 This is a block diagram illustrating an example configuration of the storage unit 400 in a variant of the first embodiment of the present technology. The storage unit 400 in the variant of the first embodiment includes an address decoder 411, a register group 414, and an output selector 413. K registers 500 are arranged in the register group 414, each register being assigned an address ADDR.

[0160] In a variation of the first embodiment, the address decoder 411 decodes the address ADDR from the access control unit 310, generates a one-hot signal DEC, and outputs the one-hot signal DEC to the register group 414 and the output selector 413.

[0161] The output selector 413 selects any one of the output signals of the independent thermal signal DEC register 500 and outputs the selected signal to the access control unit 310.

[0162] Figure 13 This is a block diagram illustrating an example configuration of register 500 in a variation of the first embodiment of the present technology. Register 500 includes AND gates 511 to 514, logic gates 515 and 516, an embedded register 520, and a 1-bit flip-flop 517.

[0163] AND gate 511 outputs the logical product of the access control signal R / W and the k-th bit DEC[k] of the hot-only signal to AND gate 512.

[0164] AND gate 512 outputs the logical product of the output signal of AND gate 511 and the frequency divider clock signal CK_DIV as the clock signal C to the clock terminal of embedded register 520.

[0165] Here, the frequency-divided clock signal CK_DIV is obtained by dividing the source clock signal CK. The source clock signal CK before frequency division is used in the circuitry outside register 500.

[0166] The data input signal D, control signal CTRL, recovery control signal SR1, storage control signal SR2, verification recovery control signal SR3, control signal LPGS, and control signal LPGB from the access control unit 310 are input to the embedded register 520. Furthermore, the embedded register 520 outputs the register output signal Q to the output selector 413 and outputs the comparison result signal CMP_OUT to the logic gate 516.

[0167] Logic gate 515 outputs the logical product of the inverted value of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal to logic gate 516.

[0168] Logic gate 516 determines the inverted value of clock signal CK, the logical product of comparison result signal CMP_OUT and output signal of logic gate 515, and outputs the logical product and register recovery signal REST to 1-bit flip-flop 517.

[0169] AND gate 514 outputs the logical product of the access control signal R / W and the k-th bit DEC[k] of the hot-only signal to AND gate 513.

[0170] AND gate 513 inputs the logical product of the output signal of AND gate 514 and the divided clock signal CK_DIV to the clock terminal of 1-bit flip-flop 517.

[0171] A 1-bit flip-flop 517 holds the tag bit TAG. A high level (i.e., a logic value "1") is input to the set terminal S of the 1-bit flip-flop 517. Furthermore, during the period when the clock signal CK is "0", the inverted value of the output signal of logic gate 516 is input to the reset terminal R of the 1-bit flip-flop 517. Additionally, in the 1-bit flip-flop 517, the value input to the reset terminal R preferentially determines the output value. Furthermore, the 1-bit flip-flop 517 outputs the tag bit TAG to the output selector 413.

[0172] Figure 14This is a block diagram illustrating an example configuration of an embedded register 520 in a variation of the first embodiment of the present technology. The embedded register 520 includes p-channel MOS (pMOS) transistors 521 to 529, negation logic product (NAND) gates 531 to 536, inverters 541 to 544, and transmission gates 551 to 554. Furthermore, the embedded register 520 includes n-channel MOS (nMOS) transistors 560 to 569, non-volatile memory circuitry 570, an OR gate 581, and a negation exclusive logic AND (XOR NOT) gate 582.

[0173] The non-volatile memory circuit 570 is a non-volatile circuit that holds 1 bit, and magnetic tunnel junction (MTJ) elements 571 and 572 are deployed within the circuit.

[0174] Inverter 541 inverts the data input signal D and outputs the inverted signal to transmission gate 551.

[0175] When the clock signal C is low and the inversion signal CB is high, the transmission gate 551 outputs the output signal of the inverter 541 to the NAND gate 533.

[0176] NAND gate 533 outputs the negative logical product of the set signal SN from access control unit 310 and the wired OR of the output signals of transmission gates 551 and 552 to transmission gate 553 and NAND gate 535.

[0177] NAND gate 535 outputs the logical product of the output signal of NAND gate 533 and the negative logic product of the reset signal CN from access control unit 310 to transmission gate 552.

[0178] When the clock signal C is low and the inversion signal CB is high, the transmission gate 552 outputs the output signal of the NAND gate 535 to the NAND gate 533.

[0179] When the clock signal C is low and the inversion signal CB is high, the transmission gate 553 outputs the output signal of the NAND gate 533 to the NAND gate 534.

[0180] NAND gate 534 outputs the negative logic product of the reset signal CN from access control unit 310 and the output signals of each of transmission gates 553 and 554 to XOR gate 582, inverter 543 and NAND gate 536.

[0181] The pMOS transistor 523 is inserted between the power supply voltage and the power supply terminal of the NAND gate 534, and the control signal LPGS is input to its gate.

[0182] Inverter 543 inverts the output signal of NAND gate 534 and outputs the inverted signal as register output signal Q.

[0183] NAND gate 536 outputs the negative logic product of the set signal SN and the output signal of NAND gate 534 to transmission gate 554.

[0184] The pMOS transistor 524 is inserted between the power supply voltage and the power supply terminal of the NAND gate 536, and the control signal LPGS is input to its gate.

[0185] When the clock signal C is low and the inversion signal CB is high, the transmission gate 554 outputs the output signal of the NAND gate 536 to the NAND gate 534.

[0186] When the recovery control signal SR1 is set to logic value "1", nMOS transistor 565 is short-circuited between NAND gates 536 and 534.

[0187] The circuit including inverters 541 and 543, transmission gates 551 to 554, NAND gates 533 to 536, pMOS transistors 523 and 524, and nMOS transistor 565 is called volatile memory circuit 530. Volatile memory circuit 530 is used as a flip-flop to hold a volatile 1 bit.

[0188] NAND gate 531 outputs the negative logic product of the output signal of MTJ element 571 and the set signal SN to NAND gate 532 and XOR gate 582.

[0189] pMOS transistor 521 is inserted between the power supply voltage and the power supply terminal of NAND gate 531, and control signal LPGB is input to its gate.

[0190] NAND gate 532 outputs the negative logic product of the output signal of NAND gate 531 and the reset signal CN to NAND gate 531.

[0191] pMOS transistor 522 is inserted between the power supply voltage and the power supply terminal of NAND gate 532, and control signal LPGB is input to its gate.

[0192] The output of the XOR gate 582, the output signal of the NAND gate 531, and the output signal of the NAND gate 534 are negated and excluded logically summed as the comparison result signal CMP_OUT.

[0193] When the verification recovery control signal SR3 is set to logic value "1", nMOS transistor 566 short-circuits between the connection node of NAND gates 531 and 532 and the reference layer of MTJ element 572.

[0194] The circuit described above, including pMOS transistors 521 and 522, NAND gates 531 and 532, XOR gate 582, and nMOS transistor 566, is used as comparator 580.

[0195] OR gate 581 outputs the logic sum of the recovery control signal SR1, the storage control signal SR2, and the verification recovery control signal SR3 to the gate of nMOS transistor 563.

[0196] pMOS transistor 529 and nMOS transistors 562 and 533 are connected in series between the power supply voltage and the ground voltage, with pMOS transistor 529 located on the power supply side.

[0197] The control signal CTRL is input to the gates of pMOS transistor 529 and nMOS transistor 562. The connection nodes of pMOS transistor 529 and nMOS transistor 562 are connected together to the free layer of MTJ elements 571 and 572.

[0198] Inverter 542 inverts the storage control signal SR2 and outputs the inverted signal to the gate of pMOS transistor 527.

[0199] pMOS transistors 527 and 528 and nMOS transistors 560 and 561 are connected in series between the power supply voltage and the ground voltage, with pMOS transistors 527 and 528 located on the power supply side.

[0200] The storage control signal SR2 is input to the gate of nMOS transistor 561. The gates of pMOS transistor 528 and nMOS transistor 560 are connected together to the connection nodes of transmission gates 553 and 554. Furthermore, the connection nodes of pMOS transistor 528 and nMOS transistor 560 are connected to the reference layer of MTJ element 572.

[0201] When the recovery control signal SR1 is set to logic value "1", the nMOS transistor 564 is short-circuited between the output terminal of the NAND gate 536 and the reference layer of the MTJ element 571.

[0202] When the recovery control signal SR1 is set to logic value "1", the nMOS transistor 569 is short-circuited between the output terminal of the NAND gate 534 and the reference layer of the MTJ element 572.

[0203] Inverter 544 inverts the storage control signal SR2 and outputs the inverted signal to the gate of pMOS transistor 525.

[0204] pMOS transistors 525 and 526 and nMOS transistors 567 and 568 are connected in series between the power supply voltage and the ground voltage, with pMOS transistors 525 and 526 located on the power supply side.

[0205] The gates of pMOS transistor 526 and nMOS transistor 567 are connected together to the connection nodes of NAND gates 534 and 536. The connection nodes of pMOS transistor 526 and nMOS transistor 567 are connected to the reference layer of MTJ element 571. Furthermore, the storage control signal SR2 is input to the gate of nMOS transistor 568.

[0206] The circuit shown in the figure is from Japanese Unexamined Patent Application Publication No. 2021-68488. Figure 8 This is described in [the document]. Note that, apart from [the document's description], [the rest of the text is missing]. Figure 8 Other circuits can also be applied to the embedded register 520.

[0207] Figure 15 This is a diagram illustrating an example of control signal settings in a variation of the first embodiment of the present technology. When the access control unit 310 performs a write-back from a non-volatile 1 bit to a volatile 1 bit (in other words, register recovery), the logic value "1" is set only to SR1, one of the recovery control signal SR1, the storage control signal SR2, and the verification recovery control signal SR3.

[0208] Furthermore, if the access control unit 310 performs a write operation from a volatile 1 bit to a non-volatile 1 bit before or during saving, the logic value "1" is set only to SR2.

[0209] Furthermore, when embedded register 520 reads and compares data from volatile 1 bit and non-volatile 1 bit, only the logic value "1" is set to SR3.

[0210] Figure 16 This is a diagram illustrating the conditions under which each signal becomes "1" in a variation of the first embodiment of the present technology.

[0211] When the logical product of the divider clock signal CK_DIV and the register recovery signal REST is set to the logical value "1" when the access control unit 310 performs register recovery, the logical value "1" is set to the control signal CTRL.

[0212] Furthermore, consider the case where the access control unit 310 performs storage to a non-volatile bit (in other words, write). In this case, the logic value "1" is set to the control signal CTRL when the inverted value of the logical sum of CK_DIV and the source clock signal CK, the write control signal W, the inverted value of the storage signal STR, and the logical product of DEC[k] are set to the logic value "1".

[0213] Consider the case where the access control unit 310 executes the save to non-volatile bit. In this case, the logic value "1" is set to the control signal CTRL when the inverted value of the logical sum of CK_DIV and CK, the logical product of the storage signal STR and the tag bit TAG is set to the logic value "1".

[0214] Consider the case where embedded register 520 reads and compares non-volatile bits and volatile bits. In this case, the logic value "1" is set to the control signal CTRL when the exclusive logical sum of CK_DIV and CK, the inverted value of the read control signal R, and the logical product of DEC[k] are set to the logic value "1".

[0215] When the access control unit 310 performs register recovery and the logical product of CK_DIV and the register recovery signal REST is set to the logical value "1", the logical value "1" is set to the recovery control signal SR1.

[0216] When the access control unit 310 executes the storage to non-volatile bit and the logical product of the inverted value of CK_DIV, W, the inverted value of STR and DEC[k] is set to the logical value "1", the logical value "1" is set to the storage control signal SR2.

[0217] When the access control unit 310 performs the save to non-volatile bit and the inverted value of CK_DIV, the logical product of STR and TAG is set to the logical value "1", the logical value "1" is set to the storage control signal SR2.

[0218] Consider the case where embedded register 520 reads and compares volatile and non-volatile bits. In this case, with the exclusive logical sum of CK_DIV and CK, the inverted value of R, and the logical product of DEC[k] set to the logical value "1", the logical value "1" is set to the verification and restoration control signal SR3.

[0219] When the access control unit 310 performs register recovery and the logical product of the inverted value of CK, CK_DIV, the inverted value of R and DEC[k] is set to the logical value "1", the logical value "1" is set to the control signal LPGS.

[0220] When embedded register 520 reads and compares the volatile and non-volatile bits, and the logical product of CK, CK_DIV, and REST is set to the logical value "1", the logical value "1" is set to the control signal LPGB.

[0221] Figure 17Figure 1 is a timing diagram illustrating an example of the clock signal waveform and operation of a digital signal processing unit in a variation of the first embodiment of the present technology. Figure 2a is a timing diagram illustrating an example of the waveforms of the source clock signal CK and the divided clock signal CK_DIV. Figure 2b is a timing diagram illustrating an example of the operation of the digital signal processing unit 220.

[0222] As shown in Figure a, the frequency-divided clock signal CK_DIV is generated by dividing the source clock signal CK by two.

[0223] Furthermore, as shown in Figure b, the access control unit 310 in the digital signal processing unit 220 performs a write operation (i.e., a storage operation) during the time period from timing T0 to T3. For example, a high-level data input signal D is written to both the volatile memory circuit 530 and the non-volatile memory circuit 570, and a high-level output signal Q is output from the embedded register 520. Additionally, the access control unit 310 controls the reset signal CN and the set signal SN to a high level, transmits a pulse of the storage control signal SR2 at timing T1, and transmits a pulse of the control signal CTRL at timing T2.

[0224] Then, during the time period from time T3 to T6, the access control unit 310 performs a read, during which the embedded register 520 compares the bit read from the volatile memory circuit 530 with the bit read from the non-volatile memory circuit 570. At time T4, the access control unit 310 transmits the pulses of the control signal CTRL, the verification and restoration control signal SR3, and the control signal LPGB. Then, if a mismatch exists, the embedded register 520 outputs a low-level comparison result signal CMP_OUT at time T5.

[0225] When the sleep period of reducing power supply voltage begins at timer T6, the access control unit 310 sets the control signal LPGB to a high level.

[0226] When the sleep period ends at time T7, the access control unit 310 supplies pulses to CTRL, pulses to the recovery control signal SR1, and pulses to the control signal LPGS, and performs recovery processing.

[0227] Figures 8 to 10 The processing shown can be performed by Figures 12 to 17 The circuit configuration and control shown are used to achieve this.

[0228] As described above, in a variation of the first embodiment of the present technology, since both the volatile memory circuit 530 and the non-volatile memory circuit 570 are deployed within a single register 500, it is no longer necessary to provide separate volatile registers and non-volatile registers.

[0229] <2. Second Embodiment>

[0230] In the first embodiment described above, data is saved to a non-volatile register file 410; however, a non-volatile memory comprising multiple memory banks may also be provided, and data may be saved to the memory bank in operation. The semiconductor chip 200 in this second embodiment differs from that in the first embodiment in that data is saved to the memory bank in operation among the multiple memory banks.

[0231] Figure 18 This is a block diagram illustrating a configuration example of a storage cell 400 according to a second embodiment of the present technology. The storage cell 400 in the second embodiment includes a non-volatile memory 430 and a volatile memory 480. The non-volatile memory 430 includes an address decoder 431, a memory bank number decoder 432, a memory cell array 433, and an output selector 434. In the memory cell array 433, a plurality of memory cells (not shown) are arranged in a two-dimensional grid pattern. The memory cell array 433 is divided into N (where N is an integer greater than or equal to 2) non-volatile memory banks 435.

[0232] Address decoder 431 pairs address ADDR NV Decode the signal and generate a K-bit one-hot signal DEC. A The address decoder 431 supplies the hot-swappable signal DEC to the memory cell array 433 and the output selector 434. A .

[0233] The memory bank number decoder 432 decodes the memory bank number BN from the access control unit 310 and generates an N-bit unique hotspot signal DEC. B The memory bank number BN indicates the number of the executing memory bank among N memory banks. Furthermore, of the N bits, only the bit corresponding to the memory bank number BN is set to the logic value "1", and the remaining bits are set to the logic value "0". The memory bank number decoder 432 supplies a unique signal DEC to the memory cell array 433 and the output selector 434. B .

[0234] Output selector 434 is based on the uniquely heated DEC signal. A and DEC B This selector 434 selects any one of the non-volatile register output signals NVQ for each memory cell. The output selector is associated with the one-hot signal DEC. B The non-volatile memory bank 435 corresponding to the bit with a logic value of "1" is selected, and the unique hot signal DEC is selected from that memory bank. AThe memory cell corresponding to the bit with a logic value of "1" is then selected. The output selector 434 then outputs the output signal (NVQ) of the selected memory cell to the volatile memory 480.

[0235] On the other hand, it is assumed that the array of memory cells (not shown) within the volatile memory 480 is not divided into multiple memory banks. Furthermore, similar to the first embodiment, the volatile memory 480 maintains a tag bit for each address. Additionally, the memory capacity of each non-volatile memory bank 435 is the same as the memory capacity of the volatile memory 480.

[0236] Figure 19 This is a block diagram illustrating a configuration example of a power-down recovery compatible CPU system 300 according to a second embodiment of the present technology. The power-down recovery compatible CPU system 300 differs from the first embodiment in that it further includes a BN register 320 and a memory switching control unit 314 is further deployed within the access control unit 310.

[0237] The memory switching control unit 314 switches the executing memory as needed. The memory switching control unit 314 maintains the memory number BN of the executing memory in the BN register 320.

[0238] In the second embodiment, the write processing unit 311 refers to the BN register 320 to obtain the memory bank number BN of the memory bank in operation, and writes the write data to the same address of the volatile memory 480 and the memory bank in operation.

[0239] Furthermore, the read processing unit 312 references the BN register 320 to obtain the memory bank number BN of the memory bank in operation, and reads and compares the read data from the volatile memory 480 and the memory bank in operation. Then, for the volatile memory 480, if the read data does not match, the volatile memory 480 is controlled to update the corresponding tag bit to the logic value "1".

[0240] The save / restore processing unit 313 performs a save operation on the memory bank in cases such as task switching caused by an interrupt handler or a drop in power supply voltage. In this save operation, the save / restore processing unit 313 uses a write pulse P2 to write read data from the same address in the volatile memory 480 to the address whose corresponding tag bit is set to a logic value "1" among all addresses in the memory bank being processed. Specifically, in the event of a power supply voltage drop, the save / restore processing unit 313 performs a comparison of the read data as a verification operation after each write operation, and repeats the write and verification operations if a mismatch exists until the write operation is complete.

[0241] Note that in the second embodiment, it is assumed that task switching of the operating system (OS) kernel is not performed. The configuration for when task switching of the OS kernel is performed will be described later.

[0242] The save / restore processing unit 313 performs a restore process when interrupt processing by the interrupt handler ends or when the power supply voltage rises. In this restore process, the save / restore processing unit 313 writes data read from all addresses of the target memory to be restored into the volatile memory 480. The target memory is the memory indicated by the memory number BN updated by the interrupt during interrupt processing, or the memory in the process of restore processing, such as when the power supply voltage rises. Each tag bit is initialized to the logic value "0". The save / restore processing unit 313 performs a comparison of the read data as a verification operation after each write operation, and repeats the write and verification operations if a mismatch exists until the write operation is complete.

[0243] It should be noted that although the non-volatile memory 430 is divided into multiple memory banks, the configuration is not limited to this. A non-volatile register file or non-volatile RAM can also be divided into multiple memory banks and used as a save destination.

[0244] Figure 20 This is a diagram illustrating an example configuration of the BN register 320 according to a second embodiment of the present technology. The BN register 320 includes a BN1 register and a BN2 register. Each register is, for example, 16 bits in size.

[0245] Here, for simplicity, interrupt numbers are set to, for example, 1 to 15. Furthermore, a fixed priority scheme is used, with higher interrupt numbers indicating higher interrupt priorities. Note that a polling scheme can be used instead of a fixed priority scheme.

[0246] Furthermore, HE01 to HE15, which enable / disable memory access for each interrupt number, are assigned bits 1 to 15 of the BN1 register. When the corresponding memory access is disabled, logic value "0" is set in all of HE01 to HE15, and logic value "1" is set when the memory access is enabled. Bit 0 of the BN1 register is reserved.

[0247] In addition, the BN2 register has a field that holds the memory bank with BNE enabled and a field that holds the memory bank number BN of the memory bank in execution.

[0248] The size of the memory enable BNE is, for example, 2 bits. When memory access is disabled for all interrupts, binary "00" is set in the memory enable BNE. Furthermore, when memory access is enabled for all interrupts except Unmasked Interrupts (NMI), binary "01" is set in the memory enable BNE. When the enabling or disabling of memory access follows the setting of the BN1 register, binary "11" is set in the memory enable BNE. For the memory enable BNE, the value of binary "10" is reserved.

[0249] Furthermore, the memory bank number BN field holds either the memory bank number of the executing memory bank or the starting address of the executing memory bank. Here, for simplicity, we assume the number of memory banks is 16, and that the interrupt number corresponds to the memory bank number. Note that memory bank number "0" is assigned to initialization processes performed, for example, during a period from startup to the point before interrupt acceptance.

[0250] Here, even when a write pulse P1 is used during storage, it is conceivable to minimize write errors by copying each bank of the non-volatile memory 430, as described in Japanese Unexamined Patent Application Publication No. 2018-021577. However, in this method, copying increases the area and power consumption of the non-volatile memory 430. In contrast, in the second embodiment, data is written during storage via a high-voltage write pulse P2, eliminating the need to copy the bank. Therefore, the effect of minimizing write errors while reducing the area and power consumption of the non-volatile memory 430 is achieved compared to Japanese Unexamined Patent Application Publication No. 2018-021577.

[0251] Furthermore, in the second embodiment, when data is saved to the memory bank, mismatched addresses are written to all addresses within that memory bank. Therefore, in the same manner as in the first embodiment, the effect of reducing inrush current during saving is also achieved in the multi-memory bank configuration.

[0252] As described above, according to the second embodiment of this technology, the save / restore processing unit 313 writes data to all addresses in the memory bank where mismatched addresses exist during the save to memory bank process. Therefore, in a multi-memory bank configuration, the effect of reducing inrush current during save is also achieved.

[0253] [Variation Example]

[0254] In the second embodiment described above, task switching performed by the OS kernel is not supported; however, the configuration is not limited to this. The semiconductor chip 200 in the variant of the second embodiment differs from that in the second embodiment in that it also supports task switching performed by the OS kernel.

[0255] Figure 21 Figure 3 is a diagram illustrating an example configuration of the BN register 320 in a variation of the second embodiment of the present technology. Figure a illustrates an example of the data structure of the BN register 320, and figure b illustrates an example configuration of the associated memory.

[0256] As shown in Figure a, the BN register 320 in the variation of the second embodiment includes a BN1 register, a BN(i) sub-register, a BN2 register, and an associated memory BN0. i is an integer from 0 to 15. The data size of the BN1 register, the BN(i) sub-register, and the BN2 register is, for example, 16 bits.

[0257] Here, for simplicity, hardware interrupt numbers are set from 1 to 15, and OS interrupt numbers are set from 1 to 255. Higher numbers indicate higher interrupt priorities, and hardware interrupts have higher priorities than OS interrupts. A fixed priority scheme is used between hardware interrupts and between OS interrupts, but a polling scheme can also be used.

[0258] Each interrupt number is set to enable or disable memory access. HE1 through HE15 are assigned to bits 1 through 15 of the BN1 register, and OSE1 through OSE255 are assigned to the corresponding bits of the 16 BN1(i) sub-registers.

[0259] When the corresponding memory bank is disabled, the logic value "0" is set in HE01 to HE15, and when the corresponding memory bank is enabled, the logic value "1" is set. Bit 0 of the BN1 register is a reserved bit.

[0260] When the corresponding memory bank is disabled, the logic value "0" is set in all of OSE1 to OSE255, and when the memory bank is enabled, the logic value "1" is set in it. The 0th bit of the BN1(0) sub-register is a reserved bit.

[0261] In addition, the BN2 register has a field that holds the memory bank with BNE enabled and a field that holds the memory bank number BN of the memory bank in execution.

[0262] The size of the memory enable BNE is, for example, 2 bits. When memory use is disabled for all interrupts, the binary value "00" is set in the memory enable BNE. Conversely, when memory use is enabled for all interrupts except NMI, the binary value "01" is set in the memory enable BNE. When the enabling or disabling of memory use follows the settings of the BN1 register and the BN(i) sub-register, the binary value "11" is set in the memory enable BNE. For the memory enable BNE, the binary value "10" is retained.

[0263] In addition, the storage bank number BN field retains either the storage bank number of the executing storage bank or the starting address of the executing storage bank.

[0264] Here, for simplicity, we assume the number of memory banks is 272, and that, for example, among memory bank numbers 0 to 271, memory bank numbers 1 to 15 correspond to hardware interrupt numbers, and memory bank numbers 17 to 271 correspond to OS interrupt numbers. Memory bank number 0 is allocated, for example, to initialization processes from startup to interrupt acceptance, and to initialization processes before OS startup. Memory bank number 16 is allocated, for example, to processes from OS startup until task execution begins.

[0265] Associative memory BN0 is a memory used to store task numbers as additional interrupt numbers during task switching performed by the OS kernel.

[0266] As shown in b in the figure, the associated memory BN0 includes 255 non-volatile registers 321, volatile registers 322, and encoders 323.

[0267] The memory switching control unit 314 can store (in other words, register) task numbers in all 255 non-volatile registers 321. OS interrupt numbers 1 to 255 correspond to the corresponding addresses of these non-volatile registers 321. Furthermore, the memory switching control unit 314 can generate query search data for one of the specified non-volatile registers 321 and maintain the query search data in the volatile register 322. The encoder 323 outputs the address of the non-volatile register 321 that matches the query search data as the corresponding OS interrupt number. Note that when using a fixed priority scheme, the priority of the task number can be changed by altering the register address of the task number.

[0268] Using the configuration shown in the figure, the memory switching control unit 314 can use the associated memory BN0 to convert the task number into an OS interrupt number. Then, if memory access is permitted, the memory switching control unit 314 can cause the BN register 320 to retain the memory number of the memory corresponding to the OS interrupt number as the memory in execution.

[0269] Furthermore, the save / restore processing unit 313 can perform save processing not only when a task switch occurs by an interrupt handler or a drop in power supply voltage occurs, but also when a task switch occurs by the OS kernel.

[0270] As described above, in a variation of the second embodiment of the present technology, since the BN(i) sub-register and associated memory BN0 are added to the BN register 320, task switching via the OS kernel can be supported.

[0271] <3. Third Embodiment>

[0272] In the first embodiment described above, a non-volatile register file 410 and a volatile register file 450 are provided; however, these can also be used as CPU register files within the CPU. The semiconductor chip 200 in the third embodiment differs from that in the first embodiment in that the non-volatile register file 410 and the volatile register file 450 are used as CPU register files.

[0273] Figure 22 This is a block diagram illustrating a configuration example of a power-off recovery compatible CPU system 300 according to a third embodiment of the present technology. The power-off recovery compatible CPU system 300 in the third embodiment includes a program read-only memory (ROM) 331, a data save / restore sequencer 332, an instruction fetch decoder 333, an address arithmetic circuit 334, a storage unit 400, and an arithmetic circuit 335.

[0274] The storage unit 400 in the third embodiment includes a non-volatile register file 410 and a volatile register file 450, as in the first embodiment. These are used as CPU register files.

[0275] The program to be executed by the CPU is stored in program ROM 331.

[0276] The data save / restore sequencer 332 performs data save and restore processes in the event of a power supply voltage drop, a task switch caused by an interrupt handler, or periodically. Detection signals and interrupt numbers are input to the data save / restore sequencer 332. The detection signals include a power drop detection signal indicating a power drop and a power rise detection signal indicating a power rise. The save and restore processes performed by the data save / restore sequencer 332 are similar to those described in the first embodiment.

[0277] The instruction fetch decoder 333 fetches and decodes instructions from the program ROM 331. The instruction fetch decoder 333 obtains the access control signal R / W and the address of the access destination by decoding the instructions indicating write or read, and supplies them to the memory unit 400.

[0278] The address arithmetic circuit 334 obtains the address of the register file by decoding the instructions.

[0279] Arithmetic circuit 335 performs various arithmetic operations as needed. This arithmetic circuit 335 supplies initial value data or data obtained through arithmetic operations to the storage unit 400 as write data. Furthermore, arithmetic circuit 335 receives read data from the storage unit 400 and performs various arithmetic operations on the read data.

[0280] Using the configuration shown in the diagram, the following can be achieved: Figure 2 Each function of the access control unit 310 shown.

[0281] Figure 23 This is a diagram illustrating a register list according to a third embodiment of the present technology. At least some of the registers shown in the figure are deployed in each of non-volatile register file 410 and volatile register file 450.

[0282] For example, general-purpose registers, stack pointer registers, program counter registers, save program counter registers, processor status word registers, and save status registers can be used. Additionally, procedure registers, multiplication registers, base registers, vector base registers, read buffer registers, and write buffer registers can also be used.

[0283] General purpose registers R0 to R n-2 It is a register that can be used as both an address register and a data register.

[0284] The stack pointer register SP is a register that indicates a stackable address within the stack region. For example, R n-1 It can be used as the SP (Service Pack). The Program Counter (PC) register is a register that indicates the address of the instruction executed by the CPU. The Save Program Counter (BPC) register is used to save the program counter when a general exception or interrupt request is received. The Processor Status Word (PSW) register is a status register that stores the result of instruction execution and the CPU's status. The Save Status Word (BPSW) register is used to save the PSW when a general exception or interrupt request is received.

[0285] The procedure register PR is used to store the return address during a subroutine call. The multiplication registers MACH and MACL are used to store the results of multiplication and multiplication-accumulation operations. The base register GBR is used to store the base address in indirect addressing mode. The vector base register VBR is used to store the base address of the exception handler. The read buffer register RDR is used to store data read from memory. The write buffer register WDR is used to store data to be written to memory.

[0286] Furthermore, in the third embodiment, the following implementation schemes can be used as the CPU configuration.

[0287] First, in the interrupt vector scheme, the BN register 320 and the interrupt vector are configured by non-volatile registers such as non-volatile multi-bit registers. The access control unit 310 repeatedly writes and reads to verify until the write is successful. Furthermore, similar non-volatile registers are also included in the control registers associated with access to the non-volatile memory.

[0288] Next, in interrupt execution with an interrupt number not permitted by BN register 320, the program is executed using only volatile registers. Assume that a processor restart triggered by an interrupt caused by a power-up detection signal is executed upon recovery from power-off. In the case of a single register, since no interrupt number is assigned, a control register is installed in memory unit 400 to store the interrupt number involving access to non-volatile memory.

[0289] Furthermore, consider the scenario where execution continues from a program context that has experienced a power interruption. In this case, control and status registers for reaching the context can be configured within memory unit 400, located within the I / O peripherals, direct memory access (DMA) controller, and interrupt controller. These control and status registers can be used... Figure 3 and Figure 4 The proposed scheme or a non-volatile memory scheme that involves repeated write and read verification until a successful write is achieved can be implemented.

[0290] In addition, the BN register 320 may have fields for specifying the following three items for each memory bank. The first is a field that can specify whether interrupt numbers are enabled or disabled. When all are disabled, only volatile memory is used to execute the program.

[0291] The second is a field used to specify whether to enable or disable task switching interrupts by registering the task number used in task switching performed by the OS kernel as an additional interrupt number in associated memory.

[0292] Third is the BN field. In the case of a register file, the BN value is used as a memory bank number specification, and in the case of high-speed scratchpad or main memory, the BN value is used as the starting address of the memory bank.

[0293] Figure 24 This is a block diagram illustrating an example configuration of a storage unit 400 according to a third embodiment of the present technology. As shown, the non-volatile register file 410 includes, for example, general-purpose registers R0 to R10. n-2And the stack pointer register SP. In addition, non-volatile register file 410 includes the program counter register PC, processor status word register PSW, procedure register PR, base address register GBR, and vector base address register VBR. Volatile register file 450, except for R0 to R... n-2 In addition to SP, PC, PSW, PR, GBR, and VBR, a tag bit TAG is also maintained for each register.

[0294] As described above, by using the non-volatile register file 410 and the volatile register file 450 as CPU register files, inrush current during storage can be reduced in a single-task CPU.

[0295] Note that, as Figure 25 As shown, a variation of the first embodiment in which non-volatile registers and volatile registers are integrated can be applied to the third embodiment.

[0296] As described above, according to the third embodiment of the present technology, since the non-volatile register file 410 and the volatile register file 450 are used as CPU register files, the effect of reducing inrush current during storage is achieved in a single-task CPU.

[0297] [Variation Example]

[0298] In the third embodiment described above, data is saved to a non-volatile register file 410; however, a non-volatile memory comprising multiple memory banks may also be provided, and data is saved to the executing memory bank. The semiconductor chip 200 in the variation of the third embodiment differs from that in the third embodiment in that data is saved to the executing memory bank among the multiple memory banks.

[0299] Figure 26 This is a block diagram illustrating an example configuration of the storage unit 400 in a modified embodiment of the present technology. The storage unit 400 in the modified embodiment includes a non-volatile memory 430 and a volatile memory 480. The non-volatile memory 430 includes N non-volatile memory banks 435.

[0300] For example, both volatile memory 480 and non-volatile memory bank 435 include registers R0 to R10. n-2 SP, PC, PSW, PR, GBR, and VBR. In addition, the volatile memory 480 includes a tag bit (TAG) for each register.

[0301] Figure 27This is a block diagram illustrating a configuration example of a power-off recovery compatible CPU system 300 in a variation of the third embodiment of the present technology. The power-off recovery compatible CPU system 300 in the variation of the third embodiment differs from that in the third embodiment in that the power-off recovery compatible CPU system 300 includes a data save / restore / memory switching sequencer 336, replacing the data save / restore sequencer 332.

[0302] In addition to performing data saving and recovery processing, the data save / recovery / memory switching sequencer 336 also performs memory switching. Within the data save / recovery / memory switching sequencer 336, the BN register 320 (not shown) described in the variant of the second embodiment is arranged.

[0303] In addition to the detection signal and interrupt number in the third embodiment, the OS task number is also input to the data save / restore / storage switching sequencer 336.

[0304] When an interrupt number or OS task number is input to the data save / restore / memory switching sequencer 336, the sequencer compares the priority of these numbers with the priority of the interrupt number (hardware interrupt number or OS interrupt number) corresponding to BN in the BN2 register. If the input number has a higher priority, the sequencer selects the memory corresponding to that number as the memory to be executed, and performs data save processing, restore processing, and memory switching.

[0305] On the other hand, when the input number has a low priority, the data save / restore / storage switching sequencer 336 waits for the completion of the process corresponding to the currently executing BN before proceeding to the switching of the storage bank corresponding to the input number. Alternatively, the data save / restore / storage switching sequencer 336 does not accept interrupt nesting. Alternatively, the data save / restore / storage switching sequencer 336 can accept interrupt nesting and handle interrupt nesting by storing its number in a first-in-first-out (FIFO) manner.

[0306] Furthermore, upon receiving a detection signal indicating a drop or rise in the power supply voltage, the data save / restore / memory switching sequencer 336 performs save and restore processes in the same manner as in the second embodiment with a multi-memory configuration.

[0307] As described above, in a variation of the third embodiment of the present technology, since the data save / restore / memory switching sequencer 336 switches the memory and saves the data during interrupts or the like, the effect of reducing the inrush current during saving in a multitasking CPU is achieved.

[0308] <4. Fourth Embodiment>

[0309] In the second embodiment described above, the non-volatile memory 430 is configured as a multi-bank structure; however, in main memory or high-speed temporary storage, the memory can be shared by multiple entities. The semiconductor chip 200 in the fourth embodiment differs from that in the second embodiment in that shared resources are provided in both the volatile memory 480 and the non-volatile memory 430.

[0310] Figure 28 This is a block diagram illustrating a configuration example of the non-volatile memory 430 according to a fourth embodiment of the present technology. The non-volatile memory 430 in the fourth embodiment includes a non-volatile memory shared resource 441 and a non-volatile memory non-shared resource 442. Note that the address decoders and output selectors within each resource are omitted in the figure.

[0311] Non-volatile shared memory resource 441 is a memory region that holds shared data shared by multiple entities (such as tasks and interrupt handlers). Non-volatile non-shared memory resource 442 is a memory region that holds data that is not part of the shared data and includes N non-volatile non-shared memory banks 443. Note that instead of non-volatile memory, a non-volatile register file can be configured in a multi-bank structure to provide non-volatile shared resources and non-shared memory banks.

[0312] Note that the non-volatile shared memory resource 441 is an example of the non-volatile shared resource described in the claims. The non-volatile non-shared memory bank 443 is an example of the non-volatile non-shared memory bank described in the claims.

[0313] Figure 29 This is a block diagram illustrating a configuration example of volatile memory 480 according to a fourth embodiment of the present technology. The volatile memory 480 in the fourth embodiment includes a shared volatile memory resource 481 and a non-shared volatile memory resource 482. Note that the address decoders and output selectors within each resource are omitted in the figure.

[0314] Volatile memory shared resource 481 is a memory region that holds shared data, and volatile memory non-shared resource 482 is a memory region that holds data that is not part of the shared data. Note that a volatile register file can also be used instead of volatile memory to provide both volatile shared and non-shared resources.

[0315] Furthermore, the size and number of addresses of the volatile memory shared resource 481 and the non-volatile memory shared resource 441 are the same. The size and number of addresses of the volatile memory non-shared resource 482 are the same as the size and number of addresses of each of the non-volatile memory non-shared memory blocks 443.

[0316] Note that volatile memory shared resource 481 is an example of a volatile shared resource as described in the claims. Volatile memory non-shared resource 482 is an example of a volatile non-shared resource as described in the claims.

[0317] Figure 30 This is a block diagram illustrating a configuration example of a power-down recovery compatible CPU system 300 according to a fourth embodiment of the present technology. The power-down recovery compatible CPU system 300 in the fourth embodiment includes a program ROM 331, a data save / restore / memory switching sequencer 336, an instruction fetch decoder 333, an address arithmetic circuit 334, and an arithmetic circuit 335. Furthermore, the power-down recovery compatible CPU system 300 includes a volatile memory shared resource address assignment register 340, a non-volatile memory shared resource 441, and a non-volatile memory non-shared resource 442. Additionally, the power-down recovery compatible CPU system 300 includes a volatile memory shared resource 481, a volatile memory non-shared resource 482, an address converter 337, a data path 338, and an address path 339.

[0318] Non-volatile memory non-shared resource 442 has the multi-bank configuration described above, and each register in the CPU register file (such as the program counter register) can be deployed in the respective memory bank and non-volatile memory non-shared resource 482. Furthermore, volatile memory shared resource 481 and volatile memory non-shared resource 482 maintain a tag bit for each address.

[0319] Address translator 337 can be implemented as a combinational circuit with flip-flop outputs. Alternatively, address translator 337 can be implemented as a register file or SRAM, in which interrupt numbers are used as addresses to register the starting address of non-volatile, non-shared memory 443. Address translator 337 can perform address translation using an address translation mechanism within the number of cycles required to transfer data via the bus.

[0320] The initial value of the starting address of the volatile memory shared resource 481 is stored in the volatile memory shared resource address specification register 340.

[0321] Furthermore, when an interrupt number or OS task number is entered, the data save / restore / storage switching sequencer 336 executes the reference. Figure 27The data saving, recovery, and storage switching processes described above.

[0322] Note that the data save / recovery / memory switching sequencer 336 can also perform data save processing periodically. For example, the data save / recovery / memory switching sequencer 336 checks the tag bits of the volatile memory at regular intervals, and writes data from the volatile memory to the non-volatile memory at the address where the tag bit has a logic value of "1" while gradually increasing the voltage of the write pulse. Then, the data save / recovery / memory switching sequencer 336 confirms whether the read data matches each other, clears the tag bits of the completed write to a logic value of "0", and can stop increasing the voltage at the voltage when all bits have been successfully written.

[0323] Furthermore, upon receiving a detection signal indicating a drop or rise in the power supply voltage, the data save / restore / memory switching sequencer 336 performs save and restore processes in the same manner as in the second embodiment with a multi-memory configuration. Therefore, even in the event of a write error to the non-volatile memory, recovery is achieved during power outages in a multitasking environment.

[0324] As described above, shared data is managed by volatile memory shared resource 481 and non-volatile memory shared resource 441, while other data is managed by volatile memory non-shared resource 482 and non-volatile memory non-shared memory 443. Therefore, the consistency of public data within shared resources is ensured.

[0325] It should be noted that the fourth embodiment can also be applied to the third embodiment.

[0326] In this way, according to the fourth embodiment of the present technology, since both shared and non-shared resources are provided in both volatile memory 480 and non-volatile memory 430, memory can be utilized more efficiently.

[0327] <5. Fifth Embodiment>

[0328] In the second embodiment with a multiple memory bank configuration described above, the semiconductor chip 200 performs data saving and recovery processing when the power supply voltage drops, provided that an auxiliary power supply is available. An energy harvester can be used as an auxiliary power supply, for example. The instantaneous power outage countermeasure system in the fifth embodiment differs from that in the second embodiment in that it utilizes an energy harvester.

[0329] Figure 31This is a block diagram illustrating a configuration example of a momentary power outage countermeasure system 100 according to a fifth embodiment of the present technology. The momentary power outage countermeasure system 100 includes a power drop / rise detection circuit 110, a semiconductor chip 200, a power control unit 120, and an energy harvester 130. The momentary power outage countermeasure system 100 shown in the figure is applied to devices such as industrial cameras.

[0330] Power supply drop / rise detection circuit 110 detects that the power supply voltage has dropped below the threshold voltage V. lw2 The value. Furthermore, the power supply drop / rise detection circuit 110 detects that the power supply voltage has risen above the threshold V. high1 The value of . As described above, the detection signal includes a power drop detection signal and a power rise detection signal. The power drop / rise detection circuit 110 supplies a power drop detection signal to the semiconductor chip 200 when a power drop is detected, and supplies a power rise detection signal to the semiconductor chip 200 when a power rise is detected. Note that the power drop / rise detection circuit 110 is an example of the detection circuit described in the claims.

[0331] The power control unit 120 detects when the power supply voltage drops to a threshold V. lw1 In the following cases, power is supplied from the energy harvester 130 to the power drop / rise detection circuit 110. Here, the threshold V... lw1 It is above the threshold V lw2 The value of . Note that the threshold V lw1 This is an example of the first threshold described in the claim, and the threshold V lw2 This is an example of the second threshold described in the claim.

[0332] Energy harvester 130 converts energy generated in the surrounding environment, such as light, heat and vibration, into electrical energy.

[0333] Furthermore, it is assumed that the semiconductor chip 200 in the fifth embodiment maintains a power-off non-volatile flag in a non-volatile register or memory. The initial value of this power-off non-volatile flag is initialized to a logic value of "0" upon first startup.

[0334] Figure 32 This is a diagram illustrating an example implementation of a momentary power outage countermeasure system 100 according to a fifth embodiment of the present technology. The momentary power outage countermeasure system 100 includes diodes 141 to 144, pMOS transistors 151 and 152, capacitors 161 and 162, a power supply drop / rise detection circuit 110, a semiconductor chip 200, a power control unit 120, and an energy harvester 130.

[0335] The anode of diode 141 is connected to the power supply voltage, and the cathode is connected to the power supply drop / rise detection circuit 110. The anode of diode 142 is connected to pMOS transistor 151, and the cathode is connected to the power supply drop / rise detection circuit 110.

[0336] The anode of diode 143 is connected to the power supply voltage and power supply drop / rise detection circuit 110, and the cathode is connected to capacitor 161 and semiconductor chip 200. The anode of diode 144 is connected to pMOS transistor 152, and the cathode is connected to capacitor 161 and semiconductor chip 200.

[0337] pMOS transistors 151 and 152 are connected in series between diodes 142 and 144. The gate of pMOS transistor 151 is connected to the power supply voltage, and the gate of pMOS transistor 152 is connected to the power supply drop / rise detection circuit 110. Furthermore, the connection node of pMOS transistors 151 and 152 is connected to the power control unit 120. Capacitor 162 is connected to the connection node between the power control unit 120 and the energy harvester 130.

[0338] First, when the power supply voltage drops to the threshold V lw1 In the following conditions, pMOS transistor 151 switches to the on state, and power control unit 120 begins to supply power from energy harvester 130 to power drop / rise detection circuit 110.

[0339] Furthermore, when the power supply voltage drops to the threshold V lw2 In the following cases, the power drop / rise detection circuit 110 detects a power drop and turns the pMOS transistor 152 to the on state. Therefore, power supply to the semiconductor chip 200 begins from the energy harvester 130.

[0340] Upon receiving the power drop detection signal, the semiconductor chip 200 performs the aforementioned data saving process and updates the power-off non-volatile flag to the logic value "1". This power-off non-volatile flag is initialized to the logic value "0" when the power supply voltage rises.

[0341] During the storage period, semiconductor chip 200 suspends instruction fetching by the CPU and completes CPU pipeline execution. During this period, necessary memory updates are performed.

[0342] Then, during the save process, as described above, the semiconductor chip 200 writes data from the volatile register file 450 to the non-volatile register file 410 via write pulse P2, to the address at which its tag bit is set to the logical value "1". After a successful write, the semiconductor chip 200 clears the tag bit of that address to the logical value "0".

[0343] Then, upon completion of the write operation, the memory switching control unit 314 within the semiconductor chip 200 notifies the save / restore processing unit 313 of the completion. The save / restore processing unit 313 notifies the power-down / up detection circuit 110 of the write completion, and this circuit causes the pMOS transistor 152 to switch to an off state, thereby resulting in a power-off state.

[0344] Then, when the power supply voltage rises above the threshold V high1 In the event of a power-down / power-up detection, the power-up detection circuit 110 detects this and notifies the semiconductor chip 200 of a power-up detection signal. Upon receiving the power-up detection signal, the semiconductor chip 200 activates the restart process and checks the power-down non-volatile flag. If the power-down non-volatile flag is set to logic "1", the semiconductor chip 200 writes back the value of the non-volatile memory bank specified by the BN register 320 to the volatile memory. On the other hand, if the power-down non-volatile flag is set to logic "0", the semiconductor chip 200 executes a normal restart sequence accompanied by the initialization of the BN register 320. Here, it is assumed that the program used to perform the above processing is stored in the non-volatile memory and executed on that memory.

[0345] Using the transient power failure countermeasure system 100 shown in the figure, rollback processing is not required when the CPU program resumes, and unauthorized re-execution can be eliminated. Furthermore, checkpoint insertion for rollback processing in the CPU program can be eliminated. In other words, adding checkpoint code becomes unnecessary.

[0346] Next, the processing specific to the case where CIS is used as semiconductor chip 200 will be described.

[0347] First, regarding the register settings of the digital signal processing unit 220, these register settings are implemented in non-volatile memory and are configured to repeatedly read and verify and rewrite until the writing is complete, in preparation for power failure. Furthermore, after the power supply voltage rises, when the startup process checks the power-off non-volatile flag, if the power-off non-volatile flag is at logic value "1", it takes no action and performs initial setting processing.

[0348] Next, regarding the line memory used for image data storage, since frame synchronization is essential, the CIS continues processing from the new frame after a restart, either discarding or overwriting the line memory. Therefore, there is no issue that the line memory is volatile. The CIS initializes the line memory in the restart handler after power restoration, regardless of the value of the non-volatile flag after power failure.

[0349] Next, consider the case where a frame memory for accumulating pixel data is installed. In this case, the CIS arranges the frame memory within storage unit 400 and performs simultaneous writes to both volatile and non-volatile frame memories. Each time the frame memory is read in subsequent processing, the CIS compares the read data and updates the tag bit. When a frame of data has been accumulated in the frame memory, the CIS sets the frame accumulation flag to a logic value "1" and clears it to a logic value "0" when a new write occurs. Furthermore, if power is interrupted during signal processing after a frame of data has been accumulated in the frame memory, the CIS can continue processing from the accumulated data or from the restarted frame. The user can select these options via register settings.

[0350] Then, upon receiving the voltage drop detection signal, the CIS begins the frame memory saving process and checks the frame accumulation flag. When the frame accumulation flag is set to logic "0", the non-volatile frame flag remains at its initial value and takes no action. On the other hand, when the frame accumulation flag is set to logic "1", the CIS writes the data at the address where the tag bit of the volatile frame memory is set to logic "1" to the non-volatile frame memory via write pulse P2, and clears the tag bit after the write is complete to logic "0". The CIS also maintains the non-volatile frame flag and writes the value "1" to the non-volatile frame flag in all successful writes. When the power-off non-volatile flag is set to logic "0", the non-volatile frame flag is initialized to "0", and when the power-off non-volatile flag is set to logic "1", it is cleared to "0" after a read. That is, if the writing of the logic value "1" is not completed during the power supply period of the auxiliary power source (such as an energy harvester), the non-volatile frame flag remains at the logic value "0".

[0351] Then, after power restoration, the CIS checks the power-off non-volatile flag in the restart procedure. If the flag is set to logic "0", the non-volatile frame memory is initialized regardless of the user-defined register setting. Conversely, if the power-off non-volatile flag is set to logic "1", the CIS checks the non-volatile frame flag. If the flag is set to logic "0", the non-volatile frame memory is initialized regardless of the user-defined register setting. If the non-volatile frame flag is set to logic "1", the CIS continues processing from the accumulated data or from the restarted frame. The user can select these options via register settings.

[0352] Next, consider the case where an AE control unit is installed. In this case, the CIS writes the statistical processing results information for analog / digital gain adjustment in AE control to volatile memory 480 and non-volatile memory 430. After a restart, the user can select which of the statistical processing results information stored in non-volatile memory 430 and the separately set default value is used for gain adjustment via register settings.

[0353] Then, upon receiving a voltage drop detection signal, the CIS stores the statistical processing result information embedded in the AE control unit. As described above, the CIS writes the data at the address where the tag bit of the volatile memory 480 is set to logic value "1" to the non-volatile memory storage 435 via the write pulse P2, and clears the tag bit after the write is completed to logic value "0". The CIS also maintains the statistical information non-volatile flag bit, and writes logic value "1" to the statistical information non-volatile flag bit in all cases of successful writes. When the power-off non-volatile flag bit is logic value "0", the statistical information non-volatile flag bit is initialized to logic value "0", and when the power-off non-volatile flag bit is logic value "1", it is cleared to logic value "0" after reading. That is, if the write of logic value "1" is not completed during the auxiliary power supply period, the statistical information non-volatile flag bit remains at logic value "0".

[0354] Then, after power is restored, the CIS checks the power-off non-volatile flag bit through the startup process. If the power-off non-volatile flag bit has a logic value of "0", the CIS uses the default value in gain adjustment and initializes the statistical processing result information regardless of the user's register settings. If the power-off non-volatile flag bit has a logic value of "1", the CIS checks the statistical information non-volatile flag bit. If the statistical information non-volatile flag bit has a logic value of "0", the CIS uses the default value in gain adjustment and initializes the statistical processing result information regardless of the user's register settings. If the statistical information non-volatile flag bit has a logic value of "1", the CIS uses either the statistical processing result information or a separately set default value for gain adjustment, corresponding to the user's register settings.

[0355] Through the above processing, a CIS that can recover properly and quickly from a power outage can be achieved.

[0356] It should be noted that the fifth embodiment can also be applied to the first embodiment, which does not have a multi-storage configuration. Furthermore, the fifth embodiment can also be applied to the third and fourth embodiments.

[0357] As described above, according to the fifth embodiment of this technology, when the power supply voltage drops below the threshold V lw1In this case, the power control unit 120 starts supplying power from the energy harvester 130, thus eliminating the need for rollback processing during recovery and preventing unauthorized re-execution.

[0358] [Variation Example]

[0359] In the fifth embodiment, the power control unit 120 is powered by the energy harvester 130; however, there is a possibility that the energy generated in the environment may be insufficient. The transient power outage countermeasure system 100 in the variation of the fifth embodiment differs from that in the fifth embodiment in that the transient power outage countermeasure system 100 also includes a battery.

[0360] Figure 33 This is a block diagram illustrating a configuration example of the instantaneous power outage countermeasure system 100 in a modified example of the fifth embodiment of the present technology.

[0361] Figure 34 This is a diagram illustrating an example of the implementation of the instantaneous power outage countermeasure system 100 in a modified embodiment of the fifth embodiment of the present technology.

[0362] like Figure 33 and Figure 34 The instantaneous power outage countermeasure system 100 in the modified version of the fifth embodiment shown in the figure differs from that in the fifth embodiment in that the instantaneous power outage countermeasure system 100 also includes a battery 170.

[0363] When the power supply voltage drops below the threshold V lw1 In this case, pMOS transistor 151 switches to the on state, and power control unit 120 starts supplying power from energy harvester 130 or battery 170 to power drop / rise detection circuit 110.

[0364] As described above, in a variation of the fifth embodiment of the present technology, since the power control unit 120 is powered by the energy harvester 130 or the battery 170, the effect of enabling continuous power supply is achieved even when the energy generated in the environment is insufficient.

[0365] It should be noted that the embodiments described above are examples embodying the present technology, and the matters in the embodiments correspond to the matters of the present invention specified in the claims. Similarly, the various matters of the present invention specified in the claims correspond to the various matters of the same name in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be embodied by applying various types of modifications to the embodiments without departing from the scope of the present technology.

[0366] It should be noted that the effects described in this article are merely examples and are not intended to be limiting; other effects can also be achieved.

[0367] Note that this technology can also have the following configurations.

[0368] (1) A semiconductor chip, comprising:

[0369] Volatile memory units;

[0370] Non-volatile memory units;

[0371] The write processing unit is configured to write write data to the same address of the volatile memory unit and the non-volatile memory unit;

[0372] The read processing unit is configured to read data from the address of a volatile memory cell as first read data, and is configured to read data from the address of a non-volatile memory cell as second read data; and

[0373] The save / restore processing unit is configured to perform a save process that writes the first read data to the address of the non-volatile memory cell where the second read data does not match the first read data.

[0374] (2) The semiconductor chip according to (1), wherein

[0375] The write processing unit is configured to use a first write pulse to write write data, and

[0376] The save / restore processing unit is configured to write the first read data using a second write pulse having at least one of a pulse width and a voltage greater than that of the first write pulse.

[0377] (3) The semiconductor chip according to (2), wherein

[0378] The save / restore processing unit is also configured to perform a restore process that writes newly read data from the non-volatile storage unit to the volatile storage unit after the save process.

[0379] (4) The semiconductor chip according to (3), wherein

[0380] The volatile memory unit retains the tag bit with the initial value for each address.

[0381] The write processing unit is configured to use a first write pulse to write data to the address and update the corresponding tag bit to a value different from the initial value.

[0382] The read processing unit is configured to update the corresponding tag bit to its initial value if the first read data and the second read data match each other.

[0383] The save / restore processing unit is configured to use a second write pulse to write the first read data to an address whose tag bit is different from the initial value among all addresses.

[0384] (5) The semiconductor chip according to (4), wherein

[0385] A non-volatile memory cell comprises multiple non-volatile memory blocks.

[0386] (6) The semiconductor chip according to (5) further includes a memory switching control unit configured to switch between multiple non-volatile memory banks during execution, wherein

[0387] The save / restore processing unit is configured to perform save processing and restore processing. The save processing uses a second write pulse to write the first read data to the address where the tag bit of the first read data is different from the initial value among all addresses of the memory bank being executed. The restore processing writes the read data read from the restore target memory bank indicated by the memory bank number BN updated by the memory bank switch after the save processing to the volatile memory unit and updates the corresponding tag bit to the initial value.

[0388] (7) The semiconductor chip according to any one of claims (1) to (6), wherein

[0389] Both volatile and non-volatile memory units include at least one of the following: general-purpose register, stack pointer register, program counter register, save program counter register, processor status word register, save status register, procedure register, multiplication register, base address register, vector base address register, read data buffer register, and write data buffer register.

[0390] (8) The semiconductor chip according to any one of (1) to (7), wherein

[0391] Volatile memory units include

[0392] Maintain the volatile shared resources of shared data shared by multiple entities, and

[0393] Maintain the volatility of non-shared resources that are not part of the shared data, and

[0394] Non-volatile memory units include

[0395] Maintain the non-volatile nature of shared data and shared resources,

[0396] Maintain multiple non-volatile, non-shared storage entities for data that does not belong to shared data.

[0397] (9) The semiconductor chip according to any one of (1) to (8), wherein

[0398] The volatile memory unit includes a predetermined number of volatile registers, and

[0399] The non-volatile memory unit includes a predetermined number of non-volatile registers.

[0400] (10) The semiconductor chip according to (1), wherein

[0401] The volatile memory cell includes a predetermined number of volatile memory circuits.

[0402] The non-volatile memory cell includes a predetermined number of non-volatile memory circuits, and

[0403] Both volatile and non-volatile memory circuits are deployed within a single register.

[0404] (11) A momentary power outage countermeasure system, comprising:

[0405] A detection circuit configured to detect when the power supply voltage drops below a second threshold value; and

[0406] A semiconductor chip includes volatile memory cells, non-volatile memory cells, a write processing unit, a read processing unit, and a save / restore processing unit. The write processing unit is configured to write write data to the same address of the volatile memory cells and the non-volatile memory cells. The read processing unit is configured to read data from the address of the volatile memory cell as first read data and is configured to read data from the address of the non-volatile memory cell as second read data. The save / restore processing unit is configured to perform a save process when the power supply voltage drops below the value of the second read data in all addresses of the non-volatile memory cell, where the second read data does not match the first read data.

[0407] (12) The instantaneous power outage countermeasure system according to (11) further includes:

[0408] Energy harvester; and

[0409] A power control unit configured to supply power from the energy harvester to the detection circuit when the power supply voltage drops below a first threshold that is higher than a second threshold.

[0410] (13) The instantaneous power outage countermeasure system according to (12) further includes a storage battery, wherein

[0411] The power control unit is configured to supply power to the semiconductor chip from at least one of the energy harvester and the battery when the power supply voltage drops below a first threshold.

[0412] (14) A method for controlling a semiconductor chip, the method comprising:

[0413] The write processing step writes the data to the same address in both volatile and non-volatile memory units.

[0414] The read processing steps include reading data from the address of a volatile memory cell as first read data and reading data from the address of a non-volatile memory cell as second read data; and

[0415] The save / restore process involves performing a save process, in which the first read data is written to the address of the non-volatile memory cell where the second read data does not match the first read data.

[0416] List of reference numerals

[0417] 100 Instantaneous Power Outage Countermeasure System

[0418] 110 Power supply drop / rise detection circuit

[0419] 120 Power Control Unit

[0420] 130 Energy Harvester

[0421] 141 to 144 diodes

[0422] 151, 152, 521 to 529 pMOS transistors

[0423] 161, 162 capacitors

[0424] 170 storage battery

[0425] 200 Semiconductor Chips

[0426] 211 Vertical Drive Circuit

[0427] 212 Timing Control Unit

[0428] 213 DAC

[0429] 214 pixel array unit

[0430] 215 signal processing units

[0431] 216 Horizontal Conveyor Control Unit

[0432] 220 Digital Signal Processing Unit

[0433] 221 External Setting Input / Output Interface

[0434] 222 Externally configured non-volatile register set

[0435] 300 Power Interruption Recovery Compatible CPU Systems

[0436] 310 Access Control Unit

[0437] 311 Write processing unit

[0438] 312 Read Processing Unit

[0439] 313 Save / Restore Processing Unit

[0440] 314 Storage Switching Control Unit

[0441] 320 BN register

[0442] 321, 420 Non-volatile Registers

[0443] 322, 460 volatile registers

[0444] 323 Encoder

[0445] 331 Program ROM

[0446] 332 Data Save / Restore Sequencer

[0447] 333 command to obtain decoder

[0448] 334 Address Arithmetic Circuit

[0449] 335 Arithmetic Circuits

[0450] 336 Data Save / Restore / Storage Switching Sequencer

[0451] 337 Address Converter

[0452] 338 Data Bus

[0453] 339 address bus

[0454] 340 Volatile Memory Shared Resource Address Specifying Register

[0455] 400 storage units

[0456] 410 Non-volatile register file

[0457] 411, 431, 451 address decoders

[0458] 412 Non-volatile register set

[0459] Output selectors 413, 434, and 453

[0460] Register set 414

[0461] Logic product (AND) gates 421, 422, 461 to 464, 511 to 514

[0462] 423, 424, 468 selectors

[0463] 425 Non-volatile Multi-bit Flip-Flop

[0464] 430 Non-volatile memory

[0465] 432 Memory Number Decoder

[0466] 433 memory cell array

[0467] 435 Non-volatile memory

[0468] 441 Non-volatile memory shared resources

[0469] 442 Non-volatile memory, non-shared resources

[0470] 443 Non-volatile memory, non-shared memory.

[0471] 450 Volatile Register File

[0472] 452 Volatile Register Set

[0473] 454, 580 comparators

[0474] Logic gates 465 and 466

[0475] 467, 581 Logic AND / OR gates

[0476] 469 Volatile Multi-bit Trigger

[0477] 470, 517 1-bit flip-flops

[0478] 480 Volatile Memory

[0479] 481 Volatile Memory Shared Resources

[0480] 482 Volatile Memory Non-Shared Resources

[0481] 500 register

[0482] Logic gates 515 and 516

[0483] 520 Embedded Register

[0484] 530 Volatile Memory Circuit

[0485] 531 to 536 Negation Logic Product (NAND) Gates

[0486] Inverters 541 to 544

[0487] Transmission gates 551 to 554

[0488] 560 to 569 nMOS transistors

[0489] 570 Non-volatile memory circuit

[0490] 571 and 572 MTJ components

[0491] 582. The logic of negation and exclusivity and the (XOR NOT) gate.

Claims

1. A semiconductor chip, comprising: Volatile memory units; Non-volatile memory units; The write processing unit is configured to write write data to the same address of the volatile memory unit and the non-volatile memory unit; The read processing unit is configured to read data from the address of the volatile memory unit as first read data, and is configured to read data from the address of the non-volatile memory unit as second read data; as well as A save / restore processing unit is configured to perform a save process that writes the first read data to an address in the non-volatile memory unit where the second read data does not match the first read data.

2. The semiconductor chip according to claim 1, wherein... The write processing unit is configured to use a first write pulse to write the write data, and The save / restore processing unit is configured to write the first read data using a second write pulse having at least one of a pulse width and voltage greater than the first write pulse.

3. The semiconductor chip according to claim 2, wherein... The save / restore processing unit is also configured to perform a restore process that writes newly read data from the non-volatile storage unit into the volatile storage unit after the save process.

4. The semiconductor chip according to claim 3, wherein The volatile storage unit maintains an initial value for the tag bit at each address. The write processing unit is configured to use the first write pulse to write the write data to the address, and update the corresponding tag bit to a value different from the initial value. The read processing unit is configured to update the corresponding tag bit to the initial value when the first read data and the second read data match each other, and The save / restore processing unit is configured to use the second write pulse to write the first read data to an address where the tag bit in all addresses is different from the initial value.

5. The semiconductor chip according to claim 4, wherein The non-volatile memory unit includes multiple non-volatile memory banks.

6. The semiconductor chip of claim 5, further comprising a memory switching control unit configured to switch between the executing memory banks among the plurality of non-volatile memory banks, wherein... The save / restore processing unit is configured to perform save processing and restore processing. The save processing uses the second write pulse to write the first read data to an address in the memory bank where the tag bit is different from the initial value. The restore processing writes the read data read from the restore target memory bank specified by the memory bank switch after the save processing to the volatile memory unit and updates the corresponding tag bit to the initial value.

7. The semiconductor chip according to claim 1, wherein... Both the volatile memory unit and the non-volatile memory unit include at least one of the following: a general-purpose register, a stack pointer register, a program counter register, a save program counter register, a processor status word register, a save status register, a procedure register, a multiplication register, a base address register, a vector base address register, a read data buffer register, and a write data buffer register.

8. The semiconductor chip according to claim 1, wherein... The volatile storage unit includes Volatile shared resources, maintaining shared data shared by multiple entities; and Volatile non-shared resources retain data that is not part of the shared data; and The non-volatile storage unit includes Non-volatile shared resources, maintaining shared data; and Multiple non-volatile, non-shared memory banks hold data that is not part of the shared data.

9. The semiconductor chip according to claim 1, wherein... The volatile memory unit includes a predetermined number of volatile registers, and The non-volatile memory unit includes a predetermined number of non-volatile registers.

10. The semiconductor chip according to claim 1, wherein The volatile memory unit includes a predetermined number of volatile memory circuits; The non-volatile memory cell includes a predetermined number of non-volatile memory circuits; and The volatile circuitry and the non-volatile memory circuitry are deployed within a single register.

11. A momentary power outage countermeasure system, comprising: The detection circuit is configured to detect when the power supply voltage drops below a second threshold value; as well as A semiconductor chip includes volatile memory cells, non-volatile memory cells, a write processing unit, a read processing unit, and a save / restore processing unit. The write processing unit is configured to write write data to the same address of the volatile memory cells and the non-volatile memory cells. The read processing unit is configured to read data from the address of the volatile memory cells as first read data and to read data from the address of the non-volatile memory cells as second read data. The save / restore processing unit is configured to perform a save process when the power supply voltage drops below a second threshold value. The save process writes the first read data to the address of the non-volatile memory cells where the second read data does not match the first read data.

12. The instantaneous power outage countermeasure system according to claim 11, further comprising: Energy harvester; as well as The power control unit is configured to supply power from the energy harvester to the detection circuit when the power supply voltage drops below a first threshold that is higher than the second threshold.

13. The instantaneous power outage countermeasure system according to claim 12 further includes a storage battery, wherein... The power control unit is configured to supply power to the semiconductor chip from at least one of the energy harvester and the battery when the power supply voltage drops below the first threshold.

14. A method for controlling a semiconductor chip, the method comprising: The write processing step writes the data to the same address in both volatile and non-volatile memory units. The read processing step involves reading data from the address of the volatile memory cell as first read data, and reading data from the address of the non-volatile memory cell as second read data. as well as The save / restore process involves performing a save process, in which the first read data is written to the address in the non-volatile memory unit where the second read data does not match the first read data.

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