Semiconductor chip, semiconductor device, information processing system, and control method for semiconductor chip

Abstract

In a semiconductor chip that performs data save and restore, increase in area and power consumption of a nonvolatile memory unit is minimized. A bank switching control unit designates any one of a plurality of nonvolatile banks other than a bank designated as a backup bank as a running bank. A normal save / restore processing unit performs save processing of writing data read from a volatile memory unit to the running bank in a case where a context is to be saved, and performs restore processing of writing data read from the running bank or a restore target bank designated by a context switch to the volatile memory unit and the backup bank in a case where the context is to be restored. A power-down save / restore processing unit performs save processing in a case where a power supply voltage drops to a value lower than a first threshold value, and performs restore processing after swapping the backup bank and the running bank in a case where the dropped power supply voltage rises to a value higher than a second threshold value.

Description

Technical Field

[0001] This technology relates to semiconductor chips. Specifically, the present invention relates to semiconductor chips, semiconductor devices, information processing systems, and control methods for semiconductor chips that perform data storage and recovery. Background Technology

[0002] Traditionally, in various semiconductor chips, data saving and recovery processes can be performed when power is reduced or interrupted. For example, processors have been proposed in which a non-volatile memory bank, used as a destination for data saving from volatile memory, is copied, and while the other is in use, data is backed up to one of the copied non-volatile memory banks (see, for example, Non-Patent Literature 1).

[0003] Reference List

[0004] Non-patent literature

[0005] Non-patent literature 1: Nakabeppu Shota et al., “Uninterrupted Processor Using Non-volatile Components”, IEICE Technical Report, Vol. 120, No. 435, pp. 97-102. Summary of the Invention

[0006] The problem to be solved

[0007] In the aforementioned related technologies, normal operation during power failure recovery is achieved by backing up data to one of the replicated non-volatile memory libraries while another is in use. However, in the aforementioned related technologies, since the non-volatile memory library needs to be replicated, the following problem exists: as the address space expands, the area and power consumption of the non-volatile memory increase.

[0008] This technology was developed in view of these circumstances, and its purpose is to minimize the increase in area and power consumption of non-volatile memory cells in semiconductor chips that perform data saving and recovery.

[0009] Solution to the problem

[0010] This technology is designed to solve the aforementioned problems, and its first aspect can be a semiconductor chip comprising: a volatile memory unit; a non-volatile memory unit including a plurality of non-volatile libraries, any one of which is designated as a backup library; a library switching control unit configured to designate any one of the plurality of non-volatile libraries, excluding the library designated as the backup library, as a runtime library; and a normal save / restore processing unit configured to perform a save process of writing data read from the volatile memory unit to the runtime library when a save context is to be performed, and configured to perform a save process of writing data from the volatile memory unit to the runtime library when a restore context is to be performed and no restore context is to be performed. The system includes a recovery process that, in the event of a context switch, writes data read from the runtime library to the volatile memory and the backup library; and a recovery process that, in the event of restoring the context and performing a context switch, writes data read from the recovery target library specified by the context switch to the volatile memory and the backup library; a power-down save / recovery processing unit configured to perform the save process when the power supply voltage drops below a first threshold value, and to perform the recovery process after swapping the backup library and the runtime library when the dropped power supply voltage rises above a second threshold value; and a method for controlling the semiconductor chip. Therefore, the system achieves the effect of minimizing the increase in area and power consumption of the non-volatile memory.

[0011] Furthermore, in the first aspect, the semiconductor chip may further include: a write processing unit configured to write write data to an address of the volatile register file 450 and an address of the runtime library corresponding to the library number BN, the addresses being identical to each other; and a read processing unit configured to read data from the address of the volatile memory unit as first read data, and configured to read data from the address of the runtime library as second read data, wherein the normal save / restore processing unit and the power-down save / restore processing unit may each be configured to, during the save processing, write the first read data to the address of the second read data among all addresses of the runtime library where it does not match the first read data, and the read processing unit may be configured to perform the above processing for reads not accompanied by writes. Therefore, the effect of reducing inrush current is achieved.

[0012] Furthermore, in the first aspect, the write processing unit can use a first write pulse to write the write data, and the normal save / restore processing unit and the power-down save / restore processing unit can each use a second write pulse having at least one of a pulse width or voltage greater than the first write pulse to write the first read data. Therefore, the effect of minimizing write errors is achieved.

[0013] Furthermore, in the first aspect, the volatile storage unit can retain an initial value tag bit for each address. The write processing unit can use the first write pulse to write the write data to the address and update the corresponding tag bit to a value different from the initial value. The read processing unit can update the corresponding tag bit to the initial value if the first read data and the second read data match. Additionally, the normal save / recovery processing unit and the power-down save / recovery processing unit can each use the second write pulse to write the first read data to an address among all addresses whose corresponding tag bit differs from the initial value. Therefore, the effect of determining whether a mismatch exists based on the tag bit is achieved.

[0014] Furthermore, in the first aspect, the semiconductor chip may also include a register that stores the respective library numbers of the runtime library and the backup library, wherein the power-down save / recovery processing unit can be configured to exchange the backup library and the runtime library by updating the register. Thus, the effect of appropriately managing library numbers is achieved even when two tasks are present.

[0015] Furthermore, in the first aspect, the semiconductor chip may further include a virtual / real library number management table, which stores virtual library numbers assigned to interrupt handling or tasks and real library numbers assigned to each of the plurality of non-volatile libraries, the virtual library numbers and the real library numbers being associated with each other, wherein the power-down save / recovery processing unit can be configured to exchange the backup library and the runtime library by updating the registers and the virtual / real library number management table. Thus, the effect of properly managing library numbers is achieved even when three or more tasks are present.

[0016] Furthermore, in the first aspect, each of the volatile memory cell and the non-volatile memory cell may include at least one of the following: a general-purpose register, a stack pointer register, a program counter register, a save program counter register, a processor status word register, a save status register, a process register, a multiplication register, a base register, a vector base register, a read data buffer register, or a write data buffer register. Therefore, the effect of minimizing the increase in area and power consumption of the non-volatile general-purpose registers, etc., is achieved.

[0017] Furthermore, in the first aspect, the volatile storage unit may include volatile shared resources that hold shared data shared by multiple entities, and volatile non-shared resources that hold data that does not correspond to the shared data. The plurality of non-volatile libraries may include a pair of non-volatile shared libraries that hold the shared data, and a plurality of non-volatile non-shared libraries that hold data that does not correspond to the shared data. Therefore, efficient use of memory is achieved.

[0018] Furthermore, a second aspect of this technology is a semiconductor device comprising: a detection circuit configured to detect a power supply voltage dropping below a first threshold and a power supply voltage rising above a second threshold; and a semiconductor chip comprising: a volatile memory cell; a non-volatile memory cell including a plurality of non-volatile libraries, any one of which is designated as a backup library; a library switching control unit configured to designate any one of the plurality of non-volatile libraries, excluding the library designated as the backup library, as a runtime library; and a normal save / restore processing unit configured to perform read operations from the volatile memory cell when a context needs to be saved. The data is written to the runtime library in a save process, and is configured to perform a recovery process that writes data read from the runtime library to the volatile storage unit and the backup library when the context needs to be restored and no context switch is performed, and to perform a recovery process that writes data read from the recovery target library specified by the context switch to the volatile storage unit and the backup library when the context needs to be restored and a context switch is performed; and a power-down save / restore process unit, configured to perform the save process when the power supply voltage drops below a first threshold value, and to perform the restore process after swapping the backup library and the runtime library when the dropped power supply voltage rises above a second threshold value. Therefore, the power consumption of the semiconductor device is reduced.

[0019] Furthermore, a third aspect of this technology is an information processing system comprising: an information processing device configured to convert source code into object code; and a semiconductor chip comprising: a volatile memory unit; a non-volatile memory unit comprising a plurality of non-volatile libraries, any one of which is designated as a backup library; a library switching control unit configured to designate any one of the plurality of non-volatile libraries, excluding the library designated as the backup library, as a runtime library; and a normal save / restore processing unit configured to perform data write operations from the volatile memory unit based on the object code when a context needs to be saved. The system includes a save process for the runtime library, configured to perform a recovery process that writes data read from the runtime library to the volatile storage unit and the backup library when the context needs to be restored and no context switch is performed, and to perform a recovery process that writes data read from the recovery target library specified by the context switch to the volatile storage unit and the backup library when the context needs to be restored and a context switch is performed; and a power-down save / restore process unit configured to perform the save process when the power supply voltage drops below a first threshold value, and to perform the restore process after swapping the backup library and the runtime library when the dropped power supply voltage rises above a second threshold value. Therefore, this achieves the effect of reducing the power consumption of the information processing system.

[0020] Furthermore, in the third aspect, the information processing device can use checkpoint insertion to merge code blocks obtained by dividing the source code into multiple parts. Therefore, it achieves the effect of saving and restoring data for each code block.

[0021] Furthermore, in the third aspect, the information processing device can analyze the data dependencies of each code block and identify the variables to be saved in the save process based on these dependencies. Therefore, it achieves the effect of reducing write instructions, read instructions, and verification instructions. Attached Figure Description

[0022] Figure 1 This is a block diagram illustrating an example configuration of a semiconductor chip according to a first embodiment of the present technology.

[0023] Figure 2 This is a block diagram illustrating a configuration example of a digital signal processing unit according to a first embodiment of the present technology.

[0024] Figure 3 This is a block diagram illustrating a configuration example of a power interruption recovery compatible central processing unit (CPU) system according to a first embodiment of the present technology.

[0025] Figure 4 This is a block diagram illustrating an example configuration of a non-volatile register file according to a first embodiment of the present technology.

[0026] Figure 5 This is a block diagram illustrating an example configuration of a volatile register file according to a first embodiment of the present technology.

[0027] Figure 6 This is a circuit diagram illustrating an example configuration of a non-volatile register according to a first embodiment of the present technology.

[0028] Figure 7 This is a circuit diagram illustrating an example configuration of a volatile register according to a first embodiment of the present technology.

[0029] Figure 8 This is a diagram illustrating an example of a signal list according to a first embodiment of the present technology.

[0030] Figure 9 This is a diagram illustrating an example configuration of a BN register according to a first embodiment of the present technology. The BN register includes a non-volatile register or non-volatile memory in which read verification is performed until a write is successful.

[0031] Figure 10 This is a flowchart illustrating an example of a write process according to a first embodiment of the present technology.

[0032] Figure 11 This is a flowchart illustrating an example of a read process according to a first embodiment of the present technology.

[0033] Figure 12 This is a flowchart illustrating an example of normal save / restore processing according to a first embodiment of the present technology.

[0034] Figure 13 This is a flowchart illustrating another example of normal save / restore processing according to a first embodiment of the present technology.

[0035] Figure 14 This is a flowchart illustrating an example of power-down save / restore processing according to a first embodiment of the present technology.

[0036] Figure 15 This is a flowchart illustrating another example of power-down save / restore processing according to a first embodiment of the present technology.

[0037] Figure 16 This is a diagram used to explain an example of normal save / restore processing according to a first embodiment of the present technology.

[0038] Figure 17This is a diagram used to explain an example of power-down save / restore processing according to a first embodiment of the present technology.

[0039] Figure 18 This is a block diagram illustrating a configuration example of a power-off recovery compatible CPU system of a first variant according to a first embodiment of the present technology.

[0040] Figure 19 This is a diagram illustrating a configuration example of a virtual / physical library number management table of a first variant according to a first embodiment of the present technology.

[0041] Figure 20 This is a circuit diagram illustrating an example configuration of a non-volatile register constituting a virtual / real library number management table in a first variant of a first embodiment of the present technology.

[0042] Figure 21 This is a diagram illustrating an example of an updated virtual / real library number management table and a BN register consisting of a non-volatile register or non-volatile memory, in which read verification is performed until a write is successful, according to a first variant of a first embodiment of the present technology.

[0043] Figure 22 This is a flowchart illustrating another example of a power-down save / restore process of a first variant according to a first embodiment of the present technology.

[0044] Figure 23 This is a diagram illustrating a configuration example of a second variant of the BN register according to a first embodiment of the present technology, wherein the BN register includes a non-volatile register or non-volatile memory in which read verification is performed until a write is successful.

[0045] Figure 24 This is a diagram illustrating an example configuration of an associated memory of a second variant according to a first embodiment of the present technology.

[0046] Figure 25 This is a block diagram illustrating a configuration example of a power-off recovery compatible CPU system according to a second embodiment of the present technology.

[0047] Figure 26 This is a diagram illustrating a register list according to a second embodiment of the present technology.

[0048] Figure 27 This is a block diagram illustrating an example configuration of a storage unit according to a second embodiment of the present technology.

[0049] Figure 28 This is a block diagram illustrating an example configuration of a storage unit according to a third embodiment of the present technology.

[0050] Figure 29This is a block diagram illustrating an example configuration of a volatile memory according to a third embodiment of the present technology.

[0051] Figure 30 This is a diagram illustrating a configuration example of a BN register according to a third embodiment of the present technology, wherein the BN register includes a non-volatile register or non-volatile memory in which read verification is performed until a write is successful.

[0052] Figure 31 This is a block diagram illustrating a configuration example of a power-off recovery compatible CPU system according to a third embodiment of the present technology.

[0053] Figure 32 This is a block diagram illustrating a configuration example of a semiconductor device according to a fourth embodiment of the present technology.

[0054] Figure 33 This is a block diagram illustrating a configuration example of an information processing system according to a fifth embodiment of the present technology.

[0055] Figure 34 This is a diagram illustrating an example of source code according to a fifth embodiment of the present technology.

[0056] Figure 35 This is a diagram illustrating an example of a code block according to a fifth embodiment of the present technology.

[0057] Figure 36 This is a diagram illustrating a revised example of a code block according to a fifth embodiment of the present technology.

[0058] Figure 37 This is a diagram illustrating an example set of assignment statements according to a fifth embodiment of the present technology.

[0059] Figure 38 This is a diagram illustrating an example of variables to be read and verified according to a fifth embodiment of the present technology.

[0060] Figure 39 This is a diagram illustrating an example of a checkpoint function to be replaced according to a fifth embodiment of the present technology.

[0061] Figure 40 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0062] Figure 41 This is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection section and the imaging section. Detailed Implementation

[0063] The following describes the methods used to implement this technology (hereinafter referred to as embodiments). The descriptions will be given in the following order.

[0064] 1. First Implementation Example (Example of exchanging runtime libraries and backup libraries)

[0065] 2. Second Implementation Example (Example of exchanging runtime and backup libraries within the CPU register file)

[0066] 3. Third embodiment (example of setting up shared and non-shared resources and exchanging runtime and backup libraries)

[0067] 4. Fourth Implementation Example (Example of exchanging runtime and backup libraries in response to power rise detection results)

[0068] 5. Fifth Implementation Example (Based on the example of code-swapping runtime and backup libraries)

[0069] 6. Application examples for moving bodies

[0070] <1. First Embodiment>

[0071] [Semiconductor chip configuration example]

[0072] Figure 1 This is a block diagram illustrating an example configuration of a semiconductor chip 200 according to an embodiment of the present technology. The semiconductor chip 200 is a CMOS image sensor (CIS) and includes a vertical drive circuit 211, a timing control unit 212, a digital-to-analog converter (DAC) 213, and a pixel array unit 214. Furthermore, the semiconductor chip 200 includes a column signal processing unit 215, a horizontal transfer control unit 216, and a digital signal processing unit 220.

[0073] In pixel array unit 214, multiple pixels are arranged in a two-dimensional grid pattern. Vertical drive circuit 211 sequentially selects rows in pixel array unit 214, drives each pixel in the selected row, and outputs an analog signal to column signal processing unit 215.

[0074] The timing control unit 212 controls the timing of operation of each of the vertical drive circuit 211, DAC 213, column signal processing unit 215 and horizontal transmission control unit 216.

[0075] DAC 213 generates a sawtooth ramp signal through digital-to-analog (DA) conversion and supplies the signal to column signal processing unit 215.

[0076] In the column signal processing unit 215, an analog-to-digital converter (ADC) is arranged for each column of the pixel array unit 214. The ADC converts the analog signal from the corresponding column into a digital signal and supplies the digital signal to the digital signal processing unit 220 under the control of the horizontal transmission control unit 216.

[0077] The horizontal transmission control unit 216 controls the column signal processing unit 215 to output digital signals for each column in sequence.

[0078] The digital signal processing unit 220 performs various signal processing operations, such as white balance correction and depixelation, on the digital signal from the column signal processing unit 215. The digital signal processing unit 220 outputs the processed image data.

[0079] [Configuration example of a digital signal processing unit]

[0080] Figure 2 This is a block diagram illustrating a configuration example of a digital signal processing unit 220 according to a first embodiment of the present technology. The digital signal processing unit 220 includes an external setting input / output interface 221, an external setting non-volatile register set 222, and a power-down recovery compatible CPU system 300.

[0081] The external setting input / output interface 221 receives data from the outside for performing initial settings or changing settings during operation, and keeps this data in the external setting non-volatile register group 222. Furthermore, the external setting input / output interface 221 sends data read from the external setting non-volatile register group 222 to the outside.

[0082] The power-out recovery compatible CPU system 300 saves data when the power supply voltage drops and restores the data when the power supply voltage is restored.

[0083] [Configuration example for a CPU system compatible with power interruption recovery]

[0084] Figure 3 This is a block diagram illustrating a configuration example of a power-down recovery compatible CPU system 300 according to a first embodiment of the present technology. The power-down recovery compatible CPU system 300 includes an access control unit 310, a BN register 340, and a memory unit 400.

[0085] The access control unit 310 includes a write processing unit 311, a read processing unit 312, a library switching control unit 313, a normal save / restore processing unit 314, and a power-down save / restore processing unit 315. The storage unit 400 includes a non-volatile register file 410 and a volatile register file 450.

[0086] Note that although non-volatile register file 410 and volatile register file 450 are used in the figure, volatile and non-volatile memory can be used instead. For example, a combination of static random access memory (SRAM) and non-volatile RAM, or a combination of dynamic random access memory (DRAM) and non-volatile RAM, can be used. Furthermore, magnetic memory can be used as a non-volatile memory, for example. Spin-torque torque (STT)-magnetoresistive random access memory (MRAM) can be used as a magnetic memory, for example. Moreover, magnetic memory is not limited to STT-MRAM, and novel magnetic memories such as voltage-controlled magnetic anisotropy (VCMA)-MRAM or spin-orbit torque (SOT)-MRAM can be used.

[0087] Furthermore, non-volatile register file 410 is an example of a non-volatile memory cell, and volatile register file 450 is an example of a volatile memory cell, as described in the claims.

[0088] The details of the processes performed by the write processing unit 311, the read processing unit 312, the library switching control unit 313, the normal save / restore processing unit 314, and the power-down save / restore processing unit 315 will be described later.

[0089] Note that a power-loss recovery compatible system with the same functions as the power-loss recovery compatible CPU system 300 can be independently configured in the automatic exposure (AE) control unit, outside of the digital signal processing unit 220. In this case, the power-loss recovery compatible system in the AE control unit performs the recovery operation after a power interruption independently of the power-loss recovery compatible CPU system 300, according to user settings.

[0090] Furthermore, although the power-loss recovery compatible CPU system 300 is housed within the semiconductor chip 200 used as a CIS, the configuration is not limited to this. The power-loss recovery compatible CPU system 300 can also be housed within various semiconductor chips, other than a CIS.

[0091] [Example of non-volatile register file configuration]

[0092] Figure 4 This is a block diagram illustrating a configuration example of a non-volatile register file 410 according to a first embodiment of the present technology. The non-volatile register file 410 includes an address decoder 411, a library number decoder 412, a non-volatile register group 413, and an output selector 414. In the non-volatile register group 413, K non-volatile registers 420 (where K is an integer greater than or equal to 2) are arranged. An address ADDR is assigned to each non-volatile register 420. NV .

[0093] Furthermore, the non-volatile register set 413 is divided into N+1 (where N is an integer greater than or equal to 2) non-volatile register libraries 415. Each of the volatile register set 450 and the N+1 non-volatile register libraries 415 is identical in size and address space. Here, the number of libraries accessible to the CPU is N out of the N+1 libraries. Therefore, with each non-volatile register library 415 having a size of B bits (where B is an integer), the size of the address space accessible to the CPU is N×B bits. Of the N+1 libraries, the additional one is designated as a data backup destination. In the following text, the library serving as the backup destination is referred to as the "backup library".

[0094] The backup library's library number is stored in register BN 340. The backup library's library number is not a fixed value but a variable one. An example of timing for changing the backup library's library number will be described later.

[0095] Address ADDR from access control unit 310 NV It is input into address decoder 411. Address decoder 411 inputs address ADDR. NV Decode and generate a K-bit one-hot signal (DEC) A In the single-heat signal DEC A In, only the address ADDR NV The corresponding bit is set to logic value "1", and the remaining bits are set to logic value "0". Address decoder 411 converts the one-hot signal DEC... A Output to non-volatile register group 413 and output selector 414.

[0096] Note that the address ADDR from the access control unit 310... NV If the value is out of range, the address decoder 411 can output a one-hot signal DEC with all bits set to logic value "0". A .

[0097] The library number decoder 412 decodes the library number BN from the access control unit 310 and generates an N-bit unique signal DEC. B The library number BN indicates the runtime library number among the N accessible libraries. This runtime library is thereafter referred to as the "runtime library". The library switching control unit 313 designates any one of the N non-volatile register libraries 415 (excluding backup libraries) as the runtime library and switches the runtime library as needed.

[0098] Furthermore, in the N-bit unique thermal signal DEC B In this process, only the bit corresponding to the library number BN is set to the logic value "1", and the remaining bits are set to the logic value "0". The library number decoder 412 converts the one-hot signal DEC...B The supplies are provided to the non-volatile register set 413 and the output selector 414.

[0099] Output selector 414 is based on the uniquely heated signal DEC. A and DEC B This output selector 414 selects any one of the non-volatile register output signals NVQ from the individual registers. B Select the non-volatile register library 415 corresponding to the bit with the logic value "1", and select the one-hot signal DEC from within that library. A The non-volatile register 420 corresponds to the bit with the logic value "1". Then, the output selector 414 outputs the non-volatile register output signal NVQ from the selected non-volatile register 420 to the volatile register file 450.

[0100] [Example of volatile register file configuration]

[0101] Figure 5 This is a block diagram illustrating a configuration example of a volatile register file 450 according to a first embodiment of the present technology. The volatile register file 450 includes an address decoder 451, a volatile register group 452, an output selector 453, and a comparator 454. K volatile registers 460 are arranged in the volatile register group 452. An address ADDR is assigned to each volatile register 460. V .

[0102] In addition, for each address ADDR V The volatile register group 452 holds a 1-bit tag (not shown).

[0103] Address decoder 451 pairs address ADDR V Decode the signal to generate a K-bit one-hot signal DEC, and output the one-hot signal DEC to the volatile register group 452 and the output selector 453.

[0104] Output selector 453 selects any one of the volatile register output signals VQ from each volatile register 460 based on the one-hot signal DEC. Output selector 453 selects the signal corresponding to the bit with the logic value "1" in the one-hot signal DEC and outputs the selected signal to comparator 454.

[0105] Comparator 454 compares the non-volatile register output signal NVQ from the non-volatile register file 410 with the volatile register output signal VQ from the output selector 453. Comparator 454 supplies a comparison result signal CMP_OUT, indicating the comparison result, to the volatile register group 452.

[0106] [Example of non-volatile register configuration]

[0107] Figure 6 This is a circuit diagram illustrating an example configuration of a non-volatile register 420 according to a first embodiment of the present technology. DEC from address decoder 411 and library number decoder 412. A [k] and DEC B [n] is input to the non-volatile register 420. Additionally, the access control signal R / W, data input signal D, register save enable signal REN, and clock signal CK from the access control unit 310 are input to the non-volatile register 420. Furthermore, the volatile register output signal VQ and tag bit TAG from the volatile register file 450 are input to the non-volatile register 420. Then, the non-volatile register 420 outputs the non-volatile register output signal NVQ to the volatile register file 450 and the output selector 414.

[0108] DEC A [k] indicates the k-th bit in the one-hot signal DECA (where k is an integer from 1 to K), and is input to the k-th non-volatile register 420 in the non-volatile register library 415. B [n] indicates the single-heater signal DEC B The nth bit (where n is an integer from 1 to N+1) is input into the nth non-volatile register bank 415.

[0109] The access control signal R / W is used to indicate whether a read or write operation is performed without writing. For example, during a read operation without writing, the access control signal R / W is set to the logic value "0", and during a write operation, it is set to the logic value "1".

[0110] The data input signal D indicates the data to be written to non-volatile register 420 and volatile register 460. The size of the data to be written is defined as J bits (where J is an integer).

[0111] The volatile register output signal VQ indicates the read data read from the volatile register 460 in the volatile register file 450. The size of this read data is also defined as J bits. Note that the volatile register output signal VQ is an example of the first read data described in the claims.

[0112] The tag bit TAG is a signal that indicates the write status of the corresponding non-volatile register 420. For example, when no write is performed to the non-volatile register 420 (in other words, the initial state) or when a write is completed, the logic value "0" is set to the initial value of the corresponding tag bit TAG, and when a temporary write is performed, the logic value "1" is set.

[0113] The register save enable signal REN is a signal that indicates whether the function of saving from volatile register 460 to non-volatile register 420 is enabled. For example, when disabled, the register save enable signal REN is set to the logical value "0", and when enabled, the register save enable signal REN is set to the logical value "1".

[0114] The non-volatile register output signal NVQ indicates the read data read from the non-volatile register 420. Note that the non-volatile register output signal NVQ is an example of the second read data described in the claims.

[0115] Here, K addresses ADDR on the non-volatile side NV and the K addresses ADDR in each library on the volatile side V They are linked one-to-one. The volatile register output signal VQ and the tag bit TAG from the k-th volatile register 460 are input to the k-th non-volatile register 420 in the runtime library. The non-volatile register output signal NVQ from the k-th non-volatile register 420 in the runtime library is output to the k-th volatile register 460 and the output selector 414.

[0116] In addition, the nonvolatile register 420 includes AND (logic product) gates 421, 422 and 423, selectors 424 and 425, and a nonvolatile multi-bit flip-flop 426.

[0117] AND gate 421 will DEC A [k] and DEC B The logical product of [n] is output to selector 424.

[0118] AND gate 422 outputs the logical product of the access control signal R / W and the output signal of AND gate 421 to selector 424.

[0119] Selector 424 selects the output signal of AND gate 422 when the register stores the enable signal REN with a logic value of "0", and selects the tag bit TAG when the register stores the enable signal REN with a logic value of "1", and outputs the selected signal to AND gate 423.

[0120] AND gate 423 outputs the logical product of the output signal of selector 424 and the clock signal CK to the clock terminal of non-volatile multi-bit flip-flop 426.

[0121] Selector 425 selects the data input signal D when the register save enable signal REN has a logic value of "0", and selects the volatile register output signal VQ when the register save enable signal REN has a logic value of "1", and outputs the selected signal to the input terminal of the non-volatile multi-bit flip-flop 426.

[0122] The non-volatile multi-bit flip-flop 426 holds the output signal of the selector 424. The non-volatile multi-bit flip-flop 426 has a size of J bits. Furthermore, the non-volatile multi-bit flip-flop 426 outputs the held signal as the non-volatile register output signal NVQ.

[0123] Using the configuration shown in the diagram, the following operations are achieved. First, the description register is stored in the case where the enable signal REN is disabled. In this case, consider that R / W has a logic value "1" indicating a write operation, and DEC... A [k] and DEC B [n] has a logic value of "1" (i.e., the k-th address in the n-th library is selected). In this case, the non-volatile register 420 at that address writes the data input signal D to the non-volatile multi-bit flip-flop 426. The "1" R / W pulse during this write is called the write pulse P1. If the condition is not met, the non-volatile register 420 retains the previous value.

[0124] Next, the case where the register save enable signal REN is enabled will be described. In this case, with the tag bit TAG from the k-th volatile register 460 having a logic value of "1", the k-th non-volatile register 420 writes VQ from the volatile register 460 to the non-volatile multi-bit flip-flop 426. If the write pulse during this write is referred to as P2, at least one of the pulse width or voltage of P2 is greater than the pulse width or voltage of P1. The pulse width and voltage of write pulse P2 are set to values ​​that result in a write success rate of 100%. Note that write pulses P1 and P2 are examples of the first and second write pulses described in the claims.

[0125] Furthermore, after a write operation during the storage period, the access control unit 310 reads data from the volatile register 460 and the non-volatile register 420, determines whether the data matches each other, and repeats the rewrite until the data matches each other. Note that the non-volatile multi-bit flip-flop 426 always outputs the stored value, and in the case of an updated value, the updated value is reflected in the output signal starting from the next cycle after the write cycle.

[0126] [Example of volatile register configuration]

[0127] Figure 7This is a circuit diagram illustrating a configuration example of a volatile register 460 according to a first embodiment of the present technology. DEC[k] from the address decoder 411, the access control signal R / W, the data input signal D, the register recovery signal REST from the access control unit 310, and the clock signal CK are input to the volatile register 460. Furthermore, the non-volatile register output signal NVQ from the non-volatile register file 410 and the comparison result signal CMP_OUT from the comparator 454 are input to the volatile register 460. The volatile register 460 then outputs the volatile register output signal VQ to the non-volatile register file 410 and the output selector 453. Additionally, the volatile register 460 outputs the tag bit TAG to the non-volatile register file 410.

[0128] The comparison result signal CMP_OUT is a signal indicating whether the read data of non-volatile register 420 and the read data of the corresponding volatile register 460 match each other. For example, if the read data match each other, the comparison result signal CMP_OUT is set to the logic value "1", and if the read data do not match each other, the comparison result signal CMP_OUT is set to the logic value "0".

[0129] The register restore signal REST is a signal indicating whether a write (in other words, a restore) is performed from the non-volatile register 420 to the corresponding volatile register 460 after a save. For example, when a restore is performed, the register restore signal REST is set to the logical value "1", and when no restore is performed, the register restore signal REST is set to the logical value "0".

[0130] In addition, the volatile register 460 includes AND gates 461 to 464, logic gates 465 and 466, OR (logic AND) gate 467, selector 468, multi-bit volatile flip-flop 469, and 1-bit flip-flop 470.

[0131] AND gate 461 outputs the logical product of the access control signal R / W and the k-th bit DEC[k] of the hot-only signal to OR gate 467.

[0132] The OR gate 467 outputs the register recovery signal REST to the AND gate 462 and the output signal of the AND gate 461, which are logically summed.

[0133] AND gate 462 outputs the logic product of the output signal of OR gate 467 and the clock signal CK to the clock terminal of multi-bit volatile flip-flop 469.

[0134] Selector 468 selects the data input signal D when the register recovery signal REST has a logic value of "0", and selects the non-volatile register output signal NVQ when the register recovery signal REST has a logic value of "1", and outputs the selected signal to the input terminal of the multi-bit volatile flip-flop 469.

[0135] The multi-bit volatile flip-flop 469 retains the output signal of the selector 468. The multi-bit volatile flip-flop 469 is J bits in size. Furthermore, the multi-bit volatile flip-flop 469 outputs the retained signal as the volatile register output signal VQ.

[0136] Logic gate 466 outputs the inverted value of the access control signal R / W to logic gate 465 and the logical product of the k-th bit DEC[k] of the one-hot signal.

[0137] Logic gate 465 obtains the inverted value of clock signal CK, the logical product of comparison result signal CMP_OUT and output signal of logic gate 466, and outputs the logical product and register recovery signal REST to 1-bit flip-flop 470.

[0138] AND gate 464 outputs the logical product of the access control signal R / W and the k-th bit DEC[k] of the hot-only signal to AND gate 463.

[0139] AND gate 463 inputs the logical product of the output signal of AND gate 464 and the clock signal CK to the clock terminal of the 1-bit flip-flop 470.

[0140] The 1-bit flip-flop 470 is volatile and reserves the tag bit TAG. A high level (i.e., a logic value "1") is input to the set terminal S of the 1-bit flip-flop 470. Additionally, the inverted value of the output signal of logic gate 465 is input to the reset terminal R of the 1-bit flip-flop 470. Furthermore, in the 1-bit flip-flop 470, the input to the reset terminal R is primarily used to determine the output value. Furthermore, the 1-bit flip-flop 470 outputs the tag bit TAG to the non-volatile register file 410.

[0141] Using the configuration shown in the diagram, the following operations are implemented. First, the case where the register recovery signal REST is disabled will be described. In this case, when R / W has a logic value "1" indicating a write and DEC[k] has a logic value "1", the volatile register 460 writes the data input signal D to the multi-bit volatile flip-flop 469 and updates the 1-bit flip-flop 470 to the logic value "1". Furthermore, when R / W has a logic value "0" indicating a read and DEC[k] has a logic value "1", the volatile register 460 initializes the 1-bit flip-flop 470 to the logic value "0" during the period when the clock signal CK is "0", provided that the comparison result signal CMP_OUT has a logic value "1". If these conditions are not met, the volatile register 460 retains its previous value.

[0142] Next, the case where the register restore signal REST is enabled will be described. In this case, volatile register 460 writes the non-volatile register output signal NVQ from non-volatile register 420 with the same DEC[k] to multi-bit volatile flip-flop 469, and initializes 1-bit flip-flop 470 to the logic value "0".

[0143] Figure 8 This is a diagram illustrating an example of a signal list according to a first embodiment of the present technology. In the diagram, reference is made to... Figure 6 and Figure 7 The signal names and descriptions of the above signals are summarized.

[0144] [BN register configuration example]

[0145] Figure 9 This is a diagram illustrating a configuration example of the BN register 340 according to a first embodiment of the present technology. The BN register 340 includes a BN1 register, a BN2 register, and a BN3 register. Each register is, for example, 16 bits in size.

[0146] Here, for simplicity, interrupt numbers are set to, for example, 1 to 15. Furthermore, a fixed priority scheme is used, with higher interrupt numbers indicating higher interrupt priorities. Note that a round-robin scheme can be used instead of a fixed priority scheme.

[0147] In addition, bits 1 to 15 of the BN1 register are assigned to enable / disable library use for each interrupt number, HE01 to HE15. A logic value of "0" is set in each of HE01 to HE15 when the corresponding library is disabled, and a logic value of "1" is set when the library is enabled. Bit 0 of the BN1 register is reserved.

[0148] In addition, the BN2 register has a field for the reserved library enable BNE and a field for the reserved runtime library library number BN.

[0149] The size of the library enable BNE is, for example, 2 bits. To disable library use for all interrupts, set the library enable BNE to binary "00". Furthermore, to enable library use for all interrupts except Non-Maskable Interrupts (NMI), set the library enable BNE to binary "01". To enable or disable library use according to the settings of the BN1 register, set the library enable BNE to binary "11". A binary value of "10" is reserved for the library enable BNE.

[0150] In addition, the library number BN field stores the library number of the runtime library or the starting address of the runtime library. Here, for simplicity, we assume there are 16 libraries, and that the interrupt number corresponds to the library number. Note that library number "0" is assigned to initialization processes performed, for example, during the period from startup to interrupt acceptance.

[0151] The BN3 register has a field that reserves the access flag AF, a field that reserves the recovery flag BF, a field that reserves the save flag EF, and a field that reserves the backup library number BBN.

[0152] The access flag AF is initially set to logic "0" and is set to logic "1" when the non-volatile register bank 415 is restored for the first time and written to the volatile register file 450. Furthermore, the access flag AF is initialized to logic "0" at the start of saving.

[0153] The recovery flag BF is 2 bits and its initial value is binary "00". When the recovery of the non-volatile register library 415 begins, the recovery flag BF is set to binary "01", and when the recovery is complete, it is set to binary "10". Furthermore, if the library number BN in register BN2 changes, the recovery flag BF is initialized to binary "00".

[0154] The save flag EF is 2 bits and its initial value is binary "00". When saving the non-volatile register library 415 begins, the save flag EF is set to binary "01", and when saving is complete, it is set to binary "10". Furthermore, if the library number BN in register BN2 changes, the save flag EF is initialized to binary "00".

[0155] The backup library number (BBN) is the library number of the backup library used in the event of a rollback due to a momentary power outage during task execution or library saving process.

[0156] [Semiconductor chip operation example]

[0157] Next, we will refer to Figures 10 to 13 This describes the operation of a power-down recovery compatible CPU system 300. Write and read instructions are issued by executing various programs within the power-down recovery compatible CPU system 300. The order of writing and reading, as well as the timing of the instructions, are determined based on the content and processing state of the programs. When a write instruction is issued, the following steps are executed: Figure 10 The write operation is performed, and if a read command is issued without a write operation, the operation is executed. Figure 11 Reading and processing.

[0158] In addition, a save instruction is issued to save and restore the CPU state (i.e., context) during interrupts, task switches, or power outages. Among these saving factors, in the case of saving the context due to reasons other than power outages (such as interrupts or task switches), execution... Figure 12 Normal save / restore processing. Additionally, when the power supply voltage drops below the threshold V... low In the case of the value, execute Figure 13 Power loss save / restore processing is used to save the context.

[0159] also, Figure 10 The diagram illustrates the processing corresponding to write instructions to both volatile register file 450 and non-volatile register file 410. Figure 12 The diagram illustrates the processing corresponding to a read instruction that compares data from both volatile register file 450 and non-volatile register file 410. Figure 13 and Figure 16 The diagram illustrates the processing corresponding to the save instruction. In addition to these three instructions, further write instructions to volatile register file 450 and read instructions from both volatile register file 450 and non-volatile register file 410 without comparison can be added. It is assumed that which instruction is assigned to which write / read instruction and the timing of the save instruction insertion are determined during compilation.

[0160] Figure 10 This is a flowchart illustrating an example of a write process according to a first embodiment of the present technology. The write processing unit 311 in the power-down recovery compatible CPU system 300 uses a write pulse P1 to write write data to the address of the volatile register file 450 and the address of the runtime library corresponding to the library number BN, which are identical to each other (step S901).

[0161] For example, the k-th address ADDR on the volatile side V When specified as the write destination, the same write data is written to both that address and the k-th address ADDR in the runtime library. NV .

[0162] In addition, the write processing unit 311 updates the tag bit corresponding to the address of the access destination to a logical value of "1" (step S902) and ends the write process.

[0163] Figure 11 This is a flowchart illustrating an example of a read process without writing according to a first embodiment of the present technology. The read processing unit 312 in the power-down-recovery compatible CPU system 300 reads data as read data from an address in the volatile register file 450 and an address in the runtime library indicated by BN, where these two addresses are identical (step S911).

[0164] For example, the k-th address ADDR on the volatile side V When designated as the read source, from that address and the k-th address ADDR in the runtime library. NV Read the data. The data read on the volatile side corresponds to the volatile register output signal VQ mentioned above, and the data read on the non-volatile side corresponds to the non-volatile register output signal NVQ mentioned above.

[0165] Comparator 454 in volatile register file 450 determines whether the read data (VQ) on the volatile side and the read data (NVQ) on the non-volatile side match each other (step S912).

[0166] If the read data matches each other (yes in step S912), the read processing unit 312 updates the tag bit of the access destination to a logical value of "0" (step S913). If the read data does not match each other (no in step S912), or after step S913, the read processing unit 312 ends the read processing.

[0167] Note that, in addition to Figure 10 and Figure 11 In addition to the processes shown, the access control unit 310 can also perform the following processes. For example, the access control unit 310 periodically checks the tag bits of the volatile register file 450, and when a tag bit with a logic value of "1" is included, the access control unit 310 implements adjustments such as gradually increasing the voltage or extending the write pulse width up to the upper limit of the time period corresponding to the frequency. Then, the access control unit 310 uses the adjusted higher voltage or longer write pulse width to write data from the volatile register file 450 to the address of the non-volatile register file 410 where the tag bit has a logic value of "1". Then, the access control unit 310 clears the tag bit of the completed write to a logic value of "0".

[0168] Here, when all tag bits are set to a logic value of "0", the access control unit 310 can store the voltage and write pulse width in non-volatile memory and use them as default values. When a logic value of "1" appears in the tag bit value, the access control unit 310 can perform an additional update. Therefore, a stable write operation is achieved by appropriately selecting a low voltage and short write pulse width according to the chip's operating state, rather than by achieving a stable write operation at a voltage or write pulse width that indicates 100% successful write beforehand.

[0169] Figure 12 This is a flowchart illustrating an example of normal save / restore processing in the first embodiment of the present technology. The normal save / restore processing unit 314 in the power-down recovery compatible CPU system 300 specifies the address of the access destination in the save context (step S921) and determines whether the tag bit of the address is a logical value of "1" (step S922).

[0170] When the tag bit is a logic value of "1" (yes in step S922), the normal save / restore processing unit 314 uses a high voltage write pulse P2 to write the read data (VQ) from the volatile register 460 to the runtime library indicated by BN (step S923).

[0171] For example, the k-th address ADDR on the non-volatile side NV If the specified and corresponding k-th tag bit is a logical value of "1", then the k-th address ADDR on the volatile side will be... V Read data (VQ) write address ADDR NV .

[0172] If the tag bit has a logical value of "0" (No in step S922), or after step S923, the normal save / restore processing unit 314 determines whether all addresses have been specified (step S924). If not all addresses have been specified (No in step S924), the normal save / restore processing unit 314 repeats step S921 and its subsequent steps. The processing from step S921 to step S924 corresponds to the save processing. Furthermore, as described later, all data corresponding to the address group with a logical value of "1" in the tag bit on the volatile side can be written to the corresponding address group on the non-volatile side in a single operation.

[0173] If all addresses have been specified (yes in step S924), the normal save / restore processing unit 314 determines whether it is timed to restore the context (step S925). If it is not timed to restore (no in step S925), the normal save / restore processing unit 314 returns to step S925.

[0174] If the timing for recovery is met (Yes in step S925), the normal save / recovery processing unit 314 specifies the address of the access destination in the runtime library indicated by BN (step S926).

[0175] Normal save / restore processing unit 314 writes the read data (NVQ) from the specified address in the runtime library to its corresponding volatile register 460 and the backup library indicated by BBN (step S927). Then, normal save / restore processing unit 314 updates the tag bit corresponding to the write destination address to a logical value of "1" (step S928).

[0176] Then, the normal save / restore processing unit 314 determines whether all addresses have been specified (step S929). If not all addresses have been specified (no in step S929), the normal save / restore processing unit 314 repeats step S926 and its subsequent steps. Furthermore, as described later, all data corresponding to all address groups on the non-volatile side can be written to the same address group corresponding to them on the volatile side in a single operation.

[0177] If all addresses have been specified (yes in step S929), the normal save / restore processing unit 314 ends the save / restore process. The processing from step S926 to step S929 corresponds to the restore process.

[0178] Alternatively, the normal save / restore processing unit 314 can also perform this function. Figure 13 The normal save / restore process is shown. The normal save / restore processing unit 314 determines whether the operation is save (step S921) or restore (step S922). If it is determined to be save ("Yes" in step S921), the normal save / restore processing unit 314 writes all data corresponding to the address group with a logic value "1" on the tag bit on the volatile side to the corresponding address group on the non-volatile side in a single operation using a high voltage (step S923). If it is determined to be restore ("Yes" in step S922), the normal save / restore processing unit 314 writes all data corresponding to all address groups on the non-volatile side to the corresponding address groups on the volatile side in a single operation (step S924). If neither is determined ("No" in both steps S921 and S922), the normal save / restore processing unit 314 performs neither save nor restore processing.

[0179] Note that in the first embodiment, task switching by the operating system (OS) kernel is not performed. The configuration for task switching by the OS kernel will be described later.

[0180] like Figure 12 and Figure 13 As shown, during the save period, VQ is written to the following address among all addresses in the non-volatile register bank 415: the read data on the non-volatile side (NVQ) at this address does not match the read data on the volatile side (VQ). Therefore, the inrush current during the save period can be reduced compared to the case where data is written to all addresses on the non-volatile side during the save period.

[0181] Furthermore, by using a write pulse P2 with a voltage and pulse width at least one greater than that of the write pulse P1, write errors can be minimized during the save period compared to the case where writes are performed using P1. During the write period prior to save, stable writes are achieved at voltages and pulse widths suitable for the chip's operating state by using P1 with a lower voltage or shorter pulse width than P2, and power consumption can be reduced.

[0182] Furthermore, even when a write pulse P1 is used during storage, it is conceivable to minimize write errors by copying the non-volatile register file 410, as described in Japanese Patent Application Publication No. 2018-0215777. However, using this method, copying leads to an increase in the area and power consumption of the non-volatile register file 410. In contrast, in the first embodiment, writing is performed using a write pulse P2 during storage, eliminating the need for copying. Therefore, compared to Japanese Patent Application Publication No. 2018-0215777, write errors can be minimized while reducing the area and power consumption of the non-volatile register file 410.

[0183] Figure 14 This is a flowchart illustrating an example of power drop save / restore processing according to a first embodiment of the present technology. When the power supply voltage drops below a threshold V... low In the case of a value, the power-down save / recovery processing unit 315 performs save processing from steps S921 to S924. However, in step S923, the power-down save / recovery processing unit 315 performs verification each time a write is performed using the write pulse P2, and repeats the write and verification until verification is successful. Furthermore, as described later, all data corresponding to the address group with a logic value "1" for the tag bit on the volatile side can be written to the corresponding address group on the non-volatile side in a single operation with a high voltage.

[0184] Note that the power-down save / recovery processing unit 315 can also begin writing using write pulse P1 instead of write pulse P2. In this case, the power-down save / recovery processing unit 315 performs verification each time it performs a write operation, and if verification fails, it increases the write voltage and repeats the write and verification process until verification succeeds.

[0185] Then, the power supply drop save / recovery processing unit 315 determines whether the dropped power supply voltage has risen above the threshold V. high The value (step S931). Before the power supply voltage rises above the threshold V. high If the value is "No" in step S931, the power-down save / restore processing unit 315 returns to step S931. Note that the threshold V... low This is an example of the first threshold described in the claim, and the threshold V high This is an example of the second threshold described in the claims.

[0186] Here, it is assumed that the device or system with semiconductor chip 200 has capacitors, but does not have an auxiliary power supply (e.g., an energy harvester) with a sufficiently long power supply voltage hold-up time, and there is a risk that the power supply may be interrupted during the storage process when the power supply drops.

[0187] The power supply voltage has risen above the threshold V. high If the value is "Yes" in step S931, the power-down save / restore processing unit 315 exchanges the runtime library indicated by BN and the backup library indicated by BNN (step S932).

[0188] In step S932, the power-down save / recovery processing unit 315 first writes the value of BN to temporary register T2 and then writes the value of BBN to temporary register T1. Next, the power-down save / recovery processing unit 315 writes the value of temporary register T2 to the field of BBN and then writes the value of temporary register T1 to the field of BN.

[0189] Since the above write corresponds to writing to non-volatile memory, the write is implemented such that reads and verifications are performed after the write until the write is successful, and in the event of a write failure, the write voltage is repeatedly increased. Alternatively, the write is implemented such that a write pulse P2 with a high voltage and a long pulse width is used to perform the write, and reads and verifications are repeated after the write until the write is successful.

[0190] After swapping BN and BBN, the power-down save / recovery processing unit 315 performs recovery processing from steps S926 to S929, and re-swaps the runtime library indicated by BN and the backup library indicated by BNN (step S930). Furthermore, as described later, all data corresponding to all address groups of the non-volatile registers specified by the BN field can be written in a single operation to all addresses of the non-volatile registers specified by the BBN field, as well as the corresponding address groups on the volatile side.

[0191] Note that the power-down save / restore processing unit 315 can also perform the following: Figure 15 The power-down save / recovery process is illustrated. The power-down save / recovery processing unit 315 writes all data corresponding to the address group with a logic value "1" on the volatile side to the corresponding address group on the non-volatile side in a single operation using a high voltage (step S921). Then, the power-down save / recovery processing unit 315 determines whether the decreased power supply voltage has risen above a threshold V. high The value (step S922). Before the power supply voltage rises above the threshold V. high If the value is "No" in step S922, the power supply drop save / restore processing unit 315 returns to step S921. This occurs when the power supply voltage has risen above the threshold V. high If the value is "Yes" in step S922, the power-down save / restore processing unit 315 swaps the runtime library indicated by BN and the backup library indicated by BNN (step S923). Then, the power-down save / restore processing unit 315 writes all data corresponding to all address groups of the non-volatile registers specified by the BN field to all addresses of the non-volatile registers specified by the BBN field and the corresponding address groups on the volatile side in a single operation (step S924). Then, the power-down save / restore processing unit 315 swaps the runtime library indicated by BN and the backup library indicated by BNN again (step S925).

[0192] Figure 16 This is a diagram illustrating an example of normal save / restore processing according to a first embodiment of the present technology.

[0193] For simplicity, the number of non-volatile register libraries 415 is set to four, and they are assigned library numbers "1" through "4". One of these libraries is designated as a backup library. The library switching control unit 313 designates one of the three libraries not designated as backup libraries as the runtime library and sets it in the BN register 340. For example, assume that the BN held by the BN register 340 is "1" and the BBN is "4". In the diagram, the destinations of the dashed arrows a and b indicate the runtime library and the backup library, respectively.

[0194] In the event that the context needs to be saved due to an interrupt or task switch, as shown by a in the figure, the normal save / restore processing unit 314 performs a save process to write the data read from the volatile register file 450 to the runtime library indicated by BN. In the figure, the destinations of the solid arrows a and b indicate the data save destination and restore destination, respectively.

[0195] Then, when a context switch is performed to restore the context, as shown by b in the figure, the normal save / restore processing unit 314 performs a restore process that writes data read from the runtime library indicated by BN to the volatile register file 450 and the backup library indicated by BBN. ​​Furthermore, when a context switch is not performed to restore the context, the normal save / restore processing unit 314 writes data read from the restore target library specified by the context switch to the volatile register file 450 and the backup library indicated by BBN.

[0196] Note that during the execution of the first of multiple tasks, the normal save / restore processing unit 314 only performs save processing and does not perform restore processing. When switching to the second or subsequent tasks, the normal save / restore processing unit 314 performs both the save and restore processes described above.

[0197] Figure 17 This is a diagram illustrating an example of power-down save / restore processing according to a first embodiment of the present technology. It is assumed that the power supply voltage is... Figure 16 The save and restore processes shown in the diagram drop below the threshold V. low The value of .

[0198] like Figure 17 As shown in Figure a, the power-down save / restore processing unit 315 does not perform any save processing that would write the data read from the volatile register file 450 to the runtime library indicated by BN.

[0199] Then, the decreasing power supply voltage rises above the threshold V. high When the value is specified, the power-down save / restore processing unit 315 swaps the runtime library and backup library by updating the BN register 340, as shown by b in the figure. Here, BN is updated from "1" to "4", and BBN is updated from "4" to "1".

[0200] After the swap, the power-down save / restore processing unit 315 performs the restore process of writing the data read from the runtime library indicated by BN to the volatile register file 450 and the backup library indicated by BBN.

[0201] As described above, the device or system in which the semiconductor chip 200 is arranged has no auxiliary power supply other than the capacitor, and there is a risk that the power supply may be interrupted during the save process when the power supply drops. For this reason, the save process may be terminated midway due to a power interruption, and a write error to library "1" may occur. In this case, if data needs to be recovered from library "1" without swapping, the CPU will no longer be able to perform the rollback process normally.

[0202] Therefore, as shown by b in the figure, the power-down save / restore processing unit 315 performs a restore process after swapping the runtime library (“1”) and the backup library (“4”) during power-up. In the restore process after the swap, the data of runtime library “4” (i.e., the backup library before the swap) is written to the volatile register file 450. In library “4”, through… Figure 16 The recovery process in step b has already backed up the data in library "1". Therefore, by recovering from library "4", the CPU can perform the rollback process normally even if power is interrupted during the save process. Furthermore, since recovery from library "1" is not performed, unlike in the case of interrupts or task switching, the save of library "1" in the volatile registers is not performed at all. In the recovery from library "4", all data in library "4" is completely written to library "1", BN register 340 is updated again, and the runtime library and backup library are swapped. Here, BN is updated from "4" to "1" again, and BBN is updated from "1" to "4". That is, before restarting execution, the backup number BBN is restored to "4".

[0203] As described in Non-Patent Document 1, power interruptions can also be addressed during storage processing by copying each of the N non-volatile register libraries 415. However, in this case, the number of libraries needs to be set to 2×N.

[0204] In contrast, in the first embodiment, only one backup library is required, and the number of libraries can be N+1. Therefore, compared to non-patent literature, the area and power consumption of the non-volatile register file 410 can be reduced.

[0205] Note that the power supply is complete. Figure 16 If the recovery process of b is interrupted before the backup is completed, the CPU will therefore need to restart the process from scratch after the power is restored.

[0206] In this way, according to the first embodiment of the present technology, since the semiconductor chip 200 performs recovery processing after exchanging the backup library and the runtime library when the power supply voltage rises, the required number of libraries is N+1. Therefore, compared with the non-patent literature where the required number of libraries is 2×N, the area and power consumption of the non-volatile register file 410 are reduced.

[0207] [First Variation]

[0208] In the first embodiment described above, the non-volatile library number specified by the backup number BBN is temporarily changed by swapping during the power-down save / recovery process, but is swapped again and becomes a fixed library number before execution restarts. With the backup non-volatile library fixed, reads and writes only occur repeatedly within that library, and there is a risk of degradation of the non-volatile components. To reduce this degradation risk, it is desirable to extend the backup number to make it variable. Therefore, the semiconductor chip 200 in the first variant of the first embodiment differs from the first embodiment in that a virtual library number is assigned to an interrupt process or task, and a management table associating virtual library numbers with actual library numbers is added.

[0209] Figure 18 This is a block diagram illustrating a configuration example of a power-down recovery compatible CPU system 300 of a first variant according to a first embodiment of the present technology. The power-down recovery compatible CPU system 300 in the first variant of the first embodiment differs from that of the first embodiment in that it also provides a virtual / physical library number management table 360.

[0210] The virtual / real library number management table 360 ​​associates the virtual library number assigned to an interrupt handler or task with the real library number assigned to each of the multiple non-volatile register libraries 415. The virtual / real library number management table 360 ​​is maintained in non-volatile memory or registers.

[0211] Figure 19 This is a diagram illustrating a configuration example of a virtual / real library number management table 360 ​​of a first variant according to a first embodiment of the present technology. As the virtual / real library number management table 360, for example, extended associative memory is used. This memory includes an address decoder 361, multiple non-volatile registers 370, a volatile register 362, and an encoder 363.

[0212] The number of non-volatile registers 370 is the same as the number of non-volatile registers in register library 415, and is N+1. The address of non-volatile register 370 is ADDR. CAM The actual library numbers of the non-volatile register library 415 correspond one-to-one with each other. For example, the nth address ADDR CAM This corresponds to the actual library number "n". In the diagram, "(R)" indicates that the number is the actual library number.

[0213] Address ADDR from access control unit 310 CAM It is input into address decoder 361. Address decoder 361 decodes address ADDR. CAM And generate an N+1 bit one-hot signal DEC CAM Unique heat signal DEC CAM The nth bit is input into the nth non-volatile register 370.

[0214] Non-volatile register 370 stores the virtual library number. The size of the data indicating the virtual library number is defined as S bits (where S is an integer). When the virtual library number is to be stored in association with the actual library number, access control unit 310 supplies an access control signal indicating write, S bits of data indicating the virtual library number, and the address ADDR corresponding to the actual library number. CAM .

[0215] Furthermore, the non-volatile register 370 outputs reserved data to the access control unit 310 based on the access control signal. When it is necessary to read the virtual library number corresponding to the actual library number, the access control unit 310 supplies an access control signal indicating read and the address ADDR corresponding to the actual library number. CAM .

[0216] Volatile register 362 holds the S-bit query search data indicating the virtual library number. Volatile register 362 compares the held data with the query search data and outputs the comparison result CMP to encoder 363. n For example, if the data held by the nth non-volatile register 370 matches the query search data, only the comparison result CMP is considered. n Set the logical value "1" in the first comparison and set the logical value "0" in the remaining comparison results.

[0217] Encoder 363 will store the address ADDR of the non-volatile register 370 containing the logic value "1" from the N+1 comparison results. CAM The data is converted to the actual library number corresponding to that address. The encoder 363 outputs the converted data to the access control unit 310.

[0218] When it is necessary to convert a virtual library number into an actual library number, the access control unit 310 supplies query search data indicating the virtual library number and receives data of the actual library number from the encoder 363.

[0219] Furthermore, during the swap operation, the power-down save / recovery processing unit 315 reads the data corresponding to the address of BN from the virtual / real library number management table 360 ​​and writes this data to temporary register T2. Additionally, the power-down save / recovery processing unit 315 reads the data corresponding to the address of BBN and writes this data to temporary register T1. Next, the power-down save / recovery processing unit 315 writes the value of temporary register T2 to the address corresponding to BBN in the virtual / real library number management table 360, and writes the value of temporary register T1 to the address corresponding to BN.

[0220] Since the above write and register operations correspond to writes to non-volatile memory, the write and register operations are implemented such that reads and verifications are performed after the write operation until the write is successful, and the write voltage is repeatedly increased in the event of a write failure. Alternatively, the write operation is implemented such that a write pulse P2 with a high voltage and a long pulse width is used to perform the write operation, and reads and verifications are repeated after the write operation until the write is successful.

[0221] Figure 20 This is a circuit diagram illustrating a configuration example of a non-volatile register 370 of a first variant according to a first embodiment of the present technology. The non-volatile register 370 includes AND gates 371 and 372, S non-volatile flip-flops 373, S XOR gates 374 and NOR gates 375.

[0222] AND gate 371 outputs the access control signal R / W from access control unit 310 to AND gate 372. CAM and DEC from address decoder 361 CAM The logical product of [n]. Access control signal R / W is used when performing a write or read operation. CAM It is set to the logical value "1", and otherwise set to the logical value "0". DEC CAM [n] indicates the nth bit of the hot-swappable signal of address decoder 361.

[0223] AND gate 372 supplies the logic product of the output signal of AND gate 371 and the clock signal CK to the clock terminal of each non-volatile flip-flop 373.

[0224] Non-volatile flip-flop 373 holds 1 bit. The s-th non-volatile flip-flop 373 (where s is an integer from 1 to S) receives the s-th bit of S-bit data indicating the virtual library number at its input terminal. In addition, the s-th non-volatile flip-flop 373 outputs the held bit to the s-th XOR gate 374 and the access control unit 310.

[0225] The s-th bit of the query data and the output bit of the s-th non-volatile flip-flop 373 are input to the s-th XOR gate 374. The XOR gate 374 outputs a mutual exclusion logic AND of these bits to the NOR gate 375.

[0226] The NOR gate 375 outputs the negative logic sum of the output signals of each of the S XOR gates 374 to the encoder 363 as the comparison result CMP. n .

[0227] Figure 21This is a diagram illustrating an example of updating the virtual / real library number management table 360 ​​and the BN register 340 according to a first variant of a first embodiment of the present technology. In the diagram, numbers marked with "(R)" are real library numbers, and numbers marked with "(V)" are virtual library numbers.

[0228] Assume that the interrupt number and task number are renumbered so that the numbers are unique and increment from 1 to N+1, and the values ​​with the same numbers are used as virtual library numbers. The virtual library number corresponding to each physical library number is stored in the virtual / physical library number management table 360. For ease of illustration, N is set to "3" (i.e., the number of libraries is set to four). Furthermore, the physical library number BN of the runtime library and the physical library number BBN of the backup library are stored in the BN register 340.

[0229] During time period Pd1, the virtual / real library number management table 360 ​​and BN register 340 are in their initial state. For example, virtual library numbers that are the same as real library numbers “1(R)” through “4(R)” are maintained in association with the real library numbers. In addition, in the initial state, BN is “1(R)” and BBN is “N+1” (i.e., “4(R)”).

[0230] Then, assume that a context switch from task number "1" to task number "2" is performed during time period Pd2. Furthermore, assume that the task number is directly used as the virtual library number. Access control unit 310 performs a save process that writes data from volatile register file 450 to BN ("1(R)"), reads the actual library number "2(R)" corresponding to virtual library number "2(V)" from virtual / actual library number management table 360, and updates the BN in BN register 340 to that number. In the figure, the shaded area indicates the updated data.

[0231] In addition, the access control unit 310 performs the process of writing data from BN (“2(R)”) to the volatile register file 450 and the recovery process of BBN (“4(R)”).

[0232] Then, assume that power is interrupted during task execution in time period Pd3, specifically during task number "2". When power is restored, access control unit 310 swaps BN and BBN. ​​Specifically, the BN field in BN register 340 is updated from "2(R)" to "4(R)", and the BBN field is updated from "4(R)" to "2(R)". After the swap, access control unit 310 performs a recovery process that writes data from BN ("4(R)") to volatile register file 450 and BBN ("2(R)").

[0233] Then, assume that a context switch from task number "2" to task number "3" is performed during time period Pd4. Access control unit 310 performs a save process to write data from volatile register file 450 to BN ("4(R)") and updates the actual library number "4(R)" in the BN field to the actual library number "3(R)" corresponding to the virtual library number "3(V)".

[0234] In addition, the access control unit 310 performs the process of writing data from BN (“3(R)”) to the volatile register file 450 and the recovery process of BBN (“2(R)”).

[0235] Then, assume that power is interrupted during task execution (task number "3") in time period Pd5. When power is restored, access control unit 310 swaps BN and BBN. ​​Specifically, the BN field in BN register 340 is updated from "3(R)" to "2(R)", and the BBN field is updated from "2(R)" to "3(R)". After the swap, access control unit 310 performs a recovery process that writes data from BN ("2(R)") to volatile register file 450 and BBN ("3(R)").

[0236] Then, assume that a context switch from task number "3" to task number "1" is performed during time period Pd6. Access control unit 310 performs a save process to write data from volatile register file 450 to BN ("2(R)") and updates the actual library number "2(R)" in the BN field to the actual library number "1(R)" corresponding to the virtual library number "1(V)".

[0237] In addition, the access control unit 310 performs the process of writing data from BN (“1(R)”) to the volatile register file 450 and the recovery process of BBN (“3(R)”).

[0238] Then, assume that power is interrupted during task execution in period Pd7, specifically during task number "1". When power is restored, access control unit 310 swaps BN and BBN. ​​Specifically, the BN field in BN register 340 is updated from "1(R)" to "3(R)", and the BBN field is updated from "3(R)" to "1(R)". After the swap, access control unit 310 performs a recovery process that writes data from BN ("3(R)") to volatile register file 450 and BBN ("1(R)").

[0239] Then, assume that a context switch from task number "1" to task number "3" is performed during time period Pd8. Access control unit 310 performs a save process to write data from volatile register file 450 to BN ("3(R)") and updates the actual library number "3(R)" in the BN field to the actual library number "2(R)" corresponding to the virtual library number "3(V)".

[0240] In addition, the access control unit 310 performs the recovery process of writing data from BN (“2(R)”) to the volatile register file 450 and BBN (“1(R)”).

[0241] Then, assume that power is interrupted during task execution (task number "3") in time period Pd9. When power is restored, access control unit 310 swaps BN and BBN. ​​Specifically, the BN field in BN register 340 is updated from "2(R)" to "1(R)", and the BBN field is updated from "1(R)" to "2(R)". After the swap, access control unit 310 performs a recovery process that writes the data from BN ("1(R)") to volatile register file 450 and BBN ("2(R)").

[0242] As shown in the figure, when there are three or more tasks, the value of the BN field may not necessarily match the interruption number or task number (i.e., the virtual library number). Therefore, the virtual / real library number management table 360 ​​must be used to manage the real library numbers stored in the BN field.

[0243] For example, in time period Pd8, when switching from task number "1" to task number "3", the switched task number (i.e., virtual library number) is "3 (V)", while the BN actual library number is "2 (R)". Even if the task number and the BN actual library number no longer match in this way, the actual library number can be properly managed by using the virtual / actual library number management table 360.

[0244] Note that in the first variant of the first embodiment, the power-down save / restore processing unit 315 can also perform the following: Figure 22 The power-down save / recovery process is illustrated. In a single operation, the power-down save / recovery processing unit 315 writes all data corresponding to the address group with a logic value "1" on the volatile side's tag bit to the same address group on the non-volatile side at a high voltage (step S921). Then, the power-down save / recovery processing unit 315 determines whether the decreased power supply voltage has risen above a threshold V. high The value (step S922). Before the power supply voltage rises above the threshold V. highIf the value is not specified in step S922 (no), the power supply drop save / restore processing unit 315 returns to step S921. This occurs when the power supply voltage has risen above the threshold V. high If the value is true (yes in step S922), the power-down save / restore processing unit 315 swaps the runtime library indicated by BN and the backup library indicated by BNN (step S923). Then, in a single operation, the power-down save / restore processing unit 315 writes all data corresponding to all address groups of the non-volatile registers specified by the BN field to all corresponding addresses of the non-volatile registers specified by the BN field and all corresponding addresses of the volatile side in a high voltage (step S924).

[0245] In this way, according to the first variation of the first embodiment of the present technology, since a virtual / real library number management table 360 ​​that associates virtual library numbers with real library numbers is further provided, the real library numbers can be properly managed even when there are three or more tasks.

[0246] [Second Variation]

[0247] In the first variant of the first embodiment described above, task switching by the OS kernel is not supported, but the configuration is not limited to this. The semiconductor chip 200 in this second variant of the first embodiment differs from the first variant in that it also supports task switching by the OS kernel.

[0248] Figure 23 This is a diagram illustrating a configuration example of the BN register 340 in a second variant of the first embodiment of the present technology. The BN register 340 in this second variant of the first embodiment includes associated memories BN0, BN1 register, BN(i) sub-register, BN2 register, and BN3 register. Here, i is an integer from 0 to 15. The data size of each of the BN1 register, BN(i) sub-register, BN2 register, and BN3 register is, for example, 16 bits.

[0249] For simplicity, hardware interrupt numbers are set from 1 to 15, and OS interrupt numbers are set from 1 to 255. Higher numbers indicate higher interrupt priority, and hardware interrupts have a higher priority than OS interrupts. A fixed priority scheme is used between hardware interrupts and between OS interrupts, but a round-robin scheme can also be used.

[0250] Each interrupt number is set to enable or disable library use. HE01 to HE15 are assigned to bits 1 to 15 of the BN1 register, and OSE1 to OSE255 are assigned to the corresponding bits of the 16 BN1(i) sub-registers.

[0251] When the corresponding library is disabled, a logical value of "0" is set in each of HE01 to HE15, and when the corresponding library is enabled, a logical value of "1" is set in it. Bit 0 of the BN1 register is a reserved bit.

[0252] When the corresponding library is disabled, a logical value of "0" is set in each of OSE1 to OSE255, and when the library is enabled, a logical value of "1" is set therein. Bit 0 of the BN1(0) sub-register is a reserved bit.

[0253] In addition, the BN2 register has a field that holds the library enabled by BNE and a field that holds the actual library number BN.

[0254] The size of the library enable BNE is, for example, 2 bits. When library use is disabled for all interrupts, a binary "00" is set in the library enable BNE. Furthermore, when library use is enabled for all interrupts except NMI, a binary "01" is set in the library enable BNE. When enabling or disabling library use follows the settings of the BN1 register and the BN(i) sub-register, a binary "11" is set in the library enable BNE. For the library enable BNE, the value of a binary "10" is retained.

[0255] In addition, the library number BN field retains the actual library number or the starting address of the running library.

[0256] For simplicity, the number of libraries is set to 272, and for example, among virtual library numbers 0 to 271, numbers 1 to 15 correspond to hardware interrupt numbers, and numbers 17 to 271 correspond to OS interrupt numbers. The value obtained by adding 16 to the hardware interrupt number and the OS interrupt number is used as the virtual library number.

[0257] The actual library number 0 always matches the virtual library number 0 and is assigned to, for example, initialization processes from startup to interrupt acceptance or from startup to OS startup. The actual library number 16 always matches the virtual library number 16 and is assigned to, for example, processes from OS startup until task execution begins.

[0258] The configuration of the BN3 register in the second variant of this first embodiment is the same as that in the first embodiment.

[0259] Associated memory BN0 is used to register the task number used by the OS kernel during task switching as an additional interrupt number.

[0260] Figure 24This is a diagram illustrating a configuration example of an associative memory BN0 of a second variant according to a first embodiment of the present technology. The associative memory BN0 includes 255 non-volatile registers 351, volatile registers 352, and an encoder 353.

[0261] The library switching control unit 313 can store (in other words, register) task numbers in each of the 255 non-volatile registers 351. OS interrupt numbers 1 to 255 correspond to the corresponding addresses of these non-volatile registers 351. Furthermore, the library switching control unit 313 can generate query search data for any of the specified non-volatile registers 351 and maintain the query search data in volatile registers 352. The encoder 353 outputs the address of the non-volatile register 351 that matches the query search data, as its corresponding OS interrupt number. Note that when using a fixed priority scheme, the priority of a task number can be changed by altering its registration address.

[0262] Using the configuration shown in the figure, the library switching control unit 313 can use the associated memory BN0 to convert the task number into an OS interrupt number. The value obtained by adding 16 to the OS interrupt number is used as the virtual library number. By using the virtual / actual library number management table 360 ​​described above, the actual library number corresponding to the virtual library number can be obtained.

[0263] In this way, according to the second variation of the first embodiment of the present technology, since the BN(i) sub-register and the associated memory BN0 are added to the BN register 340, task switching by the OS kernel can be supported.

[0264] <2. Second Embodiment>

[0265] In the second variation of the first embodiment described above, a non-volatile register file 410 and a volatile register file 450 are provided, but these can be used as CPU register files within the CPU. The difference between the semiconductor chip 200 in this second embodiment and the second variation of the first embodiment is that the non-volatile register file 410 and the volatile register file 450 are used as CPU register files.

[0266] Figure 25 This is a block diagram illustrating a configuration example of a power-down recovery compatible CPU system 300 according to a second embodiment of the present technology. The power-down recovery compatible CPU system 300 in the second embodiment includes a program read-only memory (ROM) 331, a data save / restore / library switch sequencer 332, an instruction fetch decoder 333, an address arithmetic circuit 334, a storage unit 400, and an arithmetic circuit 335.

[0267] Similar to the first embodiment, the storage unit 400 in the second embodiment includes a non-volatile register file 410 and a volatile register file 450. These are used as CPU register files.

[0268] The program to be executed by the CPU is stored in program ROM 331.

[0269] The data save / restore / library switch sequencer 332 performs data save processing, restore processing, and library switching. Detection signals, interrupt numbers, and OS task numbers are input to the data save / restore / library switch sequencer 332. The detection signals include a power drop detection signal indicating a power decrease and a power rise detection signal indicating a power increase. The save and restore processes performed by the data save / restore / library switch sequencer 332 are the same as those described in the first embodiment.

[0270] When an interrupt number or OS task number is input to the data save / restore / library switch sequencer 332, the sequencer compares the priority of each of these numbers with the priority of the interrupt number (hardware interrupt number or OS interrupt number) corresponding to BN in the BN2 register. If the input number has a higher priority, the sequencer selects the library corresponding to that number as the running library and performs data save processing, restore processing, and library switching.

[0271] On the other hand, if the input number has a low priority, the data save / restore / library switcher 332 waits for the processing corresponding to the currently active BN to complete before switching to the library corresponding to the input number. Alternatively, the data save / restore / library switcher 332 does not accept interrupt nesting. Alternatively, the data save / restore / library switcher 332 can accept interrupt nesting and handle it by storing its number in a first-in-first-out (FIFO) manner.

[0272] Furthermore, upon receiving a detection signal indicating a drop or rise in the power supply voltage, the data save / restore / library switch sequencer 332 performs the aforementioned save process as well as the exchange and restore process.

[0273] The instruction fetch decoder 333 fetches and decodes instructions from the program ROM 331. By decoding the instructions indicating write or read, the instruction fetch decoder 333 obtains the aforementioned access control signals R / W and the address of the access destination, and supplies them to the storage unit 400.

[0274] The address arithmetic circuit 334 obtains the address of the register file through instruction decoding.

[0275] Arithmetic circuit 335 performs various arithmetic operations as needed. This arithmetic circuit 335 supplies initial value data or data obtained through arithmetic operations to storage unit 400 as write data. Furthermore, arithmetic circuit 335 receives read data from storage unit 400 and performs various arithmetic operations on the read data.

[0276] Using the configuration shown in the diagram, the following can be achieved: Figure 3 and Figure 18 The various functions of the access control unit 310 are shown.

[0277] Figure 26 This is a diagram illustrating a register list according to a second embodiment of the present technology. At least some of the registers shown in the figure are arranged in each of the non-volatile register file 410 and the volatile register file 450.

[0278] For example, general-purpose registers, stack pointer registers, program counter registers, save program counter registers, processor status word registers, and save status registers can be used. Additionally, procedure registers, multiplication registers, base registers, vector base registers, read data buffer registers, and write data buffer registers can also be used.

[0279] General purpose registers R0 to R n-2 It is a register that can be used as both an address register and a data register. The stack pointer register SP is a register that indicates the stackable addresses in the stack area. For example, R n-1 It can be used as the SP (Service Pack). The Program Counter (PC) register is a register that indicates the address of the instruction executed by the CPU. The Save Program Counter (BPC) register is used to save the program counter when a general exception or interrupt request is received. The Processor Status Word (PSW) register is a status register that stores the result of instruction execution and the CPU's status. The Save Status Word (BPSW) register is used to save the PSW when a general exception or interrupt request is received.

[0280] The procedure register PR is used to store the return address during a subroutine call. The multiplication registers MACH and MACL are used to store the results of multiplication and multiply-accumulate operations. The base register GBR is used to store the base address in indirect addressing mode. The vector base register VBR is used to store the base address of the exception handler. The read data buffer register RDR is used to store data read from memory. The write data buffer register WDR is used to store data written to memory.

[0281] Furthermore, in the second embodiment, the following implementation schemes can be used as the CPU configuration.

[0282] First, in the interrupt vector scheme, the BN register 340 and the interrupt vector include non-volatile registers such as non-volatile multi-bit registers. The access control unit 310 repeatedly writes and reads to verify until the write is successful. Furthermore, the control registers associated with access to the non-volatile memory also include similar non-volatile registers.

[0283] Secondly, in interrupt execution with an interrupt number not enabled by BN register 340, the program is executed using only the volatile register. It is assumed that a restart handler is executed, triggered by an interrupt caused by a power-up detection signal upon recovery from a power failure. In the case of a single register, since no interrupt number is assigned, a control register for registering interrupt numbers involving access to non-volatile memory is installed in memory cell 400.

[0284] Furthermore, consider the scenario of resuming execution from a program context that has experienced a power outage. In this case, control registers and status registers within the I / O peripherals, direct memory access (DMA) controller, and interrupt controller that may be configured to reach the context are arranged in memory unit 400. These control registers and status registers can be used... Figure 4 and Figure 5 The proposed scheme or a non-volatile memory scheme that involves repeated write and read verification until a successful write is achieved can be implemented.

[0285] In addition, BN register 340 can be provided with fields for specifying the following three items for each library. The first is a field where interrupt numbers can be specified as enabled or disabled. When all interrupt numbers are disabled, the program is executed using only volatile memory.

[0286] The second is a field used to specify whether task switching interrupts are allowed or disabled by registering the task number used by the OS kernel during task switching in associated memory as an additional interrupt number.

[0287] Third is the BN field. In the case of a register file, the BN value is used as the library number specification, and in the case of temporary storage or main memory, the BN value is used as the starting address of the library.

[0288] Figure 27 This is a block diagram illustrating a configuration example of a storage unit 400 according to a second embodiment of the present technology. As shown, each of the N+1 non-volatile register libraries 415 includes, for example, general-purpose registers R0 to R10. n-2 and the stack pointer register SP. In addition, each non-volatile register bank 415 includes the program counter register PC, the processor status word register PSW, the procedure register PR, the base address register GBR, and the vector base address register VBR. Besides R0 to R... n-2In addition to SP, PC, PSW, PR, GBR, and VBR, the volatile register file 450 also retains the tag bit TAG for each register.

[0289] As described above, in the second embodiment, the non-volatile register file 410 and the volatile register file 450 are used as CPU register files. Therefore, even in the event of a write error to the non-volatile memory due to a power outage during save processing, the effect of a multitasking CPU that can be recovered normally can be achieved.

[0290] In this way, according to the second embodiment of the present technology, since non-volatile register file 410 and volatile register file 450 are used as CPU register files, a multitasking CPU capable of handling power outages during save processing can be realized.

[0291] <3. Third Embodiment>

[0292] In the second embodiment described above, the non-volatile register file 410 has a multi-library configuration; however, in main memory, temporary memory, etc., memory can be shared by multiple entities. The semiconductor chip 200 in the third embodiment differs from the second embodiment in that it provides shared resources in each of the volatile and non-volatile memories.

[0293] Figure 28 This is a block diagram illustrating a configuration example of a storage unit 400 according to a third embodiment of the present technology. In the storage unit 400 of the third embodiment, non-volatile memory 430 and volatile memory 480 are arranged to replace non-volatile register file 410 and volatile register file 450.

[0294] Non-volatile memory 430 includes non-volatile memory shared resources 441 and non-volatile memory non-shared resources 442. Note that the address decoders and output selectors within each resource are omitted in the figure.

[0295] Non-volatile memory shared resource 441 is a memory region that holds shared data shared by multiple entities (such as tasks and interrupt handlers) and includes two non-volatile memory shared libraries 443. One of these libraries is assigned the physical library number "1" and the other is assigned the physical library number "2".

[0296] Non-volatile memory non-shared resources 442 are memory regions that reserve data that does not correspond to shared data, and include N+1 non-volatile memory non-shared libraries 444. It should be noted that non-volatile register files can have a multi-library configuration instead of non-volatile memory.

[0297] It should be noted that nonvolatile memory shared library 443 is an example of a nonvolatile shared library, which is described in the claims. Nonvolatile memory non-shared library 444 is an example of a nonvolatile non-shared library, which is described in the claims.

[0298] Figure 29 This is a block diagram illustrating a configuration example of volatile memory 480 according to a third embodiment of the present technology. This volatile memory 480 in the third embodiment includes a shared volatile memory resource 481 and a non-shared volatile memory resource 482. Note that the address decoders and output selectors within each resource are omitted in the figure.

[0299] Volatile memory shared resource 481 is a memory region that holds shared data, and volatile memory non-shared resource 482 is a memory region that holds data that does not correspond to shared data. It should be noted that a volatile register file can also be used instead of volatile memory to provide both volatile shared and non-shared resources.

[0300] Furthermore, the size and number of addresses of the volatile memory shared resource 481 are the same as those of each non-volatile memory shared library 443. The size and number of addresses of the volatile memory non-shared resource 482 are also the same as those of each non-volatile memory non-shared library 444.

[0301] It should be noted that volatile memory shared resource 481 is an example of a volatile shared resource, which is described in the claims. Volatile memory non-shared resource 482 is an example of a volatile non-shared resource, which is described in the claims.

[0302] Figure 30 This is a diagram illustrating a configuration example of the BN register 340 according to a third embodiment of the present technology. The difference between the BN register 340 in the third embodiment and the second embodiment is that the BN3 register also has a field that reserves the shared set bit CF.

[0303] The shared setting bit CF is used to specify which of the two non-volatile memory shared libraries 443 is designated as the backup library. When the non-volatile memory shared library 443 with library number "1" is designated as the runtime library and the non-volatile memory shared library 443 with library number "2" is designated as the backup library, the logical value "0" is set in the shared setting bit CF. When the non-volatile memory shared library 443 with library number "2" is designated as the runtime library and the non-volatile memory shared library 443 with library number "1" is designated as the backup library, the logical value "1" is set in the shared setting bit CF.

[0304] Figure 31 This is a block diagram illustrating a configuration example of a power-recovery compatible CPU system 300 according to a third embodiment of the present technology. The power-recovery compatible CPU system 300 in the third embodiment includes a program ROM 331, a data save / restore / library switch sequencer 332, an instruction fetch decoder 333, address arithmetic circuitry 334, and arithmetic circuitry 335. Furthermore, the power-recovery compatible CPU system 300 includes a volatile memory shared resource address assignment register 336, a non-volatile memory shared resource 441, and a non-volatile memory non-shared resource 442. The power-recovery compatible CPU system 300 also includes a volatile memory shared resource 481, a volatile memory non-shared resource 482, an address converter 337, a data bus 338, and an address bus 339.

[0305] As described above, the non-volatile memory non-shared resource 442 has a multi-library configuration, and each register in the CPU register file described above (such as the program counter register) can be arranged in each of the libraries and in the non-volatile memory non-shared resource 482. Furthermore, the volatile memory shared resource 481 and the volatile memory non-shared resource 482 reserve tag bits for each address.

[0306] Furthermore, as described above, the non-volatile memory shared resource 441 also has a multi-library configuration, and library switching within the non-volatile memory non-shared resource 442 and library switching within the non-volatile memory shared resource 441 are performed synchronously.

[0307] To achieve this, the address arithmetic circuit 334 obtains the conversion results of the address decoder corresponding to BF and BBN as offsets. Based on these offsets, the address converter 337 calculates the start addresses of the non-volatile runtime library and backup library corresponding to the non-shared resource 482 of the volatile memory. Thus, the effect of synchronous library switching and appropriate write and read access is achieved.

[0308] Furthermore, BBN in the BN3 register is translated into the appropriate start address of the non-volatile backup library via address translation. Therefore, library swapping within the non-volatile memory shared resource 441 during power-off recovery is also performed synchronously with library swapping within the non-volatile memory non-shared resource 442.

[0309] Address converter 337 can be implemented as a combinational circuit with flip-flop outputs. Alternatively, address converter 337 can be implemented as a register file or SRAM, in which an interrupt number is used as an address to register the start address of the non-volatile memory non-shared library 444. Address converter 337 can perform address translation using an address translation mechanism within the number of cycles required for data transfer via the bus.

[0310] The initial value of the start address of the volatile memory shared resource 481 is stored in the volatile memory shared resource address specification register 336.

[0311] Furthermore, upon input of a detection signal, interrupt number, or OS task number, the data save / restore / library switch sequencer 332 executes the aforementioned reference. Figure 12 and Figure 13 The description covers data saving, recovery, and database switching.

[0312] It is important to note that the data save / restore / library switcher 332 can also perform data save processing periodically. For example, the data save / restore / library switcher 332 periodically checks the tag bits of the volatile memory and, while gradually increasing the voltage of the write pulse, writes data from the volatile memory to the address where the tag bit has a logic value of "1". Then, the data save / restore / library switcher 332 confirms whether the read data matches each other, clears the tag bits that have been written to a logic value of "0", and can stop increasing the voltage at the voltage when all bits have been successfully written.

[0313] With the above configuration, even in the event of a write error to non-volatile memory, power-loss recovery can be enabled in a multitasking environment.

[0314] As described above, shared data is managed by volatile memory shared resource 481 and non-volatile memory shared resource 441, while other data is managed by volatile memory non-shared resource 482 and non-volatile memory shared library 443. Therefore, the consistency of public data within shared resources is ensured.

[0315] In this way, according to the third embodiment of the present technology, memory can be utilized more efficiently because shared and non-shared resources are provided in each of the volatile memory 480 and the non-volatile memory 430.

[0316] <4. Fourth Embodiment>

[0317] In the second variation of the first embodiment described above, in the absence of an auxiliary power source other than a capacitor, the semiconductor chip 200 performs data saving and recovery processing in response to a detection signal indicating a drop or rise in the power supply voltage. The semiconductor chip 200 in this fourth embodiment differs from the second variation of the first embodiment in that it is housed within a semiconductor device equipped with a power supply drop / rise detection circuit.

[0318] Figure 32This is a block diagram illustrating a configuration example of a semiconductor device 100 according to a fourth embodiment of the present technology. The semiconductor device 100 includes a power drop / rise detection circuit 110, a semiconductor chip 200, a power control unit 120, and a capacitor 130. The semiconductor device 100 is assumed to be, for example, a smartphone or an in-vehicle camera.

[0319] Power supply drop / rise detection circuit 110 detects that the power supply voltage has dropped below the threshold voltage V. low The value, and the decreasing power supply voltage has risen above the threshold V. high The value of the power drop / rise detection circuit 110 supplies detection signals (power drop detection signal and power rise detection signal) indicating these detection results to the semiconductor chip 200. Threshold V high It is different from the threshold V low The value is higher than the threshold V. low The value is set to the threshold V high ,For example.

[0320] Note that the threshold V low This is an example of the first threshold described in the claim, and the threshold V high This is an example of the second threshold described in the claims.

[0321] The configuration of the semiconductor chip 200 in the fourth embodiment is the same as that in the second variant of the first embodiment. However, it is assumed that the semiconductor chip 200 in the fourth embodiment retains a power-off non-volatile flag in a non-volatile register or memory. The initial value of this power-off non-volatile flag is initialized to the logic value "0" during the first startup.

[0322] The power control unit 120 controls the power supply voltage of the semiconductor device 100.

[0323] When the power supply voltage drops, capacitor 130 maintains the power supply voltage for a certain period of time. The time from the drop in power supply voltage until the storage process is completed is not necessarily constant, but its maximum time is defined as T. max Assume that the power supply voltage is maintained by capacitor 130 for less than T. max Furthermore, there is a risk that the power supply voltage may be interrupted during the storage process.

[0324] When the power supply voltage drops below the threshold V low When the value is specified, the power supply drop / rise detection circuit 110 supplies a power supply drop detection signal to the semiconductor chip 200.

[0325] Upon receiving a voltage drop detection signal, the semiconductor chip 200 performs the aforementioned storage process and updates the power-off non-volatile flag to a logic value of "1". This power-off non-volatile flag is initialized to a logic value of "0" when the power supply voltage rises.

[0326] Then, the decreasing power supply voltage rises above the threshold V. high When the value is specified, the power supply drop / rise detection circuit 110 supplies a power supply rise detection signal to the semiconductor chip 200.

[0327] Upon receiving a power-up detection signal, the power-down save / recovery processing unit 315 within the semiconductor chip 200 initiates a restart procedure and checks the power-down non-volatile flag. If the power-down non-volatile flag has a logic value of "0", the power-down save / recovery processing unit 315 executes a normal restart sequence accompanied by the initialization of the BN register 340 and the virtual / real library number management table 360.

[0328] On the other hand, when the power-off non-volatile flag has a logic value of "1", the power-down save / recovery processing unit 315 checks the values ​​of AF, BF and EF in the BN3 register and determines whether the following formula is satisfied.

[0329] AF = "1" ∨ EF = "01" ∨ EF = "10" ... Expression 1

[0330] In the above expression, "∨" represents a logical sum.

[0331] If Expression 1 is satisfied, it indicates that a power outage occurred during task processing, during save processing, or immediately after save processing completion. In this case, the power-down save / restore processing unit 315, as described above, clears the power-down non-volatile flag to a logic value of "0" after exchanging the runtime library and backup library, and performs restore processing. If Expression 1 is not satisfied, i.e., AF = "0" ∧ EF = "00" ... Expression 2 If expression 2 is satisfied, perform recovery processing without swapping runtime and backup libraries. Here, "∧" represents a logical product.

[0332] Here, it is assumed that the program used to perform the above processing is stored in non-volatile memory and executed on that memory.

[0333] As described above, since the power supply drop / rise detection circuit 110 detects the drop and rise of the power supply voltage, the semiconductor chip 200 can perform save processing and restore processing at appropriate times according to the detection signal.

[0334] Note that the third embodiment, which includes shared and non-shared resources, can be applied to the fourth embodiment. In this case, the power-down save / recovery processing unit 315 performs a bit flip on the shared setting bit CF during the recovery process. Then, the power-down save / recovery processing unit 315 writes the runtime library data in the non-volatile memory shared resource 441 indicated by the shared setting bit CF to the volatile memory shared resource 481 and the backup library indicated by CF.

[0335] Next, we will describe the specific processing for the case where CIS is used as semiconductor chip 200.

[0336] First, regarding the register settings of the digital signal processing unit 220, these are implemented in non-volatile memory and are configured to repeatedly read and verify and rewrite during setup until the write operation is complete, in preparation for power failure. Furthermore, after the power supply voltage rises, when the startup process checks the power-off non-volatile flag, if the value of the power-off non-volatile flag is logic "1", the CIS performs initial setup processing without taking any action.

[0337] The line memory used for image data accumulation requires frame synchronization and is therefore not located in storage unit 400, but is implemented as volatile memory.

[0338] Similarly, the frame memory used for image data accumulation is not located in the storage unit 400, but is implemented as volatile memory.

[0339] Next, consider the case where an AE control unit is installed. In this case, the CIS writes the statistical processing results information used for analog / digital gain adjustment in AE control to volatile memory 480 and non-volatile memory 430. After restarting, whether to use the statistical processing results information stored in non-volatile memory 430 or a separately set default value for gain adjustment can be selected by register settings.

[0340] Then, upon receiving a voltage drop detection signal, the CIS stores the statistical processing result information embedded in the AE control unit. As described above, the CIS uses write pulse P2 to write the data at the address where the tag bit of the volatile memory 480 has a logic value of "1" to the non-volatile register bank 415, and clears the tag bit of the completed write to a logic value of "0". The CIS also retains the statistical information non-volatile flag bit, and writes a logic value of "1" to the statistical information non-volatile flag bit if all writes are successful. If the power-off non-volatile flag bit is a logic value of "0", the statistical information non-volatile flag bit is initialized to a logic value of "0", and if the power-off non-volatile flag bit is a logic value of "1", it is cleared to a logic value of "0" after reading. That is, if the write of a logic value of "1" is not completed during the power supply period via auxiliary power, the statistical information non-volatile flag bit remains at a logic value of "0".

[0341] Then, after power is restored, the CIS checks the power-off non-volatile flag by starting the process. If the power-off non-volatile flag has a logic value of "0", the CIS uses the default value for gain adjustment and initializes the statistical processing result information regardless of the user-set register value. If the power-off non-volatile flag has a logic value of "1", the CIS checks the statistical information non-volatile flag. If the statistical information non-volatile flag has a logic value of "0", the CIS uses the default value for gain adjustment and initializes the statistical processing result information regardless of the user-set register value. If the statistical information non-volatile flag has a logic value of "1", the CIS performs gain adjustment based on either the statistical processing result information or the separately set default value, according to the user-set register value.

[0342] Through the above processing, a CIS that can recover properly and quickly from a power outage can be achieved.

[0343] In this way, according to the fourth embodiment of the present technology, since the power supply drop / rise detection circuit 110 detects the drop and rise of the power supply voltage, the semiconductor chip 200 can perform save processing and restore processing at appropriate timings based on the detection signal.

[0344] <5. Fifth Embodiment>

[0345] In the fourth embodiment described above, the semiconductor chip 200 performs data saving and recovery processing when the power supply drops, etc., but preferably the code processed by the semiconductor chip 200 is optimized. The information processing system according to the fifth embodiment differs from that of the fourth embodiment in that the code executed by the semiconductor chip 200 is optimized.

[0346] Figure 33This is a block diagram illustrating a configuration example of an information processing system according to a fifth embodiment of the present technology. The information processing system includes an information processing device 500 and a semiconductor device 100.

[0347] The information processing device 500 converts the source code into target code that can be executed by the semiconductor chip 200.

[0348] The configuration of the semiconductor device 100 in the fifth embodiment is the same as that in the fourth embodiment. The semiconductor chip 200 within the semiconductor device 100 performs the aforementioned save and restore processes based on the target code from the information processing device 500.

[0349] Figure 34 This is a diagram illustrating an example of source code according to a fifth embodiment of the present technology.

[0350] Figure 35 This is a diagram illustrating an example of a code block according to a fifth embodiment of the present technology. The information processing device 500 uses, for example, the checkpoint insertion method described in Non-Patent Document 2 below to... Figure 34 The source code shown is divided into Figure 35 The multiple code blocks shown.

[0351] Non-Patent Document 2: “Catch Compiler Auxiliary Techniques for Checkpoint Setting” from the proceedings of the International Symposium on Fault-Tolerant Computing, 1990.

[0352] exist Figure 35 In the process, the information processing device 500 divides the modified code into a code block that includes all paths, starting from, for example, immediately after the call to the checkpoint function and continuing to the next call to the checkpoint function.

[0353] The information processing device 500 can define the obtained code block as a task, or it can define a continuous block of code consisting of multiple code blocks as a task. In this case, the information processing device 500 redefines the code block as a code block, retains only the last checkpoint function, and modifies the code so that variables to be saved to non-volatile memory by other checkpoint functions are saved by the last checkpoint function. In the aforementioned Non-Patent Document 2, since the code processing result changes when re-executed from a checkpoint after power failure during code execution, it is prohibited to redefine a block of code as a code block. The recovery processing scheme using the non-volatile multi-library configuration and power-down save / recovery processing unit disclosed in this patent ensures that the code processing result remains unchanged when re-executed from a power failure during the execution of the redefined code.

[0354] Figure 36This is a diagram illustrating a revised example of a code block according to a fifth embodiment of the present technology. In this diagram, the source code is divided into two code blocks, CB1 and CB2. The processing performed on these code blocks is described below.

[0355] First, the information processing device 500 obtains a set of variables WVar to be written into the non-volatile register file 410 by each checkpoint function. all The set is represented by the following formula.

[0356] WVar all ={A, B, C, D, R1, R2, R3, R4}...expression3

[0357] Then, the information processing device 500 identifies the variables to be written to the non-volatile register file 410 from among the variables on the left-hand side of the assignment statement in each code block. For example, in the case where a set of variables on the left-hand side of the assignment statement in code block CB1 is represented by LHSVar(CB1), and in the case where a set of variables on the left-hand side of the assignment statement in code block CB2 is represented by LHSVar(CB2), these are represented by the following expressions.

[0358] LHSVar (CB1)

[0359] ={a, b, c, A, B, C, D, R1, R2, R3, R4}...expression4

[0360] LHSVar (CB2)

[0361] ={b, c, B, D, R1, R2, R4}... Expression 5

[0362] After executing the operations of expressions 3 to 4, the information processing device 500 obtains the set WLHSVar (CB) for each code block. i ), which represents the code block CB i A set of LHSVar (CB) i The logical product of expression 3 and expression 4. Here, i is a number that identifies the code block. For example, based on expressions 3 through 5, WLHSVar(CB1) and WLHSVar(CB2) are calculated by the following expressions.

[0363] WLHSVar (CB1)

[0364] =LHSVar(CB1)∧WVar all

[0365] ={A, B, C, D, R1, R2, R3, R4}... Expression 6

[0366] WLHSVar (CB2)

[0367] =LHSVar(CB2)∧WVar all

[0368] ={B, C, D, R1, R2, R4}... Expression 7

[0369] In expressions 6 and 7, "∧" represents the logical product.

[0370] Here, we collect WLHSVar (CB) i The element of ) is defined as LHSvar(CB i After executing the operations of expressions 6 and 7, the information processing device 500 obtains the assignment statement set Stmt (LHS) for each code block. Var (CB) i (), its left side is the WLHSVar (CB) with the largest partial order relative to the program path formed by the code block. i This analysis can be performed using standard data dependency analysis, which is well-known as active-scope analysis or def-use analysis of variables in the compiler.

[0371] like Figure 37 As shown in (a), the assignment statement set Stmt(LHS) var (CB1) was obtained through analysis of code block CB1. Furthermore, as shown in Figure (b), the assignment statement set Stmt(LHS) var (CB2) was obtained through analysis of code block CB2.

[0372] Stmt (LHS) var The element of (CB1) is defined as stmt. The information processing device 500 only translates the write instructions obtained from Stmt into write instructions to both the volatile register file 450 and the non-volatile register file 410, wherein the same address space is allocated to the two files.

[0373] After being converted into a write instruction, the information processing device 500 identifies the variables referenced within each code block through the following process, wherein the variables are read from and verified from the non-volatile register file 410. First, the information processing device 500 obtains the variables referenced in code block CB. i It appears in Stmt (LHS) var (CB) i A set of variables following the assignment statement in WLHSVar(CB). Next, in the assignment statement contained in WLHSVar(CB i If there are references to variables in the information processing unit 500 that are not written, the information processing unit 500 simply replaces the read instruction with the read and verify instructions.

[0374] Figure 38 The dashed line encloses the portion in (a) indicating the variables to be read and verified within code block CB1, and the dashed line encloses the portion in (b) indicating the variables to be read and verified within code block CB2.

[0375] As shown in Figure (b), in code block CB2, "R2 = B" performs a write to R2, and "b = R2 + 1" performs a read from R2. However, since R2 is overwritten by the final "R2 = B", it is sufficient to store the overwritten value in the non-volatile register file 410, and no read and verification instructions are allocated before it. In this way, the number of read and verification operations is reduced. This type of analysis can also be performed using standard data dependency analysis, known as def-use analysis of variables in the compiler.

[0376] Furthermore, write instructions required for subsequent execution are translated into write instructions that perform writes to both the volatile register file 450 and the non-volatile register file 410, which are allocated the same address space. Read instructions not required for subsequent execution are replaced with read and verify instructions.

[0377] Function calls and returns

[0378] • Starting and returning from an interrupt handler

[0379] • Operations on the stack pointer, program counter, saved program counter, processor status word register, saved status word register, procedure register, base address register, and vector base address register.

[0380] After replacing the read and verify instructions, the information processing device 500 replaces the checkpoint function with a save instruction that executes a save from the volatile register file 450 to the non-volatile register library 415 indicated by the BN register. Here, in the save instruction, only the data stored in the registers whose tag bits have a logical value of "1" is saved to the runtime library.

[0381] Figure 39 This is a diagram illustrating examples of checkpoint functions to be replaced according to a fifth embodiment of the present technology. The dashed portion in (a) of the diagram indicates the checkpoint function to be replaced with a save instruction in code block CB1. The dashed portion in (b) of the diagram indicates the checkpoint function to be replaced with a save instruction in code block CB2.

[0382] As shown in the figure, since the writing and saving of the non-volatile register library are performed at the instruction level, the only increase in code is for saving. Therefore, even when combined with checkpointing, the increase in code size and number of execution cycles is minimized.

[0383] In addition, such as Figure 38 As shown, the information processing device 500 analyzes data dependencies for each code block and identifies variables to be saved in the save process based on these dependencies. Therefore, by combining the checkpoint insertion method, the number of writes to the non-volatile register file 410 and the number of read and verification instructions can be reduced.

[0384] In this way, according to the fifth embodiment of the present technology, the information processing device 500 identifies the variables to be saved by dividing the code into code blocks using a checkpointing method. Therefore, the number of writes to the non-volatile register file 410 and the number of read and verification instructions can be reduced.

[0385] <6. Application Examples for Moving Bodies>

[0386] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be used to implement devices mounted on any type of mobile body, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, or robots.

[0387] Figure 40 This is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to this disclosure can be applied.

[0388] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 40 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Additionally, a microcomputer 12051, an audio / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the integrated control unit 12050.

[0389] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 is used as a control device for drive force generating devices (such as internal combustion engines, drive motors, etc.) that generate drive force for the vehicle, drive force transmission mechanisms that transmit drive force to the wheels, steering mechanisms that adjust the vehicle's steering angle, braking devices that generate braking force for the vehicle, etc.

[0390] The body system control unit 12020 controls the operation of various types of devices installed on the vehicle body according to various types of programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power window devices, or various types of lights (such as headlights, reversing lights, brake lights, turn signals, fog lights, etc.). In this case, radio waves or signals from various types of switches sent from mobile devices that serve as alternative keys can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power window devices, lights, etc.

[0391] The exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform processing to detect objects (such as people, vehicles, obstacles, signs, text on the road, etc.) or to detect their distance.

[0392] The imaging section 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging section 12031 can output an electrical signal as an image, or it can output an electrical signal as information about the measured distance. Furthermore, the light received by the imaging section 12031 can be visible light or invisible light, such as infrared light.

[0393] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection section 12041 that detects the driver's state. The driver state detection section 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection section 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy.

[0394] The microcomputer 12051 can calculate target control values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, distance-based following, speed maintenance, collision warning, lane departure warning, etc.

[0395] In addition, the microcomputer 12051 can control the drive force generation device, steering mechanism, braking device, etc., based on information about the exterior or interior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040 to perform cooperative control for autonomous driving, which aims to enable the vehicle to drive automatically without relying on the driver's operation.

[0396] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beams to low beams, for example, based on the position of the preceding or oncoming vehicle detected by the exterior information detection unit 12030.

[0397] The sound / image output section 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the exterior of the vehicle. Figure 40 In the example, audio speaker 12061, display portion 12062, and dashboard 12063 are shown as output devices. Display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0398] Figure 41 This is a diagram depicting an example of the mounting location of the imaging section 12031.

[0399] exist Figure 41 In this, imaging portions 12101, 12102, 12103, 12104 and 12105 are included as imaging portion 12031.

[0400] Imaging units 12101, 12102, 12103, 12104, and 12105 are deployed, for example, on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, as well as on the upper part of the windshield inside the vehicle. Imaging unit 12101 on the front nose and imaging unit 12105 on the upper part of the windshield inside the vehicle primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 on the upper part of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0401] Incidentally, Figure 41 An example depicting the imaging range of imaging portions 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging portion 12101 located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging portions 12102 and 12103 located on the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging portion 12104 located on the rear bumper or rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by overlaying image data captured by imaging portions 12101 to 12104.

[0402] At least one of the imaging portions 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging portions 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0403] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time-varying nature of that distance (relative speed to the vehicle 12100) based on distance information obtained from the imaging portions 12101 to 12104, and thereby extract the nearest three-dimensional object that specifically exists on the driving path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in approximately the same direction as the vehicle 12100 as the preceding vehicle. Furthermore, the microcomputer 12051 can preset the following distance to be maintained in front of the preceding vehicle and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, cooperative control aimed at achieving autonomous driving can be executed, enabling the vehicle to drive automatically without relying on driver operation, etc.

[0404] For example, microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering via drive system control unit 12010. Microcomputer 12051 can thus assist driving to avoid collisions.

[0405] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. The microcomputer 12051 can, for example, identify a pedestrian by determining whether a pedestrian exists in the image captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the image captured by the imaging units 12101 to 12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the image captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 such that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 such that an icon representing a pedestrian, etc., is displayed at a desired location.

[0406] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. The technology according to this disclosure can be applied to the imaging portion 12031 in the aforementioned components. Specifically, Figure 1 The semiconductor chip 200 can be applied to the imaging section 12031. By applying the technology according to this disclosure to the imaging section 12031, the power consumption of the imaging section 12031 can be reduced.

[0407] It should be noted that the above embodiments are examples illustrating the present technology, and the matters in the embodiments correspond to the matters defining the invention in the claims. Similarly, the various matters defining the invention in the claims correspond to the various matters of the same name in the embodiments of the present technology. However, the present technology is not limited to the embodiments and can be embodied by applying various types of modifications to the embodiments without departing from the scope of the present technology.

[0408] Furthermore, the processes described in the above embodiments can be considered as a method comprising a series of processes, and can be considered as a program that allows a computer to execute a series of processes and a recording medium that stores the program. Examples of such recording media include compact discs (CDs), mini-CDs (MDs), digital multifunction discs (DVDs), memory cards, Blu-ray discs (registered trademark), etc.

[0409] It should be noted that the effects described in this article are merely examples and are not intended to be limiting; other effects can also be achieved.

[0410] It should be noted that, according to this technology, the following configurations are also possible.

[0411] (1) A semiconductor chip, comprising: Volatile memory units; A non-volatile storage unit, the non-volatile storage unit comprising a plurality of non-volatile libraries, any one of the plurality of non-volatile libraries being designated as a backup library; A library switching control unit is configured to designate any one of the plurality of non-volatile libraries, except for the library designated as a backup library, as the runtime library; A normal save / restore processing unit is configured to perform save processing when a save context is to be saved, wherein the save processing writes data read from the volatile storage unit to the runtime library; and is configured to perform restore processing when a restore context is to be restored and no context switch is performed, wherein the restore processing writes data read from the runtime library to the volatile storage unit and the backup library; and to perform restore processing when a restore context is to be restored and a context switch is performed, wherein the restore processing writes data read from the restore target library specified by the context switch to the volatile storage unit and the backup library; and The power-down save / restore processing unit is configured to perform save processing when the power supply voltage drops below a first threshold, and to perform restore processing after swapping the backup library and runtime library when the dropped power supply voltage rises above a second threshold.

[0412] (2) The semiconductor chip according to (1) further includes: The write processing unit is configured to write data to the address of the volatile register file 450 and the address of the runtime library corresponding to the library number BN, these addresses being identical to each other; and The read processing unit is configured to read data from the address of a volatile storage unit as first read data, and is configured to read data from the address of a runtime library as second read data. The normal save / restore processing unit and the power-down save / restore processing unit are configured to, during the save process, write the first read data to one of the addresses in the runtime library that does not match the corresponding second read data at that address.

[0413] (3) The semiconductor chip according to (2), wherein, The write processing unit is configured to use a first write pulse to write write data, and The normal save / recovery processing unit and the power-down save / recovery processing unit are each configured to write the first read data using a second write pulse having at least one of a pulse width or voltage greater than that of the first write pulse.

[0414] (4) The semiconductor chip according to (3), wherein, The volatile memory unit retains a tag bit for the initial value at each address. The write processing unit is configured to use a first write pulse to write the write data to the address and update the corresponding tag bit to a value different from the initial value. The read processing unit is configured to update its corresponding tag bit to its initial value when the first read data and the second read data match each other, and The normal save / restore processing unit and the power-down save / restore processing unit are each configured to use a second write pulse to write the first read data to addresses in all addresses whose corresponding tag bits are different from the initial value.

[0415] (5) The semiconductor chip according to any one of (1) to (4) further includes a register that holds the respective library numbers of the runtime library and the backup library, wherein the power-down save / restore processing unit is configured to exchange the backup library and the runtime library by updating the register.

[0416] (6) The semiconductor chip according to (5) further includes a virtual / real library number management table, which maintains virtual library numbers assigned to interrupt handling or tasks and real library numbers assigned to each of a plurality of non-volatile libraries, wherein the virtual library numbers and the real library numbers are associated with each other, wherein, The power-down save / recovery processing unit is configured to exchange backup libraries and runtime libraries by updating registers and the virtual / real library number management table.

[0417] (7) The semiconductor chip according to any one of (1) to (6), wherein, Each of the volatile and non-volatile memory units includes at least one of a general-purpose register, a stack pointer register, a program counter register, a save program counter register, a processor status word register, a save status register, a procedure register, a multiplication register, a base register, a vector base register, a read data buffer register, or a write data buffer register.

[0418] (8) The semiconductor chip according to any one of (1) to (7), wherein, Volatile memory units include Preserve volatile shared resources of shared data shared by multiple entities, and Retain volatile non-shared resources that do not correspond to shared data, and Multiple non-volatile libraries include A pair of non-volatile shared libraries that retain shared data, and Retain multiple non-volatile, non-shared libraries that do not correspond to shared data.

[0419] (9) A semiconductor device, comprising: The detection circuit is configured to detect when the power supply voltage drops below a first threshold and rises above a second threshold; and A semiconductor chip includes a volatile memory unit, a non-volatile memory unit comprising a plurality of non-volatile libraries, any one of the plurality of non-volatile libraries being designated as a backup library, a library switching control unit, a normal save / restore processing unit, and a power-down save / restore processing unit. The library switching control unit is configured to designate any one of the plurality of non-volatile libraries, except the library designated as a backup library, as the runtime library. The normal save / restore processing unit is configured to perform a save process when a context needs to be saved, that is, to write data read from the volatile memory unit into the runtime library, and is configured to... The system is configured to perform recovery processing when context needs to be restored and no context switch is performed, i.e., write data read from the runtime library to the volatile storage unit and the backup library; and to perform recovery processing when context needs to be restored and a context switch is performed, i.e., write data read from the recovery target library specified by the context switch to the volatile storage unit and the backup library. The power-down save / restore processing unit is configured to perform save processing when the power supply voltage drops below a first threshold, and to perform recovery processing after swapping the backup library and the runtime library when the dropped power supply voltage rises above a second threshold.

[0420] (10) An information processing system, comprising: Information processing device, configured to convert source code into object code; and A semiconductor chip includes a volatile memory unit, a non-volatile memory unit including multiple non-volatile libraries, any one of the multiple non-volatile libraries being designated as a backup library, a library switching control unit, a normal save / restore processing unit, and a power-down save / restore processing unit. The library switching control unit is configured to designate any one of the multiple non-volatile libraries, except the one designated as a backup library, as the runtime library. The normal save / restore processing unit is configured to perform save processing based on the target code when the context needs to be saved; that is, to write data read from the volatile memory unit into the runtime library. It is configured to perform recovery processing when the context needs to be restored and no context switch is performed, i.e., write data read from the runtime library to the volatile storage unit and the backup library, and to perform recovery processing when the context needs to be restored and a context switch is performed, i.e., write data read from the recovery target library specified by the context switch to the volatile storage unit and the backup library. The power drop save / restore processing unit is configured to perform save processing when the power supply voltage drops below a first threshold, and to perform recovery processing after swapping the backup library and the runtime library when the dropped power supply voltage rises above a second threshold.

[0421] (11) The information processing system according to (10), wherein, The information processing device merges code blocks obtained by dividing the source code into multiple parts using the checkpoint insertion method.

[0422] (12) The information processing system according to (11), wherein, The information processing unit analyzes the data dependencies of each code block and identifies the variables to be saved in the save process based on the dependencies.

[0423] (13) A method for controlling a semiconductor chip, the method comprising: The library switching control procedure designates any one of the multiple non-volatile libraries, except for the one designated as the backup library, as the runtime library. The normal save / restore process involves performing a save operation when the context needs to be saved (i.e., writing data read from the volatile storage unit to the runtime library), and performing a restore operation when the context needs to be restored but no context switch is performed (i.e., writing data read from the runtime library to the volatile storage unit and the backup library), and performing a restore operation when the context needs to be restored and a context switch is performed (i.e., writing data read from the restore target library specified by the context switch to the volatile storage unit and the backup library); and a power-down save / restore process involves performing a save operation when the power supply voltage drops below a first threshold, and performing a restore operation after swapping the backup library and the runtime library when the dropped power supply voltage rises above a second threshold.

[0424] List of reference numerals

[0425] 100 Semiconductor Equipment

[0426] 110 Power supply drop / rise detection circuit

[0427] 120 power control unit

[0428] 130 capacitor

[0429] 200 semiconductor chips

[0430] 211 Vertical Drive Circuit

[0431] 212 Timing Control Unit

[0432] 213 DAC

[0433] 214 pixel array unit

[0434] 215 signal processing units

[0435] 216 Horizontal Conveyor Control Unit

[0436] 220 Digital Signal Processing Unit

[0437] 221 External Setting Input / Output Interface

[0438] 222 External Initialization Non-volatile Register Set

[0439] 300 Power Outage Recovery Compatible CPU System

[0440] 310 Access Control Unit

[0441] 311 Write Processing Unit

[0442] 312 Read Processing Unit

[0443] 313 Library Switching Control Unit

[0444] 314 Normal Save / Restore Processing Unit

[0445] 315 Power Drop Save / Recovery Processing Unit

[0446] 331 Program ROM

[0447] 332 Data Save / Restore / Library Switching Sequencer

[0448] 333 command to obtain decoder

[0449] 334 address calculation circuit

[0450] 335 Arithmetic Circuits

[0451] 336 Volatile Memory Shared Resource Addressing Register

[0452] 337 Address Converter

[0453] 338 data bus

[0454] 339 address bus

[0455] 340 BN register

[0456] 351, 370, 420 Non-volatile Registers

[0457] 352, 362, 460 volatile registers

[0458] 353, 363 encoders

[0459] 360 Virtual / Physical Library Number Management Table

[0460] 361, 411, 451 address decoders

[0461] Gates 371, 372, 421 to 423, 461 to 464 (AND (Logic Product) Gates)

[0462] 373 Non-volatile Trigger

[0463] 374 Mutual Exclusion Logic and (XOR) Gates

[0464] 375 Negative Logic AND (OR NOT) Gates

[0465] 400 storage units

[0466] 410 Non-volatile Register File

[0467] 412 Library Number Decoder

[0468] 413 Non-volatile Register Set

[0469] 414, 453 Output Selectors

[0470] 415 Non-volatile Register Library

[0471] 424, 425, 468 selectors

[0472] 426 Non-volatile Multi-bit Flip-Flop

[0473] 430 non-volatile memory

[0474] 441 Non-volatile memory shared resources

[0475] 442 Non-volatile memory, non-shared resources

[0476] 443 Non-volatile Memory Shared Library

[0477] 444 Non-volatile memory non-shared library

[0478] 450 Volatile Register File

[0479] 452 Volatile Register Set

[0480] 454 comparator

[0481] Logic gates 465 and 466

[0482] 467 Logic AND / OR gates

[0483] 469 Volatile Multi-bit Trigger

[0484] 470 1-bit flip-flop

[0485] 480 volatile memory

[0486] 481 Volatile Memory Shared Resources

[0487] 482 volatile memory non-shared resources

[0488] 500 Information Processing Device

[0489] 12031 Imaging Section

Claims

1. A semiconductor chip, comprising: Volatile memory units; A non-volatile storage unit includes multiple non-volatile libraries, any one of which is designated as a backup library; The library switching control unit is configured to designate any one of the plurality of non-volatile libraries, except for the library designated as the backup library, as the runtime library; The normal save / restore processing unit is configured to perform a save process that writes data read from the volatile storage unit to the runtime library when the context needs to be saved, and is configured to perform a restore process that writes data read from the runtime library to the volatile storage unit and the backup library when the context needs to be restored and no context switch is performed, and to perform a restore process that writes data read from the restore target library specified by the context switch to the volatile storage unit and the backup library when the context needs to be restored and a context switch is performed; as well as The power drop save / restore processing unit is configured to perform the save process when the power supply voltage drops below a first threshold value, and to perform the restore process after swapping the backup library and the runtime library when the dropped power supply voltage rises above a second threshold value.

2. The semiconductor chip according to claim 1, further comprising: The write processing unit is configured to write write data to the volatile memory register file and the address of the runtime library, the addresses being identical to each other; as well as The read processing unit is configured to read data from the address of the volatile storage unit as first read data, and is configured to read data from the address of the runtime library as second read data, wherein... Both the normal save / restore processing unit and the power-down save / restore processing unit are configured to, during the save process, write the first read data to all addresses in the runtime library where the corresponding second read data does not match the address of the first read data, and The read processing unit is configured to perform the above processing for reads that are not accompanied by writes.

3. The semiconductor chip according to claim 2, wherein... The write processing unit is configured to use a first write pulse to write the write data, and Both the normal save / restore processing unit and the power-down save / restore processing unit are configured to write the first read data using a second write pulse having at least one of a pulse width or voltage greater than the first write pulse.

4. The semiconductor chip according to claim 3, wherein The volatile storage unit retains a tag bit with an initial value for each address. The write processing unit is configured to use the first write pulse to write the write data to the address, and update the corresponding tag bit to a value different from the initial value. The read processing unit is configured to update the corresponding tag bit to the initial value when the first read data and the second read data match each other, and Both the normal save / restore processing unit and the power-down save / restore processing unit are configured to use the second write pulse to write the first read data to the address in all addresses where the tag bit is different from the initial value.

5. The semiconductor chip according to claim 1, further comprising a register storing the respective library numbers of the runtime library and the backup library, wherein... The power-down save / restore processing unit is configured to swap the backup library and the runtime library by updating the registers.

6. The semiconductor chip of claim 5, further comprising a virtual / actual library number management table, wherein the virtual / actual library number management table retains virtual library numbers assigned to interrupt handling or tasks and actual library numbers assigned to each of the plurality of non-volatile libraries, wherein the virtual library numbers and the actual library numbers are associated with each other, wherein The power-down save / restore processing unit is configured to exchange the backup library and the runtime library by updating the registers and the virtual / real library number management table.

7. The semiconductor chip according to claim 1, wherein... Each of the volatile memory unit and the non-volatile memory unit includes at least one of a general-purpose register, a stack pointer register, a program counter register, a save program counter register, a processor status word register, a save status register, a process register, a multiplication register, a base register, a vector base register, a read data buffer register, or a write data buffer register.

8. The semiconductor chip according to claim 1, wherein The volatile storage unit includes: Preserve volatile shared resources of shared data shared by multiple entities, and Retain volatile non-shared resources that do not correspond to the shared data, and The plurality of nonvolatile libraries include: A pair of non-volatile shared libraries that retain the shared data, and Multiple non-volatile, non-shared libraries that do not correspond to the shared data are retained.

9. A semiconductor device, comprising: The detection circuit is configured to detect when the power supply voltage drops below a first threshold and when the power supply voltage rises above a second threshold. as well as A semiconductor chip includes a volatile memory unit, a non-volatile memory unit, a library switching control unit, a normal save / restore processing unit, and a power-down save / restore processing unit. The non-volatile memory unit includes multiple non-volatile libraries, any one of which is designated as a backup library. The library switching control unit is configured to designate any one of the multiple non-volatile libraries (excluding the backup library) as the runtime library. The normal save / restore processing unit is configured to perform a save process, writing data read from the volatile memory unit to the runtime library when a save context is required, and is configured to... The power-down save / restore unit is configured to perform a save process when the power supply voltage drops below a first threshold value, and to perform a restore process after swapping the backup library when the power supply voltage rises above a second threshold value. This process involves writing data read from the runtime library to the volatile storage unit and the backup library if the context needs to be restored without performing a context switch, and performing a restore process when the context needs to be restored with a context switch.

10. An information processing system, comprising: An information processing device is configured to convert source code into object code; as well as A semiconductor chip includes a volatile memory unit, a non-volatile memory unit, a library switching control unit, a normal save / restore processing unit, and a power-down save / restore processing unit. The non-volatile memory unit includes multiple non-volatile libraries, any one of which is designated as a backup library. The library switching control unit is configured to designate any one of the multiple non-volatile libraries (excluding the backup library) as the runtime library. The normal save / restore processing unit is configured to, when a save context is required, execute a save process based on the target code to write data read from the volatile memory unit to the runtime library. The power-down save / restore unit is configured to perform a recovery process that writes data read from the runtime library to the volatile storage unit and the backup library when the context needs to be restored and a context switch is not performed, and to perform a recovery process that writes data read from the recovery target library specified by the context switch to the volatile storage unit and the backup library when the context needs to be restored and a context switch is performed. The power-down save / restore unit is configured to perform the save process when the power supply voltage drops below a first threshold value, and to perform the restore process after swapping the backup library and the runtime library when the dropped power supply voltage rises above a second threshold value.

11. The information processing system according to claim 10, wherein The information processing device merges code blocks obtained by dividing the source code into multiple parts using a checkpoint insertion method.

12. The information processing system according to claim 11, wherein... The information processing device analyzes the data dependencies for each of the code blocks and identifies the variables to be saved in the saving process based on the dependencies.

13. A method for controlling a semiconductor chip, the method comprising: The library switching control step involves designating any one of the multiple non-volatile libraries, excluding the one designated as the backup library, as the runtime library. The normal save / restore process involves performing a save operation that reads data from the volatile storage unit and writes it to the runtime library when the context needs to be saved. And a recovery process that, in order to restore the context without performing a context switch, writes data read from the runtime library to the volatile storage unit and the backup library, and in order to restore the context and perform a context switch, writes data read from the recovery target library specified by the context switch to the volatile storage unit and the backup library; as well as The power supply drop save / restore process involves performing the save process when the power supply voltage drops below a first threshold value, and performing the restore process after swapping the backup library and the runtime library when the dropped power supply voltage rises above a second threshold value.

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