Read data capture for high-speed double data rate interface

Abstract

A memory interface circuit includes a first receiver coupled to a differential data strobe signal and a second receiver having a first input coupled to a reference voltage source and a second input coupled to one of a pair of complementary signals. A discrimination circuit is configured to detect a preamble transmission in the differential data strobe signal based on timing provided by an output of the first receiver when the memory interface circuit is in a first operating state, detect the preamble transmission in the differential data strobe signal based on timing provided by an output of the second receiver when the memory interface circuit is in a second operating state, and assert a preamble detect signal when the preamble transmission is detected. A gate circuit is configured to provide a receive clock signal when the preamble detect signal is asserted.

Description

Cross-reference to related applications

[0001] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 593,122, filed March 1, 2025, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] This disclosure relates in general to data capture in memory interface circuitry, and more specifically to techniques for propagating dynamic random access memory data gating within memory interface circuitry. Background Technology

[0003] Electronic device technology has experienced explosive growth in recent years. For example, better communication, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding range of features and services, providing users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablets, laptops, etc.) have become more powerful and complex than ever before. Wireless devices may include high-speed bus interfaces for signal communication between hardware components.

[0004] IC devices may include a memory interface having physical layer circuitry configured to read from and write to a double-data-rate random access memory device. The increasing demand for higher data rates necessitates strict timing between the circuits within this memory interface. Therefore, there is a continuous need for new technologies that provide reliable operation when high-frequency clock signals are used to control high-speed data links. Summary of the Invention

[0005] Some aspects of this disclosure relate to systems, apparatuses, methods, and techniques for implementing and calibrating memory interface circuits that can be used with clock signals that can have frequencies varying over a wide range.

[0006] In various aspects of this disclosure, a memory interface circuit includes: a first receiver coupled to a differential data strobe signal received from a memory device and comprising a pair of complementary signals; a second receiver having a first input coupled to a reference voltage source and a second input coupled to one of the complementary signals in the pair; a discrimination circuit configured to: detect preamble transmission in the differential data strobe signal based on timing provided by the output of the first receiver when the memory interface circuit is in a first operating state; detect preamble transmission in the differential data strobe signal based on timing provided by the output of the second receiver when the memory interface circuit is in a second operating state; and assert a preamble detection signal when preamble transmission is detected; and a gating circuit configured to: provide a receive clock signal representing the differential data strobe signal when the preamble detection signal is asserted.

[0007] In various aspects of this disclosure, a method for communicating with a memory device includes: detecting a preamble transmission in a differential data strobe signal based on timing provided by an output of a first receiver when configured for a first operating state, the first receiver being coupled to the differential data strobe signal, the differential data strobe signal being received from the memory device and comprising a pair of complementary signals; detecting a preamble transmission in the differential data strobe signal based on timing provided by an output of a second receiver when configured for the first operating state, the second receiver having a first input coupled to a reference voltage source and a second input coupled to one of the complementary signals in the pair of complementary signals; asserting a preamble detection signal when a preamble transmission is detected; and providing a receive clock signal representing the differential data strobe signal when the preamble detection signal is asserted.

[0008] In various aspects of this disclosure, an apparatus includes: means for receiving a data strobe signal from a memory device; means for detecting preamble transmission in a differential data strobe signal, the means for detecting preamble transmission being adaptable to an operating mode of the apparatus; and means for suppressing a receive clock signal representing the differential data strobe signal when the preamble detection signal is asserted.

[0009] In some aspects, the memory interface circuitry has a data acquisition circuitry triggered by a received clock signal. The data acquisition circuitry can be configured to capture data bits from the output of a third receiver using one or more edges of the received clock signal. The memory interface circuitry may have a deserializer configured to receive a serial stream of data bits from the data acquisition circuitry. The memory interface circuitry may have a first clock divider circuitry coupled to the received clock signal and configured to provide an output clock signal that controls the parallel data output of the deserializer. The output clock signal can be suppressed when a preamble is received in the differential data strobe signal.

[0010] In some aspects, the memory interface circuitry has a control logic block configured to: monitor the operating state of the memory interface circuitry; select between the output of a first receiver and the output of a second receiver based on the operating state of the memory interface circuitry when a preamble is received in the differential data strobe signal; and cause a gating circuit to provide a receive clock signal when the preamble detection signal is asserted. The control logic block can also be configured to: select between a first clock signal representing the differential data strobe signal and a second clock signal, which is a frequency-divided version of the first clock signal, to control the timing of one or more sub-circuits of the control logic block.

[0011] In some aspects, the memory interface circuitry includes: a first flip-flop configured to change the signaling state of its output when triggered by an edge clock in the output of a first receiver; a second flip-flop configured to change the signaling state of its output when triggered by an edge clock in the output of a second receiver; a multiplexer having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop; and a third flip-flop configured to provide a preamble detection signal by capturing the output of the multiplexer. Signals indicating the operating state of the memory interface circuitry can be used to select between the first input and the second input of the multiplexer to provide the output of the multiplexer. Attached Figure Description

[0012] Figure 1 Example components and interconnects in a system-on-a-chip (SoC) that may be adapted to implement certain aspects of this disclosure are illustrated.

[0013] Figure 2 This illustrates various aspects of the physical layer circuitry used to read data from a memory device via a data communication link.

[0014] Figure 3 Some aspects of a memory interface that can be adapted according to certain aspects of this disclosure are illustrated.

[0015] Figure 4 This is an example Figure 3 Timing diagrams illustrating certain aspects of the timing relationships in the illustrated memory interface.

[0016] Figure 5 An example of a memory interface that can be configured according to certain aspects of this disclosure is shown.

[0017] Figure 6 This is a flowchart illustrating an example of a method for communicating with a memory device according to certain aspects of the disclosure. Detailed Implementation

[0018] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only the configurations in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0019] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0020] The terms “computing device” and “mobile device” are used interchangeably herein to refer to any or all of the following: servers, personal computers, smartphones, cellular phones, tablet computers, laptop computers, netbooks, ultrabooks, handheld computers, personal data assistants (PDAs), wireless email receivers, cellular phones with multimedia internet support, global positioning system (GPS) receivers, wireless game controllers, and similar personal electronic devices that include programmable processors. While these aspects are particularly useful in mobile devices (e.g., smartphones, laptops, etc.) with limited resources (e.g., processing power, battery, size, etc.), they are generally useful in any computing device that can benefit from improved processor performance and reduced power consumption.

[0021] The term "multi-core processor" is used herein to refer to a single integrated circuit (IC) chip or chip package containing two or more independent processing units or cores (e.g., CPU cores) configured to read and execute program instructions. The term "multiprocessor" is used herein to refer to a system or device comprising two or more processing units configured to read and execute program instructions.

[0022] The term "System-on-a-Chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip containing multiple resources and / or processors integrated on a single substrate. A single SoC may contain circuitry for digital, analog, mixed-signal, and radio frequency functions. A single SoC may also include any number of general-purpose and / or special-purpose processors (digital signal processors (DSPs), modem processors, video processors, etc.), blocks of memory (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.), and resources (e.g., timers, regulators, oscillators, etc.), any one or all of which may be included in one or more cores.

[0023] The memory technologies described or referenced herein are suitable for storing instructions, programs, control signals, and / or data for use in or by a computer or other digital electronic device. Any references to terms and / or technical details relating to individual memory types, interfaces, standards, or memory technologies are for illustrative purposes only and are not intended to limit the scope of the claims to a particular memory system or technology, unless specifically stated in the language of the claims. The complexity of mobile computing device architectures has increased and now typically includes multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnects (e.g., buses and / or structures), and many other resources for executing complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0024] Certain aspects of this disclosure apply to input / output (I / O) circuitry that provides an interface between core circuitry and memory devices. Many mobile devices employ synchronous dynamic random access memory (SDRAM), including low-power double data rate SDRAM, which may be referred to as low-power DDR SDRAM (LPDDR SDRAM), or in some instances as LPDDRx, where x describes the technology generation of the LPDDR SDRAM. Later-generation LPDDR SDRAMs designed to operate at higher operating frequencies may employ lower voltage levels in the core of the SoC or memory device to mitigate the power increase associated with higher operating frequencies.

[0025] The process technologies used to manufacture semiconductor devices, including integrated circuit (IC) devices, are constantly being improved. Process technologies encompass the manufacturing methods used to fabricate IC devices and define transistor dimensions, operating voltages, and switching speeds. Features that are components of the circuitry within an IC device can be referred to as technology nodes and / or process nodes. The terms "technology node," "process node," and "process technology" are used to characterize a specific semiconductor manufacturing process and its corresponding design rules. By using smaller feature sizes to produce smaller transistors that enable the fabrication of higher-density ICs, faster and more efficient technology nodes are continuously being developed.

[0026] Certain aspects of this disclosure apply to circuits for generating, transmitting, receiving, processing, and / or propagating differential signals. A conductor pair includes two wires, a connector, an interconnect, or other conductors through which differential signals are transmitted. The differential signal is carried in two phase versions on the conductor pair, whereby the wires, connectors, interconnects, or other conductors in the conductor pair carry versions of the differential signal that are 180° out of phase with each other. The versions of the differential signal transmitted through the conductor pair may be referred to as complementary signals, complementary signal pairs, or complementary pairs. Differential signals are transmitted using voltages of equal magnitude and opposite polarity through the wires, connectors, interconnects, or other conductors.

[0027] Figure 1 Example components and interconnects in a System-on-Chip (SoC) 100 suitable for implementing certain aspects of this disclosure are illustrated. The SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. The processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.), allowing the processors to operate at much higher frequencies / clock rates than would be possible with off-chip signal propagation. The proximity of the cores also allows for the sharing of on-chip memory and resources (e.g., voltage rails), and allows for more coordinated cooperation between the cores.

[0028] SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion, and / or wireless data transmission, as well as for performing other specialized operations such as decoding high-definition video, video processing, etc. System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting processors and software clients running on computing devices. System components and resources 110 may also include circuitry for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0029] SoC 100 may also include a Universal Serial Bus (USB) or other serial bus controller 112, one or more memory controllers 114, and a Centralized Resource Manager (CRM) 116. SoC 100 may also include input / output modules (not shown) for communicating with resources outside the SoC, each of which may be shared by two or more internal SoC components.

[0030] Processors 102, 104, 106, and 108 can be interconnected via interconnect / bus module 122 to USB controller 112, memory controller 114, system components and resources 110, CRM 116, and / or other system components. This interconnect / bus module may include reconfigurable gate arrays and / or implement a bus architecture. Communication may also be provided by advanced interconnects such as high-performance on-chip networks (NoC).

[0031] Interconnect / bus module 122 may include or provide a bus master system configured to grant exclusive control of the bus to SoC components (e.g., processors, peripherals, etc.) (e.g., data transfer in burst mode, block transfer mode, etc.) to achieve settings such as duration, number of operations, number of bytes, etc. In some cases, interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously. Memory controller 114 may be a dedicated hardware module configured to manage the flow of data to and from memory 124 via memory interface / bus 126.

[0032] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuitry, and other suitable hardware configured to perform various functionalities described throughout this disclosure. In some aspects, the memory 124 may be part of a SoC 100.

[0033] Figure 2 This illustrates certain aspects of the physical layer (PHY) circuitry that enables SoC 200 to read data from memory device 240 via data communication link 250. Figure 2 The example shown illustrates data channel 254, data select channel 252, and chip select channel 256. Channels 252, 254, and 256 may include wires, metal traces, pads, pins, and other interconnects or elements of interconnects. Data channel 254 provides a signal path between a data pin (DQ) in transceiver 204 in SoC 200 and a corresponding data pin (DQ) in transceiver 244 in memory device 240. Data select channel 252 provides a signal path to the data select transceiver 202 in SoC 200 for components (RDQS_t and RDQS_c) of differential receive data strobe signals 218 received from data select transceiver 242 in memory device 240. Edges or transitions in the data strobe signals 218 received through data select channel 254 provide timing information that can be used to capture data bits from data signals transmitted through data channel 252.

[0034] The inputs of differential gating receiver 212 are configured to receive differential gating signals transmitted via data gating channel 252. The output of differential gating receiver 212 is a single-ended gating signal 220, representing the data gating signal, and is provided to the read capture window circuitry (RCW 210). In one example, RCW 210 is configured to provide a pass signal 222 by aligning an edge (transition) in the single-ended gating signal 220 with a transition in the received data signal 226 output by a pseudo-differential receiver 214, which receives the data signal from data channel 254 at one input and a reference voltage level (Vref 232) at a second input. As used herein, the term pseudo-differential receiver may refer to a differential receiver whose one of its pair of inputs is coupled to a reference voltage source. In the illustrated example, a calibration delay circuit (CDC 208) receives the pass signal 222 and can be configured to generate a read clock signal 224, where an edge occurs after a transition between bits in the received data signal 226. The illustrated example also includes a duty cycle correction circuit (DCC 216) that can be configured to maximize the time available for sampling each bit in the received data signal 226. In this example, the output 228 of DCC 216 can be sampled by a data capture circuit 206 timing via a read clock signal 224 to provide a data output 230. The data capture circuit 206 may include latches, flip-flops, shift registers, combinational logic, and other circuitry.

[0035] Chip select channel 256 provides one or more signal paths for single-ended or differential chip select (CS) signals used to select a region of a memory device or memory device, module, or subsystem for reading data, writing data, or receiving commands. CS signal transmitter 234 in SoC 200 generates CS signals to be transmitted via chip select channel 256 to CS receiver 246 in memory device 240. The depicted channels 252, 254, and 256 exemplify channels that provide signal paths, for example, for multi-bit address signals, multi-bit command and control signals (including control signals for distinguishing read and write operations), indicate that a command will be received by the memory device, and define timing signals for capturing address and command bits.

[0036] Multiple signaling schemes can be defined for interface circuitry supporting certain types of memory devices. For example, interface circuitry supporting LPDDR SDRAM devices can use multiple voltage rails to save power and reduce heat generation during battery-powered mobile operation. Voltage rails are used to distribute power within the IC device, and can be configured to provide power at industry-standard voltage levels defined by process technology and configurable to conform to one or more operating modes. Some voltage rails can be configured to provide power at one voltage level in sleep mode and can be reconfigured to provide power at another level in active mode. The amplitudes of control signals, data signals, and / or address signals can conform to the voltage levels defined for power supply in each operating mode. In one example, LPDDR5 SDRAM and LPDDR6 SDRAM drive the CS signal at different signal levels in different operating modes to wake up the SDRAM in a power-down state, thereby saving power consumption when used for battery operation or power-constrained applications such as mobile communications, mobile computing, low-power sensor systems, automotive, and artificial intelligence systems.

[0037] Figure 3 Examples of certain aspects of a memory interface 300 that can be adapted according to certain aspects of this disclosure are illustrated. The memory interface 300 includes a memory PHY circuitry 302 (e.g., an LPDDR PHY) and a memory device 350 (e.g., an LPDDR SDRAM). The memory PHY circuitry 302 includes data read circuitry that provides or supports data read paths and their associated data read gating paths. Figure 3 The circuitry providing the data write path is omitted. The illustrated memory PHY circuit 302 includes a read capture window logic block (RCW 310) and a data read block 340. RCW 310 can be used during high-speed read data capture. RCW 310 can be gated with internal clock signals that can be configured to propagate valid read clock transitions or toggles to the data read path.

[0038] In the illustrated example, RCW 310 receives a read data strobe signal 330 from RDQS differential receiver 306. RDQS differential receiver 306 is configured to receive differential strobe signals from memory device 350. The differential strobe signals include a complementary signal pair comprising RDQS_t signal 352a and RDQS_c signal 352b. RCW 310 can be configured to provide pulses in the receive clock signal 334, which can be used by data read block 340 to sample and capture data from data signal 338 provided to data read block 340 by the first pseudo-differential receiver (DQ RX 304).

[0039] In the illustrated example, the logic circuit configured as AND gate 312 is used to control the timing of the edges in the receive clock signal 334 by gating the read data strobe signal 330 with a timing control signal 332. The timing control signal 332 is generated using control logic block 322 and discrimination circuit 314, which respond to the edges in the read data strobe signal 330 and the RDQS_c signal 352b. In some specific implementations, AND gate 312 is turned on in response to the falling edge of the RDQS_c signal 352b.

[0040] The second pseudo-differential receiver (Qual RX pseudo-differential receiver 308) provides a qualifier signal 316 by comparing the voltage state of the RDQS_c signal 352b with a reference voltage level (Vref 318). The qualifier signal 316 may also be referred to as the authentication signal or the authentication signal. The term "authentication edge" can be used to indicate aspects of signal propagation through gating, degating, or otherwise modifying the timing of edges in the clock signal used for data acquisition.

[0041] In the illustrated example, an edge in the discriminator signal 316 clock-triggers a high-voltage state through the first flip-flop 324, and a corresponding edge in the read data strobe signal 330 clocks the second flip-flop 326, thereby propagating the high-voltage state to the control logic block 322. The control logic block 322 includes timing and / or combinational logic that can alter the timing or duration of the high-voltage state at the output of the second flip-flop 326. In some examples, the control logic block 322 can terminate the pulse by resetting the first flip-flop 324 and / or the second flip-flop 326 after detecting a later edge in the read data strobe signal 330. In some examples, the control logic block 322 can terminate the pulse at a point in time after detecting an initial edge in the RDQS_c signal 352b, where the termination point can be controlled by configuring a delay circuit.

[0042] For each pulse in the RDQS_c signal 352b, the start of the pulse in the receive clock signal 334 can be delayed by the timing control signal 332. The pulse in the receive clock signal 334 can also be terminated by the timing control signal 332 before the corresponding pulse in the receive clock signal 334 is terminated. The timing control signal 332 can be used to ensure that the receive clock signal 334 is configured such that the data read block 340 can reliably capture data sent by the memory device 350.

[0043] In the illustrated example, memory device 350 transmits data in a single-ended data signal 354 (DQ). A pseudo-differential receiver (DQ RX 304) provides the received data signal (Rx_Data signal 338) by comparing the voltage state of the single-ended data signal 354 with Vref 318. In the illustrated example, the Rx_Data signal 338 is provided to a data capture circuit 342 in the data read block 340. The data capture circuit 342 may include flip-flops, registers, etc., and may be clocked by the receive clock signal 334. The output of the data capture circuit 342 is provided to a deserializer 344, which is configured to assemble multiple received bits into parallel data units. In one example, the deserializer 344 is configured to output the data signal (DQ RX 304) in a single-ended data signal (DQ RX 304). Out An 8-bit byte is provided in signal 320. In another example, deserializer 344 is configured to provide 8 bits in D. Out A 16-bit word is provided in signal 320. In another example, deserializer 344 is configured to... Out Signal 320 provides a 32-bit word. In other examples, deserializer 344 is configured to operate in units with dimensions defined by the specification, protocol, or application in D... Out The captured data is provided in signal 320. For example, through the output data signal (D Out The data output by signal 320 may include additional parity or error checking and / or correction bits.

[0044] In the illustrated example, the deserializer 344 receives the captured bits based on timing information provided by the receive clock signal 334. The deserializer 344 can receive the captured bits according to the output clock signal (Clk). Out The signal (360°) is used to output parallel data. (Clk) Out Signal 360 can be generated using a frequency divider 346 or a counter configured to divide the received clock signal 334 by the number of bits in the parallel data unit output by the deserializer 344.

[0045] The timing relationship between the discriminator signal 316 and the read data strobe signal 330 determines the maximum operating frequency achievable by the PHY circuit 302. For example, the setup and hold timing of flip-flops 324 and 326 can be a key factor in achieving the desired operating frequency.

[0046] RCW 310 can be used to filter short-pulse signaling interference that may occur when the memory device 350 is idle and the RDQS_t signals 352a and RDQS_c signals 352b are not driven, are floating, or are terminated to a common voltage level. RCW 310 can also be used to filter certain control signaling received before a data burst transmitted by the memory device 350. Control signaling may include a preamble that toggles the RDQS_t signals 352a and RDQS_c signals 352b in a manner that will produce an unwanted edge in the receive clock signal 334. The first flip-flop 324 is driven by a Qual RX pseudo-differential receiver 308, which compares the signaling state of the RDQS_c signal 352b with a fixed reference voltage level (Vref 318) to distinguish short-pulse interference from valid transitions in the RDQS_c signal 352b. Control logic block 322 uses an AND gate 312 to enable or disable the receive clock signal 334. In some implementations, control logic block 322 enables AND gate 312 after a preamble has been received. The preamble may include a preamble pulse of a pre-configured number. In one example, control logic block 322 enables AND gate 312 after two valid pulses received in the preamble have propagated the high signaling state through flip-flops 324 and 326. In another example, control logic block 322 enables AND gate 312 after four valid pulses received in the preamble. In yet another example, when the number of pulses programmed for the preamble is zero, control logic block 322 enables AND gate 312 without receiving any preamble pulses.

[0047] Figure 4 This is an example Figure 3Timing diagram 400 illustrates certain aspects of the timing relationships in the illustrated PHY circuit 302. Initially, the PHY circuit 302 is in an idle or disabled operating state 402. In some embodiments, the RDQS_t signals 352a and RDQS_c signals 352b are terminated, while in other embodiments, the RDQS_t signals 352a and RDQS_c signals 352b may be in a high-impedance state. In the high-impedance state, the drivers coupled to the RDQS_t signals 352a and RDQS_c signals 352b can be disabled or turned off, and thus present high impedance to the wires, connectors, interconnects, or other conductors carrying the RDQS_t signals 352a and RDQS_c signals 352b. When the PHY circuit 302 is in the initial idle or disabled operating state 402, or after entering the idle or disabled operating state 408 after receiving a data burst, the read data strobe signal 330 may be subject to short-duration pulse interference 410, 430.

[0048] At time 412, PHY circuit 302 exits idle or disabled operation state 402 and enters read preamble operation state 404, in which PHY circuit 302 is ready to receive data. PHY circuit 302 may exit idle or disabled operation state 402 when memory device 350 initiates read activity by driving the interconnect carrying RDQS_t signal 352a and RDQS_c signal 352b to a known or predefined state. Preparation may include configuring, initializing, and / or calibrating certain circuits in PHY circuit 302. In the illustrated example, a preamble sequence is received, wherein RDQS_t signal 352a and RDQS_c signal 352b are static for two transmit clock cycles and then toggle for two transmit clock cycles. Read preamble operation state 404 is followed by read burst operation state 406, in which data is received by PHY circuit 302. When the timing control signal 332 is in a high signaling state and the AND gate 312 enables the receive clock signal 334 to follow the read data strobe signal 330, the PHY circuit 302 can receive data.

[0049] When the output of the second flip-flop 326 has transitioned to a high signaling state, the control logic block 322 generates a timing control signal 332. In one example, when the read data strobe signal 330 is in a low signaling state, the control logic block 322 can drive the timing control signal 332 to a high signaling state. The output of the first flip-flop 324 drives the input of the second flip-flop 326 to a high signaling state in response to a falling edge 414 in the discriminator signal 316. The high signaling state is propagated through the second flip-flop 326 in response to a rising edge 418 in the read data strobe signal 330.

[0050] In a conventional system, the RCW 310 operates at the frequency of the read data strobe signal 330 during read preamble operation state 404 and read burst operation state 406. During this period, the frequency of the read data strobe signal 330 is determined by the frequencies of the RDQS_t signal 352a and the RDQS_c signal 352b. The gating control timing defined for the RCW 310 requires a maximum half-cycle setup duration and a zero-cycle hold duration. Therefore, the output of the first flip-flop 324 needs to be stable after its transition at the next falling edge 416 of the read data strobe signal 330, and the output of the second flip-flop 326 needs to be stable after its transition at the first rising edge 418 of the read data strobe signal 330 in the receive clock signal 334.

[0051] The timing relationship between the discriminator signal 316 and the read data strobe signal 330 can create a bottleneck limiting the operating frequency of the memory interface 300. Timing discrepancies may arise due to differences in the construction and / or operation of the RDQS differential receiver 306 and the Qual RX pseudo-differential receiver 308. While the RDQS differential receiver 306 operates as a true differential receiver and responds to differential signals, the Qual RX pseudo-differential receiver 308 effectively operates as a single-ended receiver and can be affected by offset voltage or voltage drift in the RDQS_c signal 352b. The Qual RX pseudo-differential receiver 308 may also be affected by variations or drift in Vref 318. These and other differences can introduce timing skew between the discriminator signal 316 and the read data strobe signal 330. Timing skew typically has an increasing effect with increasing data transfer rates and may prevent reliable operation of the PHY circuitry 302 at higher frequencies.

[0052] As an example, the RCW 310 can be used in a memory subsystem that includes LPDDR5 SDRAM devices and may need to operate at a switching frequency of 5.4 GHz. When the memory subsystem includes LPDDR6 SDRAM devices, the RCW 310 may need to operate in a switching frequency range between 6.4 GHz and 7.2 GHz.

[0053] Certain aspects of this disclosure relate to read capture window circuitry in a memory interface that reliably propagates an SDRAM read data strobe signal regardless of the switching frequency. According to one aspect, the read capture window circuitry can use a single-ended receiver or a pseudo-differential receiver to generate a discriminator signal in unknown, idle, or disabled operating states. When operating in a known operating state, the read capture window circuitry can use a differential receiver to generate a discriminator signal from a differential read data strobe signal. Using a differential receiver mitigates the effects of inter-symbol interference (ISI) on the read data strobe signal. ISI can cause signal noise, distortion, or corruption due to interference in the current bit of the received data signal, which can be attributed to previously received bits in the received data signal.

[0054] According to one aspect, the read capture window circuitry can use a frequency-divided clock signal to control the timing of the internal read capture window logic. Using a frequency-divided clock signal ensures that timing requirements, such as setup and hold requirements, are met at a frequency of at least 7.2 GHz.

[0055] Figure 5 A memory interface 500 configurable according to certain aspects of this disclosure is illustrated. The memory interface 500 includes a memory PHY circuitry 502 (e.g., an LPDDR PHY) and a memory device 550 (e.g., LPDDR SDRAM). The memory PHY circuitry 502 includes data read circuitry that provides or supports a data read path and its associated read data gating path. The illustrated memory PHY circuitry 502 includes a read capture window logic block (RCW 510) and a data read block 540. The RCW 510 can be used for associated high-speed read data capture. The RCW 510 can be gated with internal clock signals that can be configured to propagate a valid read clock transition or toggle to the data read path.

[0056] In the illustrated example, RCW 510 receives a read data strobe signal 530 from RDQS differential receiver 506. RDQS differential receiver 506 is configured to receive differential strobe signals from memory device 550. The differential strobe signals comprise a complementary signal pair, which includes RDQS_t signal 552a and RDQS_c signal 552b. RCW 510 can be configured to provide pulses in a receive clock signal 534, which can be used by data read block 540 to sample and capture data from a data signal 538 provided to data read block 540. In the illustrated example, a first pseudo-differential receiver (DQ RX 504) is used to generate data signal 538.

[0057] In the illustrated RCW 510, a logic circuit configured as an AND gate 512 is used to control the timing of the edge in the receive clock signal 534 by gating the read data strobe signal 530 with a timing control signal 532. The timing control signal 532 is generated using control logic block 522 and is responsive to the discrimination circuit 514 and one or more clock signals, including the read data strobe signal 530.

[0058] The output 516 of the second pseudo-differential receiver (Qual RX pseudo-differential receiver 508) is provided to the clock input of the first flip-flop 524, which outputs the first discriminator signal 556. The input of the first flip-flop 524 is pulled high, and a rising edge in the output 516 of the Qual RX pseudo-differential receiver 508 propagates the high signaling state to the first discriminator signal 556. A rising edge in the output 516 of the Qual RX pseudo-differential receiver 508 is expected when the signaling state transition of the RDQS_c signal 552b crosses a reference voltage level (Vref 518). Vref 518 can be selected to ensure that noise or short-duration pulse interference in the RDQS_c signal 552b is filtered out and does not cause the first flip-flop 524 to be clocked.

[0059] The second discriminator signal 558 is generated by the second flip-flop 526, which is triggered by the falling edge of the read data strobe signal 530. It is expected that the second discriminator signal 558 is less affected by common-mode noise and is unaffected by changes or drift in the reference voltage. Common-mode noise can be generated by electromagnetic or electrostatic interference between two signals that equally affect the differential signal, and is therefore removed by subtraction at the differential receiver. The input of the second flip-flop 526 is pulled to a high signaling state, and the falling edge of the read data strobe signal 530 propagates the high signaling state to the second discriminator signal 558.

[0060] Multiplexer 562 is used to select between a first discriminator signal 556 and a second discriminator signal 558 to provide an input to a third flip-flop 528. Multiplexer 562 is controlled by control logic block 522. In the illustrated example, control logic block 522 provides a mode signal 564 for selecting between the first discriminator signal 556 and the second discriminator signal 558.

[0061] In some implementations, when the memory interface 500 operates in an unknown, idle, or disabled state, control logic block 522 selects the first discriminator signal 556. For example, when the memory interface 500 is idle and the RDQS_t signals 552a and RDQS_c signals 552b are not driven, are floating, or are terminated at a common voltage level, control logic block 522 selects the first discriminator signal 556, making it expected that the read data strobe signal 530 is noisy or subject to short-duration pulse interference. Using a reference voltage level (Vref 518) prevents invalid activation of RCW 510.

[0062] In some implementations, when the memory interface 500 is operating in an active state, including when the memory PHY circuit 502 is receiving a preamble sequence or a data burst, control logic block 522 selects the second discriminator signal 558. In some implementations, control logic block 522 may select the second discriminator signal 558 when the memory interface 500 has entered an idle state between rapid, continuous data transmissions. In these later implementations, the second discriminator signal 558 may continue to be selected while the RDQS_t signal 552a and RDQS_c signal 552b continue to be differentially driven. In some instances, the second discriminator signal 558 may continue to be selected for a pre-configured short duration during which the RDQS_t signal 552a and RDQS_c signal 552b are expected to maintain a complementary relationship.

[0063] Control logic block 522 may include one or more controllers or processors configured to perform various functionalities throughout the present disclosure. Examples of processors or controllers include microprocessors, microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), finite state machines, gated logic, discrete hardware circuitry, and other suitable hardware configured to perform various functionalities throughout the present disclosure. In one example, control logic block 522 may monitor and / or control the operational state of memory interface 500. Control logic block 522 may respond to the output of RCW 510 by recording changes in the operational state of memory interface 500.

[0064] The third flip-flop 528 is triggered by the falling edge of the read data strobe signal 530. The falling edge of the read data strobe signal 530 propagates the input of the third flip-flop 528 to its output. The output of the third flip-flop 528 is a preamble detection signal 572 monitored by the control logic block 522. A high signaling state in the third preamble detection signal 572 indicates that a preamble sequence has been detected. The preamble detection signal 572 may enter a high signaling state after a single valid pulse is detected in the differential strobe signals sent as complementary signals to the RDQS_t signals 552a and RDQS_c signals 552b. Response to a single valid pulse can be beneficial in certain high-speed implementations, including applications involving LPDDR5 or LPDDR6 SDRAM devices. In one example, the duty cycle of the differential strobe signal sent by the memory device 550 may be suboptimal, and the initial pulse may not be detected due to timing that does not meet specified constraints. In another example, the preamble can be configured to include more than two pulses in the differential strobe signal sent by the memory device 550.

[0065] According to certain aspects of this disclosure, control logic block 522 may be configured to prevent excessive preamble pulses from impairing data acquisition and deserialization. In the illustrated example, memory device 550 transmits data in a single-ended data signal 554 (DQ). A pseudo-differential receiver (DQ RX 504) provides the received data signal (Rx_Data signal 538) by comparing the voltage state of the single-ended data signal 554 with Vref 518. In the illustrated example, Rx_Data signal 538 is provided to data acquisition circuitry 542 in data read block 540. Data acquisition circuitry 542 may include flip-flops, registers, etc., and may be clocked by receive clock signal 534. The output of data acquisition circuitry 542 is provided to deserializer 544, which is configured to assemble multiple received bits into parallel data units. Deserializer 544 may be implemented using shift registers and / or sequentially coupled latches, flip-flops, combinational logic, and other circuitry. The deserializer 544 can be configured to receive a serial stream of data bits from the data capture circuit 542.

[0066] In one example, the deserializer 544 is configured to output the data signal (D... Out An 8-bit byte is provided in signal 520. In another example, deserializer 544 is configured to provide 8 bits in D. Out Signal 520 provides a 16-bit word. In another example, deserializer 544 is configured to... Out Signal 520 provides a 32-bit word. In other examples, deserializer 544 is configured to operate in units with dimensions defined by the specification, protocol, or application in D... OutThe captured data is provided in signal 520. For example, through the output data signal (D Out The data output by signal 520 may include additional parity or error checking and / or correction bits.

[0067] In the illustrated example, the deserializer 544 receives the captured bits based on timing information provided by the receive clock signal 534. The deserializer 544 can receive the captured bits according to the output clock signal (Clk). Out Signal 560) is used to output parallel data. In one example, Clk Out Signal 560 controls the output of deserializer 544 to parallel data. (Clk) Out Signal 560 can be generated using a frequency divider 546 or a counter configured to divide the received clock signal 534 by the number of bits in the parallel data unit output by the deserializer 544. Control logic block 522 suppresses Clk when transmitting the preamble pulse. Out Signal 560 is used to prevent excessive preamble pulses from impairing data acquisition and deserialization. Control logic block 522 can be configured with information used to determine the number of pulses in the preamble and / or the pulse pattern and interval. Control logic block 522 can also control the gating signal (Clk). Enb Signal 536 is provided to the gating logic 548 coupled to the output of frequency divider 546. Control logic block 522 can control Clk. Enb Signal 536 is configured to suppress Clk in gating logic 548. Out Signal 560 continues until the preamble is complete. The preamble bits captured by data capture circuit 542 can be discarded by overflow deserializer 544.

[0068] According to certain aspects of this disclosure, at least a portion of control logic block 522 may be configured to operate at half the frequency of the received clock signal 534. In the illustrated example, frequency divider 566 or counter may be configured to provide a logic clock signal 570 having a frequency lower than the received clock signal 534. In one example, frequency divider 566 generates a logic clock signal 570 with a frequency half that of the received clock signal 534. Using logic clock signal 570 enables certain timing circuitry in control logic block 522 to meet timing requirements, such as setup and hold requirements. Control logic block 522 operates at the full clock rate of the received clock signal 534 when a preamble is detected, and when the Clk from deserializer 544 is blocked... Out When signal 560 is used to filter the preamble pulse, it can switch to a lower frequency logic clock signal 570. In some implementations, control logic block 522 operates on the full clock when filtering the preamble pulse.

[0069] In the illustrated example, control logic block 522 asserts the timing control signal 532 so that AND gate 512 can propagate the received clock signal 534. Control logic block 522 can assert Clk. Enb Signal 536, to suppress Clk Out Signal 560. After discarding the preamble pulse, control logic block 522 can cancel the assertion Clk. Enb Signal 536, to provide Clk Out Signal 560 and enable deserializer 544 output. In one example, Clk Enb Signal 536 is a multi-bit signal that can independently control gate logic 548 and gate logic 568. Clk Enb Signal 536 can be used to enable control logic block 522 to receive logic clock signal 570. In other examples, control logic block 522 may include internal selection logic that selects between receive clock signal 534 and logic clock signal 570 to control the timing of certain sub-circuits in control logic block 522.

[0070] Figure 6 This is a flowchart illustrating an example of a method 600 for communicating with a memory device according to certain aspects of this disclosure. In one example, method 600 may use... Figure 5 The illustrated memory interface 500 is used for implementation.

[0071] At block 602, preamble transmission can be detected in the differential data strobe signal based on timing provided by the output of a first receiver when configured for a first operating state. The first receiver is coupled to the differential data strobe signal. The differential data strobe signal may be received from a memory device and includes a pair of complementary signals. At block 604, preamble transmission can be detected in the differential data strobe signal based on timing provided by the output of a second receiver when configured for a first operating state. The second receiver may have a first input coupled to a reference voltage source and a second input coupled to one of the complementary signals in the pair. At block 606, a preamble detection signal can be asserted when preamble transmission is detected. At block 608, a receive clock signal representing the differential data strobe signal can be provided when the preamble detection signal is asserted.

[0072] In some instances, one or more edges of the receive clock signal can be used to capture data bits from the output of a third receiver. The serial stream of data bits output by the data capture circuit can be deserialized, and parallel deserialized data can be output. The output of the parallel deserialized data can be controlled using an output clock signal, which is a partitioned version of the receive clock signal. The output clock signal can be suppressed when a preamble is received in the differential data strobe signal.

[0073] In some implementations, the operational status of the memory interface circuit can be monitored. When a preamble is received in the differential data strobe signal, selection can be made between the output of the first receiver and the output of the second receiver based on the operational status of the memory interface circuit. When asserting the preamble detection signal, the gating circuit can provide a receive clock signal.

[0074] In some instances, a first clock signal representing a differential data strobe signal may be selected to control the timing of one or more sub-circuits of the memory interface circuitry. In some instances, a second clock signal may be selected to control the timing of one or more sub-circuits of the memory interface circuitry. The second clock signal may be a frequency-divided version of the first clock signal. The memory interface circuitry may include: a first flip-flop configured to change the signaling state of its output when triggered by an edge clock in the output of a first receiver; a second flip-flop configured to change the signaling state of its output when triggered by an edge clock in the output of a second receiver; a multiplexer having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop; and a third flip-flop configured to provide a preamble detection signal by capturing the output of the multiplexer. Signals representing the operating state of the memory interface circuitry may be provided to select between the first input and the second input of the multiplexer to provide the output of the multiplexer.

[0075] The apparatuses and methods described herein and illustrated in the accompanying drawings can be implemented using various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0076] According to certain aspects of this disclosure, an apparatus configured to operate as a memory interface circuit includes: circuitry or a module configured to receive a data strobe signal from a memory device; circuitry or a module configured to detect preamble transmission in a differential data strobe signal; and circuitry or a module configured to suppress a receive clock signal representing the differential data strobe signal when the preamble detection signal is asserted. The components for detecting preamble transmission can be adapted to different operating modes of the apparatus.

[0077] In some specific embodiments, the apparatus further includes: circuitry or modules configured to capture data bits from a data signal received from a self-memory device; circuitry or modules configured to deserialize a serial stream of the captured data bits; and circuitry or modules configured to suppress the output of parallel deserialized data. The circuitry or modules configured to suppress the output of parallel deserialized data may also be configured to suppress the output clock signal when a preamble is received in a differential data strobe signal.

[0078] In some specific implementations, the circuit or module configured to detect preamble transmission in the differential data strobe signal may also be configured to select between the differential signal representing the data strobe signal and the single-ended signal representing the data strobe signal based on the operating state of the device. The circuit or module configured to detect preamble transmission in the differential data strobe signal may also be configured to generate a preamble detection signal when preamble transmission is detected in the selected signal representing the data strobe signal.

[0079] In some embodiments, the device includes circuitry or modules configured to select between a first clock signal representing a differential data strobe signal and a second clock signal, which is a frequency-divided version of the first clock signal, to control the timing of one or more sub-circuits of the device. After a preamble transmission is detected in the differential data strobe signal, the second clock signal can control the timing of one or more sub-circuits of the device.

[0080] According to at least one example described herein, a memory interface circuit includes a first receiver, a second receiver, an authentication circuit, and a gating circuit. The first receiver is coupled to a differential data strobe signal received from a memory device. The differential data strobe signal may include a pair of complementary signals. The second receiver may have a first input coupled to a reference voltage source and a second input coupled to one of the complementary signals in the pair. The authentication circuit is configured to: detect preamble transmission in the differential data strobe signal based on timing provided by the output of the first receiver when the memory interface circuit is in a first operating state; detect preamble transmission in the differential data strobe signal based on timing provided by the output of the second receiver when the memory interface circuit is in a second operating state; and assert a preamble detection signal when preamble transmission is detected. The gating circuit is configured to: provide a receive clock signal representing the differential data strobe signal when the preamble detection signal is asserted.

[0081] In some implementations, the memory interface circuitry includes a data acquisition circuitry triggered by a received clock signal. The data acquisition circuitry can be configured to capture data bits from the output of a third receiver using one or more edges of the received clock signal. The memory interface circuitry may include a deserializer configured to receive a serial stream of data bits from the data acquisition circuitry. The memory interface circuitry may also include a first clock divider circuitry coupled to the received clock signal and configured to provide an output clock signal that controls the parallel data output of the deserializer. The output clock signal can be suppressed when a preamble is received in the differential data strobe signal.

[0082] In some implementations, the memory interface circuit has a control logic block configured to: monitor the operating state of the memory interface circuit; select between the output of a first receiver and the output of a second receiver based on the operating state of the memory interface circuit when a preamble is received in the differential data strobe signal; and cause a gating circuit to provide a receive clock signal when the preamble detection signal is asserted. The control logic block can also be configured to: select between a first clock signal representing the differential data strobe signal and a second clock signal, which is a frequency-divided version of the first clock signal, to control the timing of one or more sub-circuits of the control logic block.

[0083] In some specific implementations, the memory interface circuitry includes: a first flip-flop configured to change the signaling state of its output when triggered by an edge clock in the output of a first receiver; a second flip-flop configured to change the signaling state of its output when triggered by an edge clock in the output of a second receiver; a multiplexer having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop; and a third flip-flop configured to provide a preamble detection signal by capturing the output of the multiplexer. Signals indicating the operating state of the memory interface circuitry can be used to select between the first input and the second input of the multiplexer to provide the output of the multiplexer.

[0084] In some implementations, certain functions or portions thereof may be implemented using software residing in a computer-readable form on a memory device or other computer-readable medium. In some implementations, the computer-readable medium maintains instructions and information, wherein these instructions are configured to cause one or more processors or controllers to perform certain functions and processes.

[0085] In one example, a processor-readable storage medium stores or retains code for: detecting preamble transmission in a differential data strobe signal based on timing provided by the output of a first differential receiver when configured for a first operating state, the first differential receiver being coupled to the differential data strobe signal, the differential data strobe signal being received from a memory device and comprising a pair of complementary signals; detecting preamble transmission in the differential data strobe signal based on timing provided by the output of a second receiver when configured for the first operating state, the second differential receiver having a first input coupled to a reference voltage source and a second input coupled to one of the complementary signals in the pair of complementary signals; asserting a preamble detection signal when preamble transmission is detected; and providing a receive clock signal representing the differential data strobe signal when the preamble detection signal is asserted.

[0086] In some implementations, the processor-readable storage medium stores or retains code for: capturing data bits from the output of a third differential receiver using one or more edges of a receive clock signal; deserializing a serial stream of data bits output by a data capture circuit; and controlling the parallel deserialized data output using an output clock signal, which is a partitioned version of the receive clock signal. The processor-readable storage medium may also store or retain code for: suppressing the output clock signal upon receiving a preamble in a differential data strobe signal.

[0087] In some specific implementations, the processor can read the storage medium to store or retain code for the following operations: monitoring the operating state of the memory interface circuitry; selecting between the output of the first differential receiver and the output of the second differential receiver based on the operating state of the memory interface circuitry when a preamble is received in the differential data strobe signal; and causing the gating circuitry to provide a receive clock signal when the preamble detection signal is asserted.

[0088] In some implementations, the processor-readable storage medium stores or retains code for selecting between a first clock signal representing a differential data strobe signal and a second clock signal, which is a frequency-divided version of the first clock signal, to control the timing of one or more sub-circuits of a memory interface circuit. The one or more processors or controllers may be included in the memory interface circuit having: a first flip-flop configured to change the signaling state of an output when triggered by an edge clock in the output of a first differential receiver; a second flip-flop configured to change the signaling state of an output when triggered by an edge clock in the output of a second differential receiver; a multiplexer having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop; and a third flip-flop configured to provide a preamble detection signal by capturing the output of the multiplexer. The processor-readable storage medium may store or retain code for providing a signal representing the operating state of the memory interface circuit to select between a first input and a second input of the multiplexer to provide the output of the multiplexer.

[0089] Some specific implementation examples are described in the following numbered clauses:

[0090] 1. A memory interface circuit, the memory interface circuit comprising: a first receiver coupled to a differential data strobe signal received from a memory device and comprising a pair of complementary signals; a second receiver having a first input coupled to a reference voltage source and a second input coupled to one of the complementary signals in the pair of complementary signals; a discrimination circuit configured to: detect preamble transmission in the differential data strobe signal based on timing provided by an output of the first receiver when the memory interface circuit is in a first operating state; detect the preamble transmission in the differential data strobe signal based on timing provided by an output of the second receiver when the memory interface circuit is in a second operating state; and assert a preamble detection signal when the preamble transmission is detected; and a gating circuit configured to: provide a receive clock signal representing the differential data strobe signal when the preamble detection signal is asserted.

[0091] 2. The memory interface circuit according to Clause 1, further comprising: a data capture circuit, the data capture circuit being clocked by the receive clock signal and configured to capture data bits from the output of a third receiver using one or more edges of the receive clock signal; a deserializer, the deserializer being configured to receive a serial stream of data bits from the data capture circuit; and a first clock divider circuit, the first clock divider circuit being coupled to the receive clock signal and configured to provide an output clock signal controlling the parallel data output of the deserializer.

[0092] 3. The memory interface circuit according to Clause 1 or Clause 2, wherein the output clock signal is suppressed when the preamble is received in the differential data strobe signal.

[0093] 4. The memory interface circuit according to any one of claims 1 to 3, further comprising a control logic block configured to: monitor the operating state of the memory interface circuit; when the preamble is received in the differential data strobe signal, select between the output of the first receiver and the output of the second receiver based on the operating state of the memory interface circuit; and when the preamble detection signal is asserted, cause the gating circuit to provide the receive clock signal.

[0094] 5. The memory interface circuit according to Clause 4, wherein the control logic block is further configured to: select between a first clock signal representing the differential data strobe signal and a second clock signal being a frequency-divided version of the first clock signal to control the timing of one or more sub-circuits of the control logic block.

[0095] 6. The memory interface circuit according to any one of claims 1 to 5, further comprising: a first flip-flop configured to change a signaling state of the output of the first flip-flop when triggered by an edge clock in the output of the first receiver; a second flip-flop configured to change a signaling state of the output of the second flip-flop when triggered by an edge clock in the output of the second receiver; a multiplexer having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop; and a third flip-flop configured to provide the preamble detection signal by capturing the output of the multiplexer.

[0096] 7. The memory interface circuit according to Clause 6, wherein a signal indicating the operating state of the memory interface circuit is selected between the first input of the multiplexer and the second input of the multiplexer to provide the output of the multiplexer.

[0097] 8. An apparatus comprising: means for receiving a data strobe signal from a memory device; means for detecting a preamble transmission in the differential data strobe signal, the means for detecting the preamble transmission being adaptable to an operating mode of the apparatus; and means for suppressing a receive clock signal representing the differential data strobe signal when asserting the preamble detection signal.

[0098] 9. The apparatus according to Clause 8, further comprising: means for capturing data bits from a data signal received from the memory device; means for deserializing a serial stream of the captured data bits; and means for suppressing the output of parallel deserialized data.

[0099] 10. The apparatus according to Clause 8 or Clause 9, wherein the component for suppressing the output of parallel deserialized data is configured to suppress the output clock signal when the preamble is received in the differential data strobe signal.

[0100] 11. The apparatus according to any one of claims 8 to 10, wherein the component for detecting preamble transmission in the differential data strobe signal is configured to: select between a differential signal representing the data strobe signal and a single-ended signal representing the data strobe signal based on the operating state of the apparatus; and generate a preamble detection signal when the preamble transmission is detected in the selected signal representing the data strobe signal.

[0101] 12. The apparatus according to any one of clauses 8 to 11, the apparatus further comprising: a component for selecting between a first clock signal representing the differential data strobe signal and a second clock signal being a frequency-divided version of the first clock signal to control the timing of one or more sub-circuits of the apparatus.

[0102] 13. The apparatus according to Clause 12, wherein after the preamble transmission is detected in the differential data strobe signal, the second clock signal controls the timing of the one or more sub-circuits of the apparatus.

[0103] 14. A method for communicating with a memory device, the method comprising: detecting a preamble transmission in a differential data strobe signal based on timing provided by an output of a first receiver when configured for a first operating state, the first receiver being coupled to the differential data strobe signal, the differential data strobe signal being received from the memory device and comprising a pair of complementary signals; detecting a preamble transmission in the differential data strobe signal based on timing provided by an output of a second receiver when configured for the first operating state, the second receiver having a first input coupled to a reference voltage source and a second input coupled to one of the complementary signals in the pair of complementary signals; asserting a preamble detection signal when the preamble transmission is detected; and providing a receive clock signal representing the differential data strobe signal when the preamble detection signal is asserted.

[0104] 15. The method according to Clause 14, further comprising: capturing data bits from the output of a third receiver using one or more edges of the received clock signal; deserializing a serial stream of data bits output by the data capture circuit; and controlling parallel deserialized data output using an output clock signal, the output clock signal being a partitioned version of the received clock signal.

[0105] 16. The method according to Clause 14 or Clause 15, the method further comprising: suppressing the output clock signal when the preamble is received in the differential data strobe signal.

[0106] 17. The method according to any one of claims 14 to 16, the method further comprising: monitoring the operating state of the memory interface circuit; selecting between the output of the first receiver and the output of the second receiver based on the operating state of the memory interface circuit when the preamble is received in the differential data strobe signal; and causing the gating circuit to provide the receive clock signal when the preamble detection signal is asserted.

[0107] 18. The method according to any one of Clauses 14 to 17, further comprising: selecting between a first clock signal representing the differential data strobe signal and a second clock signal being a frequency-divided version of the first clock signal to control the timing of one or more sub-circuits of the memory interface circuitry.

[0108] 19. The method of claim 18, wherein the memory interface circuitry comprises: a first flip-flop configured to change a signaling state of the output of the first flip-flop when triggered by an edge clock in the output of the first receiver; a second flip-flop configured to change a signaling state of the output of the second flip-flop when triggered by an edge clock in the output of the second receiver; a multiplexer having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop; and a third flip-flop configured to provide the preamble detection signal by capturing the output of the multiplexer.

[0109] 20. The method according to Clause 19, further comprising: providing a signal indicating an operational state of the memory interface circuitry to select between a first input of the multiplexer and a second input of the multiplexer to provide the output of the multiplexer.

[0110] As used in this article, the phrase “at least one of” in a list of items refers to any combination of these items, including a single member. For example, “at least one of a, b, or c” is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0111] This disclosure is provided so that any person skilled in the art can make or use various aspects of it. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory interface circuit, the memory interface circuit comprising: A first receiver, coupled to a differential data gating signal, the differential data gating signal being received from a memory device and comprising a pair of complementary signals; The second receiver has a first input coupled to a reference voltage source and a second input coupled to one of the complementary signals in the pair of complementary signals; The identification circuit is configured to: When the memory interface circuit is in the first operating state, the preamble transmission is detected in the differential data strobe signal based on the timing provided by the output of the first receiver. When the memory interface circuit is in the second operating state, the preamble transmission is detected in the differential data strobe signal based on the timing provided by the output of the second receiver, and When the preamble transmission is detected, an assertion is made regarding the preamble detection signal; and A gating circuit configured to provide a receive clock signal representing the differential data strobe signal when the preamble detection signal is asserted.

2. The memory interface circuit according to claim 1, further comprising: A data capture circuit, which is clock-triggered by the receive clock signal and configured to use one or more edges of the receive clock signal to capture data bits from the output of a third receiver; A deserializer configured to receive a serial stream of data bits from the data capture circuit; and A first clock divider circuit is coupled to the received clock signal and configured to provide an output clock signal that controls the parallel data output of the deserializer.

3. The memory interface circuit according to claim 2, wherein the output clock signal is suppressed when the preamble is received in the differential data strobe signal.

4. The memory interface circuit according to claim 1, wherein the memory interface circuit further comprises a control logic block, the control logic block being configured to: Monitor the operating status of the memory interface circuit; When the preamble is received in the differential data strobe signal, a selection is made between the output of the first receiver and the output of the second receiver based on the operating state of the memory interface circuit; and When the preamble detection signal is asserted, the gating circuit provides the receive clock signal.

5. The memory interface circuit according to claim 4, wherein the control logic block is further configured to: A selection is made between a first clock signal representing the differential data strobe signal and a second clock signal, which is a frequency-divided version of the first clock signal, to control the timing of one or more sub-circuits of the control logic block.

6. The memory interface circuit according to claim 1, further comprising: A first flip-flop is configured to change the signaling state of its output when triggered by an edge clock in the output of the first receiver. A second flip-flop, configured to change the signaling state of the output of the second flip-flop when triggered by an edge clock in the output of the second receiver; A multiplexer having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop; and A third trigger is configured to provide the preamble detection signal by capturing the output of the multiplexer.

7. The memory interface circuit of claim 6, wherein a signal indicating the operating state of the memory interface circuit is selected between the first input of the multiplexer and the second input of the multiplexer to provide the output of the multiplexer.

8. An apparatus comprising: A component used to receive data strobe signals from a memory device; A component for detecting preamble transmission in differential data gating signals, wherein the component for detecting the preamble transmission is adaptable to the operating mode of the device; and A component used to suppress the receive clock signal representing the differential data strobe signal when the assertion preamble detection signal is received.

9. The apparatus according to claim 8, further comprising: Components for capturing data bits from data signals received from the memory device; A component used to deserialize the serial stream of captured data bits; and A component used to suppress the output of parallel deserialized data.

10. The apparatus of claim 9, wherein the component for suppressing the output of parallel deserialized data is configured to: When the preamble is received in the differential data strobe signal, the output clock signal is suppressed.

11. The apparatus of claim 8, wherein the component for detecting preamble transmission in the differential data strobe signal is configured to: The selection is made between a differential signal representing the data gating signal and a single-ended signal representing the data gating signal based on the operating state of the device; and When the preamble transmission is detected in the selected signal representing the data strobe signal, the preamble detection signal is generated.

12. The apparatus according to claim 8, further comprising: A component for selecting between a first clock signal representing the differential data strobe signal and a second clock signal, which is a frequency-divided version of the first clock signal, to control the timing of one or more sub-circuits of the device.

13. The apparatus of claim 12, wherein after the preamble transmission is detected in the differential data strobe signal, the second clock signal controls the timing of the one or more sub-circuits of the apparatus.

14. A method for communicating with a memory device, the method comprising: The preamble transmission is detected in the differential data strobe signal based on timing provided by the output of the first receiver when configured for a first operating state. The first receiver is coupled to the differential data strobe signal, which is received from a memory device and includes a pair of complementary signals. Preamble transmission is detected in the differential data gating signal based on timing provided by the output of the second receiver when configured for the first operating state. The second receiver has a first input coupled to a reference voltage source and a second input coupled to one of the complementary signals in the pair of complementary signals. When the preamble transmission is detected, an assertion is made regarding the preamble detection signal; as well as When asserting the preamble detection signal, a receive clock signal representing the differential data strobe signal is provided.

15. The method according to claim 14, further comprising: Data bits are captured from the output of the third receiver using one or more edges of the received clock signal; The serial stream of data bits output by the data capture circuit is deserialized; as well as An output clock signal is used to control the parallel deserialization data output, wherein the output clock signal is a partitioned version of the received clock signal.

16. The method according to claim 15, further comprising: When the preamble is received in the differential data strobe signal, the output clock signal is suppressed.

17. The method of claim 14, further comprising: Monitor the operational status of the memory interface circuit; When the preamble is received in the differential data strobe signal, a selection is made between the output of the first receiver and the output of the second receiver based on the operating state of the memory interface circuit; as well as When the preamble detection signal is asserted, the gating circuit provides the receive clock signal.

18. The method according to claim 14, further comprising: Choosing between a first clock signal representing the differential data strobe signal and a second clock signal, which is a frequency-divided version of the first clock signal, to control the timing of one or more sub-circuits of the memory interface circuit.

19. The method of claim 18, wherein the memory interface circuit comprises: A first flip-flop is configured to change the signaling state of its output when triggered by an edge clock in the output of the first receiver. A second flip-flop, configured to change the signaling state of the output of the second flip-flop when triggered by an edge clock in the output of the second receiver; A multiplexer having a first input coupled to the output of the first flip-flop and a second input coupled to the output of the second flip-flop; and A third trigger is configured to provide the preamble detection signal by capturing the output of the multiplexer.

20. The method according to claim 19, further comprising: A signal indicating the operating state of the memory interface circuitry is provided to select between the first input of the multiplexer and the second input of the multiplexer to provide the output of the multiplexer.

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