Method and apparatus for training an spi controller for high frequency operation

Abstract

A method for training a serial peripheral interface (SPI) controller is provided. The method can include receiving a first set of data at a first clock frequency based on a plurality of delayed clock signals corresponding to a plurality of tap values, obtaining a second set of data at a second clock frequency based on the plurality of delayed clock signals corresponding to the plurality of tap values, determining a plurality of pass / fail states for the respective plurality of tap values by comparing the second set of data obtained at the second clock frequency to the first set of data received at the first clock frequency, setting the plurality of pass / fail states based on the comparison, and selecting a selected tap value from the plurality of tap values corresponding to one of the plurality of delayed clock signals based on the plurality of pass / fail states.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. nonprovisional patent application No. 19 / 169,556, filed April 3, 2025, and Indian provisional patent application No. 202441027512, filed April 3, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates in its entirety to a serial peripheral interface (SPI), and more specifically to methods and apparatus for training a serial peripheral interface controller for high-frequency operation. Background Technology

[0003] Serial Peripheral Interface (SPI) flash memory has become a widely used technology in embedded systems due to its simplicity, low power consumption, and suitability for short-range communication. However, with increasing demands for faster server boot times and higher data transfer rates, some SPI controllers have encountered limitations when operating at higher frequencies. During SPI communication, data from the SPI flash memory (RX data) is driven on the falling edge of the clock signal (SCK) and captured by the controller on the rising edge. At high frequencies, the time required for the data to stabilize before being captured affects the ability to accurately capture the data. Some controllers may not be able to resolve this settling time issue, resulting in data capture errors. It is possible to delay the clock signal SCK by using multiple delay units of fixed duration to enable correct data reception. The output of each delay unit is called a tap (TAP) point, and the delayed clock signal output from one or more tap points can be used to sample incoming data. Currently, tap values ​​are selected and programmed into the controller during the verification phase. However, variations in manufacturing (process), power supply fluctuations (voltage), and operating temperature can significantly alter the propagation delay of the clock signal. Over time, pre-programmed tap values ​​may become insufficient to avoid data capture errors. Some controllers lack the ability to dynamically adjust tap values ​​based on real-time environmental conditions. Therefore, there is a need for a method and apparatus that addresses the limitations of some SPI controllers operating at higher frequencies and in challenging environments. Summary of the Invention

[0004] According to one or more example aspects, a method is provided for training a Serial Peripheral Interface (SPI) controller for high-frequency operation. The method may include: receiving a first dataset at a first clock frequency, obtaining a second dataset at a second clock frequency, and training the SPI controller for a predetermined number of iterations. The training operation may include: identifying a pass / fail status for each of a plurality of tap values. The identification operation may include: comparing the second dataset obtained at the second clock frequency with the first dataset received at the first clock frequency and setting a pass / fail status based on the comparison.

[0005] A first dataset can be received from the boot address of an external SPI flash memory. The method may include storing the first dataset in the non-volatile memory of the SPI controller. A second dataset may be obtained from the external SPI flash memory. The training operation may include calculating the average tap value of multiple tap values ​​for each iteration over a predetermined number of iterations. The calculation operation may include identifying the lowest and highest indexed tap values ​​that result in a pass state and calculating the average tap value of the lowest and highest indexed tap values. The training operation may include determining a selected tap value based on the highest occurrence count of the average tap values ​​within the multiple average tap values. The method may include storing the selected tap value in a tap control register. The method may include storing multiple pass / fail states for each of the multiple tap values ​​in static random access memory (SRAM). The method may include repeating the receive, acquire, and training operations for one or more other chip selects of the SPI controller.

[0006] According to one or more examples, a Serial Peripheral Interface (SPI) controller is provided, which may include a plurality of shift registers, comparators operatively coupled to the plurality of shift registers, and a training control circuitry. The training control circuitry may receive a first dataset at a first clock frequency, obtain a second dataset at a second clock frequency, and train the SPI controller for a predetermined number of iterations by identifying a pass / fail state for each of a plurality of tap values. The identification operation may include comparing the second dataset obtained at the second clock frequency with the first dataset received at the first clock frequency and setting a pass / fail state based on the comparison.

[0007] The training control circuitry can receive a first dataset from the boot address of an external SPI flash memory. This first dataset can be stored in the non-volatile memory of the SPI controller. The training control circuitry can obtain a second dataset from the external SPI flash memory. The training control circuitry can calculate an average tap value for multiple tap values ​​in each iteration of a predetermined number of iterations by identifying the lowest and highest indexed tap values ​​that result in a pass state and calculating the average tap value of the lowest and highest indexed tap values. The training control circuitry can determine a selected tap value based on the highest occurrence count of the average tap value among the multiple average tap values. The SPI controller may include a tap control register for storing the selected tap value determined by the training control circuitry. The SPI controller may include static random access memory (SRAM) for storing multiple pass / fail states for each of the multiple tap values. The training control circuitry can repeat receive, acquire, and training operations for one or more other chip selects of the SPI controller.

[0008] According to one or more example aspects, a computer-readable storage medium is provided that stores instructions which, when executed by a processor, cause the processor to perform a method for training a Serial Peripheral Interface (SPI) controller for high-frequency operation. Attached Figure Description

[0009] Figure 1 A block diagram illustrating a Serial Peripheral Interface (SPI) controller according to one or more examples is shown.

[0010] Figure 2 A flowchart illustrating a method for training a Serial Peripheral Interface (SPI) controller for high-frequency operation, based on one or more examples, is shown.

[0011] Figure 3A and Figure 3B A flowchart illustrating a block for training a Serial Peripheral Interface (SPI) controller, based on one or more examples, is shown.

[0012] Figure 4 A block diagram illustrating a tap selection system for a Serial Peripheral Interface (SPI) controller, based on one or more examples, is shown. Detailed Implementation

[0013] Reference will now be made to the various examples illustrated in the accompanying drawings, in which the same reference numerals always denote the same elements. These examples may be presented in various forms, and are not limited to those described herein.

[0014] Figure 1A block diagram illustrating a Serial Peripheral Interface (SPI) controller 100 according to one or more examples is shown. The SPI controller 100 may include an application processor 102, non-volatile memory 104, static random access memory (SRAM) 108, training control circuitry 106, delay line circuitry 110, tap control register 112, tap selection circuitry 114, multiple shift registers 116, and comparator 120. The multiple shift registers 116 may include multiple data flip-flops 118.

[0015] Application processor 102 can be used as the central processing unit of SPI controller 100 to coordinate various aspects of the training operation. Application processor 102 can access addresses and perform various operations within SPI controller 100 to control the training operation. Application processor 102 can initiate training of SPI controller 100 by triggering training control circuitry 106. Application processor 102 can access SPI flash addresses that correspond to specific locations within external SPI flash memory identified during training operations associated with chip select of SPI controller 100. Specifically, application processor 102 can interact with training control circuitry 106, read data from external SPI flash memory, and communicate with other components.

[0016] Non-volatile memory 104 may store SPI flash memory addresses, mode information, and firmware. In one or more examples, non-volatile memory 104 may be one-time programmable (OTP) memory and flash memory. Application processor 102 may access the SPI flash memory addresses stored in non-volatile memory 104 to initiate training operations for the corresponding chip select. Mode information may indicate the communication mode of the external SPI flash memory. In one or more examples, the communication mode may be a single-wire communication mode, a two-wire communication mode, and a four-wire communication mode.

[0017] Firmware may be a set of instructions stored in non-volatile memory 104. Firmware may act as middleware between hardware (e.g., application processor 102) and software (e.g., application program). Firmware may provide application processor 102 with specific instructions to perform various tasks related to the training of SPI controller 100. Application processor 102 may fetch and interpret firmware instructions from non-volatile memory 104 during the training of SPI controller 100. Firmware instructions may instruct application processor 102 to access and interpret SPI flash addresses. Firmware may instruct application processor 102 to access a specific SPI flash address stored in non-volatile memory 104 and identify that SPI flash address as a trigger for initiating training of SPI controller 100.

[0018] The firmware provides instructions to the application processor 102 to interact with other components of the SPI controller 100, such as the comparator 120, delay line circuitry 110, and training control circuitry system 106. These instructions may include sending signals, retrieving data, and performing calculations. The firmware may determine operations involved in the training process, such as adjusting the delay line circuitry 110, reading data from external SPI flash memory, storing pass / fail states, and identifying selected tap values. The application processor 102, equipped with its processing capabilities, executes the aforementioned instructions to ensure smooth and efficient training of the SPI controller 100.

[0019] The training control circuitry 106 controls the training operation, thereby managing the adjustment and data analysis of the delay line circuitry 110 of the SPI controller 100. The training control circuitry 106 can receive a first dataset at a first clock frequency. This first dataset can serve as a reference for comparisons during the training operation. The first dataset can be received from the boot address of an external SPI flash memory. The first dataset can be stored in the non-volatile memory 104 of the SPI controller 100. The training control circuitry 106 can obtain a second dataset from the external SPI flash memory at a second clock frequency. This second dataset can correspond to the actual data received at a higher frequency by the chip select of the SPI controller 100 during the training operation. The second clock frequency can be higher than the first clock frequency.

[0020] The training control circuitry 106 can run a predetermined number of iterations to train the SPI controller 100. The training control circuitry 106 can be operatively coupled to the delay line circuitry 110 to adjust the tap values ​​for each iteration. The training control circuitry 106 can be operatively coupled to a comparator 120 to compare a second dataset obtained at a second clock frequency with a first dataset received at a first clock frequency to identify the pass / fail status of each of the plurality of tap values. The training control circuitry 106 can set the pass / fail status of each of the plurality of tap values ​​based on the comparison between the second dataset and the first dataset.

[0021] The training control circuitry 106 can identify the lowest and highest indexed tap values ​​in which a pass state is generated by comparison. The training control circuitry 106 can calculate an average tap value between the lowest and highest indexed tap values, which can correspond to the average tap value of multiple tap values ​​in each iteration over a predetermined number of iterations. The training control circuitry 106 can determine a selected tap value for tuning the delay line circuitry 110 based on the highest occurrence count of the average tap value among the multiple average tap values. The selected tap value can correspond to the most frequently occurring average tap value across a predetermined number of iterations. The selected tap value can be stored in a tap control register 112.

[0022] The SPI controller 100 may include SRAM 108 for storing multiple pass / fail states derived from a comparison of a first dataset and a second dataset for each iteration in a predetermined number of iterations, thereby enabling iterative refinement of the clock delay setting of the delay line circuit 110. The training control circuitry system 106 may repeat receive, acquire, and training operations for one or more other chip selects of the SPI controller 100. The SPI controller 100 may include a reset tap register (not shown) operable to reset tap values.

[0023] Delay line circuit 110 may include multiple delay elements ( Figure 4 As shown in the diagram, each delay element has an input and an output. The delay line circuit 110 can control the serial peripheral interface clock signal via multiple delay elements. This allows the SPI controller 100 to explore multiple tap values ​​during training operations. The delay line circuit 110 is operatively coupled to a tap selection circuit 114. The tap selection circuit 114 can select a selected tap value stored in the tap control register 112, identified during training operations. The tap selection circuit 114 can receive the selected tap value having the highest count for data capture. The tap selection circuit 114 can use the selected tap value to control multiple delay elements of the delay line circuit 110.

[0024] Tap selection circuit 114 can effectively control the delay introduced by multiple delay elements of delay line circuit 110 based on a selected tap value. Tap selection circuit 114 can be operatively coupled to multiple shift registers 116. The multiple shift registers 116 may each include multiple data flip-flops 118. Data streams from external SPI flash memory can be fed into the multiple data flip-flops 118 of the corresponding multiple shift registers 116. The selected tap value can be communicated through tap selection circuit 114 to the multiple data flip-flops 118 to control the timing of data streams from external SPI flash memory being fed into the multiple shift registers 116.

[0025] Figure 2 A flowchart 200 illustrating a method for training a Serial Peripheral Interface (SPI) controller 100 for high-frequency operation, according to one or more examples, is shown. It should be noted that reference will be made to the method described in flowchart 200 in order to explain its meaning. Figure 1 The components explained in the text.

[0026] Flowchart 200 begins at operation 202. At operation 204, the method may include: receiving a first dataset at a first clock frequency. At operation 206, the method may include: obtaining a second dataset at a second clock frequency. At operation 208, the method may include: training the SPI controller 100 for a predetermined number of iterations by identifying the pass / fail state of each of a plurality of tap values.

[0027] Flowchart 200 terminates at operation 210. It should be noted that flowchart 200 is to be interpreted as having the process operations described above; however, those skilled in the art will understand that flowchart 200 may have more or fewer process operations that can implement all the above examples of this disclosure.

[0028] Figure 3A and Figure 3B Flowcharts for training an SPI controller 100 are illustrated in combination according to various examples. At operation 300, the application firmware configures the SPI controller 100 (which may be a four-wire mode serial peripheral interface controller) to operate at a clock frequency of approximately 12 MHz for chip select (e.g., CS0#). At operation 302, the application firmware initiates a read operation to receive a first dataset from the boot address of an external SPI flash memory using a 12 MHz clock frequency. An existing byte hash can be used to store the first dataset within non-volatile memory 104. At operation 304, a variable (e.g., a 32-bit variable named pass_status) can be created in static random access memory 108 to store pass / fail status.

[0029] At operation 306, the `pass_status` variable can be initialized, so all bits are set to a logical value of zero (bits `Pass_Status[31:0]=0x0`). At operation 308, the application firmware can configure the four-wire mode serial peripheral interface controller to operate at a clock frequency of approximately 96 MHz for chip select. At operation 310, the application firmware can use a clock frequency of approximately 96 MHz to initiate a read operation to obtain a second dataset from external SPI flash memory. At operation 312, a FOR loop can be executed for a predetermined number of iterations (e.g., for (j=0; j<16; j++)). In one or more examples, the predetermined number of iterations can be approximately 16. At operation 314, the method can iterate over multiple tap values ​​(which can be approximately 32) to identify the pass / fail status of each tap value (e.g., for (i=0; i<32; i++)). For example, at operation 316, it is determined whether the second dataset obtained using the current tap value at a clock frequency of approximately 96 MHz matches the first dataset received earlier at a clock frequency of approximately 12 MHz. If a match exists between the first and second datasets, the current tap value can be set to a logical value of 1 via a state variable.

[0030] At operation 318, it is determined whether the current tap value "i" is equal to the last tap value, which, depending on the example, could be 32. If it is determined in operation 318 that the current tap value is not equal to 32, the method returns to operation 314, where the current tap value is incremented. The method then proceeds to operation 316, where it is determined whether a second dataset obtained using the current tap value (which has been incremented since the previous tap value was used) at a clock frequency of approximately 96 MHz matches an earlier first dataset received at a clock frequency of approximately 12 MHz. If a match exists between the first and second datasets, the pass_status variable of the current tap value can be set to a logical value of 1. At step 318, it is again determined whether the current tap value "i" is equal to the last tap value. If the current tap value "i" is not equal to the last tap value, the method returns to operation 314, where the current tap value is incremented again, and operations 316 and 318 are repeated to determine the value of the pass_status variable for each tap value. When it is determined in operation 318 that the current tap value "i" matches the last tap value, the method proceeds to operation 320.

[0031] At operation 320, the pass_status variable for the current iteration "j" is copied to the pass_iteration variable (pass_iteration[j] = pass_status). In operation 322, it is determined whether the current iteration "j" is equal to a predetermined number of iterations, such as 16. If it is determined in operation 322 that the current iteration for the chip select is not equal to the predetermined number of iterations, the method proceeds to operation 312, where the current iteration number is incremented, and operations 314, 316, and 318 are repeated for each tap value "i" in the tap value "i", and the pass_status value for each tap value "i" is determined. When operations 314, 316, and 318 have been performed for each tap value "i" of the current iteration "j", in operation 320, the pass_status variable for the current iteration "j" is copied to the pass_iteration variable (pass_iteration[j] = pass_status). In operation 322, it is determined again whether the current iteration "j" is equal to the predetermined number of iterations, and if not, the method returns to operation 312, where the current iteration is incremented, and operations 314, 316, and 318 are repeated for each tap value. The method continues in this manner until it is determined in operation 322 that the current iteration "j" for the chip select is equal to the predetermined number of iterations, in which case the method may proceed to operation 324.

[0032] At operation 324, for each iteration "j", the lowest and highest indexed tap values ​​that cause the pass_iteration variable to be set to 1 can be identified. At operation 326, the average of the lowest and highest indexed tap values ​​can be calculated. At operation 328, the average tap value for each iteration "j" can be stored in an integer variable, which can be specified as "pass_tapvalue[j]". At operation 330, the most frequently occurring average tap value among multiple average tap values ​​can be identified. At operation 332, the identified most frequent average tap value can be selected for high-frequency operation. At operation 334, the selected tap value can be stored in the tap control register 112 of the SPI controller 100 for chip select. At operation 336, it is determined whether training for different chip selects (e.g., CS1#) has been completed. If training for different chip selects has been completed at operation 336, the training operation stops at operation 338. If it is determined in operation 336 that training for different chip selects has not been completed, the method returns to operation 300 and repeats the method for the next chip select. By training the SPI controller 100 according to the example described herein, tap values ​​can be adjusted to account for external factors such as board parasitics and environmental conditions. The ability to adjust tap values ​​based on such factors allows the SPI controller to operate more reliably at higher frequencies and to account for variations in process, voltage, and temperature.

[0033] Figure 4 A block diagram illustrating a tap selection system for a Serial Peripheral Interface (SPI) controller 100 according to one or more examples is shown. It should be noted that, for the purpose of explaining the tap selection system, reference will be made to... Figure 1 The components explained in the text. The tap selection system may include a delay line circuit 110, a tap selection circuit 114, and multiple data flip-flops 118.

[0034] Delay line circuit 110 may include multiple delay elements 410. Delay line circuit 110 can control a serial peripheral interface clock signal designated "SPI_CLK" via the multiple delay elements. The multiple delay elements 410 are operatively coupled to tap selection circuit 114. Tap selection circuit 114 can select a selected tap value stored in tap control register 112, identified during training operation. Tap selection circuit 114 can receive the selected tap value with the highest count via a tap selection signal from tap control register 112. Tap selection circuit 114 can use the selected tap value to control the multiple delay elements 410 of delay line circuit 110.

[0035] Tap selection circuit 114 can effectively control the delay introduced by the multiple delay elements 410 of delay line circuit 110 based on a selected tap value. Tap selection circuit 114 can be operatively coupled to multiple data flip-flops 118. A data stream designated as “SPI_IO[0]” from an external SPI flash memory can be fed to multiple data flip-flops 118 in each of multiple shift registers 116. Tap selection circuit 114 can use the selected tap value to output a delayed clock signal to the multiple data flip-flops 118 to control the timing of the SPI_IO[0] signal from the external SPI flash memory being fed into the multiple shift registers 116.

[0036] Various examples have been disclosed herein in conjunction with the foregoing description and accompanying drawings. It should be understood that describing and illustrating each combination and sub-combination of these examples literally would be an undue repetition. Therefore, all examples can be combined in any manner and / or combination, and this specification (including the accompanying drawings) should be construed as constituting a complete written description of all combinations and sub-combinations of these examples herein, as well as the ways and processes of preparing and using them, and should support the claims for any such combinations or sub-combinations.

[0037] Those skilled in the art will understand that the examples described herein are not limited to those specifically shown and described above. Furthermore, unless the contrary is mentioned above, it should be noted that all figures are not drawn to scale. Various modifications and variations are possible in accordance with the above teachings.

Claims

1. A method for training a Serial Peripheral Interface (SPI) controller, the method comprising: Multiple delayed clock signals are generated based on the received clock signal, wherein the multiple delayed clock signals correspond to multiple tap values, and the multiple tap values ​​indicate the amount of delay of the multiple delayed clock signals. A first dataset is received at a first clock frequency, wherein the first dataset includes data received based on a plurality of delayed clock signals corresponding to the plurality of tap values; A second dataset is obtained at a second clock frequency, wherein the second dataset includes data received based on the plurality of delayed clock signals corresponding to the plurality of tap values; as well as Training the SPT controller for a predetermined number of iterations, wherein the training operation includes: Multiple pass / fail states of the corresponding plurality of tap values ​​are determined by comparing the second dataset obtained at the second clock frequency with the first dataset received at the first clock frequency. Based on the comparison, the multiple pass / fail states are set; and Based on the plurality of pass / fail states, a selected tap value is selected from the plurality of tap values ​​corresponding to one of the plurality of delayed clock signals.

2. The method of claim 1, wherein the first dataset is received from the boot address of an external SPI flash memory.

3. The method according to claim 1, further comprising: The first dataset is stored in the non-volatile memory of the Serial Peripheral Interface (SPI) controller.

4. The method according to claim 1, wherein the second dataset is obtained from an external SPI flash memory.

5. The method according to claim 1, wherein the training operation includes: For each iteration in the predetermined number of iterations: The comparison results in a pass state, and the comparison results in a plurality of lowest indexed tap values ​​and a plurality of highest indexed tap values, wherein the plurality of lowest indexed tap values ​​and the plurality of highest indexed tap values ​​each correspond to the predetermined number of iterations; as well as Calculate multiple average tap values ​​corresponding to the plurality of lowest indexed tap values ​​and the plurality of highest indexed tap values ​​for the predetermined number of iterations.

6. The method according to claim 5, wherein the training operation includes: The selected tap value is determined based on the highest occurrence count of the average tap value among the plurality of average tap values.

7. The method according to claim 6, further comprising: The selected tap value is stored in the tap control register.

8. The method according to claim 1, further comprising: The multiple pass / fail states of the multiple tap values ​​are stored in static random access memory (SRAM).

9. The method according to claim 1, further comprising: For one or more other chip selects of the SPI controller, repeat the receive operation, the acquire operation, and the training operation.

10. A Serial Peripheral Interface (SPI) controller, the SPI controller comprising: Multiple shift registers; Comparators, which are operatively coupled to the plurality of shift registers; A delay line circuit is used to generate multiple delayed clock signals based on a received clock signal, wherein the multiple delayed signals correspond to multiple tap values, and the multiple tap values ​​indicate the amount of delay of the multiple delayed clock signals. and Training control circuit system, the training control circuit system being used for: A first dataset is received at a first clock frequency, wherein the first dataset includes data received based on a plurality of delayed clock signals corresponding to the plurality of tap values; A second dataset is obtained at a second clock frequency, wherein the second dataset includes data received based on the plurality of delayed clock signals corresponding to the plurality of tap values; as well as The SPI controller is trained for a predetermined number of iterations: Multiple pass / fail states of the corresponding plurality of tap values ​​are determined by comparing the second dataset obtained at the second clock frequency with the first dataset received at the first clock frequency. The multiple pass / fail states are set based on the comparison; as well as Based on the plurality of pass / fail states, a selected tap value is selected from the plurality of tap values ​​corresponding to one of the plurality of delayed clock signals.

11. The SPI controller of claim 10, wherein the training control circuitry is configured to receive the first dataset from the boot address of an external SPI flash memory.

12. The SPI controller of claim 10, wherein the first dataset is stored in the non-volatile memory of the SPI controller.

13. The SPI controller of claim 10, wherein the training control circuitry is configured to obtain the second dataset from an external SPI flash memory.

14. The SPI controller of claim 10, wherein for each iteration in the predetermined number of iterations, the training control circuitry is configured to: The comparison results in a plurality of lowest-indexed tap values ​​and a plurality of highest-indexed tap values ​​for a given state, wherein the plurality of lowest-indexed tap values ​​and the plurality of highest-indexed tap values ​​each correspond to the predetermined number of iterations; and Calculate multiple average tap values ​​corresponding to the plurality of lowest indexed tap values ​​and the plurality of highest indexed tap values ​​for the predetermined number of iterations.

15. The SPI controller of claim 14, wherein the training control circuitry is configured to determine the selected tap value based on the highest occurrence count of the average tap value among the plurality of average tap values.

16. The SPI controller of claim 15, wherein the SPI controller includes a tap control register for storing the selected tap value determined by the training control circuitry.

17. The SPI controller of claim 10, further comprising static random access memory (SRAM) for storing the plurality of pass / fail states of the plurality of tap values.

18. The SPI controller of claim 10, wherein the training control circuitry is configured to train the SPI controller for a predetermined number of iterations for a plurality of chip selects of the SPI controller.

19. A computer-readable storage medium storing instructions, which, when executed by a processor, cause the processor to perform a method comprising the following operations: Multiple delayed clock signals are generated based on the received clock signal, wherein the multiple delayed clock signals correspond to multiple tap values, and the multiple tap values ​​indicate the amount of delay of the multiple delayed clock signals. A first dataset is received at a first clock frequency, wherein the first dataset includes data received based on a plurality of delayed clock signals corresponding to the plurality of tap values; A second dataset is obtained at a second clock frequency, wherein the second dataset includes data received based on the plurality of delayed clock signals corresponding to the plurality of tap values; as well as Training the SPI controller for a predetermined number of iterations, wherein the training operation includes: Multiple pass / fail states of the corresponding plurality of tap values ​​are determined by comparing the second dataset obtained at the second clock frequency with the first dataset received at the first clock frequency. Based on the comparison, the multiple pass / fail states are set; and Based on the plurality of pass / fail states, a selected tap value is selected from the plurality of tap values ​​corresponding to one of the plurality of delayed clock signals.

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