Sense circuit for rram-based crossbar circuit

Abstract

This disclosure provides a readout circuit for a cross-switching circuit. The cross-switching circuit may include a plurality of bit lines crossing a plurality of word lines and a plurality of cross-point devices. Each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines. The cross-switching circuit may further include an output sensor that generates a digital output representing the sum of currents flowing through one or more bit lines of the cross-switching circuit. The output sensor includes a first transistor connected in series with a second transistor and an analog-to-digital converter configured to output the digital output. The readout circuit is an open-loop circuit. The readout circuit may be selectively connected to one of the plurality of bit lines to perform a readout operation.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 587,561, filed February 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure generally relate to electronic circuits, and more specifically, to readout circuits for cross-switching circuits that include resistive random access memory (RRAM or ReRAM) devices. Background Technology

[0003] A cross-switch circuit is a circuit structure having interconnected conductive lines that clamp storage elements, such as resistive switching materials, at their intersections. The resistive switching materials may include, for example, memristors (also known as resistive random access memory (RRAM or ReRAM)). Cross-switch circuits can be used to implement in-memory computing applications, non-volatile solid-state memories, image processing applications, neural networks, etc. Summary of the Invention

[0004] The following is a simplified overview of this disclosure, intended to provide a basic understanding of certain aspects of this disclosure. This overview is not a comprehensive summary of this disclosure, nor is it intended to identify key or essential elements of this disclosure, nor to define any scope of the specific embodiments or claims of this disclosure. Its sole purpose is to present certain concepts of this disclosure in a simplified form as a prelude to the more detailed description that follows.

[0005] According to one or more aspects of this disclosure, an apparatus is provided. The apparatus includes a plurality of bit lines intersecting a plurality of word lines, a plurality of intersection devices, and at least one output sensor that generates a digital output representing the sum of currents flowing through the first bit line of the plurality of bit lines. Each of the plurality of intersection devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines. The output sensor includes a first transistor connected in series with a second transistor, and an analog-to-digital converter configured to output the digital output.

[0006] In some embodiments, the drain of the first transistor is connected to the input of the analog-to-digital converter.

[0007] In some embodiments, the drain of the first transistor is also connected to the drain of the second transistor.

[0008] In some embodiments, the output sensor further includes a first resistor, wherein the drain of the first transistor is connected to the source of the second transistor via the first resistor.

[0009] In some embodiments, the gate of the first transistor is connected to a bit line reference voltage.

[0010] In some embodiments, the gate of the second transistor is connected to a second bit line among the plurality of bit lines.

[0011] In some embodiments, the source of the second transistor is connected to a power supply via a second resistor.

[0012] In some embodiments, the apparatus further includes a first plurality of switches configured to selectively connect the plurality of bit lines to the gate of the second transistor.

[0013] In some embodiments, the apparatus further includes a second plurality of switches configured to selectively connect the plurality of bit lines to the source of the first transistor.

[0014] In some embodiments, the input of the analog-to-digital converter is also connected to the first terminal of a capacitor.

[0015] In some embodiments, the second terminal of the capacitor is grounded.

[0016] In some embodiments, the crosspoint device includes at least one of a memristor, a phase-change memory (PCM) device, a floating-gate device, a spintronic device, a ferroelectric device, or a resistive random access memory (RRAM) device. Attached Figure Description

[0017] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting the present disclosure to the specific embodiments, and are for explanation and understanding only.

[0018] Figure 1 This is a schematic diagram illustrating an example of a cross switch circuit according to some embodiments of the present disclosure; Figure 2A and Figure 2B This is a schematic diagram illustrating examples of intersection devices according to some embodiments of the present disclosure; Figure 3 This is a circuit diagram illustrating an example of a cross switch circuit according to one implementation of the present disclosure; Figure 4 This is a circuit diagram illustrating an example of a cross switch circuit in another implementation according to this disclosure. Detailed Implementation

[0019] This disclosure provides readout circuitry for cross-switching circuitry including resistive random-access memory (RRAM or ReRAM) devices. The cross-switching circuitry may include crossed conductive lines (e.g., row lines, column lines, etc.) and crosspoint devices arranged in one or more arrays. Each crosspoint device may be connected to word lines, bit lines, and select lines. Crosspoint devices may include, for example, phase-change memory (PCM) devices, floating-gate devices, spintronic devices, ferroelectric devices, resistive random-access memory (RRAM) devices, etc. The cross-switching circuitry can be used in multi-level memory (MLM) circuitry and in-memory computing (IMC) circuitry.

[0020] Traditional cross-switch circuits typically employ operational amplifier (op-amp)-based readout circuits to first convert the memory cell current or accumulated array current into a voltage, which is then converted into a digital output using an analog-to-digital converter (ADC). The slew rate and bandwidth of the op-amp design limit the readout speed of MLM circuits or the operating speed of vector-matrix multiplication (VMM) for IMC circuits. Open-loop readout circuits can stabilize much faster with significantly lower power consumption. However, traditional open-loop circuits generally exhibit poor linearity and accuracy. Furthermore, these circuits are susceptible to device mismatch and variations in process, voltage, and temperature (PVT). Additionally, adjusting the gain of an open-loop circuit without significantly affecting linearity is challenging. While variable gain can be advantageous in certain applications, it presents challenges in open-loop circuit design.

[0021] This disclosure provides an open-loop readout circuit that can be integrated into a cross-switch circuit. In some embodiments, the readout circuit may include two transistors connected in series. The gate of the first transistor is connected to a reference voltage. The source of the second transistor in the readout circuit may be connected to the drain of the first transistor. The junction between the source of the second transistor and the drain of the first transistor may be selectively connected to the input of an analog-to-digital converter (ADC). The ADC may output a digital signal representing the current flowing through the bit line. In some embodiments, the source of the second transistor is connected to a resistor, which is further connected to the drain of the first transistor, and the resistance value of the resistor may be adjusted to change the gain of the readout circuit without affecting the linearity of the circuit. The readout circuit may be selectively connected to the bit line to perform a readout operation.

[0022] Compared to traditional bit line (BL) stabilized closed-loop circuits, the open-loop readout circuit disclosed herein offers the following advantages. First, the settling time is no longer limited by the operational amplifier bandwidth, resulting in a faster response speed. Second, the circuit consumes no additional power, leading to higher energy efficiency. Furthermore, the circuit requires only two transistors and two resistors, resulting in a smaller footprint. Third, the open-loop design eliminates the stability issues common in closed-loop circuits. Finally, the output voltage exhibits a linear relationship with the bit line current, similar to the closed-loop scheme. The output swing can be adjusted without affecting the circuit's linearity, providing greater flexibility.

[0023] Figure 1 This is a schematic diagram illustrating an example 100 of a cross switch circuit according to some embodiments of the present disclosure. As shown, the cross switch circuit 100 may include a plurality of interconnecting conductors, for example for n rows. The crossbar switch array 100 comprises one or more row lines 111a, 111b, ..., 111i, ..., 111n and column lines 113a, 113b, ..., 113j, ..., 113m. The crossbar switch circuit 100 may also include crosspoint devices 120a, 120b, ..., 120z, etc. Each crosspoint device may connect to one row line and one column line. For example, crosspoint device 120ij may connect to row line 111i and column line 113j. The number of column lines 113a-m may be the same as or different from the number of row lines 111a-n. The crossbar switch circuit 100 may also include word line (WL) logic 105, which is connected to the crosspoint devices via row lines 111a-n. Word line logic 105 may include any suitable components for applying input signals to selected crosspoint devices via row lines 111a-n, such as one or more digital-to-analog converters (DACs), amplifiers, etc. Each input signal can be a voltage signal, a current signal, etc.

[0024] Row lines 111a-n may include a first row line 111a, a second row line 111b, ..., 111i, ... and an nth row line 111n. Each row line 111a, ..., 111n may be and / or include any suitable conductive material. In some embodiments, each row line 111a-n may be a metal wire.

[0025] Column lines 113a-113m may include a first column line 113a, a second column line 113b, ..., and an m-th column line 113m. Each column line 113a-m may be and / or include any suitable conductive material. In some embodiments, each column line 113a-m may be a metal wire. In some embodiments, each row line 111a-n may be a word line, and each column line 113a-m may be a bit line.

[0026] Each cross-point device 120a-120z can be and / or include any suitable device with adjustable resistance, such as memristors, phase-change memory (PCM) devices, floating-gate devices, spintronic devices, ferroelectric devices, RRAM devices, etc.

[0027] Each row line 111a-111n may be connected to one or more row switches 131 (e.g., row switches 131a, 131b, ..., 131n). Each row switch 131 may include any suitable circuit structure for controlling the current flowing through the row lines 111a-111n. For example, the row switch 131 may be and / or include CMOS switching circuitry.

[0028] Each column line 113a-m may be connected to one or more column switches 133 (e.g., switches 133a, ..., 133m). Each column switch 133a-133m may include any suitable circuit structure for controlling the current flowing through the column line 113a-m. For example, the column line switches 133a-m may be and / or include CMOS switching circuitry. In some embodiments, one or more of the switches 131a-n and 133a-m may also provide fault protection, electrostatic discharge (ESD) protection, noise reduction, and / or any other suitable functionality for one or more portions of the cross-switch circuit 100.

[0029] Output sensor 140 converts the current flowing through column lines 113a-m into an output signal. For example, output sensor 140 may include readout circuitry 141 that converts the current flowing through the respective column lines into a corresponding voltage signal. Output sensor 140 may also include an analog-to-digital converter (ADC) 143 that converts the voltage signal into a digital output. In some embodiments, output sensor 140 may also include one or more multiplexers (not shown). In some embodiments, output sensor 140 may include... Figure 3 The output sensor 320 and / or Figure 4 The output sensor 420 is included.

[0030] Programming circuit 160 can program crosspoint devices 120a-z selected by switches 131 and / or 133 to suitable conductance values. For example, programming a crosspoint device may include applying a suitable voltage or current signal across the crosspoint device. The resistance of each crosspoint device can be electrically changed between high and low resistance. Setting a crosspoint device may include changing the resistance of the crosspoint from high to low. Resetting a crosspoint device may include changing the resistance of the crosspoint from low to high.

[0031] The cross-switch circuit 100 can perform parallel weighted voltage multiplication and current summation operations. For example, an input voltage signal can be applied to one or more rows of the cross-switch circuit 100 (e.g., one or more selected rows). The input voltage signal can flow through the cross-point devices in the rows of the cross-switch circuit 100. The conductance of the cross-point devices can be tuned to a specific value (also called a “weight”). According to Ohm’s law, the input voltage is multiplied by the cross-point conductance and a current is generated from the cross-point device. According to Kirchhoff’s laws, the sum of the currents flows through the active cross-point devices in the corresponding columns (also called “bit line currents”), which can be read from the column. According to Ohm’s law and Kirchhoff’s current law, the input-output relationship of the cross-switch array can be expressed as I=VG, where I represents the output signal matrix as current; V represents the input signal matrix as voltage; and G represents the conductance matrix of the cross-point devices. Therefore, the input signal is weighted at each cross-point device according to Ohm’s law through its conductance. The weighted current (“bit line current”) is output through each column line and can be accumulated according to Kirchhoff’s current law. This can be achieved through in-memory computation (IMC) via parallel multiplication and summation operations performed in a crossbar switch array.

[0032] The crossover switch circuit 100 can be configured to perform vector-matrix multiplication (VMM). A VMM operation can be represented as Y = XA, where Y, X, and A each represent a corresponding matrix. More specifically, for example, the input vector X can be mapped to the input voltage V of the crossover switch circuit 100, matrix A can be mapped to the conductance value G, and the output current I can be read and mapped back to the output result Y. In some embodiments, the crossover switch circuit 100 can be configured to implement part of a neural network by performing vector-matrix multiplication.

[0033] In some embodiments, the cross-switch circuit 100 may perform convolution operations. For example, performing a two-dimensional convolution on input data may involve applying a single convolution kernel to the input signal. Performing a depthwise convolution on input data may involve convolving each channel of the input data with a corresponding kernel corresponding to that channel and stacking the convolved outputs together. The convolution kernel may have a specific size defined by multiple dimensions (e.g., width, height, channels, etc.). The convolution kernel may be applied to portions of input data of the same size to produce an output. The output may be mapped to elements in the convolution result that correspond to the positions of the input data portions.

[0034] Figure 2A and Figure 2B This is a schematic diagram illustrating examples of crosspoint devices 1220a and 1220b according to some embodiments of the present disclosure. Crosspoint devices 1220a and 1220b may be referred to as a 1 transistor 1 resistor (1T1R) configuration.

[0035] like Figure 2A and Figure 2B As shown, cross-point device 1220a or 1220b may include RRAM device 1201 and transistor 1203 connected in series. The transistor may include four terminals, labeled as gate (G), source (S), drain (D), and body (B), respectively. Figure 2A and Figure 2B (Not shown in the image). Reference Figure 2A The first terminal of RRAM device 1201 can be connected to the drain of transistor 1203. The second terminal of RRAM device 1201 can be connected to bit line 1211. The source of transistor 1203 can be connected to word line 1215, and the gate of transistor 1203 can be connected to select line 1213.

[0036] like Figure 2B As shown, in some embodiments, the second terminal of the RRAM device 1201 may be connected to word line 1215, and the source of transistor 1203 may be connected to bit line 1211. Word line 1215 may correspond to... Figure 1 The row line 111a-n and bit line 1211 in the text can correspond to Figure 1 The column line 123a-m.

[0037] Transistor 1203 can function as a selector and current controller, setting the current compliance of RRAM device 1201 during programming. The gate voltage of transistor 1203 can set the current compliance of crosspoint devices 1220a-b during programming, and thus control the conductance and analog behavior of crosspoint devices 1220a-b. For example, when crosspoint devices 1220a-b are set from a high-resistance state to a low-resistance state, a setting signal (such as a voltage signal, current signal) can be provided via bit line (BL) 1211 or word line (WL) 1215. Another voltage (also called the select voltage or gate voltage) can be applied to the transistor gate via select line (SEL) 1213 to turn on the gate and set the current compliance, while word line (WL) 1215 or bit line (BL) 1211 can be grounded. When crosspoint devices 1220a-b are reset from a low-resistance state to a high-resistance state, the gate voltage can be applied to the gate of transistor 1203 via select line 1213 to turn on the transistor gate. Meanwhile, the reset signal can be sent to the RRAM device 1201 via word line 1215 or bit line 1211, while bit line 1211 or word line 1215 can be grounded.

[0038] Figure 3 This is a circuit diagram illustrating an example of a cross switch circuit 300 in one implementation according to the present disclosure.

[0039] As shown in the figure, the cross switch circuit 300 may include a cross switch array 310 and an output sensor 320. The cross switch array 310 may include multiple word lines (WL1, WL2, ..., WLn) interconnected with multiple bit lines (e.g., BL1, ..., BLm). The cross switch array 310 may also include multiple cross-point devices 315a, ..., 315z, each cross-point device connected to at least one of the word lines and at least one of the bit lines. The cross switch array 310 may be and / or include... Figure 1 The cross switch array 101 in the middle.

[0040] Output sensor 320 may include readout circuitry 330 and ADC 340. Readout circuitry 330 may be selectively connected to the input of ADC 340 via switch 350 to provide a voltage signal Vout to ADC 340. ADC 340 may convert the voltage signal Vout into a digital signal Dout. In some embodiments, output sensor 320 may further include one or more suitable capacitors 360 connected to ADC 340. In some embodiments, a first terminal of capacitor 360 may be connected to the input of ADC 340. A second terminal of capacitor 360 may be grounded.

[0041] The readout circuit 330 may include a first transistor 331a, a second transistor 331b, and one or more resistors 333. As shown, resistor 333 is connected between the voltage source VDD and the source of the second transistor 331b. The first transistor 331a and the second transistor 331b may be connected in series with each other. For example, the drain of the second transistor 331b is connected to the drain of the first transistor 331a. The gate of transistor 331a is connected to a reference voltage BL_REF. The junction of the source of the second transistor 331b and the drain of the first transistor 331a provides the output voltage Vout.

[0042] The readout circuit 330 can be selectively connected to bit lines BL1, ..., BLm to perform a read operation. In some embodiments, the cross-switch circuit 300 may include multiple sets of switches configured to selectively connect bit lines to the readout circuit 330. For example, the cross-switch circuit 300 may include a first plurality of switches (e.g., switches 370a, ..., 370m) configured to connect corresponding bit lines BL1, ..., BLm to the gate of the second transistor 331b and a second plurality of switches (e.g., switches 375a, ..., 375m) configured to connect corresponding bit lines BL1, ..., BLm to the source of the first transistor 331a. For example, the readout circuit 330 can be connected to bit line BL1 via switches 370a and 375a (e.g., by closing switches 370a and 375a). Switches 370a and 375a can selectively connect bit line BL1 to the gate of the second transistor 331b and the source of the first transistor 331a, respectively. As another example, the readout circuit 330 can be connected to the bit line BLm via switches 370m and 375m (e.g., by closing switches 370m and 375m). Switches 370m and 375m can selectively connect the bit line BLm to the gate of the second transistor 331b and the source of the first transistor 331a, respectively. In some embodiments, the readout circuit 330 is configured to connect to only one selected bit line during a read operation (e.g., by closing a set of switches connected to the selected bit line and opening a set of switches connected to other bit lines).

[0043] As the BL current increases, the drain-source saturation voltage (Vdsat) of the first transistor 331a rises, causing the BL voltage to decrease. Without the second transistor 331b, the decrease in BL voltage would reduce the cell current, thus increasing the output voltage of the readout circuit. The presence of the second transistor 331b effectively compensates for output voltage Vout fluctuations that may be caused by changes in bit line current in the open-loop circuit. Resistor 333 can be used to adjust the linearity of the output voltage.

[0044] Figure 4 This is a circuit diagram illustrating an example of a cross switch circuit 400 according to another implementation of this disclosure.

[0045] As shown in the figure, the cross switch circuit 400 may include a cross switch array 310 and an output sensor 420. The output sensor 420 may include a readout circuit 430 and an ADC 440. The readout circuit 430 may be selectively connected to the ADC 440 via a switch 450 to provide a voltage signal Vout as input to the ADC 440. The ADC 440 may convert the voltage signal Vout into a digital signal. In some embodiments, the output sensor 420 may also include one or more suitable capacitors 460 connected to the ADC 440.

[0046] The readout circuit 430 may include a first transistor 431a, a second transistor 431b, and resistors 433a and 433b. As shown, the first transistor 431a and the second transistor 431b may be connected in series with each other. The drain of the second transistor 431b is connected to resistor 433b (also referred to as the "first resistor"), which is further connected to the drain of the first transistor 431a. The source of the first transistor 431a is connected to a first bit line, and the gate of the transistor 431a is connected to a reference voltage BL_REF, which may be a reference voltage used to control the operation of the first transistor 431a. The connection point between the first resistor 433b and the drain of the first transistor 431a provides an output voltage Vout. Resistor 433a (also referred to as the "second resistor") is connected between a voltage source VDD and the source of the second transistor 431b. Resistors 433a and / or 433b may be variable resistors with adjustable resistance values.

[0047] The resistance value of resistor 433b can be changed to adjust its gain without affecting the linearity of the readout circuit 430. Adding a passive resistor (i.e., resistor 433b) to the readout circuit provides a gain adjustment method with minimal impact on linearity.

[0048] The readout circuit 430 can be selectively connected to bit lines BL1, ..., BLm to perform a read operation. In some embodiments, the cross-switch circuit 400 may include multiple sets of switches configured to selectively connect bit lines to the readout circuit 430. For example, the cross-switch circuit 400 may include a first plurality of switches (e.g., switches 470a, ..., 470m) configured to connect corresponding bit lines BL1, ..., BLm to the gate of the second transistor 431b and a second plurality of switches (e.g., switches 475a, ..., 475m) configured to connect corresponding bit lines BL1, ..., BLm to the source of the first transistor 431a. For example, the readout circuit 430 can be connected to bit line BL1 via switches 470a and 475a (e.g., by closing switches 470a and 475a). Switches 470a and 475a can selectively connect bit line BL1 to the gate of the second transistor 431b and the source of the first transistor 431a, respectively. As another example, the readout circuit 430 can be connected to the bit line BLm via switches 470m and 475m (e.g., by closing switches 470m and 475m). Switches 470m and 475m can selectively connect the bit line BLm to the gate of the second transistor 431b and the source of the first transistor 431a, respectively. In some embodiments, the readout circuit 430 is configured to connect to only one selected bit line during a read operation (e.g., by closing a set of switches connected to the selected bit line and disconnecting a set of switches connected to other bit lines).

[0049] As used in this disclosure, the terms “about,” “approximately,” and “substantially” can refer to normal tolerances in the art, such as within two standard deviations of the mean, within ±20% of the target size in some embodiments, within ±10% of the target size in some embodiments, within ±5% of the target size in some embodiments, within ±2% of the target size in some embodiments, within ±1% of the target size in some embodiments, and even within ±0.1% of the target size in some embodiments. The terms “about” and “approximately” can include the target size. Unless specifically stated or clearly indicated by the context, all numerical values ​​described in this disclosure are modified by the term “about.”

[0050] As used in this disclosure, a range includes all values ​​within that range. For example, a range of 1 to 10 may include any number, combination of numbers, subranges, and fractions of 1, 2, 3, 4, 5, 6, 7, 8, 9, 10.

[0051] Many details have been set forth in the foregoing description. However, it will be apparent that this disclosure may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form rather than in detailed form to avoid obscuring this disclosure.

[0052] The terms “first,” “second,” “third,” “fourth,” etc., used in this disclosure are merely labels to distinguish different elements and do not necessarily have an sequential meaning based on their numerical designations.

[0053] The terms “example” or “exemplary” used in this disclosure are intended to mean as an example, instance, or illustration. Any aspect or design described in this disclosure as an “example” or “exemplary” is not necessarily to be construed as superior to other aspects or designs. Rather, the use of the term “example” or “exemplary” is intended to present concepts in a specific manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated or the context clearly indicates, “X includes A or B” is intended to mean any natural inclusive arrangement. In other words, “X includes A or B” holds true if X includes A; X includes B; or X includes both A and B. Furthermore, the articles “a” and “an” used in this application and the appended claims should generally be interpreted as “one or more” unless otherwise stated or the context clearly indicates the singular form. In this specification, references to “an embodiment” or “an implementation” mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases “an embodiment” or “an implementation” appearing throughout this specification do not necessarily refer to the same embodiment.

[0054] As used in this disclosure, when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on the other element or layer, or there may be intermediate elements or layers present. Conversely, when an element or layer is referred to as being "directly on" another element or layer, there are no intermediate elements or layers present.

[0055] While many modifications and variations of this disclosure will undoubtedly become apparent to those skilled in the art after reading the foregoing description, it should be understood that any particular embodiment shown and described by way of example is in no way intended to be limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which themselves merely enumerate those features considered to be part of this disclosure.

Claims

1. An apparatus comprising: Multiple bit lines that intersect with multiple word lines; A plurality of cross-point devices, wherein each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines; as well as At least one output sensor generates a digital output representing the sum of the currents flowing through the first bit line of the plurality of bit lines, the output sensor comprising: The first transistor connected in series with the second transistor; as well as An analog-to-digital converter configured to output the digital output, wherein the drain of the first transistor is connected to the input of the analog-to-digital converter.

2. The apparatus of claim 1, wherein the drain of the first transistor is further connected to the drain of the second transistor.

3. The apparatus of claim 2, wherein the output sensor further comprises a first resistor, wherein the drain of the first transistor is connected to the source of the second transistor through the first resistor.

4. The apparatus of claim 2, wherein the gate of the first transistor is connected to a bit line reference voltage.

5. The apparatus of claim 4, wherein the source of the second transistor is connected to a power supply via a second resistor.

6. The apparatus of claim 1, further comprising a first plurality of switches configured to selectively connect the plurality of bit lines to the gate of the second transistor.

7. The apparatus of claim 6, further comprising a second plurality of switches configured to selectively connect the plurality of bit lines to the source of the first transistor.

8. The apparatus of claim 1, wherein the input of the analog-to-digital converter is further connected to a first terminal of a capacitor.

9. The apparatus of claim 8, wherein the second terminal of the capacitor is grounded.

10. The apparatus of claim 1, wherein the crossover device comprises at least one of a memristor, a phase-change memory (PCM) device, a floating-gate device, a spintronic device, a ferroelectric device, or a resistive random access memory (RRAM) device.

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