Distance protection with symmetrical three-phase fault detection

Abstract

A method and apparatus for determining a symmetrical fault in a three-phase transmission line is provided. The method includes the steps of obtaining real-time current signals and real-time voltage signals at a relay location at one end of the transmission line for each measured phase circuit, determining a set point voltage signal and a relay point voltage signal based on the real-time current signals and real-time voltage signals for each measured phase circuit, determining an operating signal and a suppression signal for each measured phase circuit, determining whether the operating signal for a certain measured phase circuit exceeds the suppression signal, determining whether the relay point phase voltage for the measured phase circuit exceeds the set point phase voltage, and detecting a fault if it is determined that the operating signal exceeds the suppression signal and the relay point phase voltage exceeds the set point phase voltage.

Description

Technical Field

[0001] This disclosure relates to a method, apparatus, and system for controlling and protecting an electrical system including transmission lines. Background Technology

[0002] In electrical systems including transmission lines, accurate fault identification is crucial for implementing further corrective measures. Distance protection is widely used to protect transmission lines. However, with the increasing use of variable renewable sources, traditional methods face challenges in processing measurement results due to fault current waveform distortion and high-order harmonic components, especially for transmission lines connected to doubly-fed induction generators (DFIGs). The basic principles of distance protection and the traditional methods used in conjunction with it are briefly discussed below.

[0003] Traditionally, distance protection relies on the calculation of the impedance of the line under test, which reflects the positive-sequence impedance of the protected transmission line. This calculation is based on Ohm's law as follows: Impedance measurements may involve two types of calculation loops: 1) based on the phase-to-ground loop and 2) based on the phase-to-phase loop. The phase-to-ground loop impedance can be calculated as follows:

[0004] in, This represents the phase-to-ground voltage measured at the relay position on the transmission line. This refers to the phase-to-ground loop current measured at the relay position on the transmission line, for example... , This represents the zero-sequence current measured from the three-phase current, i.e. , Indicates the compensation factor, for example, , This represents the zero-sequence impedance as seen from the relay position to the end of the protected area, and This represents the positive sequence impedance as seen from the relay position to the end of the protected area.

[0005] The phase-to-phase circuit impedance can be calculated as follows.

[0006]

[0007] in, and This represents the phase-to-ground voltage measured at the relay position on the transmission line, for example, , and among them, and This represents the phase-to-ground current measured at the relay position on the transmission line, for example, .

[0008] As can be clearly seen from the equations above, these calculations are based on Ohm's law, which requires that input variables such as voltage and current must be in the same frequency domain. For a 50 Hz power system, these measurement inputs should be 50 Hz phasors to justify the calculations.

[0009] However, in the case of a line connected to a variable regenerative source, the measured voltage and measured current on the variable regenerative source side may not have the same frequency during the fault period, so the calculation results of equations (1) and (2) may be incorrect. This may lead to misjudgments, such as over-range distance protection or under-range distance protection.

[0010] Given the above, the first method can determine the reach point of the distance protection by combining sequence voltage with phase domain calculations. The basic concept of this method is to calculate the sequence voltage at the reach point: the positive sequence voltage at the reach point. Negative sequence voltage at the setting point and the zero-sequence voltage at the setting point. Then, taking the AG fault at the set point as an example, the operating quantity of equation (3) and the suppression quantity of equation (4) can be calculated and compared with each other.

[0011]

[0012]

[0013] If the operation volume Greater than the inhibition amount This allows for the determination of an internal fault within the protected area, enabling the issuance of a trip signal. Note that equations (3) and (4) are calculated for the detection of asymmetric faults associated with phase A (such as AG fault, ABG fault, ACG fault, AB fault, and AC fault). In the case of faults associated with phase B or phase C, the calculation of equations (3) and (4) can be based on the corresponding phase signal. For example, for a BG fault, the operating value is determined by... V b0,rp and V b2,rp The sum is formed, and the amount of inhibition can be achieved by using V b1,rp Formation. Here, V b0,rp It is the zero-sequence voltage of phase B calculated at the setting point.V b2,rp It is the negative sequence voltage of phase B calculated at the setting point. V b1,rp It is the positive sequence voltage of phase B calculated at the setting point.

[0014] The calculation of the setpoint sequence voltage can be based on the phasor domain. In this case, it can be calculated by subtracting the corresponding sequence voltage drop along the line from the relay measurement point. , and Equal setting point sequence voltage.

[0015]

[0016]

[0017]

[0018] Here, These represent the positive sequence impedance, negative sequence impedance, and zero sequence impedance from the relay position to the setting point, respectively.

[0019] (8) in, a = -0.5 + j0.866, and a 2 = -0.5 - j0.866.

[0020] The setting point voltage can also be calculated based on the phasor domain by using line parameters, especially by using the original three-phase transmission line self-impedance and coupling impedance, as well as the original three-phase current in the phase domain.

[0021]

[0022] Here, This represents the transmission line self-impedance of each phase in a three-phase transmission line. This represents the coupling impedance between each pair of phases, such as AB, BC, and CA. It is assumed that the three-phase line transposes between each pair of phases with the same coupling impedance and the same self-impedance. , and It is the three-phase current in the phasor domain. and Based on the setting value (i.e. " The phasor domain voltage of the set point calculated is typically 0.8 for line protection, which is 80% of the line length.

[0023] The setting point voltage can also be calculated based on the time domain. Here, two steps are proposed using time-domain differential equations, as follows: In the first step, the setting point voltage is calculated based on the voltage and current signals measured locally by IWD and the line impedance parameters R and L. Here, R=R 1 is the positive sequence resistance at the setting point, and L=L 1 is the positive inductance at the setting point.

[0024]

[0025] Here, R 0 is the zero-sequence resistance at the setting point, and X 0 is the zero-sequence reactance at the setpoint. i 0 represents zero-sequence current. u a , u b , u c It is the three-phase voltage measured by the relay, and i a , i b , i c It is the three-phase current measured by the relay.

[0026] In the second step, the setpoint voltage is converted into a phasor using a Fourier transform.

[0027] Furthermore, for calculating the receiving and transmitting voltages of long lines, alternative solutions can be used to calculate the setting point voltage, such as distributed transmission line modeling based on telegraph equations or hyperbolic trigonometric functions. For short lines, another solution can be achieved by using the Pi model based on lumped line parameters.

[0028] However, there is a need for improved methods, devices, and systems for controlling electrical systems, including power transmission lines.

[0029] Specifically, power system faults in transmission lines include A-phase-to-ground faults, B-phase-to-ground faults, C-phase-to-ground faults, AB-phase-to-ground faults, BC-phase-to-ground faults, CA-phase-to-ground faults, AB-phase faults, BC-phase faults, CA-phase faults, as well as three-phase faults ABC and ABC-to-ground faults. During ABC or ABCG faults, both the negative-sequence and zero-sequence components become zero, making equation (3) no longer applicable for detecting ABC / ABCG faults. Therefore, a new solution is needed. Summary of the Invention

[0030] Therefore, this disclosure provides a method and apparatus for determining symmetrical faults in a three-phase transmission line as defined in the appended independent claims; the dependent claims describe embodiments of this disclosure.

[0031] The method according to this disclosure includes the following steps: obtaining real-time current and real-time voltage signals at the relay position at one end of the protected transmission line for each of the phase circuits under test; determining the setting point voltage signal and the relay point voltage signal based on the real-time current and real-time voltage signals for each of the phase circuits under test; determining the operating quantity and suppression quantity, as well as the optional phase quantity, for each of the phase circuits under test; determining whether the operating quantity of a given phase circuit under test exceeds the suppression quantity; determining whether the relay point phase voltage of the phase circuit under test exceeds the setting point phase voltage; and detecting a fault if it is determined that the operating quantity exceeds the suppression quantity and the relay point phase voltage exceeds the setting point phase voltage.

[0032] This disclosure presents a solution based on the idea that for internal faults, the setting point voltage is opposite in direction to the local relay measured voltage, while for external faults, the setting point voltage is in the same direction as the local relay voltage. Accordingly, taking phase A as an example, this solution relies on the relay point voltage U... A and the setpoint voltage U comp The calculation. Therefore, based on the calculated relay point voltage U. A and the setpoint voltage U comp Determine the new operation quantity U op and compare it with the inhibition level U restrain By comparing these parameters, ABC / ABCG faults can be detected. Therefore, this disclosure can be used for ABC / ABCG fault detection in three-phase power transmission systems.

[0033] In other words, the relay position phase voltage / phase-to-phase voltage and setting point phase voltage / phase-to-phase voltage are proposed to form new operating characteristics of the compensation relay, thereby improving the reliability and safety under the conditions of connecting variable and renewable power grid applications.

[0034] According to this disclosure, new operating quantities and suppression quantities are determined in the phasor domain as follows.

[0035] U op = | U A – U comp | U restrain = | U A |。(10) Determine the relay point voltage U in the phasor domain or time domain A and the setpoint voltage U comp The setpoint sequence voltage in the phasor domain can be calculated using the Fourier transform method.

[0036] When the operating quantity exceeds the suppression quantity, an internal fault can be identified. Equivalently, the relay point voltage U can be calculated using trigonometric cosine functions. A With the setpoint voltage U comp The internal fault is determined by the output of the phase angle difference between the two phases. Therefore, the internal fault can be determined as follows.

[0037] U op >U restrain cos( U A _ phasor _ angle – U com _ phasor _ angle )<0 (11) Here, U op It is the amount of operation; U restrain It is the inhibitory amount; U A _ phasor _ angle It is the relay point voltage U A The phasor angle, in degrees; and U com _ phasor _ angle It is the setpoint voltage U comp The phasor angle, in degrees. If the cosine is determined to be less than 0 as described above, a fault is identified in Zone 1.

[0038] According to the embodiment, it is not necessary to detect external faults. The protection solution according to this embodiment can detect only internal faults within the setting area. For external faults, the given solution can accept them as safe or stable. On the other hand, when the operating amount is less than the suppression amount, that is, when the setting point voltage has the same polarity as the relay point voltage in this case, a positive external fault can be determined. Equivalently, the relay point voltage U can be calculated using trigonometric cosine functions. A With the setpoint voltage U comp The output of the phase angle difference between the two phase angles determines the positive external fault. Therefore, the positive external fault can be determined as follows.

[0039] U op restrain ​cos( U A _ phasor _ angle – U com _ phasor _ angle )>0 (12) Similarly, U op It is the amount of operation; U restrain It is the inhibitory amount; U A _ phasor _ angle It is the relay point voltage U A The phasor angle, in degrees; and U com _ phasor _ angle It is the setpoint voltage U comp The phasor angle, in degrees. If the cosine is determined to be greater than 0 as described above, a positive external fault is identified.

[0040] In a preferred embodiment, a positive direction element is added by comparing the relay position voltage in one phase with the corresponding phase voltage at the setting point. Here, taking phase A as an example, the positive direction criterion is shown in equation (13).

[0041] > (13) Here, It is the phasor amplitude of phase A voltage measured at the relay position, and This is the calculated phasor amplitude of the A-phase setting point voltage. By adding a forward directional element, stability under reverse fault conditions is ensured. Therefore, the line protection is more reliable.

[0042] The given solutions described in equations (10), (11), (12) and (13) can be referred to as voltage-based distance protection (VDP).

[0043] Furthermore, this disclosure provides an apparatus for determining internal symmetrical faults in a three-phase power transmission line. The apparatus includes a processor configured to acquire real-time current and voltage signals at a relay position at one end of the transmission line; determine a setting point voltage signal and a relay point voltage signal based on the real-time current and voltage signals; determine an operating signal and a suppression signal; determine whether the operating signal exceeds the suppression signal; determine whether the relay point phase voltage exceeds the setting point phase voltage; and detect a fault if it is determined that the operating signal exceeds the suppression signal and the relay point phase voltage exceeds the setting point phase voltage.

[0044] The device may further include equipment for obtaining phase voltage signals on a three-phase transmission line.

[0045] This disclosure further provides a system for determining symmetrical faults in three-phase power transmission, the system comprising the equipment and three-phase transmission line as described above.

[0046] This disclosure enables faster, cheaper, and safer identification of symmetrical faults, particularly in three-phase transmission lines. The methods, apparatus, and systems of this disclosure significantly improve the reliability of existing distance protection solutions used in AC power systems with or without wind farm connections. Attached Figure Description

[0047] The present disclosure will be described in more detail below with reference to the accompanying drawings, wherein, Figure 1 A diagram illustrating the internal three-phase fault conditions is shown. Figure 2 A diagram illustrating external three-phase fault conditions is provided. Figure 3 A typical transmission line connected to two source ends is shown. Figure 4 It is a graph showing the current and voltage measured at the relay position. Figure 5 It is a graph showing the calculated setpoint voltage. Figure 6 This is a graph showing the operating and suppression quantities during an internal fault. Figure 7 This is a graph showing the phase angle measurements and cosine values ​​corresponding to the ABCG fault in zone 1 boundary. Figure 8 This is a graph showing the operational and suppression quantities during an external ABCG fault at 85% of the line length. Figure 9 This is a graph showing the phase angle measurements and cosine values ​​corresponding to an external fault at 85% of the line length. Figure 10 The stability of the direction detection unit in blocking three-phase ABCG fault operation is shown for reverse faults. Figure 11 This illustrates the action of the directional element due to Va_IED_M > Va_RP-M in the case of a positive fault, and Figure 12 The diagram illustrates a grid-connected converter commonly used in wind farms. Figure 13 This illustrates the impact of weak sources on the PLL output during ABCG faults. Figure 14 This illustrates the impact of a strong source on the PLL output during an ABCG fault. Figure 15 This demonstrates the impact of the nonlinear behavior of grid-type converters on known fault detection solutions. Figure 16 The impact of system strength on known voltage-based distance protection solutions is shown. Figure 17 A mitigation solution for ABCG faults at 70% of the line length under weak system conditions is presented. Figure 18 The effects of nonlinear behavior when the method according to this disclosure is applied are shown. Figure 19 A flowchart of another method for a phase-to-ground loop according to an embodiment is shown, and Figure 20 A flowchart of another method for phase-to-phase loops according to an embodiment is shown. Detailed Implementation

[0048] As those skilled in the art may note, equations (3) and (4) have used the negative-sequence voltage and zero-sequence voltage at the setting point as operating quantities for fault detection. However, this only applies to unbalanced faults, since no negative-sequence voltage and zero-sequence voltage are available during three-phase faults, which are balanced faults. As a result, equations (3) and (4) cannot actually be used for three-phase fault detection. Therefore, this disclosure provides a novel solution for fault identification by using new operating quantities to cover three-phase faults, as will be described below.

[0049] Given the problem that conventional operating quantities are unavailable during three-phase faults, this disclosure relies on new ideas or solutions to determine the required suppression quantity U. restrain New operation quantity U for comparison opThis allows for the detection of ABC / ABCG faults. This can be achieved by replacing the calculations of the operating and suppressing quantities given in equations (3) and (4) with the calculations given in equation (10) above.

[0050] When using the phasor domain setpoint voltage calculated according to equation (10), the mathematical expression of the proposed solution can be given as follows.

[0051] U op = | U A – U comp | U restrain = | U A | (10) Setting point voltage U comp The phasor domain quantities can be calculated using typical Fourier transform methods. The setting point C represents one end of zone 1 of the protected line, as described below. Figure 1 and Figure 2 As described.

[0052] Based on the new operating quantity, a new solution for three-phase fault detection can be provided, which is based on the comparison between the operating quantity and the suppression quantity as given in equation (10) above.

[0053] When the operation exceeds the inhibition amount and the angle U A _ phasor _ angle – U com _ phasor _ angle When the cosine of the equation is negative, an internal fault is confirmed. This is because, in cases such as... Figure 1 In the case of the internal fault shown, U A with U comp The difference between them is greater than U A Self. This is because in this situation, U A and U comp The direction is opposite. In other words, U A and U comp They have opposite polarities. This is because, compared to relay point A, setting point C is located on the opposite side of the protected transmission line relative to fault point F.

[0054] An external fault is determined to exist when the operating amount is less than the suppression amount and the cosine of the angle is positive. This is because, in cases such as Figure 2 In the case of the external fault shown, U A with U comp The difference between them is less than U A Self. This is because in this situation, U A and U comp The directions are the same. In other words, U A and U comp They have the same polarity. This is because the setting point C and the relay point A are located on the same side of the protected transmission line relative to the fault point F.

[0055] The solutions proposed in this disclosure can be provided based on a test system, such as... Figure 3 As shown in the figure, this diagram illustrates a typical transmission line connected to two source ends.

[0056] To further verify this method, it has been used as follows: Figure 3 The two sources connected by the transmission line shown were tested against different types of imbalance faults. The tests show that the given solution is stable under these conditions.

[0057] Specifically, as an example, a test was conducted on an internal three-phase fault located at 80% of the line length, and the results were stable. The corresponding results are as follows: Figures 4 to 7 As shown.

[0058] Figure 4 The upper window shows the three-phase voltage during an internal three-phase ABCG fault at 80% of the line length, and the lower window shows the corresponding three-phase current. Figure 5 The upper window displays the calculated setpoint voltage for each of the three phases, and the bottom window displays their average values. Figure 6 The corresponding operating and suppression values ​​are displayed in the upper window, and the corresponding trip signals are displayed in the bottom window. Figure 7 The phasor angle of the relay point voltage is shown in the upper window. U A _ phasor _ angle phasor angle with the setpoint voltage U com _ phasor _ angle And the corner is shown in the bottom window. U A _ phasor_ angle – U com _ phasor _ angle The cosine of .

[0059] Specifically, as an example, a test was conducted on an external three-phase ABCG fault located at 85% of the line length, and the results were stable. The corresponding results are as follows: Figures 8 to 9 As shown.

[0060] Figure 8 The upper window shows the three-phase voltage during an external three-phase ABCG fault at 85% of the line length, and the corresponding three-phase current is shown in the bottom window. Figure 9 The upper window displays the calculated setpoint voltage for each of the three phases, and the bottom window displays their average values.

[0061] Figure 10 As shown, for a reverse fault, since the local device voltage Va_IED_M does not exceed the setting point voltage Va_RP_M, the direction detection unit configured to perform fault detection according to this disclosure will remain stable to block the three-phase ABCG fault. Figure 11 As shown, for a positive fault, the directional element will always be active because the local device voltage Va_IED_M exceeds the setting point voltage Va_RP_M.

[0062] Therefore, the results presented confirm that the solution proposed in this disclosure can reliably detect three-phase faults in protected areas.

[0063] In specific applications of transmission lines in power grids involving renewable sources (such as wind farms), it is natural to observe different source intensities on the grid side. Within the power system protection domain, source intensity is measured as the source impedance ratio (SIR), which is the ratio of the source impedance (…). Z s Divide by the protection line impedance ( Z 1) The ratio. This means that if the SIR is low, the source is strong, and if the SIR is high, the source is weak. On the other hand, it is well known that most wind farms still use converters controlled by grid-connected controllers. Typical control of grid-connected converters can be found in... Figure 12 (a) shows the main circuit and control system structure, and (b) shows the phase-locked loop (PLL).

[0064] The main requirement for grid-connected converters is to use the grid-side three-phase voltage input at the point of common coupling (PCC). VpccThis is used to form a phase-locked loop (PLL), ensuring that the converter output has the same frequency as the connected power grid. For example, from... Figure 12 As can be seen, the PLL output has a phase angle proportional to the given power grid frequency. In cases of weak grid-side systems, the PLL output may become out of sync with the given grid during three-phase fault periods.

[0065] To verify this phenomenon, ABCG faults were applied to 70% of the transmission line length, with the grid connecting the Type 4 wind farm being a weak source (SIR = 2). Figure 13 The effect on the PLL output during the ABCG fault is shown, and it is indicated that the PLL output frequency will not return to 50 Hz after the ABCG fault, which means that the grid follower controller loses synchronization with the connected grid.

[0066] If the grid-side source strength increases to SIR = 0.5, the PLL output will be synchronized with the grid frequency even after an ABCG fault. Figure 13 The results are shown.

[0067] Therefore, the aforementioned problems with weak sources on the power grid side will introduce nonlinear behavior into the fault detection solution described above for ABCG fault detection. Figure 15 This illustrates this type of nonlinear problem when the source on the grid side is a weak source with SIR = 2. For an ABCG fault at the boundary of Zone 1 with Rf = 0.01 ohms, the operating value Vop_RP_3p_Am (the lower line in the figure) is at the same level as the suppression value V_IED_local_D. Then, applying the same fault with Rf = 10 ohms, a brief crossover period is observed between the operating and suppression values. As a result, previously existing protection solutions may trip incorrectly. On the other hand, if Rf is increased to Rf = 20 ohms, a significant gap again appears between the operating and suppression values.

[0068] Different SIR values ​​can be used to further explore the impact of grid-side source strength. Figure 16 The results of the exploration are shown. It can be noted that for the same ABCG fault with Rf = 10 ohms, the nonlinear behavior disappears when the system strength is increased to SIR < 1.0.

[0069] This disclosure provides an additional solution to this problem by offering a new suppression measure that delays the local relay voltage by several cycles, such as 2 to 10 cycles, or for example, 5 cycles. This allows for the checking of the operating and suppression quantities during three-phase faults. This addition is particularly useful under weak system conditions.

[0070] Figure 17The diagram illustrates the corresponding behavior of applying ABCG faults at 70% of the transmission line length with different Rf values ​​in an additional solution for weak systems. Three graphs show the voltage-based distance protection (VDP) for resistance values ​​of Rf = 0.01 ohms, Rf = 10 ohms, and Rf = 20 ohms, respectively. The upper curve shows V... op_RP The lower curve shows V IED Z1 is set to 70% of the line length.

[0071] Figure 18 The same behavior under the same conditions is shown, with the corresponding trip signal in the lower figure. As can be seen, the nonlinear effect has been mitigated by delaying the voltage of phase A of the local relay by 5 cycles.

[0072] Figure 19 A flowchart of another method for a phase-to-ground loop according to an embodiment is shown, which serves as a general method for detecting different types of faults associated with phase-to-ground faults.

[0073] exist Figure 19 In the first step shown at the top, a real-time sampling signal i is provided. a (t), i b (t), i c (t), U a (t), U b (t) and U c (t). In subsequent steps, the setpoint voltage is calculated. In subsequent steps, the phasors, operating signals, and suppression signals for the three phase-to-ground loops are calculated based on the real-time sampled signal and the setpoint voltage, as follows: U op_Φ = | U Φ – U Φ_rp |and U Φ_restrain = | U Φ |, in, U Φ Φ represents the phase-to-ground voltage at the relay position; in other words, Φ is A, B, or C. Φ_rp This represents the phase-to-ground voltage at the setpoint; in other words, Φ is A, B, or C. In the two subsequent steps, the operating signal, suppression signal, and phasor are checked for two conditions as follows: U op_Φ > U Φ_restrain as well as U Φ > U Φ_rp .

[0074] You can press as follows Figure 19 The conditions are checked in the order shown, i.e., the second condition is checked after the first condition has been confirmed. Alternatively, the conditions can be checked in reverse order or simultaneously. During line protection, all the steps described above are performed continuously or periodically for each of the phase circuits under test. Once both conditions of the phase circuit under test are confirmed, a fault is detected, and a trip signal is triggered for the faulty phase-to-ground circuit.

[0075] Figure 20 A flowchart of another method for phase-to-phase loops according to an embodiment is shown, which serves as a general method for detecting different types of faults associated with phase-to-phase faults. This method is similar to... Figure 19 The method for the phase-to-ground loop scenario is shown.

[0076] exist Figure 20 In the first step shown at the top, a real-time sampling signal i is provided. a (t), i b (t), i c (t), U a (t), U b (t) and U c (t), where i a (t), i b (t), i c (t) is the real-time current signal, and U a (t), U b (t) and U c (t) is the real-time voltage signal. In subsequent steps, the setpoint voltage is calculated. In these subsequent steps, the phasors, operating signals, and suppression signals for the three phase-to-phase loops are calculated based on the real-time sampled signal and the setpoint voltage, as follows: U op_ΦΦ = | U Φ Φ – U ΦΦ _rp |and U ΦΦ _restrain = | U ΦΦ |, Among them, U Φ Φ It is the phase-to-phase voltage measured at the relay position; in other words, ΦΦ is AB, BC, or CA.

[0077] U ΦΦ _rpThis is the phase-to-phase voltage calculated at the setting point; in other words, ΦΦ is AB, BC, or CA. In the two subsequent steps, the operating signal, suppression signal, and phasor are checked for two conditions as follows: U op_ΦΦ > U ΦΦ_restrain as well as U ΦΦ > U ΦΦ_rp .

[0078] You can press as follows Figure 20 The conditions are checked in the order shown, i.e., the second condition is checked after the first condition has been confirmed. Alternatively, the conditions can be checked in reverse order or simultaneously. During line protection, all the steps described above are performed continuously or periodically for each of the phase circuits under test. Once both conditions of the phase circuit under test are confirmed, a fault is detected, and a trip signal is triggered for the faulty phase-to-phase circuit.

[0079] Therefore, this approach is applicable to systems connected to variable renewable sources and offers improved reliability and security for different types of fault detection and protection. Consequently, this disclosure can significantly improve the reliability and security of existing distance protection solutions used in AC power systems connected to wind farms.

[0080] While various embodiments of this disclosure have been described above, it should be understood that these embodiments are presented by way of example only and not by way of limitation. Similarly, various figures may depict exemplary architectures or configurations provided to enable those skilled in the art to understand the exemplary features and functionality of this disclosure. However, those skilled in the art should understand that this disclosure is not limited to the illustrated exemplary architectures or configurations, but can be implemented using various alternative architectures and configurations. Furthermore, as those skilled in the art will understand, one or more features of one embodiment may be combined with one or more features of another embodiment described herein. Therefore, the breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above.

[0081] It should also be understood that any reference to elements in this document using names such as "first," "second," etc., generally does not restrict the number or order of those elements. Rather, these names may be used in this document as a convenient way to distinguish two or more elements or instances of elements. Therefore, referring to the first and second elements does not imply that only two elements can be used, or that the first element must somehow precede the second element.

[0082] Furthermore, those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, and symbols (e.g., possibly mentioned in the above description) can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0083] Those skilled in the art will further understand that any of the various illustrative logic blocks, units, processors, devices, circuits, methods, and functions described in conjunction with the aspects disclosed herein can be implemented by electronic hardware (e.g., digital implementation, analog implementation, or a combination of both), firmware, various forms of program or design code containing instructions (which may be referred to herein as "software" or "software unit" for convenience), or any combination of these technologies.

[0084] To clearly illustrate this interchangeability of hardware, firmware, and software, various illustrative components, blocks, units, circuits, and steps have been described above generally according to their functions. Whether such functionality is implemented as hardware, firmware, or software, or a combination of these technologies, depends on the specific application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in various ways for each specific application, but such implementation decisions will not lead to a departure from the scope of this disclosure. According to various embodiments, processors, devices, components, circuits, structures, machines, units, etc., can be configured to perform one or more functions described herein. The terms "configured to" or "configured for" as used herein with respect to a specified operation or function refer to processors, devices, components, circuits, structures, machines, units, etc., physically constructed, programmed, and / or arranged to perform the specified operation or function.

[0085] Furthermore, those skilled in the art will understand that the various illustrative methods, logic blocks, units, devices, components, and circuits described herein can be implemented within or executed by an integrated circuit (IC) that may include a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices or any combination thereof. Logic blocks, units, and circuits may further include antennas and / or transceivers for communication with various components within a network or device. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other suitable configuration to perform the functions described herein. If implemented in software, these functions may be stored as one or more instructions or code on a computer-readable medium. Therefore, the steps of the methods or algorithms disclosed herein can be implemented as software stored on a computer-readable medium.

[0086] Computer-readable media include computer storage media and communication media, including any medium capable of transferring computer programs or code from one place to another. Storage media can be any available medium that is accessible to a computer. By way of example and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer.

[0087] Additionally, memory or other storage devices and communication components may be employed in the embodiments of this disclosure. It should be understood that, for clarity, the above description has referenced various functional units and processors in the embodiments of this disclosure. However, it will be apparent that any suitable functional distribution among different functional units, processing logic elements, or domains may be used without departing from this disclosure. For example, functions illustrated to be performed by a separate processing logic element or controller may be performed by the same processing logic element or controller. Therefore, references to specific functional units are merely references to suitable means for providing the described functions and do not represent a strict logical or physical structure or organization.

[0088] Various modifications to the embodiments described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments shown herein, but is intended to be accorded the maximum scope consistent with the novel features and principles disclosed herein, as set forth in the appended claims.

Claims

1. A method for detecting faults in a transmission line, the method comprising: The real-time current and voltage signals of each tested phase circuit at the relay position at one end of the transmission line are obtained. The setting point voltage signal and the relay point voltage signal are determined based on the real-time current signal and the real-time voltage signal of each of the phase circuits under test. Determine the operating signal and suppression signal for each of the phase circuits under test. Determine whether the operating signal of a given phase circuit under test exceeds the suppression signal. Determine whether the phase voltage at the relay point of the measured phase circuit exceeds the phase voltage at the setting point, and A fault is detected if the operating signal exceeds the suppression signal and the relay phase voltage exceeds the setting phase voltage.

2. The method according to claim 1, wherein, The suppression signal is determined as the phasor amplitude of the relay point voltage signal for each measured phase circuit in the phasor domain.

3. The method according to claim 1 or 2, wherein, The operation signal is defined as the phasor amplitude of the difference between the setting point voltage signal and the relay point voltage signal for each measured phase circuit in the phasor domain.

4. The method according to any one of claims 1 to 3, wherein, The detected fault is an internal fault within the protected area.

5. The method according to any one of claims 1 to 4, further comprising generating a trip signal for the tested phase circuit in response to detecting the fault.

6. An apparatus for detecting faults in a transmission line, the apparatus comprising a processor configured to: Obtain the real-time current and voltage signals for each phase circuit under test. The setting point voltage signal and the relay point voltage signal are determined based on the real-time current signal and the real-time voltage signal of each measured phase circuit. Determine the phasor, operating signal, and suppression signal for each phase loop under test. Determine whether the operating signal of a certain phase circuit under test exceeds the suppression signal. Determine whether the phase voltage at the relay point of the measured phase circuit exceeds the phase voltage at the setting point, and A fault is detected if the operating signal exceeds the suppression signal and the relay phase voltage exceeds the setting phase voltage.

7. The device of claim 6, wherein the processor is further configured to determine the suppression signal as the phasor amplitude of the relay point voltage signal for each measured phase circuit.

8. The device according to claim 6 or 7, wherein the processor is further configured to determine the operating signal as the phasor amplitude of the difference between the setting point voltage signal and the relay point voltage signal for each measured phase circuit.

9. The device according to any one of claims 6 to 8, wherein, When the real-time voltage signal is a phase-to-ground loop voltage signal, the setting point voltage signal, the relay point voltage signal, the operating signal, and the suppression signal are phase-to-ground loop voltage signals, and the phasor is the phase-to-ground loop phasor of each measured phase loop, wherein the measured phase loop is a phase-to-ground pair, and When the real-time voltage signal is an interphase loop voltage signal, the setting point voltage signal, the relay point voltage signal, the operation signal, and the suppression signal are interphase loop voltage signals, and the phasor is the interphase loop phasor of each measured phase loop, wherein the measured phase loop is an interphase pair.

10. The device according to any one of claims 6 to 9, wherein, The detected fault is an internal fault within the protected area.

11. A system for determining faults in three-phase power transmission, the system comprising: The device according to claims 6 to 10, and Three-phase transmission line.

12. The system according to claim 11, wherein, The transmission lines connect variable renewable sources in the power grid, particularly wind farms.

13. The system according to claim 12, wherein, The signal corresponding to one phase is delayed by several cycles.

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