Frequency multiplier circuit for frequency multiplying an input signal and corresponding apparatus and method

Abstract

A frequency multiplier circuit comprising a resonant tank tunable to a harmonic of a differential mode, DM, injection voltage, the resonant tank comprising an inductance and a voltage controlled capacitance for tuning the resonant tank, an injection locking circuit arranged for receiving the DM injection voltage, the injection locking circuit comprising a transistor for providing the harmonic of the differential mode, DM, injection voltage to the resonant tank, a tuning circuit comprising an amplifier configured to receive a tuning voltage at a first input and a voltage at a second input at a center tap of the resonant tank, wherein the frequency multiplier circuit comprises a feedback path from an output of the amplifier to the center tap of the resonant tank.

Description

Technical Field

[0001] This disclosure generally relates to the field of frequency multiplier circuits, and more specifically to frequency multiplier circuits with center frequency tuning capability. Background Technology

[0002] In the context of wireless communication technology, pushing towards higher frequencies (particularly millimeter waves and the Asia-Pacific Hertz range) is a characteristic of anticipated 6G telecommunications standards. However, operating oscillators at these high frequencies can present challenges, potentially requiring innovative solutions. One technique employed in these scenarios is the use of frequency multipliers.

[0003] At these high frequencies, traditional methods for directly generating the local oscillator (LO) frequency may face certain obstacles. Existing techniques are finding it increasingly difficult to handle the complexity of oscillators operating in these domains. Frequency multipliers offer a workaround for this problem.

[0004] Instead of directly generating the LO frequency, the subharmonic oscillator is designed to operate at a portion of the LO frequency. The output of this subharmonic oscillator is then fed into a frequency multiplier circuit to generate the desired LO frequency.

[0005] Generating the required LO frequency directly or using a traditional frequency multiplier circuit may present some challenges.

[0006] Varactor diodes and switched capacitors, commonly used in frequency tuning circuits, are known to exhibit increased losses at 8AHz frequencies. These losses can lead to reduced efficiency and performance of the tuning circuit.

[0007] Amplifiers operating at high frequencies typically require significant amounts of energy. This high energy demand can present challenges in terms of power consumption, potentially leading to inefficiency and increased energy costs.

[0008] In the direct LO method, using a dedicated LO frequency synthesizer for each front end may be costly in terms of chip area and may be less flexible compared to multiplier solutions. Summary of the Invention

[0009] The purpose of this disclosure is to provide a frequency multiplier circuit capable of providing at least an increased tuning range. Additional objectives include related apparatus and methods.

[0010] In a first aspect of this disclosure, a frequency multiplier circuit is provided.

[0011] The frequency multiplier circuit includes a resonant circuit tunable to a harmonic of the differential-mode DM injection voltage, the resonant circuit including an inductor and a voltage-controlled capacitor for tuning the resonant circuit.

[0012] The frequency multiplier circuit also includes an injection lockout circuit arranged to receive the DM injection voltage, the injection lockout circuit including a transistor for providing the harmonic of the differential-mode DM injection voltage to the resonant circuit.

[0013] The frequency multiplier circuit also includes a tuning circuit containing an amplifier configured to receive a tuning voltage at a first input and a voltage at the center tap of the resonant circuit at a second input. The frequency multiplier circuit includes a feedback path from the amplifier output to the center tap of the resonant circuit.

[0014] The inventors have discovered that including a tuning circuit in conjunction with a feedback path can be beneficial. This allows for tuning the DC voltage of the resonant circuit. This will be further explained in the examples below in this disclosure.

[0015] In the example, as described above, the voltage-controlled capacitor is composed of the parasitic capacitances of the transistor present in the resonant circuit. These parasitic capacitances are, for example, the gate-drain capacitance and the gate-source capacitance.

[0016] As described above, the feedback path directs the voltage at the center tap of the resonant circuit to the tuning voltage applied to the amplifier. This voltage affects the parasitic capacitance of the transistors in the resonant circuit. Therefore, the tuning voltage controls the voltage-controlled capacitor of the resonant circuit, allowing the oscillation frequency of the resonant circuit to be tuned.

[0017] In the context of electronic circuits, a resonant circuit is a combination of one or more inductors and one or more capacitors arranged in a manner that produces a resonant circuit. This resonant circuit has a natural frequency, or resonant frequency, at which it exhibits maximum energy storage and transfer. The term "circuit" is used because the circuit can store and release energy in a manner similar to a loop storing and distributing liquid.

[0018] In a frequency multiplier circuit, a resonant circuit is used to generate a periodic waveform, such as a sinusoidal signal. Specifically, it can generate an radio frequency (RF) carrier. The combination of an inductor and a capacitor allows energy to oscillate between them, thus producing the desired waveform. This resonant frequency is determined by the values ​​of the inductor and capacitor.

[0019] This disclosure allows for voltage-controlled capacitors used to tune resonant circuits, i.e., for tuning resonant circuits in the frequency domain. The voltage used to control the capacitor is a DC voltage at the center tap of the resonant circuit. The tuning circuit, in conjunction with a feedback path, is arranged to control the voltage at the center tap of the resonant circuit to the tuning voltage applied to the amplifier of the tuning circuit. Therefore, this allows for frequency tuning of the frequency multiplier circuit.

[0020] The injection lockout circuit is configured to receive the differential-mode DM injection voltage. The injection voltage can be a signal originating from an oscillator operating at a subharmonic frequency.

[0021] The transistor contained in the injection-locked circuit generates harmonics of the DM injection voltage. Therefore, the subharmonic frequency (i.e., the fundamental frequency) originating from the oscillator is injected into the transistor, which also injects fundamental harmonic signal energy due to the transistor's nonlinear behavior. The fundamental frequency (i.e., the subharmonic frequency originating from the oscillator) and its harmonic frequencies are thus generated and provided to the resonant circuit. The resonant circuit is tuned, for example, to the third or fifth harmonic frequency. For example, if the resonant circuit is tuned to the third harmonic, a third harmonic is achieved. If the resonant circuit is tuned to the fifth harmonic, a fifth harmonic is achieved.

[0022] Note that the harmonics are not limited to 3 or 5. In this disclosure, the resonant circuit is tuned to an output frequency, which can be any harmonic frequency corresponding to the fundamental frequency derived from the oscillator.

[0023] Therefore, introducing harmonic signals from a transistor into a resonant circuit induces a resonance effect, which helps generate frequency multiplication. This frequency multiplication is an aspect of the overall circuit operation, allowing it to produce an output signal with a frequency that is a multiple of the original input signal.

[0024] Transistors, particularly field-effect transistors (FETs) or bipolar junction transistors (BJTs), are used to effectively amplify and manipulate electrical signals. These transistors function by nonlinearly amplifying the input signal, thereby generating harmonics. Nonlinear devices such as transistors generate harmonics due to distortion introduced during signal amplification. The resonant circuit is then “tuned” to the specific harmonic content of the input signal.

[0025] In the example, the feedback path further includes: - A transistor, wherein the output of the amplifier is connected to the control terminal of the transistor, and wherein the output of the transistor is connected to the injection lock-in circuit.

[0026] In another example, the resonant circuit includes: - Two inductors connected in series to provide the inductance, wherein the center tap is between the two inductors connected in series.

[0027] Two inductors connected in series can be implemented in a semiconductor material. The inductors can be separated from each other and mirrored, with a center tap between them. Alternatively, a single inductor can be implemented, where the single inductor has a center tap.

[0028] For two inductors connected in series, the point between them is called the center point or center tap. This center point serves as the reference point in the circuit. This disclosure defines the voltage at this point that is directed to the tuning voltage applied to the amplifier.

[0029] Similarly, in the case of a single inductor with a center tap, this means that the inductor has a winding connected at the center point. This center tap can also serve as a reference point in the circuit.

[0030] In another example, the resonant circuit further includes: - At least one fixed capacitor, such that the resonant circuit is tuned to the harmonic of the differential mode DM injection voltage using the inductor, the voltage-controlled capacitor and the fixed capacitor.

[0031] As described above, the resonant circuit has a voltage-controlled capacitor for controlling / tuning the resonant frequency of the resonant circuit. This voltage-controlled capacitor can be a parasitic capacitance of a transistor present in the resonant circuit, such as a field-effect transistor (FET) present in the resonant circuit.

[0032] The behavior of a FET depends heavily on the voltage applied to its gate terminal, especially the parasitic capacitances associated with the FET. FETs can exhibit three types of parasitic capacitances: gate-source capacitance Cgs, gate-drain capacitance Cgd, and drain-source capacitance Cds, all of which are generated by the physical structure of the transistor. When a voltage is applied to the gate, it generates an electric field that modifies the charge distribution within the transistor.

[0033] The gate voltage affects the width of the depletion region between the semiconductor material and the gate terminal. This modulation in the depletion region, in turn, affects the value of the parasitic capacitance. Specifically, Cgs and Cgd are voltage-dependent, meaning their amplitudes change with the gate voltage. This voltage-controlled capacitance can be important in resonant circuits where FETs operate at high frequencies.

[0034] An amplifier is used in conjunction with a feedback path to direct one or more gate voltages to a tuning voltage.

[0035] In addition to the above, at least one fixed capacitor can be provided in the resonant circuit.

[0036] As mentioned above, in FET-based resonant circuits, the inherent parasitic capacitances of the FET, such as Cgs and Cgd, can be used as voltage-controlled capacitors. This characteristic can become significant in high-frequency applications where the resonant behavior of the resonant circuit is crucial. However, to fine-tune and stabilize this resonant behavior, an additional fixed capacitor can be introduced into the resonant circuit.

[0037] Including a fixed capacitor serves several purposes. First, by selecting a value for the fixed capacitor to complement the voltage-controlled capacitor (VDC) which compensates for the parasitic capacitance of the FET, precise tuning of the resonant frequency is possible. This ensures that the resonant frequency can be adjusted as needed. Second, the fixed capacitor may contribute to circuit stability, compensating for variations in the FET's parasitic capacitance caused by factors such as manufacturing tolerances or temperature changes. This stability promotes consistent performance. The combination of the VDC and the fixed capacitor can further improve the Q factor of the resonant circuit, providing a sharper and more defined resonance.

[0038] In another example, the injection locking circuit includes: - Two injection-locked transistors are arranged to receive the DM injection voltage at the gate of the respective two injection-locked transistors, wherein the output of the first of the two injection-locked transistors is connected to a first terminal of the resonant circuit, and wherein the output of the second of the two injection-locked transistors is connected to a second terminal of the resonant circuit opposite to the first terminal.

[0039] For example, the transistor mentioned above can be a FET or a BJT.

[0040] In another example, the resonant circuit includes: - Two field-effect transistors (FETs), wherein the sources of the two transistors are connected to each other, wherein the gate of the first FET is connected to the drain of the second FET, and wherein the gate of the second FET is connected to the drain of the first FET. And wherein the drain of the first of the two FETs is connected to the first terminal of the inductor, And the drain of the second of the two FETs is connected to the second terminal of the inductor.

[0041] As an alternative, the resonant circuit includes: - Two bipolar junction transistors (BJTs), wherein the emitter terminals of the two BJTs are connected to each other, wherein the base terminal of the first of the two BJTs is connected to the collector terminal of the second of the two BJTs, and wherein the base terminal of the second of the two BJTs is connected to the collector terminal of the first of the two BJTs. And wherein the collector terminal of the first of the two BJTs is connected to the first terminal of the inductor, And wherein the collector terminal of the second BJT of the two BJTs is connected to the second end of the inductor.

[0042] In a second aspect of this disclosure, a signal generator is provided, comprising a frequency multiplier circuit according to any of the foregoing examples, and including control circuitry for controlling the tuning voltage, the control circuitry comprising: - A mixer is arranged to mix the differential-mode DM injection voltage with the output of the resonant circuit; A control mechanism is arranged to detect the power in the output of the mixer and to control the tuning voltage based on the detected power.

[0043] Note that the advantages explained with reference to the first aspect of this disclosure (i.e., the frequency multiplier circuit) also apply to the second aspect of this disclosure, i.e., the signal generator.

[0044] The basic idea is to tune the resonant frequency of the circuit to a multiple of the frequency of the injected DM voltage. For example, the resonant frequency of the resonant circuit is three or five times the frequency of the injected DM voltage.

[0045] A mixer mixes one or both of the differential-mode DM injection voltages with the output of a resonant circuit. The mixer output contains the mixed frequency, including the sum and difference of the original frequencies. In the above case, where the frequency of the injected DM voltage is approximately one-third of the frequency output of the frequency multiplier circuit, the output will include the sum and difference frequency components of the two input signals, as well as the original frequency itself.

[0046] If the resonant circuit is perfectly tuned, it means there is little or no detectable power around DC. If power is detected near DC, it means the resonant circuit is not tuned to its resonant frequency perfectly.

[0047] The control mechanism can control the tuning voltage based on the detected power (e.g., detected power near DC).

[0048] In the example, the control mechanism further includes: A low-pass filter is arranged to filter the output of the mixer before the power is detected. In another example, the mixer includes: - An XOR gate, wherein the first input of the XOR gate is connected to one of the two inputs for the differential-mode DM injection voltage, and wherein the second input of the XOR gate is connected to one of the two outputs of the resonant circuit.

[0049] If power is detected at both inputs of the XOR gate, the output of the XOR gate is zero. If power is detected at only one input of the XOR gate, the output of the XOR gate is 1.

[0050] In a third aspect of this disclosure, a phase-locked loop is provided, comprising a signal generator according to any one of the foregoing examples and / or a frequency multiplier circuit according to any one of the foregoing examples.

[0051] In a fourth aspect, an electronic device is provided, comprising a signal generator according to any one of the foregoing examples and / or a frequency multiplier circuit according to any one of the foregoing examples.

[0052] For example, electronic devices can be communication devices.

[0053] In another example, the communication equipment is a user equipment (UE) for a cellular communication system or a radio base station for a cellular communication system, such as a gNodeB or eNodeB.

[0054] In another aspect of this disclosure, a method for operating a frequency multiplier circuit according to any one of the foregoing examples is provided, wherein the method comprises the following steps: - The injection-locked circuit receives the DM injection voltage and provides the harmonic of the differential-mode DM injection voltage to the resonant circuit; The amplifier receives the tuning voltage at the first input and the voltage at the center tap of the resonant circuit at the second input. The frequency multiplier circuit includes a feedback path from the amplifier output to the center tap of the resonant circuit.

[0055] In another example, the feedback path also includes a transistor, and the method further includes the following steps: The output of the amplifier is received by the transistor.

[0056] In another example, the resonant circuit includes two series-connected inductors for providing the inductance, wherein the center tap is between the two series-connected inductors.

[0057] In yet another example of this disclosure, a method for operating a signal generator according to any one of the foregoing examples is provided, wherein the method includes the following steps: - The differential-mode DM injection voltage is mixed with the output of the resonant circuit by the mixer; The control mechanism detects the power in the output of the mixer, and The control mechanism controls the tuning voltage based on the detected power.

[0058] In another example, the control mechanism further includes a low-pass filter, and the method further includes the following steps: - Before the power is detected, the output of the mixer is filtered by the low-pass filter.

[0059] In yet another example, the mixer includes an XOR gate, wherein a first input of the XOR gate is connected to one of the two inputs for the differential-mode DM injection voltage, and wherein a second input of the XOR gate is connected to one of the two outputs of the resonant circuit.

[0060] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash and a second reference numeral after the reference numeral, the second reference numeral used to distinguish similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the second reference numeral.

[0061] The foregoing and other aspects of this disclosure will become apparent and illustrated by referring to the examples described below. Attached Figure Description

[0062] Figure 1 An adaptive antenna system (AAS) arrangement with a local oscillator synthesizer is disclosed, which also includes local phase shift functionality for each front end; Figure 2 An AAS arrangement is disclosed, wherein the center frequency is fed to a plurality of phase shifters, and each phase shifter then drives a multiplier M circuit to feed to the front end; Figure 3 An implementation of a frequency multiplier circuit according to this disclosure is disclosed; Figure 4 Examples of signal generators according to this disclosure are disclosed; Figure 5 A flowchart based on this disclosure is disclosed; Figure 6 Examples of electronic devices according to this disclosure are disclosed; Figure 7a and 7b The tuning ranges corresponding to the third and fifth harmonics of the injected fundamental frequency are disclosed. Detailed Implementation

[0063] Note that in the description of the accompanying drawings, the same reference numerals indicate the same or similar components that perform the same or substantially similar functions.

[0064] A more detailed description is provided with reference to specific examples, some of which are illustrated in the accompanying drawings, to enable a more detailed understanding of the features of this disclosure. Note that the drawings show only typical examples and should therefore not be construed as limiting the scope of the claims. The accompanying drawings are provided for ease of understanding and are therefore not necessarily drawn to scale. The advantages of the claimed subject matter will become apparent to those skilled in the art when the specification is read in conjunction with the accompanying drawings.

[0065] The above and following descriptions provide only one or more preferred exemplary embodiments and are not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of one or more preferred exemplary embodiments will provide those skilled in the art with a description of preferred exemplary embodiments for implementing this disclosure. It should be understood that various changes may be made to the function and arrangement of elements, including combinations of features from different embodiments, without departing from the scope of this disclosure.

[0066] Unless the context explicitly requires it, throughout the specification and claims, the words “comprising,” “including,” etc., should be interpreted as encompassing, not exclusive or exhaustive; that is, in the sense of “including, but not limited to.” As used herein, the terms “connection,” “coupling,” or any variation thereof mean any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements can be physical, logical, electromagnetic, or a combination thereof. Furthermore, when used in this application, the words “in this document,” “above,” “below,” and similar terms refer to the entire application and not any particular part of it. Where the context permits, singular or plural words used in the detailed description may also include the plural or singular, respectively. The word “or,” when referring to a list of two or more items, covers all of the following interpretations: any item in the list, all items in the list, and any combination of items in the list.

[0067] Figure 1 An adaptive antenna system (AAS) arrangement with a local oscillator synthesizer is disclosed, which also includes local phase shift functionality for each front end.

[0068] In antenna array systems, a local oscillator path is typically chosen to enhance phase control functionality. Figure 1 An example implementation is shown, in which each front end has a local phase-locked loop (PLL) system with phase-shifting capability, followed by a frequency multiplier.

[0069] This solution can be expensive in terms of chip area, as each local PLL would occupy a significant area. An attractive solution would have a central PLL generate continuous waves for all front-ends. This... Figure 2 As shown in the image.

[0070] Phase control functionality is achieved by adding a phase shifter before or after the frequency multiplier. Figure 2 The diagram shows a phase shifter connected to the PLL output. To compensate for the losses in the phase shifter, buffers and amplifiers are typically inserted to boost the signal level. The advantage of phase shifting before multiplication is that, since the signals are multiplied at frequencies, applying the phase shift at a lower frequency reduces the total tuning range to one-M, where M is the harmonic ratio.

[0071] This disclosure relates to a frequency multiplier circuit that can multiply a frequency input signal by, for example, 3 or 5, depending on whether the input signal frequency is a third or fifth harmonic. Figure 3 The specific implementation is shown in the figure.

[0072] This is achieved by injecting a nonlinear signal containing the fundamental frequency and harmonic frequencies into a resonant circuit tuned to a specific output frequency.

[0073] An injection lockout circuit is provided to receive the differential-mode DM injection voltage. In this specific scenario, the injection lockout circuit consists of devices M4 and M5. Therefore, injection is performed using differential signals via devices M4 and M5. The devices can be biased to allow for higher harmonic amplitudes, which may be desirable. The output of the injection device is the current directly injected into the resonant circuit.

[0074] Resonant circuits typically include an inductor connected in parallel or series with an adjustable capacitor (i.e., a varactor diode) or a bank of switched capacitors. Such capacitors may be difficult to use at high frequencies (e.g., above 100 GHz). This is because varactor diodes and switches have very low Q factors, resulting in low output amplitudes. Therefore, high power dissipation is required to maintain the oscillation of the output frequency.

[0075] A resonant circuit is provided that is tunable to the harmonics of the differential-mode DM injection voltage, wherein the resonant circuit includes an inductor and a voltage-controlled capacitor for tuning the resonant circuit.

[0076] exist Figure 3 In the example shown, the resonant circuit includes inductors LT1 and LT2, and (among other things) the gate-drain capacitances of field-effect transistors M2 and M3.

[0077] A tuning circuit is provided for tuning the resonant frequency of a resonant circuit. The tuning circuit includes an amplifier, shown as an operational amplifier (OPAMP). The amplifier is configured to receive a tuning voltage V at its first input. tuneIt also receives the voltage at the center tap of the resonant circuit at the second input. The center tap of the resonant circuit is located between inductors LT1 and LT2.

[0078] The frequency multiplier circuit also includes a feedback path from the amplifier output to the center tap of the resonant circuit. In this particular case, the feedback includes FETs M6, M4, and M5, as well as inductors LT1 and LT2.

[0079] Here, the amplifier's output is connected to the control terminal of FET M6, i.e., the gate terminal of FET M6. The output of FET M6 is connected to the injection-locked circuit, i.e., connected to FETs M4 and M5.

[0080] exist Figure 3 In the example shown, the varactor diode can be avoided by applying this feedback path, which measures the center tap voltage of the resonator inductors LT1 and LT2, i.e., the multiplier common-mode VCM. This voltage is then compared with a predetermined tuning voltage (i.e., V). tune The comparison is performed, and the output is fed to the gate of M6, forcing the differential DC voltage to become close to V. tune .

[0081] Changing this voltage also alters the voltage-controlled capacitors in the active device, primarily the field-effect transistors (FETs) M2, M3, M4, and M5. These capacitors include the gate-drain capacitance Cgd and the gate-source capacitance Cgs. This results in a change in the oscillator's operating frequency without requiring a varactor diode.

[0082] The advantage of using a feedback section is that no resistors are needed in the signal path. Excessive resistance in that path would cause AM-FM conversion, which directly increases the phase noise level.

[0083] Figure 4 Examples of signal generators according to this disclosure are disclosed.

[0084] The goal is to detect whether the frequency multiplier circuit is locked to the injected signal. This would allow for improvements in the locking range and consideration of different process corners.

[0085] To demonstrate the possibility of lock detection using a simple mixer function, the inputs and outputs of a frequency multiplier circuit (multiplier core) are connected to an XOR gate. The XOR gate is treated as a mixer.

[0086] The low-pass filtered XOR mixer output can include a frequency component corresponding to the frequency difference between the injected signal and the multiplier subharmonic. The mixer output is connected to a low-pass filter (LPF) for signal filtering. The presence of an RF signal at the mixer output can be determined using an RF power detector (PowDet) compared to a threshold level—and thus, whether the frequency multiplier circuit is locked.

[0087] The comparison with the threshold level is considered as a comparator module. The output of the comparator module is provided to the finite state machine (FSM). The tuning voltage V is then generated by the digital-to-analog converter (D / A). tune This digital-to-analog converter converts the digital output of the FSM into an analog tuned voltage V. tune .

[0088] Because the frequency multiplier circuit has a large lock-in range, there is a lower limit to the mixer output frequency, which simplifies the search for frequency components. The proposed algorithmic solution still involves extensive searching to ensure that the selected tuning voltage results in the center of the tuning range.

[0089] To avoid the ambiguity of not detecting changes when the multiplier is not running (i.e., when it is not generating an output signal), another power detector can be used to detect the power, and then its output can be monitored to detect changes in its output voltage. In this case, the locking algorithm can begin.

[0090] As an alternative to the aforementioned startup algorithm, an A / D converter can be used to digitize the mixer output, and a correlator can be used to identify the frequency content in the digital domain. The advantage of this approach is that it provides more information about the actual frequency deviation without locking the multiplier.

[0091] Figure 5 A flowchart based on this disclosure is provided.

[0092] First, the phased array system can be configured to include a central PLL that drives a remote frequency multiplier circuit. An initial tuning voltage can be applied to the frequency multiplier circuit. The inputs and outputs of the frequency multiplier circuit can be mixed. The radio frequency (RF) power can then be detected at the output of the frequency multiplier circuit.

[0093] If RF power is detected, this indicates that the frequency multiplier circuit is not tuned, i.e., out of range. If no RF power is detected, this indicates that the frequency multiplier circuit is tuned, i.e., within range. This process can be performed over the entire tuning range, adjusting the tuning voltage each time. The tuning voltage is applied at the center of the locked range.

[0094] Figure 6 Examples of electronic devices according to this disclosure are disclosed.

[0095] Electronic device 42 includes an input terminal 44, an input device 43, an output terminal 46, and an output device 45.

[0096] The electronic device may also include a processor 47 connected to the memory 48.

[0097] In addition to the above, based on any of the examples provided above, the electronic device may include a frequency multiplier circuit and / or a signal generator 49.

[0098] Electronic devices can be communication devices, such as user equipment (UE) or base stations, such as eNodeB or gNodeB.

[0099] Already in 22 nm technology Figure 3 The circuit implementation was simulated. Parasitic models were included for the MOS devices and passive components to approximate the results with respect to the layout circuit. A 5 fF capacitor load was also added to the output to account for the output buffer. Figure 7a and 7b The tuning ranges corresponding to the third and fifth harmonics of the injected fundamental frequency are disclosed. For Figure 7a and Figure 7b Under the same operating conditions, the circuit output frequency is concentrated around 127 GHz. The tuning range is defined here as when the circuit produces an amplitude of at least 100 mV peak.

[0100] Horizontal axes 103 and 303 show frequencies in GHz, and vertical axes 102 and 302 show the third harmonic (GHz). Figure 7a The amplitude in mV for the fifth harmonic and the fifth harmonic (Figure 8b).

[0101] These graphs illustrate when the output frequency is one-third ( Figure 7a ) and one-fifth of the output frequency ( Figure 7b The frequency tuning range when injecting differential signals is 101 and 301. When injected at one-third of the output frequency under different tuning voltages, the frequency range becomes, for example, 112.5 GHz to 142.5 GHz, where the tuning range is 23%.

[0102] When one-fifth of the output frequency is applied, the tuning range becomes, for example, 117.5 GHz to 137.5 GHz, reduced to about 16% due to the decreased injection efficiency.

[0103] It should be noted that the above examples are illustrative rather than limiting of the idea, and those skilled in the art will be able to devise many alternative examples without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude a plurality, and a single processor or other unit may perform the functions of several units recited in the claims.

[0104] Any reference numerals in the claims should not be construed as limiting their scope.

Claims

1. A frequency multiplier circuit, comprising: - Resonant circuits (LT1, LT2, M2, M3) are tunable to the harmonics of the differential mode DM injection voltage, and the resonant circuits (LT1, LT2, M2, M3) include inductors and voltage-controlled capacitors for tuning the resonant circuits (LT1, LT2, M2, M3). - An injection lockout circuit (M4, M5) is arranged to receive the DM injection voltage, the injection lockout circuit (M4, M5) including a transistor for providing the harmonic of the differential mode DM injection voltage to the resonant circuit (LT1, LT2, M2, M3); - Includes a tuning circuit for an amplifier configured to receive a tuning voltage at a first input and a voltage at the center tap of the resonant circuit (LT1, LT2, M2, M3) at a second input. The frequency multiplier circuit includes a feedback path (M6) from the output of the amplifier to the center tap of the resonant circuit (LT1, LT2, M2, M3).

2. The frequency multiplier circuit according to claim 1, wherein, The feedback path also includes: - Transistor (M6), wherein the output of the amplifier is connected to the control terminal of the transistor, and wherein the output of the transistor is connected to the injection lock-in circuit (M4 M5).

3. The frequency multiplier circuit according to any one of the preceding claims, wherein, The resonant circuit (LT1, LT2, M2, M3) includes: - Two inductors connected in series to provide the inductance, wherein the center tap is between the two inductors connected in series.

4. The frequency multiplier circuit according to any one of the preceding claims, wherein, The resonant circuit (LT1, LT2, M2, M3) also includes: - At least one fixed capacitor, such that the resonant circuit (LT1, LT2, M2, M3) is tuned to the harmonic of the differential mode DM injection voltage using the inductor, the voltage-controlled capacitor and the fixed capacitor.

5. The frequency multiplier circuit according to any one of the preceding claims, wherein, The injection locking circuit (M4, M5) includes: - Two injection-locked transistors are arranged to receive the DM injection voltage at the gate of the respective two injection-locked transistors, wherein the output of the first of the two injection-locked transistors is connected to the first terminal of the resonant circuit (LT1, LT2, M2, M3), and the output of the second of the two injection-locked transistors is connected to the second terminal of the resonant circuit (LT1, LT2, M2, M3) opposite to the first terminal.

6. The frequency multiplier circuit according to any one of the preceding claims, wherein, The resonant circuit (LT1, LT2, M2, M3) includes: - Two field-effect transistors (FETs) (M2, M3), wherein the drains of the two transistors are connected to each other, wherein the gate of the first FET is connected to the source of the second FET, and wherein the gate of the second FET is connected to the source of the first FET. And wherein the source of the first of the two FETs is connected to the first terminal of the inductor, And wherein the source of the second of the two FETs is connected to the second terminal of the inductor.

7. The frequency multiplier circuit according to any one of claims 1-5, wherein, The resonant circuit (LT1, LT2, M2, M3) includes: - Two bipolar junction transistors (BJTs), wherein the emitter terminals of the two BJTs are connected to each other, wherein the base terminal of the first of the two BJTs is connected to the collector terminal of the second of the two BJTs, and wherein the base terminal of the second of the two BJTs is connected to the collector terminal of the first of the two BJTs. And wherein the collector terminal of the first of the two BJTs is connected to the first terminal of the inductor, And wherein the collector terminal of the second BJT of the two BJTs is connected to the second end of the inductor.

8. A signal generator comprising a frequency multiplier circuit according to any one of the preceding claims, and comprising control circuitry for controlling the tuning voltage, the control circuitry comprising: - A mixer is arranged to mix the differential-mode DM injection voltage with the output of the resonant circuit (LT1, LT2, M2, M3); A control mechanism is arranged to detect the power in the output of the mixer and to control the tuning voltage based on the detected power.

9. The signal generator according to claim 8, wherein, The control mechanism also includes: A low-pass filter (LPF) is arranged to filter the output of the mixer before the power is detected.

10. The signal generator according to any one of claims 8-9, wherein, The mixer includes: - An XOR gate, wherein the first input of the XOR gate is connected to one of the two inputs for the differential mode DM injection voltage, and wherein the second input of the XOR gate is connected to one of the two outputs of the resonant circuit (LT1, LT2, M2, M3).

11. A phase-locked loop, comprising a signal generator according to any one of claims 8-10 and / or a frequency multiplier circuit according to any one of claims 1-7.

12. An electronic device comprising a signal generator according to any one of claims 8-10 and / or a frequency multiplier circuit according to any one of claims 1-7.

13. The electronic device according to claim 12, wherein, The electronic device is a communication device.

14. The electronic device of claim 13, wherein, The communication device is a user equipment (UE) used in a cellular communication system.

15. The electronic device according to claim 12, wherein, The communication equipment is a radio base station for a cellular communication system.

16. A method of operating a frequency multiplier circuit according to any one of claims 1-7, wherein the method comprises the following steps: - The injection-locked circuit receives the DM injection voltage and provides the harmonics of the differential-mode DM injection voltage to the resonant circuit (LT1, LT2, M2, M3); The amplifier of the tuning circuit receives the tuning voltage at the first input and the voltage of the center tap of the resonant circuit (LT1, LT2, M2, M3) at the second input. The frequency multiplier circuit includes a feedback path from the output of the amplifier to the center tap of the resonant circuit (LT1, LT2, M2, M3).

17. The method of claim 16, wherein, The feedback path further includes a transistor, and the method further includes the following steps: The output of the amplifier is received by the transistor.

18. The method according to any one of claims 16-17, wherein, The resonant circuit (LT1, LT2, M2, M3) includes two inductors connected in series for providing the inductance, wherein the center tap is located between the two inductors connected in series.

19. A method of operating a signal generator according to any one of claims 8-11, wherein the method comprises the following steps: - The differential mode DM injection voltage is mixed with the output of the resonant circuit (LT1, LT2, M2, M3) by the mixer; The control mechanism detects the power in the output of the mixer, and The control mechanism controls the tuning voltage based on the detected power.

20. The method of claim 19, wherein, The control mechanism further includes a low-pass filter, and the method further includes the following steps: - Before the power is detected, the output of the mixer is filtered by the low-pass filter.

21. The method according to any one of claims 19-20, wherein, The mixer includes an XOR gate, wherein a first input of the XOR gate is connected to one of two inputs for the differential-mode DM injection voltage, and wherein a second input of the XOR gate is connected to one of the two outputs of the resonant circuit (LT1, LT2, M2, M3).

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