Programmable delay line circuit with single delay array and real-time calibration

Abstract

A programmable delay line circuit is provided that includes a single ring oscillator that is continuously calibrated by calibration logic circuitry. A clock edge sampler samples an input clock in response to a plurality of oscillator output signals from the ring oscillator to form a corresponding plurality of data output signals. A clock edge voter processes the data output signals to identify a first one of the oscillator output signals in which an edge transition of the input clock is sampled. Based on a desired delay, a decoder selects a second one of the oscillator output signals for use in generating an output clock signal.

Description

[0001] Cross-referencing

[0002] This application claims priority and benefit to U.S. nonprovisional patent application No. 18 / 440,726, filed February 13, 2024, the entire contents of which are incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] This application relates generally to delay line circuits, and more specifically to programmable delay line circuits with a single delay array and real-time calibration. Background Technology

[0004] Programmable delay line circuits have a wide variety of applications. For example, dynamic random access memory (DRAM) controllers typically include programmable delay line circuits. By adjusting the delay from the programmable delay line circuit, the DRAM controller can delay the data gating relative to the memory clock signal to center the data gating at the data eye. Programmable delay line circuits are also used in delay-locked loop circuits. Although programmable delay line circuits are therefore very useful, they are subject to process, voltage, and temperature variations that affect their accuracy. Summary of the Invention

[0005] According to one aspect of this disclosure, a delay line circuit for delaying an input clock signal is provided, the delay line circuit comprising: a ring oscillator including a plurality of delay units, the ring oscillator being configured to generate an oscillator output signal; a clock edge sampler configured to generate a data output signal, the clock edge sampler including a plurality of flip-flops corresponding to the plurality of delay units on a one-to-one basis, each flip-flop being configured to latch the input clock signal in response to an oscillator output signal from the corresponding delay unit to generate a corresponding data output signal; and a delay output decoder configured to process the data output signal to select a first oscillator output signal from the oscillator output signals for forming an output clock signal.

[0006] According to another aspect of this disclosure, a method is provided, comprising: generating a corresponding oscillator output signal in each of a plurality of delay units arranged to form a ring oscillator; sampling an input clock signal in response to each oscillator output signal to form a plurality of data output signals; processing the data output signals to identify a first oscillator output signal among the oscillator output signals as a signal of an edge transition sampled to the input clock signal; and a second oscillator output signal among the output oscillator output signals as an output clock signal.

[0007] Finally, according to another aspect of this disclosure, a delay line circuit is provided, comprising: a single ring oscillator configured to generate a plurality of oscillator output signals; a clock edge sampler configured to sample an input clock signal based on the plurality of oscillator output signals to provide a plurality of data output signals; and a decoder configured to select one of the oscillator output signals as an output clock signal in response to processing the plurality of data output signals.

[0008] These and other advantageous features can be better understood through the detailed description below. Attached Figure Description

[0009] Figure 1 An example of a programmable delay line circuit according to one aspect of the present disclosure is shown.

[0010] Figure 2 This is a diagram of some waveforms from a programmable delay line circuit according to one aspect of this disclosure.

[0011] Figure 3 It is a truth table of a clock edge voter according to one aspect of this disclosure.

[0012] Figure 4 Examples of methods for using according to one aspect of this disclosure are illustrated. Figure 1 An example delay circuit of a ring oscillator for a programmable delay line circuit.

[0013] Figure 5 This is a flowchart of an operation method of a programmable delay line circuit according to one aspect of this disclosure.

[0014] Figure 6 Some example electronic systems including programmable delay line circuits according to one aspect of this disclosure are illustrated.

[0015] The specific embodiments of this disclosure and its advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. Detailed Implementation

[0016] Various methods have been developed to address process, voltage, and temperature variations that affect the accuracy of delays from programmable delay line circuits. In one approach, the programmable delay line circuit may include a master-slave pair of delay arrays. The master delay array in this pair is continuously calibrated relative to a reference clock signal. The slave delay array in this pair generates a delayed output signal within the delay-locked loop based on the PLL output signal from a phase-locked loop (PLL) that includes the master delay array. Although the delayed output signal is thus continuously calibrated, there is an uncalibrable static delay error between the master and slave delay arrays. Furthermore, the delayed output signal undergoes a relatively long settling time, thus hindering instantaneous delay tracking capabilities. Analog designs of PLLs are also not easily ported from one process node to another.

[0017] In another architecture, two delay arrays alternate between delay and calibration modes, such that when one delay array is in calibration mode, the remaining delay array is in delay mode to drive the delayed output signal. However, switching between the two delay arrays to drive the delayed output signal introduces delay uncertainty. Furthermore, the ability to track voltage and temperature variations during calibration may be limited.

[0018] A calibrated programmable delay line circuit is provided that uses a single delay array (also referred to herein as a ring oscillator), thus avoiding mismatch between delay arrays. Furthermore, calibration is always on, allowing easy tracking of process, voltage, and temperature variations. Additionally, the delayed output signal is derived from the initial clock cycle, thus avoiding any prolonged settling time. Figure 1 An example programmable delay line circuit 100 is shown. A glitch-free ring oscillator 105 includes n (e.g., 4, 8, 16, etc.) delay circuits arranged in a ring, from the zeroth delay circuit to the (n-1)th delay circuit. Each delay circuit is also referred to herein as a delay unit. As is known in the art of ring oscillators, each delay circuit is used to delay the output signal from the preceding delay circuit in the ring oscillator 105. For example, the zeroth delay circuit delays the output signal from the (n-1)th delay circuit to drive the delayed output signal to a first delay circuit. The first delay circuit then drives the delayed output signal to a second delay circuit (not illustrated). In this way, each subsequent delay circuit in the ring oscillator 105 delays the output signal from the preceding delay circuit. For example, the (n-1)th delay circuit delays the output signal from the (n-2)th delay circuit.

[0019] The output signal from each delay circuit is also referred to herein as an oscillator output signal. Therefore, the ring oscillator 105 generates n oscillator output signals, all sharing the same frequency, but each signal having a unique phase. Since each oscillator output signal has the same frequency, all oscillator output signals have the same oscillation period. The number n of delay circuits determines the corresponding number n of phases of the oscillator clock signal from the ring oscillator 105. For example, the zeroth delay circuit can be considered as generating a corresponding oscillator output signal (Ph) with a clock edge transition synchronized with the start of the oscillation period (a rising edge from ground to the supply voltage or a falling edge from the supply voltage to ground). <0> Then, the first delay circuit will generate the corresponding oscillation output signal (Ph). <1> The corresponding oscillating output signal changes at the 1 / nth moment of the oscillation period after the start of the oscillation period. More generally, the i-th delay circuit generates the corresponding oscillating output signal, which changes at the i / nth moment of the oscillation period after the start of the oscillation period, where i represents the integer index of the delay circuit in the progressive sequence from 0 to n-1.

[0020] The n oscillation output signals from the n delay circuits in the ring oscillator 105 are sampled by the clock edge sampler 110 at the edge transitions of the input clock signal (clk_in), e.g., the rising edge from ground to the power supply voltage. Each oscillation output signal is sampled by a corresponding memory element (such as a data (D) type flip-flop). For example, the zeroth flip-flop (FF) samples the zeroth oscillation output signal Ph from the zeroth delay circuit. <0> Sampling is performed. Similarly, the first flip-flop responds to the first oscillation output signal Ph from the first delay circuit. <1> Sampling is performed. In the same manner, the (n-2)th flip-flop outputs the (n-2)th oscillation signal Ph from the (n-2)th delay circuit. <n-2>Sampling is then performed. Finally, the (n-1)th flip-flop samples the (n-1)th oscillation output signal from the (n-1)th delay circuit.

[0021] Each of the n flip-flops in the clock edge sampler 110 receives an input clock signal at its data (D) input and is clocked by a corresponding oscillation output signal. Therefore, the zeroth flip-flop will output the zeroth oscillation signal Ph. <0> The input clock signal is registered at the rising edge of the zero flip-flop. Therefore, the data output signal Dout from the zero flip-flop... <0> The zeroth oscillation output signal Ph <0> The rising edge of the input clock signal captures the binary value (0 or 1). Similarly, the first flip-flop outputs the first oscillation signal Ph. <1> The input clock signal is registered at the rising edge of the first flip-flop. Therefore, the data output signal Dout from the first flip-flop... <1> First oscillation output signal Ph <1> The binary value of the input clock signal is captured at the rising edge. The (n-2)th flip-flop oscillates at the (n-2)th edge to output the signal Ph. <n-2>The input clock signal is registered at the rising edge of the (n-2)th flip-flop. Therefore, the data output signal Dout from the (n-2)th flip-flop... <n-2>The output signal Ph is generated during the (n-2)th oscillation. <n-2>The binary value of the input clock signal is captured at the rising edge. Finally, the (n-1)th flip-flop oscillates at the (n-1)th edge to output the signal Ph. <n-1>The input clock signal is registered at the rising edge of the (n-1)th flip-flop. Therefore, the data output signal Dout from the (n-1)th flip-flop... <n-1>The output signal Ph is generated during the (n-1)th oscillation. <n-1>The binary value of the input clock signal is captured at the rising edge.

[0022] After the rising edge of the input clock signal, the input clock signal is held in a state charged to the supply voltage according to the duty cycle of the input clock signal. Depending on the duty cycle, a corresponding number of data output signals will have a binary one value after the rising edge of the input clock signal. However, since the clock edge sampling of the n flip-flops in the clock edge sampler 110 is asynchronous with respect to the input clock signal, a given data output signal may have a binary one or zero value due to glitches. Therefore, the delayed output decoder 120 includes a clock edge voter 125 that examines three consecutive data output signals in the data output signal. For example, the clock edge voter 125 processes the zeroth data output signal Dout. <0> First data output signal Dout <1> Second data output signal Dout <2> Similarly, the clock-edge voter 125 processes the first data output signal Dout. <1> Second data output signal Dout <2> and the third data output signal Dout <3> And so on. This processing of the three data output signals is advantageous in preventing glitches from being interpreted as the detection of the rising edge of the input clock signal.

[0023] To process these three consecutive data output signals, the clock-edge voter 125 receives n data output signals Dout. <n-1:0>In addition, the clock-edge voter 125 receives a single-sample delayed version of the n data output signals, Dout. <n-2:0>、Doubt <n-1>It also receives a double-sampled, delayed version of Dout that outputs n data signals. <n-3:0>、Doubt <n-1:n-2>Dout comes from n data output signals. <n-1:0>The current data output signal can be represented as signal B. Similarly, the single-sample-first data output signal relative to the current data output signal can be represented as signal A. Finally, the single-sample-delayed output signal relative to the current data output signal can be represented as signal C. The clock edge voter 125 therefore processes signals A, B, and C to determine whether the current data output signal has been sampled at the rising edge of the input clock signal.

[0024] In one implementation, the clock edge voter 125 may include a first logic gate, such as a first NAND gate 135 that performs a NAND operation on data output signals A and B, and a second logic gate, such as a second NAND gate 140 that performs a NAND operation on data output signals B and C. The third NAND gate 145 performs a NAND operation on the output signal from NAND gate 135, the output signal from NAND gate 140, and its inverted output signal inverted by inverter 150 to generate a current data vote output signal representing a vote on whether the current data output signal B has been sampled at the rising edge of the input clock signal. The clock edge voter 125 generates n votes corresponding to n data output signals. For example, when the current data output signal is the second data output signal Dout... <2> At the same time, the clock-edge voter 125 also checks the first data output signal Dout. <11> and the third data output signal Dout <3> To determine whether it is the second data voting output signal D_vot <2> (Not illustrated) Set the binary value. More generally, the clock-edge voter 125 checks the i-th data output signal Dout. The (i-1)th data output signal Dout <i-1>and the (i+1)th data output signal Dout<i+1> Determine the i-th data voting output signal D_vot The binary value of i, where i represents the integer index of the current data output signal in the progressive sequence from 0 to n-1.

[0025] If the i-th data output signal Dout and data output signal Dout <i-1>and Dout<i+1> If at least one of the values ​​is equal to binary one, then the clock-edge voter 125 will output the vote signal D_vot for the i-th data. Set to binary 1. Assume the i-th data output signal Dout. The result is a binary zero solely due to a clock edge sampling glitch, which is caused by the output signal Ph of the i-th oscillator. This is caused by a lack of synchronization with the clock input signal and / or by the instability of the i-th flip-flop. In this case, the preceding data output signal Dout... <i-1>and the subsequent data output signal Dout<i+1> Both will be binary one. Then, although the i-th data output signal Dout... There is a glitch at the point, and the clock-edge voter 125 will still output the i-th data as the voting signal D_vot. Set to binary 1. The i-th data is voted on at the rising edge of the input clock signal, resulting in the output signal D_vot. In the detected case, decoder 130 can then output signal Ph from oscillator according to the desired delay. <n-1:0>The selection is made within this range. For example, suppose the desired delay is equal to the (m / n)th moment of the oscillation period, where m is a positive integer less than n. Then, the decoder 130 can output the oscillator output signal Ph.<i+m> As a delay, the output clock signal.

[0026] Figure 2 The diagram shows some example operating waveforms for a specific implementation of a clock edge sampler 110 and a delayed output decoder 120, where n (the number of oscillation output signals from ring oscillator 105) is equal to sixteen. Therefore, the range of the oscillation output signals is from the zeroth oscillation output signal Ph. <0> The fifteenth oscillation output signal Ph <15> The clock input signal (clk_in) has a slight difference in the second oscillation output signal Ph. <2> The previous rising edge. Zero data output signal Dout <0> and the first data output signal Dout <1> Both will be binary zero. The first data vote output signal is D_vot. <1> (Not shown) will also be binary zero because the first data output signal Dout <1> and its preceding data output signal Dout <0> Both are binary zeros. The second data output signal, Dout. <2> It can be binary zero, binary one, or a glitch, depending on the stability of the second flip-flop. However, the third data output signal, Dout... <3> It will be binary one because the third oscillation output signal Ph <3> The rising edge of the second data output signal, Dout, occurs much later than the rising edge of the clock input signal. <2> If the sampled value is binary 1, then the second data voting output signal D_vot <2> It will be binary one because the second data output signal Dout <2> and the third data output signal Dout <3> Both are binary 1. However, if the second data output signal Dout... <2> If it is a binary zero or a glitch, then the second data voting output signal D_vot <2> It will be binary zero.

[0027] Example truth table for clock edge voter 125 is as follows: Figure 3 As shown, the data voting output signal is represented as "output," while the binary values ​​of data output signals A, B, and C are represented as "input." The "output" signal is binary one only if at least two of the data output signals A, B, and C are binary one. Otherwise, the "output" signal is binary zero.

[0028] Assume the second data voting output signal is D_vot <2> It's binary one. Decoder 130 ( Figure 1 Next, the oscillation output signal Ph will be selected.<m+2> , where m is the expected integer delay as discussed previously. If m equals 11, then decoder 130 will output the thirteenth oscillation output signal Ph. <13> This forms the delayed output clock signal (clk_out). The selected oscillating output signal used to form the delayed output clock signal can also be referred to herein as the first oscillating output signal in the oscillating output signal.

[0029] Refer again Figure 1 It should be noted that the oscillation period and frequency of the ring oscillator 105 are subject to process, voltage, and temperature variations. For example, the oscillation frequency will decrease as the temperature decreases, which increases the oscillation period and thus increases the delay between consecutive oscillating output signals in the oscillation output signal. To calibrate against these process, voltage, and temperature variations, calibration logic circuitry (such as a counter-based calibration finite state machine (FSM) circuit 115) receives one of the oscillation output signals as the oscillator clock signal (osc_clk). The counter-based FSM circuit 115 also receives a stable clock signal, such as the crystal oscillator clock signal Tcxo. The counter-based FSM circuit 115 can count according to the cycle of the crystal oscillator signal to establish a count of the oscillation period or frequency of the ring oscillator 105. If the count is too low, the counter-based FSM circuit 115 adjusts the tuning signal Txdelay. <m:0>To increase the oscillation frequency of the ring oscillator 105, the tuning signal Txdelay has a resolution of m+1 bits, where m is a positive integer. Alternatively, if the count is too high, the counter-based FSM circuit 115 adjusts the tuning signal Txdelay to reduce the oscillation frequency of the counter-based FSM circuit 115.

[0030] In response to the tuning signal Txdelay, it can be done as follows: Figure 4 Each delay circuit of the ring oscillator is implemented as shown in the example delay circuit 400. Delay circuit 400 includes multiple delay units arranged in series, the resolution of which depends on the tuning signal Txdelay. For example, suppose the tuning signal Txdelay is a 5-bit tuning signal. This 5-bit tuning signal can be converted into a 32-bit thermometer-coded enable signal, the range of which is from the zero enable signal en controlling the zeroth delay unit 405. <0> The thirty-first enable signal en of the thirty-first delay unit 410 is controlled. <31> The oscillator input signal to the zeroth delay unit 405 is received by a NAND gate 490, which also receives the power supply voltage. The output signal from the NAND gate 490 is processed by a NAND gate 420, which also performs a NAND operation on the output signal from a latch formed by a cross-coupled pair of NAND gates 435 and 430. The NAND gate 425 performs a NAND operation on the output signal from the NAND gate 420 and the output signal from the first delay unit (not shown) to form the oscillator output signal for the delay circuit 400. The NAND gate 430 also performs a NAND operation on the output signal from the first delay unit. The AND gate 440 performs an AND operation on the oscillator output signal to form the clock signal for the D-type flip-flops in each delay unit. For example, the first delay unit 405 includes a D-type flip-flop 415, which latches the zeroth enable signal en in response to a clock drive from an oscillator output signal. <0> This drives the input of the NAND gate 435.

[0031] Each delay unit contributes to the delay of the oscillator output signal according to its corresponding enable signal. For example, the thirty-first delay unit includes a D-type flip-flop 450, which latches the thirty-first enable signal en when driven by the oscillator output signal clock. <31> The input of NAND gate 470, which is cross-coupled with NAND gate 465 to form a latch, is driven. NAND gate 455 performs a NAND operation on the output signals from NAND gates 445 and 470. NAND gate 455 performs a NAND operation on the output signal from the thirtieth delay unit (not shown) and the Q output signal from the D-type flip-flop (not shown) in the thirtieth delay unit. NAND gate 460 performs a NAND operation on the output signal from NAND gate 455. The output signal from NAND gate 445 is also processed serially through three NAND gates 475, 480, and 485, which are configured as inverters to drive NAND gates 465 and 460. The output signal from NAND gate 460 is received by an equivalent (not shown) of NAND gate 430 in the thirtieth delay unit.

[0032] It should be understood that other architectures can be used to form each delay circuit in the ring oscillator 105. In this regard, Figure 4 The NAND gates in the delay cells can be replaced with other types of logic gates. Regardless of how the delay cells are formed, it should be noted that the programmable delay line circuit 100 uses only one ring oscillator 105, which is advantageously continuously calibrated. Therefore, as discussed earlier, there is no mismatch problem between the delay arrays, and no settling time is required.

[0033] Now relative to Figure 5 The flowchart discusses the operation method of the programmable delay line disclosed herein. The method includes action 500: generating a corresponding oscillator output signal in each of a plurality of delay units arranged to form a ring oscillator. n oscillator output signals Ph are generated in the ring oscillator 105. <n-1:0>This is an example of action 500. The method also includes action 505: sampling the input clock signal in response to each oscillator output signal to form a plurality of data output signals. Sampling the input clock clk_in by clock edge sampler 110 is an example of action 505. In addition, the method includes action 510: processing the data output signals to identify a first oscillator output signal in the oscillator output signals as a signal of an edge transition sampled to the input clock signal. Processing the data output signals as discussed with respect to clock edge voter 125 is an example of action 510. Finally, the method includes action 515: outputting a second oscillator output signal in the output oscillator output signals as an output clock signal. This is similar to the output clock signal Ph discussed with respect to decoder 130. <n-1:0>The choice made is an example of action 515.

[0034] The programmable delay line circuits disclosed herein can be incorporated into a wide variety of electronic systems. For example, such as... Figure 6 As shown, the cellular phone 600, laptop computer 605, and tablet PC 610 can all include the programmable delay line circuitry according to this disclosure. Other example electronic systems (such as earphones, music players, video players, communication devices, and personal computers) may also be configured with programmable delay line circuitry constructed according to this disclosure.

[0035] This disclosure will now be outlined through the following example clauses: Clause 1. A delay line circuit for delaying an input clock signal, the delay line circuit comprising: A ring oscillator, the ring oscillator including a plurality of delay units, the ring oscillator being configured to generate an oscillator output signal; A clock edge sampler configured to generate a data output signal includes multiple flip-flops corresponding to the plurality of delay units on a one-to-one basis. Each flip-flop is configured to latch the input clock signal in response to an oscillator output signal from the corresponding delay unit to generate the corresponding data output signal. A delayed output decoder, configured to process the data output signal to select a first oscillator output signal from the oscillator output signals for forming an output clock signal.

[0036] Clause 2. The delay line circuit according to Clause 1, further comprising: A calibration logic circuit configured to calibrate the oscillation frequency of the ring oscillator.

[0037] Clause 3. The delay line circuit according to Clause 2, wherein the calibration logic circuit is configured to count in response to the period of the crystal oscillator signal to calibrate the oscillation frequency of the ring oscillator.

[0038] Clause 4. The delay line circuit according to any one of Clauses 1 to 3, wherein each of the plurality of flip-flops comprises a data (D) type flip-flop.

[0039] Clause 5. The delay line circuit according to any one of Clauses 1 to 4, wherein the delay output decoder is configured to process three consecutive data output signals in the data output signals to identify the second oscillator output signal in the oscillator output signals as a signal sampled at the transition edge of the input clock signal, and wherein the first oscillator output signal in the oscillator output signals is delayed by an integer number of the oscillator output signals relative to the second oscillator output signal in the oscillator output signals.

[0040] Clause 6. The delay line circuit according to Clause 5, wherein the delay output decoder is further configured to process the three consecutive data output signals by identifying whether at least two of the three consecutive data output signals in the data output signals have the same binary value.

[0041] Clause 7. The delay line circuit according to any one of Clauses 1 to 6, wherein the ring oscillator comprises n delay circuits, where n is a multiple of two, and wherein the plurality of flip-flops comprises n flip-flops.

[0042] Clause 8. The delay line circuit as described in Clause 7, where n equals sixteen.

[0043] Clause 9. The delay line circuit according to Clause 5, wherein the delay output decoder includes a clock voting circuit having a first logic gate configured to process a first data output signal and a second data output signal from the three consecutive data output signals, and a second logic gate configured to process the second data output signal and a third data output signal from the three consecutive data output signals.

[0044] Clause 10. The delay line circuit according to Clause 9, wherein the first logic gate includes a first NAND gate, and wherein the second logic gate includes a second NAND gate.

[0045] Clause 11. The delay line circuit according to Clause 10, wherein the clock voter circuit further comprises: The third "AND" gate; and An inverter configured to invert the output signal from the third NAND gate, wherein the third NAND gate is configured to perform a NAND operation on the output signals from each of the first NAND gate, the second NAND gate, and the inverter.

[0046] Clause 12. A method comprising: In each of the multiple delay units arranged to form a ring oscillator, a corresponding oscillator output signal is generated; The input clock signal is sampled in response to the output signal of each oscillator to form multiple data output signals; Process the plurality of data output signals to identify the first oscillator output signal among the oscillator output signals as a signal sampled at the edge transition of the input clock signal; and The second oscillator output signal in the output oscillator signal is used as the output clock signal.

[0047] Clause 13. The method described in Clause 12, further comprising: The oscillation frequency of the ring oscillator is calibrated.

[0048] Clause 14. The method according to Clause 13, wherein calibrating the oscillation frequency of the ring oscillator includes adjusting the oscillation frequency of the ring oscillator relative to the oscillation frequency of the crystal oscillator signal.

[0049] Clause 15. The method according to any one of Clauses 12 to 14, wherein processing the data output signal includes identifying whether three consecutive data output signals in the data output signal include at least two data output signals having a binary value of one.

[0050] Clause 16. A delay line circuit, the delay line circuit comprising: A single ring oscillator, the single ring oscillator being configured to generate multiple oscillator output signals; A clock edge sampler, configured to sample an input clock signal based on the output signals of the plurality of oscillators to provide a plurality of data output signals; and A decoder configured to select one of the oscillator output signals as an output clock signal in response to processing of the plurality of data output signals.

[0051] Clause 17. The delay line circuit according to Clause 16, further comprising: A calibration logic circuit configured to calibrate the oscillation frequency of the single ring oscillator during operation of the single ring oscillator.

[0052] Clause 18. The delay line circuit according to Clause 17, wherein the calibration logic circuit is further configured to perform counting in response to a crystal oscillator signal to form a count and to calibrate the oscillation frequency in response to the count.

[0053] Clause 19. The delay line circuit according to any one of Clauses 16 to 18, wherein the clock edge sampler comprises a plurality of flip-flops.

[0054] Clause 20. The delay line circuit according to Clause 19, wherein the single ring oscillator includes a plurality of delay circuits corresponding to the plurality of triggers on a one-to-one basis.

[0055] As those skilled in the art will understand to date and depending on the specific application at hand, many modifications, substitutions, and variations may be made to the materials, apparatus, configurations, and methods of using the device as defined by the appended claims, without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments illustrated and described herein (as they are merely examples), but should be fully equivalent to the appended claims and their functional equivalents.

Claims

1. A delay line circuit for delaying an input clock signal, the delay line circuit comprising: A ring oscillator, the ring oscillator including a plurality of delay units, the ring oscillator being configured to generate an oscillator output signal; A clock edge sampler configured to generate a data output signal includes multiple flip-flops corresponding to the plurality of delay units on a one-to-one basis, each flip-flop being configured to latch the input clock signal in response to an oscillator output signal from the corresponding delay unit to generate the corresponding data output signal; and A delayed output decoder, configured to process the data output signal to select a first oscillator output signal from the oscillator output signals for forming an output clock signal.

2. The delay line circuit according to claim 1, further comprising: A calibration logic circuit configured to calibrate the oscillation frequency of the ring oscillator.

3. The delay line circuit of claim 2, wherein the calibration logic circuit is configured to count in response to the period of the crystal oscillator signal to calibrate the oscillation frequency of the ring oscillator.

4. The delay line circuit of claim 1, wherein each of the plurality of flip-flops comprises a data (D) flip-flop.

5. The delay line circuit of claim 1, wherein the delay output decoder is configured to process three consecutive data output signals in the data output signal to identify the second oscillator output signal in the oscillator output signal as a signal sampled at the transition edge of the input clock signal, and wherein the first oscillator output signal in the oscillator output signal is delayed by an integer number of the oscillator output signals relative to the second oscillator output signal in the oscillator output signal.

6. The delay line circuit of claim 5, wherein the delay output decoder is further configured to process the three consecutive data output signals by identifying whether at least two of the three consecutive data output signals in the data output signals have the same binary value.

7. The delay line circuit according to claim 1, wherein the ring oscillator comprises n delay circuits, where n is a multiple of two, and wherein the plurality of flip-flops comprises n flip-flops.

8. The delay line circuit according to claim 7, wherein n equals sixteen.

9. The delay line circuit of claim 5, wherein the delay output decoder includes a clock voting circuit having a first logic gate configured to process a first data output signal and a second data output signal from the three consecutive data output signals, and a second logic gate configured to process the second data output signal and a third data output signal from the three consecutive data output signals.

10. The delay line circuit of claim 9, wherein the first logic gate includes a first NAND gate, and wherein the second logic gate includes a second NAND gate.

11. The delay line circuit of claim 10, wherein the clock voting circuit further comprises: The third "AND" gate; and An inverter configured to invert the output signal from the third NAND gate, wherein the third NAND gate is configured to perform a NAND operation on the output signals from each of the first NAND gate, the second NAND gate, and the inverter.

12. A method, the method comprising: In each of the multiple delay units arranged to form a ring oscillator, a corresponding oscillator output signal is generated; The input clock signal is sampled in response to the output signal of each oscillator to form multiple data output signals; The plurality of data output signals are processed to identify the first oscillator output signal among the oscillator output signals as a signal sampled at the edge transition of the input clock signal; as well as The second oscillator output signal in the output oscillator signal is used as the output clock signal.

13. The method according to claim 12, further comprising: The oscillation frequency of the ring oscillator is calibrated.

14. The method of claim 13, wherein calibrating the oscillation frequency of the ring oscillator comprises adjusting the oscillation frequency of the ring oscillator relative to the oscillation frequency of a crystal oscillator signal.

15. The method of claim 12, wherein processing the data output signal includes identifying whether three consecutive data output signals in the data output signal include at least two data output signals having a binary value of one.

16. A delay line circuit, the delay line circuit comprising: A single ring oscillator, the single ring oscillator being configured to generate multiple oscillator output signals; A clock edge sampler is configured to sample an input clock signal based on the output signals of the plurality of oscillators to provide a plurality of data output signals; and A decoder configured to select one of the oscillator output signals as an output clock signal in response to processing of the plurality of data output signals.

17. The delay line circuit according to claim 16, further comprising: A calibration logic circuit configured to calibrate the oscillation frequency of the single ring oscillator during operation of the single ring oscillator.

18. The delay line circuit of claim 17, wherein the calibration logic circuit is further configured to perform counting in response to a crystal oscillator signal to form a count and to calibrate the oscillation frequency in response to the count.

19. The delay line circuit of claim 16, wherein the clock edge sampler comprises a plurality of flip-flops.

20. The delay line circuit of claim 19, wherein the single ring oscillator comprises a plurality of delay circuits corresponding to the plurality of triggers on a one-to-one basis.

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