Method and system for operating a double-sided double-base bipolar junction transistor

Abstract

The present disclosure relates to operating a double-sided double-base bipolar junction transistor. At least one example is a method of operating a switch assembly, the method comprising: conducting a forward load current from an upper terminal of the switch assembly into an upper collector-emitter of a double-sided double-base bipolar junction transistor (DSDB-BJT), through the DSDB-BJT, out through a lower collector-emitter of the DSDB-BJT, and then through a lower terminal of the switch assembly; and then stopping the conducting of the forward load current. The stopping the conducting of the forward load current can be done by: coupling a lower base of the DSDB-BJT to the lower terminal; and driving a pinch-off voltage to the lower collector-emitter of the DSDB-BJT to reduce a reverse recovery current through the lower base.

Description

Cross-reference of related applications

[0001] This application claims the benefit of U.S. Patent Application No. 18 / 583,188, filed February 21, 2024, entitled "Methods and Systems of Operating a Double-Sided Double-Base Bipolar Junction Transistor." The application is incorporated herein by reference as if reproduced in its entirety below. Background Technology

[0002] A double-sided double-base (DSDB) bipolar junction transistor (BJT) is a junction transistor consisting of a base and collector-emitter junction on a first side of the bulk region and separate, independent base and collector-emitter junctions on a second side of the bulk region opposite the first side. When properly configured by an external driver, current can selectively flow through the collector-emitter junction of the DSDB BJT in either direction, and therefore this device is considered a bidirectional device. Summary of the Invention

[0003] At least one example is a method of operating a switch assembly, the method comprising: conducting a forward load current from an upper terminal of the switch assembly to the upper collector-emitter of a dual-base bipolar junction transistor (DSDB-BJT), through the DSDB-BJT, out through the lower collector-emitter of the DSDB-BJT, and then through the lower terminal of the switch assembly; and then stopping the conduction of the forward load current. The stopping of the conduction of the forward load current may be performed by coupling the lower base of the DSDB-BJT to the lower terminal; and driving a pinch-off voltage to the lower collector-emitter of the DSDB-BJT to reduce the reverse recovery current through the lower base.

[0004] In an exemplary method, driving the pinch-off voltage to the lower collector-emitter may include: driving the pinch-off voltage to the lower collector-emitter for a predetermined period of time that is continuously non-zero; and then causing the lower collector-emitter to float electrically.

[0005] In an exemplary method, driving the pinch-off voltage to the lower collector-emitter may include: driving the pinch-off voltage to the lower collector-emitter for a period between 200 nanoseconds and 500 nanoseconds, including a boundary value; and then allowing the lower collector-emitter to float electrically.

[0006] In an exemplary method, driving the pinch-off voltage to the lower collector-emitter may include driving the pinch-off voltage between 10 volts and 50 volts, and including both 10 volts and 50 volts.

[0007] In an exemplary method, driving the pinch-off voltage to the lower collector-emitter may include driving the pinch-off voltage to approximately 30 volts.

[0008] In an exemplary method, conducting the main load current may include injecting charge carriers into the upper drift region of the DSDB-BJT. Injecting charge carriers into the upper drift region may include injecting charge carriers through the upper base of the DSDB-BJT. Conducting the main load current may further include injecting charge carriers into the lower drift region of the DSDB-BJT. Injecting charge carriers into the lower drift region may include injecting charge carriers through the lower base of the DSDB-BJT.

[0009] The exemplary method may further include: conducting a reverse load current from the lower terminal of the switching assembly to the upper collector-emitter, through the DSDB-BJT, out through the upper collector-emitter, and then through the upper terminal of the switching assembly; and then stopping the conduction of the reverse load current. The conduction of the reverse load current can be stopped by coupling the upper base to the upper terminal; and by driving a pinch-off voltage to the upper collector-emitter of the DSDB-BJT to reduce the reverse recovery current through the upper base.

[0010] Another example is a switching assembly comprising: an upper terminal, a lower terminal, and a control input; a double-sided double-base bipolar junction transistor (DSDB-BJT) defining an upper base, an upper collector-emitter junction, an upper base, and an upper collector-emitter junction; an upper main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper collector-emitter junction, and a gate; a lower main FET defining a first lead coupled to the lower collector-emitter junction, a second lead coupled to the lower terminal, and a gate; and a driver coupled to the control input, the gate of the upper main FET, the gate of the lower main FET, and the control input. The driver describes the upper base and the lower base of the DSDB-BJT; in response to an assertion of the control input, and for a first applied voltage across the upper and lower terminals, the driver is configured to arrange the DSDB-BJT such that the main load current flows from the upper terminal of the switching assembly to the upper collector-emitter of the DSDB-BJT, through the DSDB-BJT, out through the lower collector-emitter, and then through the lower terminal of the switching assembly; and in response to a deassertion of the control input, and for the first applied voltage, the driver is configured to stop the conduction of the main load current. The conduction of the main load current can be stopped by coupling the lower base of the DSDB-BJT to the lower terminal; and by driving a pinch-off voltage to the lower collector-emitter to reduce the reverse recovery current through the lower base.

[0011] In an exemplary switching assembly, when the driver drives the pinch-off voltage to the lower collector-emitter, the driver can be configured to: drive the pinch-off voltage to the lower collector-emitter for a predetermined period of time while maintaining a non-zero voltage; and then allow the lower collector-emitter to float electrically.

[0012] In an exemplary switching assembly, when the driver drives the pinch-off voltage to the lower collector-emitter, the driver can be configured to: drive the pinch-off voltage to the lower collector-emitter for a duration between 200 nanoseconds and 500 nanoseconds, including a boundary value; and then allow the lower collector-emitter to float electrically.

[0013] In an exemplary switch assembly, when the driver drives the pinch-off voltage to the lower collector-emitter, the driver can be configured to drive the pinch-off voltage between 10 volts and 50 volts, including both 10 volts and 50 volts.

[0014] In an exemplary switch assembly, the driver can be configured to drive the pinch-off voltage of approximately 30 volts when the driver drives the pinch-off voltage to the lower collector-emitter.

[0015] In an exemplary switching assembly, when the driver is positioned over the DSDB-BJT to conduct the main load current, the driver can be configured to inject charge carriers into the upper drift region of the DSDB-BJT. While injecting charge carriers into the upper drift region, the driver can also be configured to inject charge carriers through the upper base of the DSDB-BJT. When the driver is positioned over the DSDB-BJT to conduct the main load current, the driver can be configured to inject charge carriers into the lower drift region of the DSDB-BJT. While injecting charge carriers into the lower drift region, the driver can also be configured to inject charge carriers through the lower base of the DSDB-BJT. Attached Figure Description

[0016] To illustrate exemplary embodiments in detail, reference will now be made to the accompanying drawings, in which:

[0017] Figure 1 Showing a switch assembly according to at least some embodiments;

[0018] Figure 2 A bidirectional switch is shown according to at least some embodiments;

[0019] Figure 3A-3G A simplified representation of a double-sided double-base bipolar junction transistor with an exemplary external electrical connection and a PNP structure is shown to illustrate several operating states.

[0020] Figure 4 This diagram shows partial block diagrams and partial electrical schematics of a switch assembly according to at least some embodiments; and

[0021] Figure 5 The method is illustrated according to at least some embodiments.

[0022] definition

[0023] Various terms are used to refer to specific system components. Different companies may use different names to refer to components, and this document is not intended to distinguish between components with different names but the same function. In the following discussion and in the claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as meaning "including but not limited to...". Furthermore, the term "coupled" is intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, the connection can be a direct connection or an indirect connection via other devices and connections.

[0024] As used herein, “(a, an)” and “the” refer to singular and plural indicators, respectively, unless the context clearly specifies otherwise. By way of example, “processor” programmed to perform various functions refers to one processor programmed to perform each and every function, or more than one processor programmed together to perform each of the various functions. For clarity, the initial reference to “a [referring to]” followed by the subsequent reference to “the [referring to]” for prior grounds purposes should not preclude the referencing of objects from being plural.

[0025] The word “about” in relation to the described parameter should mean the described parameter plus or minus 10 percent (+ / - 10%).

[0026] "Assertion" should be understood as generating or maintaining a first predetermined state of a Boolean signal. At the circuit designer's discretion, a Boolean signal can be asserted as high or having a higher voltage, and a Boolean signal can be asserted as low or having a lower voltage. Similarly, "de-assertion" should be understood as generating or maintaining a second predetermined state of the Boolean signal that is the opposite of the asserted state.

[0027] "FET" should refer to a field-effect transistor, such as a junction gate FET (JFET) or a metal-oxide-semiconductor FET (MOSFET).

[0028] The term "closing" in relation to an electrically controlled switch (e.g., a FET) should be understood as turning on the electrically controlled switch. For example, closing a FET used as an electrically controlled switch could mean driving the FET to a fully on state.

[0029] The term "off" in relation to an electrically controlled switch (e.g., a FET) should be understood to mean that the electrically controlled switch is not conducting. Leakage current should not negate the state where the electrically controlled switch is not conducting.

[0030] "DSDB-BJT" should refer to a double-sided double-base (DSDB) bipolar junction transistor (BJT), which has a base and collector-emitter junction on a first side of the drift region, and different and independent base and collector-emitter junctions on a second side of the drift region opposite to the first side. The drift region can be continuous, or the drift region can include an upper drift region associated with an upper base and upper collector-emitter junction, and a lower drift region associated with a lower base and lower collector-emitter junction.

[0031] The term "collector-emitter" in a bipolar junction transistor (BJT) should refer to the region of the BJT through which the main load current flows. For the purposes of this specification and claims, the designation as collector-emitter is independent of the underlying device physics within the BJT. For example, in a double-sided double-base PNP transistor, the main load current can flow from the upper P-type region through the bulk N-type drift region and then out of the lower P-type region, and when used in this way, the upper and lower P-type regions are considered the collector-emitter. However, in other cases, such as those described in co-pending and co-assigned U.S. Application No. 18 / 483,939, filed October 10, 2023, entitled “Methods and Systems of Operating a PNP Bi-Directional Double-Base Bipolar Junction Transistor,” the main load current can flow from the upper N-type region through the bulk N-type drift region and then through the lower N-type region, and when used in this way, the upper and lower N-type regions are considered as collector-emitter junctions.

[0032] The term "base" in a bipolar junction transistor (BJT) refers to the region of the BJT through which control current flows, which is different from the main load current. For the purposes of this specification and claims, the designation of the base is independent of the underlying device physics within the BJT. For example, in a bidirectional double-base PNP transistor, control current may flow to either the upper N-type region or the lower N-type region, and when used in this way, both the upper and lower N-type regions are considered the base. However, in other cases, such as those described in the co-pending and co-assigned U.S. Application No. 18 / 483,939 mentioned above, control current may flow to either the upper P-type region or the lower P-type region, and when used in this way, both the upper and lower P-type regions are considered the base.

[0033] The term "upper" in relation to components (e.g., upper collector-emitter, upper base) should not be interpreted as referring to the position of the described component relative to gravity. In the exemplary figures, "upper" can be derived from the position of the device.

[0034] The term "lower" in relation to components (e.g., lower collector-emitter, lower base) should not be interpreted as referring to the position of the described component relative to gravity. In the exemplary figures, "lower" can be derived from the position of the device.

[0035] When used as nouns, the terms "input" and "output" refer to connections (e.g., electrical, software) and should not be interpreted as verbs requiring action. For example, a timer circuit may define a clock output. An exemplary timer circuit may generate or drive a clock signal at the clock output. In systems implemented directly in hardware (e.g., on a semiconductor substrate), these "inputs" and "outputs" define electrical connections. In systems implemented in software, these "inputs" and "outputs" define parameters that are read or written by instructions that implement the function.

[0036] "Controller" should be used individually or in combination to mean an individual circuit component configured to read inputs and drive outputs in response to inputs, an application-specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computing (RISC) with control software, a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), a field-programmable gate array (FPGA), or a programmable system-on-a-chip (PSOC). Detailed Implementation

[0037] The following discussion pertains to various embodiments of the invention. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended only as an example of the described embodiments and is not intended to imply that the scope of this disclosure, including the claims, is limited to the described embodiments.

[0038] Various examples are provided for methods and systems of operating a dual-base bipolar junction transistor (DSDB-BJT). More specifically, during the transition of the DSDB-BJT from on to off, various examples are provided for driving the DSDB-BJT to reduce the reverse recovery current through the blocking PN junction of the DSDB-BJT. The specification turns to exemplary systems to guide the reader.

[0039] Figure 1An exemplary switch assembly 100 is shown. Specifically, the exemplary switch assembly 100 defines an upper terminal 102, a lower terminal 104, and a control input or control terminal 106. Internally, the exemplary switch assembly 100 includes a driver 108 and a bidirectional switch 110. The driver 108 defines the control terminal 106, and the driver 108 is coupled to the bidirectional switch 110, as shown in connection 112. As discussed in more detail below, although shown as a single connection, connection 112 represents multiple electrical connections to the bidirectional switch 110, the on state of which can vary. The driver 108 controls the on state of the bidirectional switch 110 by arranging voltage / current on connection 112.

[0040] An example of a switch assembly 100 may include a single bidirectional switch 110. Another exemplary switch assembly 100 may have two or more bidirectional switches 110, such as... Figure 1 The diagram illustrates a "stacked" arrangement of the bidirectional switch 110. When multiple bidirectional switches 110 are present, they are electrically connected in parallel to share the main load current (forward or reverse). To avoid overcomplicating the specification, the following discussion assumes a single bidirectional switch 110. However, those skilled in the art to which this disclosure pertains will understand that multiple bidirectional switches may exist depending on the designed current carrying capacity of any particular switch assembly 100.

[0041] Figure 2 A schematic diagram of an exemplary bidirectional switch 110 is shown. Specifically, the exemplary bidirectional switch 110 includes a DSDB-BJT 200. The exemplary DSDB-BJT 200 defines an upper base 202, a lower base 204, an upper collector-emitter 206, and a lower collector-emitter 208. The exemplary bidirectional switch 110 further includes a lower master or lower cascode FET 210, which defines a drain 212 coupled to the lower collector-emitter 208, a source 214 coupled to the lower terminal 104, a gate 216 coupled to the driver 108, and a body diode 218. Finally, the exemplary bidirectional switch 110 includes an upper master or upper cascode FET 220, which defines a drain 222 coupled to the upper collector-emitter 206, a source 224 coupled to the upper terminal 102, a gate 226 coupled to the driver 108, and a body diode 228.

[0042] The driver 108 is coupled to the bidirectional switch 110 via multiple electrical connections. Figure 2In the example, the electrical connections to driver 108 may include connections to: the gate 226 of the upper cascode FET 220; the upper collector-emitter 206; the upper base 202; the lower base 204; the lower collector-emitter 208; and the gate 216 of the lower cascode FET 210. To describe when each of these connections to driver 108 can be active, the specification turns to the exemplary operation of the DSDB-BJT 200.

[0043] Figure 3A-3G The bidirectional switch 110 is shown in simplified form. Specifically, in Figures 3A-3F Each of these components includes an upper cascode FET 220 and a lower cascode FET 210, along with their respective host diodes 228 and 218. For clarity, the cascode FETs 220 and 210 are shown as single-pole single-throw (SPS) switches. When the cascode FET is on, the SPS is shown as closed, and when the cascode FET is off, the SPS is shown as open. Note that even if the cascode FET is off, the host diode of the cascode FET may be on, depending on the polarity of the voltage applied to the bidirectional switch 110.

[0044] Figure 3A-3G Each of the exemplary DSDB-BJT 200 in the examples is shown as a partial cross-sectional view of a PNP-constructed device to illustrate several operating states. Specifically, Figure 3A-3G This demonstrates seven exemplary states of the DSDB-BJT 200, which is arranged to carry the main load current across or through the N-type region. The six states are: passive shutdown (…). Figure 3A Passive connection ( ); Figure 3B Actively connect ( Figure 3C ); Replace active connection ( Figure 3D Pre-shutdown ( Figure 3E Reverse recovery Figure 3F ); and alternative reverse recovery ( Figure 3G ).exist Figure 3A-3G In the example, it is assumed that the switch assembly 100 is forward biased (e.g., the upper terminal 102 has a greater positive polarity relative to the lower terminal 104), and therefore the switch assembly 100 carries a forward load current. Each example state is solved in turn.

[0045] Figure 3AThis illustrates a passive shutdown arrangement of an exemplary DSDB-BJT 200. Specifically, in this exemplary passive shutdown arrangement, the upper base 202 is electrically floated by a driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102 via an upper cascode FET 220 or its body diode 228. The lower base 204 is coupled to the lower terminal 104 via a driver 108. The lower collector-emitter 208 is electrically floated, for example, due to an applied voltage, causing the lower cascode FET 210 to be off and its body diode 218 to be non-conducting. Figure 3A In this arrangement, due to the obstruction caused by the PN junction formed between the lower base 204 and the drift region 304, no significant current flows through the DSDB-BJT 200. Figure 3A The state is called "passive shutdown" because the electrical arrangement can be implemented using purely passive components (e.g., diodes and resistors), and therefore the driver 108 does not need to have operating power to implement it. Figure 3A The arrangement. In the passive turn-off arrangement, the DSDB-BJT 200 blocks voltage and current, and therefore the non-conducting lower cascode FET 210 can experience a relatively small drain-to-source voltage (e.g., 30 V or less for a 1200 V applied across the upper terminal 102 and the lower terminal 104).

[0046] Figure 3B This illustrates a passive turn-on arrangement of an exemplary DSDB-BJT 200. Specifically, the upper base 202 is electrically floated by driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102 via an upper cascode FET 220 or its host diode 228. The lower base 204 is electrically floated by driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 via a lower cascode FET 210. Figure 3B In this arrangement, the voltage drop across the DSDB-BJT 200 is based on the substrate resistance (e.g., approximately 2 ohms for a 160-micrometer-thick substrate). For an example of a 30-ampere (A) main load current, in a passively switched-on arrangement, the DSDB-BJT 200 has a voltage drop of approximately 60 V measured from the upper collector-emitter 206 to the lower collector-emitter 208. Figure 3B The exemplary state is called "passively turned on" because the on state does not involve the injection of charge carriers to reduce the forward voltage drop V. CEON .exist Figure 3C An example of charge carrier injection is shown in the active turn-on arrangement.

[0047] Figure 3CThis demonstrates an active-on arrangement of an exemplary DSDB-BJT 200, still featuring a forward-biased switching assembly 100. Specifically, the upper base 202 is coupled to the upper terminal 102 via a driver 108 and a source 302 (e.g., a voltage source, a current source). The upper collector-emitter 206 is coupled to the upper terminal 102 via an upper cascode FET 220 or its body diode 228. The lower base 204 is electrically floated by the driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 via a lower cascode FET 210. The source 302 provides a positive bias to the upper base 202 relative to the upper collector-emitter 206, and the source 302 can provide any suitable bias voltage (e.g., 0.2 V to 2 V). Source 302 injects charge carriers across the PN junction into the bulk substrate or drift region 304. For a main load current of 30 A, this will result in a forward voltage drop V measured from the upper collector-emitter 206 to the lower collector-emitter 208. CEON It decreased to approximately 0.2 V. Specifically, Figure 3C The arrangement injects charge carriers into the upper part of the drift region 304.

[0048] Figure 3D An alternative active-on arrangement is shown for the exemplary DSDB-BJT 200, still featuring a forward-biased switching assembly 100. Specifically, the upper base 202 is coupled to the upper terminal 102 via a driver 108 by means of a source 302. The upper collector-emitter 206 is coupled to the upper terminal 102 via an upper cascode FET 220 or its body diode 228. The lower base 204 is coupled to the lower terminal 104 via a driver 108 by means of a source 306 (e.g., a voltage source, a current source). The lower collector-emitter 208 is coupled to the lower terminal 104 via a lower cascode FET 210. The source 302 provides a positive bias to the upper base 202 relative to the upper collector-emitter 206, and the source 306 provides a positive bias to the lower base 204 relative to the lower collector-emitter 208. Source 302 injects charge carriers across the upper PN junction into the upper portion of drift region 304, and source 306 injects charge carriers across the lower PN junction into the lower portion of drift region 304. For a main load current of 30 A, the injection of charge carriers reduces the forward voltage drop V measured from the upper collector-emitter 206 to the lower collector-emitter 208. CEON It then dropped again to about 0.2 V.

[0049] Figure 3EThis illustrates a pre-shutdown arrangement of an exemplary DSDB-BJT 200. Specifically, the upper base 202 is coupled to the upper terminal 102 via driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102 via an upper cascode FET 220 or its host diode 228. The lower base 204 is coupled to the lower terminal 104 via driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 via a lower cascode FET 210. An equivalent arrangement could omit the coupling from the upper base 202 to the upper terminal 102. Figure 3E In the pre-shutdown arrangement, the exemplary DSDB-BJT 200 presents a resistance of approximately 2 ohms between terminals 102 and 104. Therefore, for the exemplary 30 A main load current, Figure 3F In the pre-shutdown arrangement, the DSDB-BJT 200 exhibits a voltage drop of approximately 60 V, measured from the upper collector-emitter 206 to the lower collector-emitter 208.

[0050] Figure 3F This illustrates the reverse recovery arrangement of an exemplary DSDB-BJT 200. Specifically, the upper collector-emitter 206 is coupled to the upper terminal 102 via an upper cascode FET 220 or its host diode 228. The lower base 204 is coupled to the lower terminal 104 via a driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 via a source 308 (e.g., a voltage source, a current source) of the driver 108. The upper base 202 may be electrically floated by the driver 108. When the switching assembly 100 is forward biased, the PN junction formed by the lower base 204 becomes the primary current / voltage blocking mechanism of the DSDB-BJT 200, thus limiting the current / voltage blocking after one conduction cycle from the upper collector-emitter 206 to the lower collector-emitter 208. Figure 3F The reverse recovery arrangement can be used to shorten the diode reverse recovery time of the PN junction formed between the lower base 204 and the drift region 304. That is, the positive voltage between the lower collector-emitter 208 and the lower base 204 pinches off the N+ / P region formed between the lower collector-emitter 208 and the lower base 204, thereby reducing the reverse recovery current between the upper collector-emitter 206 and the lower base 204. In other words, in Figure 3C In a 3D active-on arrangement, excess charge carriers are injected into the drift region to reduce the forward voltage drop Vceon. However, from Figure 3A In the transition from an active turn-on arrangement to a passive turn-off arrangement, excess charge carriers generate an undesirable reverse recovery current (I0) from the lower base 204. RR This increases the reverse recovery time (T) accordingly. RRCompared to an implementation scheme that does not implement this reverse recovery step, implementing it within a non-zero predetermined time period... Figure 3F The reverse recovery arrangement reduces the reverse recovery current I. RR And thus reduce the reverse recovery time T RR .

[0051] Figure 3G An alternative reverse recovery arrangement for the exemplary DSDB-BJT 200 is shown. Specifically, the upper collector-emitter 206 is coupled to the upper terminal 102 via a voltage source 428, and the upper cascode FET 220 is disconnected. The upper base 202 is coupled to the upper terminal 102 via a driver 108. The lower base 204 is coupled to the lower terminal 104 via a driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 via a source 308 (e.g., a voltage source, a current source) of the driver 108. As... Figure 3F Similar to the reverse recovery arrangement, when the switch assembly 100 is forward biased, since the PN junction formed by the lower base 204 becomes the main current / voltage blocking mechanism of the DSDB-BJT 200, after a conduction cycle from the upper collector-emitter 206 to the lower collector-emitter 208, Figure 3G An alternative reverse recovery arrangement can be used to shorten the diode reverse recovery time of the PN junction formed between the lower base 204 and the drift region 304. That is, the positive voltage between the lower collector-emitter 208 and the lower base 204 pinches off the N+ / P region formed between the lower collector-emitter 208 and the lower base 204, thereby reducing the reverse recovery current between the upper collector-emitter 206 and the lower base 204. Similarly, the positive voltage between the upper collector-emitter 2906 and the upper base 202 helps to pinch off the N+ / P region formed between the lower collector-emitter 208 and the lower base 204. In other words, in Figure 3C In a 3D active-on arrangement, excess charge carriers are injected into the drift region to reduce the forward voltage drop Vceon. However, from Figure 3A In the transition from an active turn-on arrangement to a passive turn-off arrangement, excess charge carriers generate an undesirable reverse recovery current (I0) from the lower base 204. RR This increases the reverse recovery time (T) accordingly. RR Compared to an implementation scheme that does not implement this reverse recovery step, implementing it within a non-zero predetermined time period... Figure 3G Alternative reverse recovery arrangements reduce reverse recovery current I RR And thus reduce the reverse recovery time T RR .

[0052] Regarding the transition of the switch assembly 100 from non-conducting to conducting, without implementing intermediate arrangements or states, the exemplary DSDB-BJT 200 can be arranged from... Figure 3A The passive shutdown deployment was directly transformed into Figure 3C Or one of the 3D active connection arrangements. Nevertheless, Figure 3B A passive switching arrangement can be useful in certain situations. Regarding the transition of switch assembly 100 from conducting to non-conducting, in various examples, the DSDB-BJT 200... Figure 3C Or one of the 3D active connection arrangements is transformed to Figure 3F One of the reverse recovery arrangements or 3G configurations, in some cases lasting between 200 and 500 nanoseconds including boundary values, and in certain cases, lasting approximately 400 nanoseconds. After implementing either the reverse recovery arrangement or configuration, the DSDB-BJT 200 can then be converted to... Figure 3A The passive shutdown state.

[0053] In some cases, such as when the DSDB-BJT 200 does not conduct during a zero-current event through the switch assembly 100, it can be omitted. Figure 3F Or 3G reverse recovery setup, and DSDB-BJT 200 can be directly converted to Figure 3A Passive shutdown arrangement. Figure 3E Pre-shutdown arrangements can be useful in certain situations.

[0054] Figure 3A-3G The example is that the switch assembly 100 is forward biased and carries a forward load current. However, the bidirectional switch 110 is a symmetrical device, and it is now understood how the current through the DSDB-BJT 200 is controlled when the switch assembly 100 is forward biased, and the current control when the switch assembly 100 is reverse biased (i.e., has a larger positive polarity relative to the upper terminal 102 associated with the lower terminal 104) and carries a reverse load current follows directly. Hereafter, the terms "forward" and "reverse" are arbitrarily assigned to aid in the description. Furthermore, various operating states of the PNP configuration with the main load current flowing through the N-type region are now understood, and those skilled in the art can derive equivalent arrangements of the PNP and NPN arrangements with the main load current flowing through the P-type region.

[0055] Refer again Figure 3AThe exemplary DSDB-BJT 200 is shown as a monolithic structure. That is, the upper base 202 and the upper collector-emitter 206 are associated with or close to the upper portion of the drift region 304. Similarly, the lower base 204 and the lower collector-emitter 208 are associated with or close to the lower portion of the drift region 304. The exemplary drift region 304 is a continuous structure. The exemplary DSDB-BJT 200 can be manufactured by forming the upper base 202 and the upper collector-emitter 206 on the upper side of the wafer. The wafer is then flipped and bonded to a disposal wafer, and thereafter the lower base 204 and the lower collector-emitter 208 are formed on a second side of the wafer. Having a continuous drift region 304 means that, for the positive polarity at the upper terminal 102, charge carriers are injected into the upper base 202 (e.g., Figure 3C The amount of charge carriers injected from both sides is sufficient to reduce Vceon, making it possible to inject charge carriers from both sides (e.g., Figure 3D This provides a small additional benefit. In other words, for a device in which the drift region 304 is continuous, charge carriers are injected into the emitter-base junction (e.g., Figure 3C In many cases, this provides sufficient Vceon reduction, and due to the injection of charge carriers in the collector-base junction (e.g., Figure 3D The resulting further increase in forward voltage drop may not justify the additional component and part count.

[0056] However, in other cases, DSDB-BJTs can be produced using discontinuous drift regions. For example, DSDB-BJTs can be manufactured by producing multiple partial components, each including a base region, a collector-emitter region, and a drift region. The partial components can be cut or split, and then the drift regions of two partial components can be bonded to produce the DSDB-BJT. However, DSDB-BJTs with discontinuous drift regions can be produced according to… Figures 3A-3F Either of these can be used for operation, although for discontinuous drift regions, charge carriers are injected from both sides of the device. Figure 3D The active connection deployment is comparable to Figure 3E One-sided injection of charge carriers has advantages.

[0057] In various examples, charge carrier injection can take many forms. Specifically, Figure 3C and 3D Examples use voltage sources. In cases where voltage is injected from both sides of the device (e.g., Figure 3DThe voltages may be the same. For example, the voltage provided by source 302 may be the same as the voltage provided by source 306. In other cases, the voltages may be different. For example, the voltage on the collector side (e.g., source 302) may be greater than the voltage on the emitter side (e.g., source 306).

[0058] In other cases, charge carrier injection can be achieved using a current source. Figure 3C In the example, source 302 can provide a setpoint current independent of the voltage used to drive the setpoint current. Figure 3D In the example where charge carriers are injected from both sides, the magnitude of the current supplied to the upper base 202 may be the same as the magnitude of the current supplied to the lower base 204. In other cases, the magnitude of the current supplied to the upper base 202 may differ from the magnitude of the control current supplied to the lower base 204. All such variations are contained in the specification and claims.

[0059] Figure 4 Partial block diagrams and partial electrical schematics of an exemplary switch assembly 100 are shown. Specifically, the exemplary switch assembly 100 includes an exemplary DSDB-BJT 200 of PNP construction and a driver 108. The DSDB-BJT 200 is shown by exemplary circuit symbols having two emitters and two bases. The circuit symbols show an upper base 202, a lower base 204, an upper collector-emitter 206, and a lower collector-emitter 208. The exemplary driver 108 defines an upper collector-emitter terminal 408 coupled to the upper collector-emitter 206, an upper conductive terminal 410 coupled to the upper base 204, a lower collector-emitter terminal 412 coupled to the lower collector-emitter 208, and a lower conductive terminal 414 coupled to the lower base 204.

[0060] The exemplary driver 108 includes a controller 416, an electrical isolator 418, and an isolation transformer 420. To place the DSDB-BJT 200 in various conducted and non-conducted modes, the exemplary driver 108 includes multiple electrically controlled switches and charge carrier sources. Specifically, the exemplary driver 108 includes a switch 422 having a first lead coupled to an upper terminal 102, a second lead coupled to an upper base 202, and a control input coupled to the controller 416. The exemplary switch 422 is shown as a single-pole single-throw switch, but in practice, the switch 422 can be a FET, with its control input being the gate of the FET. Therefore, when the switch 422 is turned on by asserting its control input, the upper base 202 is coupled to the upper terminal 102.

[0061] The driver 108 further includes a source 302, illustratively shown as a battery. Source 302 has a negative lead coupled to the upper terminal 102. Another electrically controlled switch 426 (hereinafter referred to as switch 426) has a first lead coupled to the positive terminal of source 302, a second lead coupled to the upper base 202, and a control input coupled to the controller 416. The exemplary switch 426 is also shown as a single-pole single-throw switch, but in practice, switch 426 can be a FET, with its control input being the gate of the FET. Therefore, when switch 426 is turned on, source 302 is coupled between the upper terminal 102 and the upper base 202.

[0062] The driver 108 further includes a source 428, illustratively shown as a battery. Source 428 has a negative lead coupled to the upper terminal 102. Another electrically controlled switch 430 (hereinafter referred to as switch 430) has a first lead coupled to the positive terminal of source 428, a second lead coupled to the upper collector-emitter 206, and a control input coupled to controller 416. The exemplary switch 430 is also shown as a single-pole single-throw switch, but in practice, switch 430 can be a FET, with its control input being the gate of the FET. Therefore, when switches 422 and 430 are turned on, source 428 is coupled between the upper base 202 and the upper collector-emitter 206 (e.g., for a reverse recovery of an externally applied voltage corrected at the lower terminal 104, or for an alternative reverse recovery of an externally applied voltage corrected at the upper terminal 102).

[0063] The driver 108 further includes an upper cascode FET 220. The upper cascode FET 220 is schematically shown as a single-pole single-throw switch. Thus, when the upper collector FET 220 is turned on, for example by asserting its control input, the upper terminal 102 is coupled to the upper collector-emitter 206.

[0064] Turning now to the lower side of the DSDB-BJT 200, the exemplary driver 108 further includes a switch 432 having a first lead coupled to a lower terminal 104, a second lead coupled to a lower base 204, and a control input coupled to a controller 416. The exemplary switch 432 is shown as a single-pole single-throw switch, but in practice, the switch 432 can be a FET, with its control input being the gate of the FET. Therefore, when the switch 432 is turned on by asserting its control input, the lower base 204 is coupled to the lower terminal 104.

[0065] The driver 108 further includes a source 306, exemplarily shown as a battery. Source 306 has a negative lead coupled to a lower terminal 104. Another electrically controlled switch 436 (hereinafter referred to as switch 436) has a first lead coupled to the positive terminal of source 306, a second lead coupled to the lower base 204, and a control input coupled to controller 416. The exemplary switch 436 is shown as a single-pole single-throw switch, but in practice, switch 436 can be a FET, with its control input being the gate of the FET. Therefore, when switch 436 is turned on, source 306 is coupled between the lower terminal 104 and the lower base 204.

[0066] The exemplary driver 108 further includes a source 308, exemplarily shown as a battery. Source 308 has a negative lead coupled to a lower terminal 104. Another electrically controlled switch 440 (hereinafter referred to as switch 440) has a first lead coupled to the positive terminal of source 308, a second lead coupled to a lower collector-emitter 208, and a control input coupled to controller 416. The exemplary switch 440 is shown as a single-pole single-throw switch, but in practice, switch 440 can be a FET, with its control input being the gate of the FET. Therefore, when switches 432 and 440 are turned on, source 308 is coupled between the lower base 204 and the lower collector-emitter 208 (e.g., ...). Figure 3F (The reverse recovery shown in the figure).

[0067] The exemplary driver 108 further includes a lower cascode FET 210. The lower cascode FET 210 is shown as a single-pole single-throw switch. Thus, when the lower cascode FET 210 is turned on, for example by asserting that its control input is on, the lower terminal 104 is coupled to the lower collector-emitter.

[0068] Controller 416 defines control inputs 442 and 444 and control outputs 446, 448, 450, 452, 454, 456, 458, and 460, which are respectively coupled to the control inputs of the upper cascode FET 220, switches 430, 426, 422, 432, 436, and 440, and the lower cascode FET 210. When control input 442 is asserted, controller 416 is designed and configured to arrange the DSDB-BJT 200 to conduct current from the upper terminal 102 to the lower terminal 104. Conversely, when control input 442 is deasserted, controller 416 is designed and configured to arrange the DSDB-BJT 200 to block current flow from the upper terminal 102 to the lower terminal 104. Similarly, when control input 444 is asserted, controller 416 is designed and configured to arrange DSDB-BJT 200 to conduct current from lower terminal 104 to upper terminal 102. Conversely, when control input 444 is deasserted, controller 416 is designed and configured to arrange DSDB-BJT 200 to block current flow from lower terminal 104 to upper terminal 102. When both control inputs 442 and 444 are asserted, controller 416 arranges DSDB-BJT 200 to allow current to flow in both directions (e.g., AC circuit breaker service), and when both control inputs 442 and 444 are deasserted, controller 416 blocks current flow in both directions.

[0069] The arrangement of the non-conductive DSDB-BJT 200 depends on the polarity of the applied voltage. Therefore, the exemplary controller 416 may further define a polarity input 462 that receives a Boolean indication of the applied polarity. In the exemplary driver 108, the comparator 480 has a first input coupled to the upper terminal 102 (the connection shown by bubble "A") and a second input coupled to the lower terminal 104. The comparator 480 defines a comparison output coupled to the polarity input 462. Although... Figure 4 The first and second inputs are shown as being directly coupled to their respective conductive terminals. However, in practice, when not conducting, the voltage across the DSDB-BJT 200 can be very large (e.g., 1200 V), and therefore each of the first and second inputs can be coupled to its respective conductive terminal via a corresponding voltage divider circuit. In a further embodiment, the applied polarity can be determined by systems and devices external to the switch assembly 100, and a Boolean signal is sent across the electrical isolator 418 to the polarity input 464.

[0070] Changing the DSDB-BJT 200 from non-conducting to conducting and then back to non-conducting may be a multi-step process. To implement this multi-step process, the controller 416 may be an individual circuit component, application-specific integrated circuit (ASIC), microcontroller with control software, reduced instruction set computing (RISC), digital signal processor (DSP), processor with control software, programmable logic device (PLD), field-programmable gate array (FPGA), system-programmable single-chip (PSOC), and / or combinations thereof.

[0071] In the exemplary system, the switch assembly 100 is electrically floating. To receive control inputs 442 and 444 in the electrical domain of the switch assembly 100, the exemplary driver 108 implements an electrical isolator 418. The exemplary electrical isolator 418 may take any suitable form, such as an optocoupler or a capacitive isolation device. Regardless of the precise nature of the electrical isolator 418, external control signals (e.g., Boolean signals) may be coupled to control inputs 464 and 466 of the electrical isolator 418. Either control input 464 or 466 may be... Figure 1 The control terminal 106 is schematically shown. The electrical isolator 418 then transmits the control signal to the electrical domain of the switch assembly 100. In this example, external control signals are transmitted to become control inputs 442 and 444 of the controller 416.

[0072] Turning now to isolation transformer 420. Various devices within switch assembly 100 can utilize operating power. For example, controller 416 can utilize bus voltage and power to enable various operating modes of the DSDB-BJT 200. Furthermore, sources within the system can be implemented as individual voltage sources in the form of switch power converters, or as individual current sources in the form of switch power converters. The switch power converters implementing the sources can utilize bus voltage and power. Isolation transformer 420 is provided to provide operating power within the electrical domain of switch assembly 100. An external system (not specifically shown) can provide an alternating current (AC) signal (e.g., 15 V AC) across the primary leads 468 and 470 of isolation transformer 420. Isolation transformer 420 generates AC voltage on secondary leads 472 and 474. The AC voltage on the secondary side of isolation transformer 420 can be provided to AC-DC power converter 476, which rectifies the AC voltage and passes it through a bus voltage V relative to the common terminal 478. BUSPower is provided at (e.g., 3.3 V, 5 V, 12 V). The power provided by the AC-DC power converter 476 can be used by various components of the switching assembly 100. In other cases, multiple isolation transformers may be present (e.g., one on each side of the DSDB-BJT). Alternatively, a single isolation transformer with multiple secondary windings may be used. The discussion now turns to exemplary arrangements for turning the DSDB-BJT 200 on and / or off in the case of the switching assembly 100.

[0073] As an example, consider the case where the applied voltage has a positive polarity at the upper terminal 102. Further consider the case where the control input 464 applied to the isolator 418 is deasserted, and therefore the control signal applied to the control input 442 of the controller 416 is deasserted. Based on the deasserted state of the control input 442, considering the applied polarity (e.g., read by the controller 416 via the polarity input 462), the controller 416 is designed and configured to place the DSDB-BJT 200 in a non-conducting arrangement. Therefore, in the example arrangement, the upper cascode FET 220 is turned on, the lower cascode FET 210 is not turned on, and the switch 432 is turned on (passively turned off). In some examples, the controller 416 asserts the control output 446, causing the upper cascode FET 220 to turn on. However, in other cases, the body diode of the upper cascode FET 220, and therefore the conductivity of the upper cascode FET 220, may be based at least initially on the applied voltage that forward-biases the body diode of the FET. A similar arrangement and / or operation may exist for the lower cascode FET 210 when arranged to block currents of opposite polarity.

[0074] Still considering the exemplary arrangement of positive polarity at the upper terminal 102, it is now considered that the control signal applied to the control input 464 of the electrical isolator 418 is asserted, and therefore the control signal applied to the control input 442 of the controller 416 is also asserted. Based on this assertion, in the exemplary switch assembly 100, the controller 416 can be designed and configured to place the DSDB-BJT200 directly in an active-on arrangement. Figure 3CTo this end, controller 416 may assert control output 446 (if not already asserted) to turn on the upper cascode FET 220, assert control output 450 to turn on switch 426, assert control output 460 to turn on the lower cascode FET 210, and deassert or remain deasserted on the remaining control outputs. In other cases, to put DSDB-BJT 200 into the on state, controller 416 may be designed and configured to turn on switch 426 for a predetermined period of time (e.g., from about 0.1 μs to 5 μs) before the lower cascode FET 210 is made. Turning on switch 426 before turning on the lower cascode FET 210 charges the upper collector-emitter 206 to the upper base 202 capacitor, allowing DSDB-BJT 200 to turn on more quickly once the lower cascode FET 210 is turned on. In some cases, controller 416 may be designed and configured to implement Figure 3D The alternative active turn-on arrangement is used, and therefore the controller 416 can also assert the control output 456 to couple the source 306 between the lower terminal 104 and the lower base 204.

[0075] Optionally, by again utilizing the positive polarity at the upper terminal 102, the controller 416 can be designed and configured to pass the DSDB-BJT 200 through an intermediate conduction arrangement before it reaches the active-on arrangement. For example, the controller 416 can temporarily place the DSDB-BJT 200 in a passive-on arrangement. Figure 3B When in use, the passive switching arrangement can be maintained for a predetermined period of time (e.g., from about 0.1 μs to 5 μs).

[0076] In the active-on configuration, and with positive polarity at the upper terminal 102, the source 302 injects charge carriers into the upper base 202. Injecting charge carriers into the upper base 202 increases the number of charge carriers in the drift region of the DSDB-BJT 200, which reduces the V measured across the collector-emitter junctions 206 and 208. CEON In one example, for a current of approximately 30 A to 100 A flowing through collector-emitter 206 and 208, source 302 injecting charge carriers can reduce VA. CEON Reduced to approximately 0.2 V. Source 302 can be used with any suitable voltage between 0.5 V and 5.0 V, and in some cases between 0.6 V and 1.5 V.

[0077] Still referencing Figure 4Furthermore, the positive polarity on the upper terminal 102 is still considered. Further consideration is given to the control input 464 applied to the electrical isolator 418 changing from assertion to deassertion, and therefore the control signal applied to the control input 442 of the controller 416 changing from assertion to deassertion. Based on this change, the controller 416 is designed and configured to place the DSDB-BJT 200 in a reverse recovery arrangement. Figure 3F To this end, controller 416 deasserts control output 460 to de-enable the lower cascode FET 210, thereby interrupting the main load current through the DSDB-BJT 200; deasserts control output 450 to de-enable switch 426; asserts control output 454 to en-enable switch 432, thereby coupling the lower base 204 to the lower terminal 104; and asserts control output 458 to en-enable switch 440, thereby coupling the source 308 between the lower base 204 and the lower collector-emitter 208. As previously described, the reverse recovery arrangement can be implemented for a predetermined time period, in some cases approximately 400 nanoseconds. Afterward, controller 416 can switch the DSDB-BJT 200 to... Figure 3A Passive shutdown arrangement.

[0078] about Figure 4 The exemplary operation described utilizes the positive polarity on the upper terminal 102. However, again, the exemplary DSDB-BJT 200 and its associated driver 108 are symmetrical, and it is now understood how the DSDB-BJT 200 can be arranged in various on and off states, directly following the control of current flow in the opposite direction.

[0079] Figure 5 A method of operating a switch assembly according to at least some embodiments is illustrated. Specifically, the method begins (block 500) and includes: conducting a forward load current from the upper terminal of the switch assembly to the upper collector-emitter of the DSDB-BJT, through the DSDB-BJT, out through the lower collector-emitter of the DSDB-BJT, and then through the lower terminal of the switch assembly (block 502); and then stopping the conduction of the forward load current (block 504). The stopping of the forward load current can be achieved by coupling the lower base of the DSDB-BJT to the lower terminal (block 506); and driving a pinch-off voltage to the lower collector-emitter of the DSDB-BJT to reduce the reverse recovery current through the lower base (block 508). The method then ends (block 510).

[0080] Many electrical connections in the accompanying drawings are shown as direct couplings without intermediaries, but this is not explicitly stated in the description above. However, this paragraph should serve as a preliminary basis in the claims for referring to any electrical connection as a “direct coupling” in connection with the direct couplings shown in the drawings. Furthermore, this paragraph should not preclude the term “direct coupling” from referring to a base connected via a transistor to the collector-emitter junction.

[0081] The foregoing discussion is intended to illustrate the principles and various embodiments of the invention. Once fully understanding the above disclosure, those skilled in the art will recognize numerous variations and modifications. The appended claims are intended to be interpreted as encompassing all such variations and modifications.

Claims

1. A method for operating a switch assembly, the method comprising: The forward load current is conducted from the upper terminal of the switching assembly to the upper collector-emitter of the dual-base bipolar junction transistor (DSDB-BJT), flows through the DSDB-BJT, and exits through the lower collector-emitter of the DSDB-BJT; and then... The conduction of the positive load current is stopped by the following method: The lower base of the DSDB-BJT is coupled to the lower terminal; and The pinch-off voltage is driven to the lower collector-emitter of the DSDB-BJT to reduce the reverse recovery current through the lower base.

2. The method of claim 1, wherein driving the pinch-off voltage to the lower collector-emitter comprises: Drive the pinch-off voltage for a predetermined period of time during which the lower collector-emitter junction remains non-zero; And then The lower collector-emitter junction is made to float.

3. The method of claim 1, wherein driving the pinch-off voltage to the lower collector-emitter comprises: The pinch-off voltage is driven to the lower collector-emitter junction for a duration between 200 nanoseconds and 500 nanoseconds, including the boundary value. And then The lower collector-emitter junction is made to float.

4. The method of claim 1, wherein driving the pinch-off voltage to the lower collector-emitter comprises driving the pinch-off voltage between 10 volts and 50 volts, and including both 10 volts and 50 volts.

5. The method of claim 1, wherein driving the pinch-off voltage to the lower collector-emitter includes driving the pinch-off voltage at approximately 30 volts.

6. The method of claim 1, wherein conducting the main load current comprises injecting charge carriers into the upper drift region of the DSDB-BJT.

7. The method of claim 6, wherein injecting charge carriers into the upper drift region comprises injecting charge carriers through the upper base of the DSDB-BJT.

8. The method of claim 6, wherein conducting the main load current further comprises injecting charge carriers into the lower drift region of the DSDB-BJT.

9. The method of claim 8, wherein injecting charge carriers into the lower drift region comprises injecting charge carriers through the lower base of the DSDB-BJT.

10. The method of claim 1, further comprising: The reverse load current is conducted from the lower terminal of the switching assembly to the upper collector-emitter junction, through the DSDB-BJT, out through the upper collector-emitter junction, and then through the upper terminal of the switching assembly; and then The conduction of the reverse load current can be stopped by the following method: Couple the upper base to the upper terminal; and The pinch-off voltage is driven to the upper collector-emitter of the DSDB-BJT to reduce the reverse recovery current through the upper base.

11. A switch assembly comprising: Upper terminals, lower terminals, and control inputs; A double-sided double-base bipolar junction transistor (DSDB-BJT) defines an upper base, an upper collector-emitter junction, a lower base, and a lower collector-emitter junction. The upper main FET defines a first lead coupled to the upper terminal, a second lead coupled to the upper collector-emitter, and a gate; The lower main FET defines a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate; A driver coupled to the control input, the gate of the upper main FET, the gate of the lower main FET, and the upper and lower bases of the DSDB-BJT; In response to the assertion of the control input, and for a first applied voltage across the upper and lower terminals, the driver is configured to arrange the DSDB-BJT such that the main load current flows from the upper terminal of the switching assembly to the upper collector-emitter of the DSDB-BJT, through the DSDB-BJT, out through the lower collector-emitter, and then through the lower terminal of the switching assembly; and In response to the release assertion of the control input, and for the first applied voltage, the driver is configured to stop the conduction of the main load current in such a way as follows: The lower base of the DSDB-BJT is coupled to the lower terminal; and The pinch-off voltage is driven to the lower collector-emitter junction to reduce the reverse recovery current through the lower base.

12. The switching assembly of claim 11, wherein when the driver drives the pinch-off voltage to the lower collector-emitter junction, the driver is configured to: The pinch-off voltage is driven until the lower collector-emitter junction remains non-zero for a predetermined period of time; and then The lower collector-emitter junction is made to float.

13. The switching assembly of claim 11, wherein when the driver drives the pinch-off voltage to the lower collector-emitter junction, the driver is configured to: The pinch-off voltage is driven to the lower collector-emitter junction for a duration between 200 nanoseconds and 500 nanoseconds, including the boundary value; and then... The lower collector-emitter junction is made to float.

14. The switching assembly of claim 11, wherein when the driver drives the pinch-off voltage to the lower collector-emitter, the driver is configured to drive the pinch-off voltage between 10 volts and 50 volts and including both 10 volts and 50 volts.

15. The switching assembly of claim 11, wherein the driver is configured to drive the pinch-off voltage of approximately 30 volts when the driver drives the pinch-off voltage to the lower collector-emitter.

16. The switching assembly of claim 11, wherein when the driver is arranged to conduct the main load current to the DSDB-BJT, the driver is configured to inject charge carriers into the upper drift region of the DSDB-BJT.

17. The switching assembly of claim 16, wherein when the driver injects charge carriers into the upper drift region, the driver is configured to inject charge carriers through the upper base of the DSDB-BJT.

18. The switching assembly of claim 16, wherein when the driver is arranged to conduct the main load current to the DSDB-BJT, the driver is configured to inject charge carriers into the lower drift region of the DSDB-BJT.

19. The switching assembly of claim 18, wherein when the driver injects charge carriers into the lower drift region, the driver is configured to inject charge carriers through the lower base of the DSDB-BJT.

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