Method, apparatus and system for polar encoding with parity check

Abstract

Methods, apparatuses, and systems for parity check polar encoding are described. A parity check encoding vector is generated based on a bit vector of information bits to be encoded. The parity check encoding vector includes a plurality of sub-blocks, where information bits of a first sub-vector of the bit vector are assigned to information bit positions of a first sub-block of the plurality of sub-blocks, and one or more parity check bits generated from the information bits of the first sub-vector are assigned to frozen bit positions of the first sub-block. A parity check polar codeword is generated by applying a polar code to the parity check encoding vector. The parity check polar codeword is output.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 608,940, filed December 12, 2023, entitled “METHODS, APPARATUS, AND SYSTEM FOR PARITY-CHECKPOLAR CODING”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to wireless communications, and more particularly to methods, apparatus and systems for parity-check (PC) polar coding. Background Technology

[0004] In wireless communication, channel quality constantly changes due to fading effects at both fast and slow scales. Therefore, channel coding design always aims to adapt to channel conditions. Adaptive modulation and coding schemes (MCS) are an effective method for handling changes in channel conditions, with the core being the real-time adjustment of modulation order, code length, and coding rate. Therefore, the channel coding scheme needs to be able to flexibly adjust the code length and code rate in a fine-grained manner, while simultaneously achieving good error correction performance under all possible configurations. This fine-grained flexibility of channel codes is one of the most challenging problems faced by engineers in this field.

[0005] At the same time, the complexity of both encoding and decoding algorithms needs to be sufficiently low. On the hardware side, complexity can be assessed by measuring chip area and energy efficiency. These are related to algorithm complexity, but more closely related to hardware cost and battery life. Therefore, when designing encoding schemes, it is necessary to reduce implementation complexity.

[0006] Future communication systems, such as the so-called sixth-generation (6G) systems, are likely designed to support several challenging scenarios, including immersive communication, massive MIMO, and ultra-reliable and low-latency communication. Key performance indicators (KPIs) related to channel coding include coding gain, reliability, throughput, latency, and the trade-offs between these metrics. For example, 6G could target throughput exceeding 1 Tbps while reducing energy efficiency to 1 pJ / bit. Coding schemes supporting flexible rate matching and incremental redundancy-hybrid automatic repeat request (IR-HARQ) are also beneficial. Therefore, designing code sets to achieve all these KPIs and capabilities is challenging. Summary of the Invention

[0007] In various examples, this disclosure describes methods, systems, and apparatuses for PC polar coding. In the examples disclosed herein, PC coding and polar coding can be used to generate PC polar codewords. IR-HARQ retransmission of polar codes can also be supported by the examples disclosed herein.

[0008] Examples of this disclosure include possible configurations for PC polar coding based on physical channel type and / or code parameters and / or application scenario. Examples of this disclosure include possible configurations for PC polar coding, such as carrying PC bits by allowing some or all of the frozen bit positions. Compared to existing techniques for PC polar coding, examples of this disclosure can provide technical advantages by achieving more stable performance over a wider range of code lengths and code rates. Examples of this disclosure can provide the following technical advantages: support for PC polar coding with longer code lengths (e.g., greater than 20) and more stable performance (e.g., lower bit error rate).

[0009] Examples of this disclosure include possible configurations for generating polar codewords, wherein PC encoding is used on different sub-blocks of the codeword. By implementing PC polar coding that performs PC encoding on a sub-block basis (rather than the entire codeword), computational resource savings can be achieved. For example, the decoder may only need to decode one sub-block at a time, instead of decoding the entire codeword. This means the decoder may require fewer memory resources and less chip area. Similarly, the decoder can be able to successfully decode a sub-block independently of any other sub-block of the codeword. This means different sub-blocks can be transmitted separately. Therefore, examples of this disclosure can provide technical advantages by supporting the use of PC polar coding in various retransmission schemes that include multiple transmissions and retransmissions of different sub-blocks encoded as codewords (e.g., with multiple redundant versions). The examples disclosed herein can also support IR-HARQ retransmissions of low-density parity-check (LDPC) and polar codes.

[0010] Exemplary methods according to embodiments of this disclosure may include rules or configurations for determining whether and how to perform PC encoding (e.g., whether to perform PC encoding based on physical channel type and / or code parameters and / or application scenario); how to perform PC encoding (marking frozen bits as PC bits, etc.) and / or methods for performing PC encoding on different parts of the code (e.g., methods for performing subblock-wise PC encoding; performing PC encoding on different subblocks of the code; performing PC encoding on different redundant versions and transmissions, etc.).

[0011] Some embodiments of this disclosure may include one or more of the following features, which may be used individually or together as a complete solution.

[0012] An exemplary first aspect of this disclosure relates to a method for determining whether to perform PC encoding, comprising one or more of the following features: a rule for specifying whether to perform PC encoding based on a physical channel type; a rule for specifying whether to perform PC encoding based on code parameters; a rule for specifying whether to perform PC encoding based on both physical channel type and code parameters; a rule for specifying whether to perform PC encoding based on an application scenario and priority; and / or a rule for specifying different ways of performing PC encoding under different physical channels and encoding parameters and selecting which way to perform the encoding.

[0013] An exemplary second aspect of this disclosure relates to a method for performing PC encoding on different portions of a code. The method may include one or more of the following configurations: applying PC encoding to different sub-blocks of the code; and / or applying PC encoding to different redundant versions and transmissions.

[0014] The following section will further describe additional details of the disclosed examples and their technical advantages.

[0015] In one exemplary aspect, this disclosure describes a method for generating codewords, the method comprising: generating a parity check coding vector based on a bit vector of information bits to be encoded, the parity check coding vector comprising a plurality of sub-blocks, wherein information bits of a first sub-vector of the bit vector are assigned to information bit positions of a first sub-block among the plurality of sub-blocks, and one or more parity bits generated from the information bits of the first sub-vector are assigned to frozen bit positions of the first sub-block; generating a parity check polar codeword by applying polar codes to the parity check coding vector; and outputting the parity check polar codeword.

[0016] In one example of the above exemplary aspect, the one or more parity bits assigned to the freeze bit position of the first sub-block may be generated independently of the second sub-block among the plurality of sub-blocks.

[0017] In one example of the above exemplary aspect, the information bits of the second subvector of the bit vector may be assigned to the information bit positions of the second subblock, and the second subblock may have no parity bit.

[0018] In one example of the above exemplary aspect, the one or more parity bits generated from the information bits of the first subvector can form a first set of one or more parity bits; the information bits of the second subvector of the bit vector can be assigned to the information bit positions of the second subblock; the second set of one or more parity bits generated from the information bits of the second subvector can be assigned to the frozen bit positions of the second subblock, and the first set of one or more parity bits can be decoupled from the second set of one or more parity bits.

[0019] In one example of the above exemplary aspect, a circular shift register may be used to generate a first set of the one or more parity bits and a second set of the one or more parity bits, and the circular shift register may be cleared between generating the first set of the one or more parity bits and generating the second set of the one or more parity bits.

[0020] In one example of the above exemplary aspect, the circular shift register can be cleared by resetting all bit values ​​stored in the circular shift register to a single predefined value or a set of predefined values.

[0021] In one example of the exemplary aspects described above, the set of predefined values ​​may be based on a radio network temporary identifier (RNTI).

[0022] In one example of some of the exemplary aspects described above, a circular shift register may be used to generate the one or more parity bits from the information bits of the first subvector.

[0023] In one example of some of the above exemplary aspects, the pretransformation matrix may be used to generate the one or more parity bits from the information bits of the first subvector.

[0024] In one example of the above exemplary aspect, the pre-transformation matrix may be an upper triangular matrix.

[0025] In one example of some of the exemplary aspects described above, a hash function may be used to generate the one or more parity bits from the information bits of the first subvector.

[0026] In one example of some of the exemplary aspects described above, a lookup table may be used to generate the one or more parity bits from the information bits of the first subvector.

[0027] In any of the above exemplary aspects, the bit length of the first subvector may be a power of 2.

[0028] In any of the above exemplary aspects, the bit vector of the information bits may include a first polarization codeword for data transmission with a first redundancy version and a second polarization codeword for another data transmission with a second redundancy version, and the first subvector may correspond to the first polarization codeword.

[0029] In one example of the above exemplary aspect, the data transmission with a first redundant version may be an initial data transmission, and the data transmission with a second redundant version may be a data retransmission.

[0030] In any of the above exemplary aspects, all frozen bit positions in the first sub-block whose index is greater than the index of the first information bit in the first sub-block can be allocated to carry parity bits.

[0031] In any of the above exemplary aspects, the parity polarization codeword may be generated based on the type of the physical channel through which the parity polarization codeword is to be transmitted.

[0032] In one example of the above exemplary aspects, the parity check polar code may be generated based on: the physical channel type being a physical uplink control channel carrying uplink control including indication feedback and scheduling request information; the physical channel type being a physical uplink control channel carrying uplink control including indication channel state information; the physical channel type being a physical uplink control channel not multiplexed on a physical uplink shared channel; the physical channel type being an arbitrary physical uplink control channel; the physical channel type being a physical uplink control channel or a physical broadcast channel; the physical channel type being a physical uplink control channel or a physical downlink control channel; the physical channel type being a physical uplink control channel, a physical downlink control channel, or a physical broadcast channel; the physical channel type being a level 1 physical downlink control channel; the physical channel type being an arbitrary physical control channel; or the physical channel type being an arbitrary physical uplink channel.

[0033] In any of the above exemplary aspects, the parity polar codeword may be generated based on one or more code parameters.

[0034] In one example of the exemplary aspects described above, the one or more code parameters may include one or more of the following: code length within the maximum code length; block length within the maximum block length; code rate within the maximum code rate; or code length within the maximum code length and code rate within the maximum code rate.

[0035] In any of the above exemplary aspects, the parity polar codeword may be generated based on one or more communication scenarios.

[0036] In one example of the exemplary aspects described above, the one or more communication scenarios may include one or more of the following: communication for ultra-reliable low-latency communication; or communication for high-priority communication.

[0037] In any of the above exemplary aspects, the method may further include: transmitting the parity-check polar codeword via a communication channel.

[0038] In any of the above exemplary aspects, the method may further include: obtaining the bit vector of the information bits.

[0039] In another exemplary aspect, this disclosure describes a method for decoding a codeword, the method comprising: decoding the first sub-block by using one or more parity bits in at least a first sub-block of a parity-polarized codeword having a plurality of sub-blocks to assist in decoding the first sub-block; and outputting the decoded first sub-block.

[0040] In one example of the above exemplary aspect, the first sub-block may be received in the absence of a second sub-block among the plurality of sub-blocks.

[0041] In one example of the above exemplary aspect, the second sub-block of the plurality of sub-blocks may have no parity bit, and the method further includes: decoding the second sub-block independently of the first sub-block; and outputting the decoded second sub-block.

[0042] In one example of the above exemplary aspect, the method may further include: decoding the second sub-block independently of the first sub-block by using one or more parity bits in a second sub-block of the plurality of sub-blocks to assist in decoding the second sub-block; and outputting the decoded second sub-block.

[0043] In any example of any of the above exemplary aspects, the method may further include: receiving at least the first sub-block.

[0044] In another exemplary aspect, this disclosure describes an apparatus comprising: a processor; and a memory including instructions that, when executed by the processor, cause the apparatus to perform any of the aforementioned exemplary aspects of the method.

[0045] In another exemplary aspect, this disclosure describes an apparatus comprising: an encoding module for performing steps of any of the aforementioned exemplary aspects of a method for generating codewords; and a decoding module for performing a receiving step of any of the aforementioned exemplary aspects of a method for decoding codewords.

[0046] In another exemplary aspect, this disclosure describes a non-transitory computer-readable medium storing machine-executable instructions, characterized in that, when executed by a device, the instructions cause the device to perform any of the aforementioned exemplary aspects of the method.

[0047] In another exemplary aspect, this disclosure describes a processing module for controlling a device to cause the device to perform any of the above exemplary aspects of the method.

[0048] In another exemplary aspect, this disclosure describes a chip or chipset including a processor for executing instructions to cause a device to perform any of the above exemplary aspects of the method.

[0049] In another exemplary aspect, this disclosure describes a computer program that, when run on a computer, causes the computer to perform any of the above exemplary aspects of the method. Attached Figure Description

[0050] The accompanying drawings, which now illustrate exemplary embodiments of this application, are shown by way of example, wherein:

[0051] Figure 1 This is a simplified schematic diagram of a communication system that can be used to implement the examples of this disclosure;

[0052] Figure 2 This is a block diagram illustrating an example of a communication system that can be used to implement the examples of this disclosure;

[0053] Figure 3 This is a block diagram illustrating an example of a communication system that can be used to implement the examples of this disclosure;

[0054] Figure 4 This is a block diagram illustrating exemplary units or modules in a device that can be used to implement examples of this disclosure;

[0055] Figure 5 This is a grid diagram illustrating examples of polar codes that can be used to implement examples of this disclosure;

[0056] Figure 6 This is a table illustrating exemplary interleaver schemes that can be used to implement examples of this disclosure;

[0057] Figure 7 An example of punching or truncating using a circular buffer that can be used to implement the examples of this disclosure is shown;

[0058] Figure 8 An exemplary collection of transports with incremental freezing is shown, which can be implemented using examples of this disclosure;

[0059] Figure 9 An exemplary implementation of a PC polar coding scheme using a cyclic shift register, implemented using examples of this disclosure, is shown;

[0060] Figure 10 An example of polar coding in an IR-HARQ scheme implemented using examples of this disclosure is shown;

[0061] Figure 11 Examples of polarization transformation matrices that can be used to implement this disclosure and can be used for different transmissions in an IR-HARQ scheme are shown;

[0062] Figure 12 An example is shown of how information bits are encoded to generate PC-polarized encoded bits according to an example of this disclosure;

[0063] Figures 13A to 13C Examples of how PC encoding according to this disclosure can be applied to different sub-blocks of polar codewords are shown;

[0064] Figure 14Examples of how PC encoding according to this disclosure can be applied to arbitrary sub-blocks of polar codewords are shown;

[0065] Figure 15 Examples of how two shorter polarization codewords according to this disclosure can be further combined and polarized into longer polarization codewords are shown;

[0066] Figure 16 Exemplary codewords are shown in the example according to this disclosure, in which different sub-blocks correspond to data transmissions with different redundancy versions;

[0067] Figure 17 Another exemplary codeword is shown, according to an example of this disclosure, in which different sub-blocks correspond to data transmissions with different redundancy versions;

[0068] Figure 18 Exemplary pseudocode for applying PC encoding to generate vectors to be encoded as polar codewords, according to an example of this disclosure, is shown;

[0069] Figure 19 Exemplary pseudocode is shown for generating vectors to be encoded as polar codewords without PC encoding, according to examples of this disclosure;

[0070] Figure 20A and Figure 20B This is a block diagram illustrating exemplary units or modules in a device that can be used to implement examples of this disclosure;

[0071] Figure 20C An example of a code chain that can be used to implement the examples of this disclosure is shown;

[0072] Figure 21 This is a flowchart illustrating an exemplary method for generating PC polar codewords according to an example of this disclosure; and

[0073] Figure 22 This is a flowchart illustrating an exemplary method for decoding PC polarized codewords according to an example of this disclosure.

[0074] Similar reference numerals may be used in different accompanying drawings to denote similar components. Detailed Implementation

[0075] In various examples, this disclosure describes methods, apparatus, and systems for PC polar coding. The examples of this disclosure can implement PC polar coding methods in which PC coding is used in conjunction with polar coding in a coding chain. The examples disclosed herein can support the use of PC polar coding in retransmission schemes (e.g., with multiple redundant versions).

[0076] To aid in understanding this disclosure, first refer to Figure 1.

[0077] refer to Figure 1 As a non-limiting illustrative example, a simplified schematic diagram of a communication system is provided. Communication system 100 includes a radio access network 120. Radio access network 120 can be a next-generation (e.g., sixth-generation, 6G, or later) radio access network or a traditional (e.g., 5G, 4G, 3G, or 2G) radio access network. One or more electronic devices (EDs) 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h, 110i, 110j (collectively referred to as 110) can be interconnected with each other or connected to one or more network nodes (170a, 170b, collectively referred to as 170) within radio access network 120. Core network 130 can be part of the communication system and can depend on or be independent of the radio access technology used in communication system 100. In addition, the communication system 100 includes a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160.

[0078] Figure 2 An exemplary communication system 100 is illustrated. Typically, the communication system 100 enables multiple wireless or wired components to transmit data and other content. The purpose of the communication system 100 may be to provide content such as voice, data, video, and / or text via broadcast, multicast, unicast, etc. The communication system 100 can operate by sharing resources (e.g., carrier spectrum bandwidth) among its constituent components. The communication system 100 may include terrestrial communication systems and / or non-terrestrial communication systems. The communication system 100 can provide a wide variety of communication services and applications (such as earth monitoring, remote sensing, passive sensing and positioning, navigation and tracking, autonomous delivery and mobility, etc.). The communication system 100 can provide high availability and robustness through the joint operation of terrestrial and non-terrestrial communication systems. For example, integrating a non-terrestrial communication system (or components thereof) into a terrestrial communication system can create a heterogeneous network that can be viewed as comprising multiple layers. Compared to traditional communication networks, heterogeneous networks can achieve better overall performance through efficient multi-link joint operation between terrestrial and non-terrestrial networks, more flexible function sharing, and faster physical layer link switching.

[0079] Terrestrial communication systems and non-terrestrial communication systems can be considered subsystems of a communication system. Figure 2In the example shown, communication system 100 includes electronic devices (EDs) 110a, 110b, 110c, and 110d (collectively referred to as ED110), radio access networks (RANs) 120a and 120b, a non-terrestrial communication network 120c, a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160. RANs 120a and 120b include corresponding base stations (BSs) 170a and 170b, which are generally referred to as terrestrial transmit and receive points (T-TRPs) 170a and 170b. The non-terrestrial communication network 120c includes access nodes 172, which are generally referred to as non-terrestrial transmit and receive points (NT-TRPs) 172.

[0080] Any ED 110 can be used, alternatively or additionally, to connect, access, or communicate with any T-TRP 170a, T-TRP 170b, and NT-TRP 172, Internet 150, core network 130, PSTN 140, other network 160, or any combination thereof. In some examples, ED 110a can transmit uplink and / or downlink traffic with T-TRP 170a via terrestrial air interface 190a. In some examples, ED 110a, 110b, 110c, and 110d can also communicate directly with each other via one or more sidelink air interfaces 190b. In some examples, ED 110d can transmit uplink and / or downlink traffic with NT-TRP 172 via non-terrestrial air interface 190c.

[0081] Air interfaces 190a and 190b can use similar communication technologies, such as any suitable wireless access technology. For example, communication system 100 can implement one or more channel access methods in air interfaces 190a and 190b, such as code division multiple access (CDMA), space division multiple access (SDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), and single-carrier FDMA (SC-FDMA) (also known as discrete fourier transform spread OFDMA (DFT-s-OFDMA)). Air interfaces 190a and 190b can employ other higher-dimensional signal spaces, which may involve combinations of orthogonal and / or non-orthogonal dimensions.

[0082] The non-terrestrial air interface 190c enables communication between the ED 110d and one or more NT-TRP 172s via a wireless link or simply through a link. In some examples, the link is a dedicated connection for unicast transmission, a connection for broadcast transmission, or a connection for multicast transmission between a group of ED 110s and one or more NT-TRP 172s.

[0083] RANs 120a and 120b communicate with the core network 130 to provide various services, such as voice, data, and other services, to EDs 110a, 110b, and 110c. RANs 120a and 120b, and / or the core network 130, can communicate directly or indirectly with one or more other RANs (not shown), which may or may not be directly served by the core network 130, and may or may not use the same radio access technology as RANs 120a and / or RAN 120b. The core network 130 can also serve as a gateway access between (i) RANs 120a and 120b, or EDs 110a, 110b, and 110c, or both, and (ii) other networks (e.g., PSTN 140, Internet 150, and other networks 160). Furthermore, some or all of EDs 110a, 110b, and 110c may include the ability to communicate with different wireless networks via different radio links using different radio technologies and / or protocols. Instead of wireless communication (or other than wireless communication), ED 110a, 110b, and 110c can also communicate with service providers or exchanges (not shown) via wired communication channels and with the Internet 150. PSTN 140 may include a circuit-switched telephone network for providing plain old telephone service (POTS). The Internet 150 may include a network of computers and subnets (internal networks) or both, incorporating protocols such as Internet Protocol (IP), Transmission Control Protocol (TCP), and User Datagram Protocol (UDP). ED 110a, 110b, and 110c may be multimode devices capable of operating under various wireless access technologies and include multiple transceivers required to support these technologies.

[0084] Figure 3Another example of an ED 110 and base stations 170a, 170b, and / or 170c is shown. The ED 110 is used to connect people, objects, machines, etc. The ED 110 can be widely used in various scenarios, including, for example, cellular communication, device-to-device (D2D), vehicle-to-everything (V2X), peer-to-peer (P2P), machine-to-machine (M2M), machine-type communications (MTC), internet of things (IoT), virtual reality (VR), augmented reality (AR), mixed reality (MR), metaverse, digital twins, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, drones, robots, remote sensing, passive sensing, positioning, navigation and tracking, autonomous delivery, and mobility.

[0085] Each ED 110 represents any suitable end-user equipment for wireless operation and may include (or be referred to as): user equipment / device (UE), wireless transmit / receive unit (WTRU), mobile station, fixed or mobile subscriber unit, cellular phone, station (STA), machine type communication (MTC) device, personal digital assistant (PDA), smartphone, laptop, computer, tablet, wireless sensor, consumer electronics, smart book, vehicle, car, truck, bus, train, or IoT device, wearable device (e.g., watch, glasses, head-mounted device, etc.), industrial equipment, or devices comprising or including the foregoing (e.g., communication module, modem, or chip), etc. Next-generation ED 110 may be referred to using other terms. Base stations 170a and 170b are T-TRPs, referred to below as T-TRP 170. Similarly, Figure 3As shown, NT-TRP will be referred to as NT-TRP 172 below. Each ED 110 connected to T-TRP 170 and / or NT-TRP 172 can be dynamically or semi-statically started (i.e., established, activated, or enabled), shut down (i.e., released, deactivated, or disabled), and / or configured in response to one or more of connectivity availability and connectivity necessity.

[0086] ED 110 includes a transmitter 201 and a receiver 203 coupled to one or more antennas 204. Only one antenna 204 is shown in the figure to avoid congestion. One, some, or all of the antennas 204 may alternatively be panels. The transmitter 201 and receiver 203 may, for example, be integrated as a transceiver. The transceiver is used to modulate data or other content for transmission by at least one antenna 204 or a network interface controller (NIC). The transceiver may also be used to demodulate data or other content received through at least one antenna 204. Each transceiver includes any suitable structure for generating signals for wireless or wired transmission and / or processing signals received wirelessly or wiredly. Each antenna 204 includes any suitable structure for transmitting and / or receiving wireless or wired signals.

[0087] ED 110 includes at least one memory 208. Memory 208 stores instructions and data used, generated, or acquired by ED 110. For example, memory 208 may store software instructions or modules executed by one or more processing units (e.g., processor 210) for implementing some or all of the functions and / or embodiments described herein. Each memory 208 includes any suitable volatile and / or non-volatile storage and retrieval device. Any suitable type of memory can be used, such as random access memory (RAM), read-only memory (ROM), hard disk, optical disk, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, and on-processor cache, etc.

[0088] ED 110 may also include one or more input / output devices (not shown) or interfaces (such as those connected to...). Figure 1(Wired interface of Internet 150 in the network). Input / output devices or interfaces support interaction with users or other devices in the network. Each input / output device or interface includes any suitable structure for providing or receiving information from the user, and / or for communication on the network interface. Suitable structures include, for example, speakers, microphones, keypads, keyboards, displays, touchscreens, etc.

[0089] ED 110 includes a processor 210 for performing operations, including operations related to: operations related to preparing uplink transmissions to NT-TRP 172 and / or T-TRP 170; operations related to processing downlink transmissions received from NT-TRP 172 and / or T-TRP 170; and operations related to processing sidelink transmissions to and from another ED 110. Processing operations related to preparing uplink transmissions may include operations such as encoding, modulation, transmit beamforming, and symbol generation for transmission. Processing operations related to processing downlink transmissions may include operations such as receive beamforming, demodulation, and decoding of received symbols. According to an embodiment, the downlink transmissions may be received by receiver 203 possibly using receive beamforming, and processor 210 may extract signaling from the downlink transmissions (e.g., by detecting and / or decoding signaling). For example, an example of signaling may be a reference signal transmitted by NT-TRP 172 and / or T-TRP 170. In some embodiments, processor 210 performs transmit beamforming and / or receive beamforming based on beam direction indications (e.g., beam angle information (BAI)) received from T-TRP 170. In some embodiments, processor 210 may perform operations related to network access (e.g., initial access) and / or downlink synchronization, such as operations related to detecting synchronization sequences, decoding, and acquiring system information. In some embodiments, processor 210 may perform channel estimation, for example, using reference signals received from NT-TRP 172 and / or from T-TRP 170.

[0090] Although not shown, processor 210 may be part of transmitter 201 and / or receiver 203. Although not shown, memory 208 may be part of processor 210.

[0091] The processing components of processor 210, transmitter 201, and receiver 203 may each be implemented by the same or different one or more processors for executing instructions stored in memory (e.g., memory 208). Alternatively, some or all of the processing components of processor 210, transmitter 201, and receiver 203 may each be implemented using dedicated circuitry such as a programmable field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or hardware accelerator (e.g., a graphics processing unit (GPU) or artificial intelligence (AI) accelerator).

[0092] In some implementations, the T-TRP 170 can use other names, such as base station, base transceiver station (BTS), wireless base station, network node, network device, network-side device, transmit / receive node, NodeB, evolved NodeB (eNodeB or eNB), home eNodeB, next-generation NodeB (gNB), transmission point (TP), site controller, access point (AP), wireless router, relay station, ground node, ground network device, ground base station, base band unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), location node, etc. The T-TRP 170 can be a macro BS, pico BS, relay node, or donor node, or a combination thereof. T-TRP 170 may refer to the aforementioned device or a component of the aforementioned device (e.g., a communication module, modem, or chip).

[0093] In some embodiments, the various parts of T-TRP 170 may be distributed. For example, some of the modules of T-TRP 170 may be located at the far end of the device housing the antenna 256 of T-TRP 170 and may be coupled to the device housing the antenna 256 via a communication link (not shown) sometimes referred to as a fronthaul (e.g., a common public radio interface (CPRI)). Therefore, in some embodiments, the term T-TRP 170 may also refer to network-side modules that perform processing operations such as determining the location of ED 110, resource allocation (scheduling), message generation, and encoding / decoding, which are not necessarily part of the device housing the antenna 256 of T-TRP 170. These modules may also be coupled to other T-TRPs. In some embodiments, T-TRP 170 may actually be multiple T-TRPs operating together to serve ED 110, for example, through cooperative multicast transmission.

[0094] T-TRP 170 includes at least one transmitter 252 and at least one receiver 254 coupled to one or more antennas 256. Only one antenna 256 is shown in the figure to avoid congestion. One, some, or all of the antennas 256 may alternatively be panels. The transmitter 252 and receiver 254 may be integrated as a transceiver. T-TRP 170 also includes a processor 260 for performing operations including operations related to: preparing downlink transmissions to ED 110, processing uplink transmissions received from ED 110, preparing backhaul transmissions to NT-TRP 172, and processing transmissions received from NT-TRP 172 via backhaul. Processing operations related to preparing downlink or backhaul transmissions may include operations such as encoding, modulation, precoding (e.g., multiple-input multiple-output (MIMO) precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to receiving or backhauling transmissions in the uplink may include receive beamforming, demodulating received symbols, and decoding received symbols. Processor 260 may also perform operations related to network access (e.g., initial access) and / or downlink synchronization, such as generating the contents of a synchronization signal block (SSB), generating system information, etc. In some embodiments, processor 260 also generates an indication of beam direction (e.g., BAI), which scheduler 253 may schedule for transmission. Processor 260 performs other network-side processing operations described herein, such as determining the location of ED 110, determining the deployment location of NT-TRP 172, etc. In some embodiments, processor 260 may generate signaling, such as configuring one or more parameters of ED 110 and / or one or more parameters of NT-TRP 172. Any signaling generated by processor 260 is transmitted by transmitter 252. Note that the term "signaling" as used herein may alternatively be referred to as control signaling. Signaling can be transmitted in physical layer control channels such as the physical downlink control channel (PDCCH). In this case, the signaling can be called dynamic signaling. Signaling transmitted in the downlink physical layer control channel is called downlink control information (DCI). Signaling transmitted in the uplink physical layer control channel is called uplink control information (UCI). Signaling transmitted in the sidelink physical layer control channel is called sidelink control information (SCI).Signaling can be included in higher-layer (e.g., above the physical layer) packets transmitted in physical layer data channels such as the Physical Downlink Shared Channel (PDSCH). In this case, the signaling can be referred to as higher-layer signaling, static signaling, or semi-static signaling. Higher-layer signaling can also refer to radio resource control (RRC) protocol signaling or media access control-control element (MAC-CE) signaling.

[0095] Scheduler 253 may be coupled to processor 260. Scheduler 253 may be included within T-TRP 170 or may operate separately from T-TRP. Scheduler 253 may schedule uplink, downlink, lateral link, and / or backhaul transmissions, including issuing scheduling authorizations and / or configuring schedule-free (e.g., “configuration authorization”) resources. T-TRP 170 also includes memory 258 for storing information and data. Memory 258 stores instructions and data used, generated, or acquired by T-TRP 170. For example, memory 258 may store software instructions or modules executed by processor 260 for implementing some or all of the functions and / or embodiments described herein.

[0096] Although not shown, processor 260 may constitute part of transmitter 252 and / or receiver 254. Furthermore, although not shown, processor 260 may implement scheduler 253. Although not shown, memory 258 may constitute part of processor 260.

[0097] The processor 260, the scheduler 253, the processing components of the transmitter 252, and the processing components of the receiver 254 may each be implemented by the same or different one or more processors for executing instructions stored in memory (e.g., memory 258). Alternatively, some or all of the processing components of the processor 260, scheduler 253, transmitter 252, and receiver 254 may be implemented using dedicated circuitry such as a programmed FPGA, hardware accelerator (e.g., GPU or AI accelerator), or ASIC.

[0098] Although the NT-TRP 172 is shown as an example of a drone only, it can be implemented in any suitable non-terrestrial form, such as satellites and high-altitude platforms including international mobile telecommunications base stations and unmanned aerial vehicles. Furthermore, the NT-TRP 172 may be referred to by other names in some implementations, such as a non-terrestrial node, a non-terrestrial network device, or a non-terrestrial base station. The NT-TRP 172 includes a transmitter 272 and a receiver 274 coupled to one or more antennas 280. Only one antenna 280 is shown in the figure to avoid congestion. One, some, or all of the antennas may alternatively be panels. The transmitter 272 and receiver 274 may be integrated as a transceiver. The NT-TRP 172 also includes a processor 276 for performing operations including operations related to: preparing downlink transmissions to be sent to ED 110, processing uplink transmissions received from ED 110, preparing backhaul transmissions to be sent to T-TRP 170, and processing transmissions received from T-TRP 170 via backhaul. Processing operations related to preparing to transmit downlink or backhaul transmissions may include operations such as encoding, modulation, precoding (e.g., MIMO precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to processing transmissions received in the uplink or received via backhaul may include operations such as receive beamforming, demodulating received symbols, and decoding received symbols. In some embodiments, processor 276 implements transmit beamforming and / or receive beamforming based on beam direction information (e.g., BAI) received from T-TRP 170. In some embodiments, processor 276 may generate signaling, for example, for configuring one or more parameters of ED 110. In some embodiments, NT-TRP 172 implements physical layer processing but does not implement higher-layer functions, such as those in the medium access control (MAC) layer or radio link control (RLC) layer. Since this is only an example, NT-TRP 172 may more generally implement higher-layer functions in addition to physical layer processing.

[0099] The NT-TRP 172 also includes a memory 278 for storing information and data. Although not shown, a processor 276 may form part of the transmitter 272 and / or the receiver 274. Although not shown, the memory 278 may form part of the processor 276.

[0100] The processing components of processor 276, transmitter 272, and receiver 274 may each be implemented by the same or different one or more processors for executing instructions stored in memory (e.g., memory 278). Alternatively, some or all of the processing components of processor 276, transmitter 272, and receiver 274 may be implemented using dedicated circuitry such as a programmed FPGA, hardware accelerator (e.g., GPU or AI accelerator), or ASIC. In some embodiments, NT-TRP 172 may actually be multiple NT-TRPs operating together, for example, via cooperative multicast service ED 110.

[0101] T-TRP 170, NT-TRP 172 and / or ED 110 may include other components, but for clarity these components have been omitted.

[0102] according to Figure 4 One or more steps of the methods in the embodiments provided herein may be performed by the corresponding units or modules. Figure 4 Units or modules in the device are shown, such as in ED 110, T-TRP 170, or NT-TRP 172. For example, signals may be transmitted or output by a transmitting unit or transmitting module. Signals may be received or input by a receiving unit or receiving module. Signals may be processed by a processing unit or processing module. Other steps may be performed by an artificial intelligence (AI) module or a machine learning (ML) module. The corresponding units or modules may be implemented using hardware, one or more components or devices executing software, or a combination thereof. For example, one or more of these units or modules may be circuits such as integrated circuits. Examples of integrated circuits include programmed FPGAs, GPUs, or ASICs. For example, one or more of these units or modules may be logical, such as logical functions performed by circuits, by a portion of an integrated circuit, or by software instructions executed by a processor. It should be understood that if these modules are implemented using software executed by a processor, etc., then these modules may be retrieved by the processor, wholly or partially, individually or collectively, for processing, in single or multiple instances, and these modules themselves may include instructions for further deployment and instantiation.

[0103] Although not shown, the transmitting module and receiving module can be part of a transceiver module, or they can be combined to form a transceiver module. A transceiver module can also be called an interface module, or simply an interface, and is used for input and output operations.

[0104] Additional details regarding ED 110, T-TRP 170, and NT-TRP 172 are known to those skilled in the art. Therefore, these details are omitted herein.

[0105] The channel coding module in the communication system will Each source bit is encoded as follows Each code bit provides error correction capabilities against adverse channel conditions such as noise and interference. The code rate is [number] bits. In fact, bitrate It is selected based on channel quality.

[0106] Polar codes are capacity-capable codes, representing a significant breakthrough in coding theory. When the code length approaches infinity, the synthesized channel (also called a subchannel, created by or associated with a polar code) becomes a noise-free or purely noisy subchannel. Information can be transmitted using noise-free subchannels, and it has been proven that their proportion can achieve the channel capacity defined by Shannon. This channel polarization phenomenon occurs under successive cancellation (SC) or SC-based decoding, and its complexity is relatively low.

[0107] LDPC codes are capacity approximation codes. LDPC codes can be defined by a PC matrix, which typically has far more zeros than one; in other words, it has low density. Decoding performance can be improved by strategically designing the positions of the 1s in the matrix. Although LDPC codes can theoretically be considered a type of random code, certain structures, both conceptually and physically, can facilitate the hardware implementation of LDPC encoders and decoders. Quasi-cyclic (QC) structures are exemplary structures that can improve performance and / or implementation complexity. QC-LDPC schemes first define a small base matrix or base graph (BG), and then perform a "lifting" operation, replacing the 1s in the base matrix or base graph with cyclically shifted versions of the identity matrix.

[0108] Rate matching is performed after channel coding by punching, truncating, or repeating some code points. The purpose of this operation is to obtain a code point sequence of the required length for transmission over limited channel resources.

[0109] Rate-compatible polar coding is a necessary technique for wireless applications. In one example of polar rate matching, a combination of puncturing, truncating, and repetition is used with a fixed reliability sequence to balance performance and complexity. Specifically, sub-block interleaving and interleaving are used for puncturing and truncating. The puncturing and truncating patterns are symmetrical.

[0110] With the mother code length being The code length is In this case, the specific rate matching scheme adopted is as follows: when Repeat; when Drilling holes at the time; when Cut the time short.

[0111] Channel interleaving is applied after channel coding and rate matching by permuting code bits. Its purpose is to provide stable or superior performance in high-order modulation or fading channels.

[0112] Before punching and truncation, sub-block interleaving is performed first. The interleaver will interleave lengths of... The mother code is divided into 32 sub-blocks, each sub-block being of size . They are then interleaved. An exemplary interleaver scheme is as follows: Figure 6 As shown in Table 600, this is reproduced from the 3GPP standard specification.

[0113] Hybrid Automatic Repeat Request (HARQ) is a mechanism that provides reliable wireless transmission by combining forward error correction (FEC) and automatic repeat request (ARQ). In HARQ, the initial transmission is an FEC codeword with accompanying means to support error detection at the receiver (e.g., CRC bits). If a decoding error is detected, the receiver sends back a negative acknowledgment (NACK) signal to notify the transmitter of the error and request a retransmission. The retransmitted bits can be selected directly from the initially transmitted bits, or they can be incrementally generated bits that, together with the initially transmitted bits, form a longer codeword. The former method is called chase-combining HARQ (CC-HARQ), and the latter is called IR-HARQ. Generally, IR-HARQ outperforms CC-HARQ due to the additional coding gain from incremental redundancy.

[0114] Polar codes belong to the category of linear block codes. For a polar code of length N, its generator matrix is... The encoding process is as follows ,in It is a binary information vector. It is a binary code vector. binary matrix ,in For polarization kernel matrix, , For Kronecker product.

[0115] Usually, there are One information bit needs to be encoded as Each code point. Therefore, given the inequality... Get the bitrate This means only a portion The bits used to carry information are usually called freeze bits. To represent a set of information bits (or a set of information), use This indicates the frozen bit set (or frozen set). Sometimes, there is an additional PC bit set, represented by... The frozen bits are known before decoding (usually set to all zeros, but could also be other known values ​​or sequences), therefore they do not carry any payload information. The PC bits are generated from a subset of the information bits. Therefore, the PC bits are known once the associated information bits have been decoded. The goal of polar code decoding is to recover all the information bits.

[0116] Sending code length It is not always a power of 2, that is In fact, punching and truncating are used to reduce the number of bits sent from... Reduce to For convenience, this disclosure will refer to... This is called the mother code length. This is called the code length. Specifically, punched bits are unsent bits unknown to the decoder, while truncated bits are unsent bits known to the decoder (usually set to all zeros).

[0117] have , Examples of polar codes in Figure 5 The grid diagram 500 is shown. Each "butterfly cell" 502 in the diagram represents a primary polarization, i.e. In this example, the information set is... Frozen set .

[0118] Sequential elimination (SC) is a basic decoding algorithm for polar codes, in which all frozen bits and information bits are decoded sequentially, i.e., bit by bit. The preceding bits are usually decoded first.

[0119] Successive cancellation list (SCL) is an enhanced decoding algorithm for polar codes, in which multiple (e.g., ...) cancellations are performed. (Number) SC decoding instances. Each instance is called a "decoding path". When decoding each bit, both the "0" and "1" branches are expanded to each path, producing... Each path. Then compare all. Of the possible paths, retain the most likely one. Choose one path and discard the least likely one. Each path is expanded or pruned. These path expansion and pruning operations are performed while decoding each information bit until all information bits are decoded. Finally, the most probable path is selected as the decoded output.

[0120] The CRC-aided successive cancellation list (CA-SCL) works almost the same way as SCL, except that in the final step, the most likely path that passes the CRC check is selected as the decoding output.

[0121] The parity-check successive cancellation list (PC-SCL) works in almost the same way as SCL, except that when decoding the PC bit, the parity value of the associated previous bit is used as the bit determination result. The PC bit can be regarded as a bit type other than freeze bits and information bits.

[0122] Low-density parity-check (LDPC) codes are a channel coding scheme that can achieve performance close to the Shannon limit, and has good overall performance and low complexity.

[0123] LDPC codes are encoded using a PC matrix. One type of LDPC code has a special structure called quasi-cyclic (QC). In QC-LDPC codes, the shift value of each block is designed to avoid undesirable structures such as short cycles and to improve the code distance. Decoding algorithms for LDPC codes include Min-Sum (MS) and Belief Propagation (BP). BP decoding performs better in terms of decoding performance, but it requires more information storage, has higher computational overhead, and is less convenient for hardware implementation. Therefore, in practical communication systems, offset MS and normalized MS decoding algorithms are used. Example LDPC code implementations use "1"s in a square matrix extended base graph (BG), where the square matrix is ​​a cyclically shifted version of the identity matrix. The BG of a QC-LDPC code can be defined as... ,in Corresponding to variables, Corresponding to the verification equation, It is its edge connection. The Tanner diagram is obtained after QC improvement, and the expansion factor is . That is, we obtain a bipartite graph. ,in For variable nodes, For verification nodes, For connecting edges, the number of columns in the corresponding odd / even matrix The number of rows in the check matrix. The number of non-zero elements in the parity check matrix is .

[0124] In one example, the LDPC payload comprises information block lengths ranging from 1 to 8448. The LDPC code implementation includes two PC matrices: BG1 and BG2. The same base map, with different boost sizes, can accommodate a variety of code rates and code lengths. This flexible implementation can be achieved, for example, by storing a list of boost sizes and shift values ​​in a lookup table, and then performing rate matching and IR-HARQ based on the table.

[0125] In an exemplary rate-matching scheme for LDPC codes, the codeword before rate matching (called the mother codeword) comprises three disjoint parts: the systematic bits, the core parity bits, and the extended parity bits. Four distinct redundancy versions (RVs) are generated from the rate-matched mother codeword: RV0, RV1, RV2, and RV3. In the initial transmission, RV0 is typically chosen; in RV0, most of the systematic bits are included in the set of coded bits. Depending on the effective code rate, a portion or all of the core parity bits, along with the extended parity bits, are included in RV0. Therefore, RV0 has the highest self-decoding capability of all RVs (i.e., RV0 can self-decode at the highest code rate). In retransmissions, the transmitter can choose RV1, RV2, or RV3. In this particular example, only RV3 is self-decoding, while RV1 and RV2 are not self-decoding at high code rates. At some code rates, RV1 and RV2 may only include the parity bits, causing decoding failure at the receiver.

[0126] In some embodiments, since puncturing is performed starting from the first bit and truncation starts from the last bit, the rate matching module is efficiently implemented using a circular buffer. All master bits are placed in the circular buffer. Punching is accomplished by skipping the first few bits and selecting the remaining bits for transmission in a clockwise order, while truncation is accomplished by selecting bits for transmission in a clockwise order and skipping the last few bits. An exemplary circular buffer is used in... Figure 7 As shown in the image.

[0127] Figure 7 An example of mother code 702 is shown. As shown, if puncturing is performed (e.g., at a low code rate), the punctured bits 704 start from the first code bit. If truncation is performed (e.g., at a high code rate), the truncation bits 706 are the last few ending bits up to the last code bit. Figure 7Examples of how the circular buffer 710 can be used to punch or truncate the master code 702 are also shown. Bits of the master code 702 are placed in the circular buffer 710, and these bits are selected from the circular buffer 710 starting at a start position 712 and ending at an end position 714. In example 720, where punching or truncation is not performed, the start position 712 is located at the first bit of the master code 702, and the end position 714 is located at the last bit of the master code 702, such that all bits of the master code 702 are selected. In example 730, where punching is performed, the start position 712 is shifted such that bit selection begins at (NM) bits after the first bit, and the end position 714 is at the last bit of the master code 702, such that (NM) bits are punched. In example 740, which performs truncation, the start position 712 is located at the first code bit of the mother code 702, and the end position 714 is shifted such that the bit selection stops at (NM) bits before the last bit, thereby truncating (NM) bits.

[0128] Another example of polarization rate matching involves the incremental freeze HARQ method, which supports the transmission of multiple short codewords. As more and more short codewords are sent, the overall code length increases, and the overall code rate decreases.

[0129] In the first transmission, the data is constructed, encoded, and sent. Polar codes. The code rate is... Typically, determining the bitrate requires meeting certain conditions. ,in This refers to the channel capacity during the first transmission. However, in cases of fading channels or inaccurate channel estimation, inequalities may arise. Decoding will fail, and a second transmission is required.

[0130] In the second transmission, from the first transmission Select the least reliable information bit One information bit. In fact... The selection is based on the estimated channel capacity for the second transmission. Based on this, the signal is constructed, encoded, and transmitted. Polar codes. However, if If the decoding fails again, a third transmission will be required.

[0131] The third and fourth transmissions are constructed similarly, and so on.

[0132] On the receiver side (i.e., at the receiving device), the decoder should always decode the last received codeword because it has the lowest code rate and therefore the greatest chance of successful decoding. After the last transmission is correctly decoded, all corresponding information bits from previous transmissions become known and can be decoded as frozen bits with known values. This process is repeated as more codewords are decoded until all codewords from the first transmission are decoded. All bits have been decoded. The term "incremental freeze" refers to the operation where, once the subsequently transmitted codeword has been decoded, some additional bits from the previously transmitted information are frozen.

[0133] Figure 8 An example is shown, where and , , , .

[0134] Figure 8 An exemplary set of subchannels is shown, ranging from the most reliable to the least reliable (it should be understood that the subchannels are conceptually ordered from most reliable to least reliable, and...). Figure 8 The order shown may not indicate any actual order of the subchannels. An example of four transmissions is shown in the diagram. In this example, the code length is 16 for all four transmissions (i.e., This means that the 16x16 polarization transformation matrix 802 (sometimes called the generator matrix) is represented as This is used for all four transmissions. The number of bits for the information to be sent is 12 (i.e., ...). ).

[0135] In the first transmission 804, all 12 information bits are selected (i.e., (i) Construct, encode, and transmit on the most reliable sub-channels. Polar codes. In cases of channel fading or inaccurate channel estimation, the code rate may exceed the channel capacity, potentially causing decoding failure. A second transmission may be required.

[0136] In the second transmission 806, information bits are selected from those sent in the first transmission 804. The least reliable bit of information. In this example, This indicates the information bits selected for transmission in the six least reliable sub-channels, i.e., bits. Based on this, construct, encode, and transmit on the most reliable sub-channel. Polar code. If decoding fails again, a third transmission is required.

[0137] In the third transmission 808, selected bits are chosen from the least reliable information bits sent in the second transmission 806 and the least reliable bits from the first transmission 804 that have not yet been retransmitted. Specifically, the bits selected for the third transmission 808... Of the 100 information bits, select the two least reliable information bits from the second transmission 806 (i.e., ... ), and select the two least reliable bits from the first transmission 804 that have not yet been retransmitted (i.e. Based on this, construct, encode, and transmit on the most reliable sub-channel. Polar code. If decoding fails again, a fourth transmission is required.

[0138] In the fourth transmission 810, selected bits are chosen from all previously transmitted, least reliable information bits that have not yet been retransmitted. Specifically, in the selection for the fourth transmission 810... Of the 100 information bits, select the least reliable information bit from the third transmission 808 (i.e., ), select the least reliable bit from the unretransmitted bits of the second transmission 806 (i.e. ), and select the least reliable bit from the unretransmitted bits of the second transmission 806 (i.e. Based on this, construct, encode, and transmit on the most reliable sub-channel. Polar codes.

[0139] In this example, decoding is successful after the fourth transmission 810. Then, using the successfully decoded bits from the fourth transmission 810, the remaining bits from the third transmission 808 can be decoded. Then, after successfully decoding the bits from the third transmission 808, the bits from the second transmission 806 can be decoded, and so on, until all 12 bits are successfully decoded.

[0140] PC polar codes can be used to improve the minimum distance of polar codes. PC polar codes can also be used to support IR-HARQ. In the latter case, the PC bits are used to couple multiple retransmissions into a longer polar code with additional coding gain.

[0141] The PC bit can be considered as another bit type besides information bits and freeze bits. The value of the PC bit is determined by its preceding information bits, specifically by a binary linear combination of a subset of the preceding information bits. This binary linear combination is specified by the PC function:

[0142] ,

[0143] in It is a bit index. Because... It is the maximum index in the PC function. It can be called the PC bit, and its value is the binary sum of all other (previous) bits in the PC function.

[0144] To improve the minimum distance (or weight spectrum), from the polarization transformation matrix... The PC position is selected from the indexes of the non-frozen bit set with the minimum row weight. The non-frozen bit set is the complement of the frozen set.

[0145] An exemplary polar code scheme uses a hardware-friendly, simple PC function based on a fixed interval p. For example, p can be set to the value 5. That is, for an index of... The PC bit is the modulo-2 sum of all previous information bits spaced 5 bits apart. That is, The PC bit can be easily generated using a circular shift register of length p, such as... Figure 9 As shown.

[0146] Figure 9 An example of how a circular shift register can be used during bit assignment to bit positions (where different bit positions correspond to different sub-channels) is shown. In this example, The value is 5 (i.e., a circular shift register storing a 5-bit value is used). For the bit position at the current index, it is determined whether the bit position should carry an information bit, a PC bit, or a freeze bit. If the bit position should carry an information bit, the information bit value is stored in circular shift register 902, and circular shift register 902 is shifted by 1. If the bit position should carry a PC bit, the PC bit value is output from circular shift register 902, and circular shift register 902 is shifted by 1. In this example, the freeze bit value is always 0, and circular shift register 902 is shifted by 1.

[0147] Some examples of PC polar codes can also be implemented to support IR-HARQ. In such examples, the PC bits may no longer be primarily used to improve the minimum code distance, but rather they may be primarily used to couple multiple retransmissions into a longer polar code with additional coding gain.

[0148] The PC function used for IR-HARQ can be considered a special case where some information bits are copied from the initially transmitted code block to the retransmitted code block. This one-to-one parity check relationship between two shorter code blocks effectively couples the two code blocks into a longer code block.

[0149] For example, the initial transmission is Polar codes, in which For information set, This is a frozen set. Its encoding process is as follows: Figure 10 As shown.

[0150] like Figure 10As shown, during the encoding process of the initial transmission 1002, bit vector 1004 contains the information bit (denoted by I) at the most reliable bit position and the frozen bit (denoted by F) at the least reliable bit position. Bit vector 1004 and polarization transformation matrix Multiply to generate code vector 1006.

[0151] In the first retransmission, four additional bits are sent. These four bits are coupled with the initial eight bits to form... Polar codes. This coupling is achieved by encoding... Copy the value This is achieved by generating the PC function. (or equivalent) As mentioned above, the largest index in this PC function corresponds to the PC bit (here, ). During decoding, It is decoded as information bits, and Then according to It is decoded as the PC bit. For information set, For PC set, For a frozen set, the encoding process is as follows: Figure 10 As shown.

[0152] like Figure 10 As shown, in the encoding process of the first retransmission 1012, bit vector 1014 contains the information bits and freeze bits of the initial bit vector 1004, coupled to four additional bits, one of which is an information bit (i.e., ) is copied to one of the appended bits (i.e. This additional bit is used as the PC bit (denoted by P). Bit vector 1014 and polarization transformation matrix Multiply to generate code vector 1016.

[0153] In the second retransmission, the remaining 4 bits are sent. , , , ,form Polar code. But this time, no new PC bits will be generated.

[0154] From the perspective of polarization transformation matrix, it has an effective code length , , The three transmissions in Figure 11 As shown in the image.

[0155] Figure 11 The diagram illustrates the encoding that can be used to perform the initial transmission, first retransmission, and second retransmission as described above. , and An example of a polarization transformation matrix. It is worth noting that... and The polarization transform matrix will cause problems during the encoding process. The value is copied .

[0156] Rate-compatible LDPC coding is another technique required for wireless applications. LDPC rate matching may involve combinations of punching, truncation, and repetition, and is used in conjunction with quasi-cyclic lifting based on the base map (BG) and a set of shift values. In a specific example, according to Will increase size The group is divided into eight sets, among which and From the same The derived lift sizes belong to the same set and share the same shift values. The shift values ​​for all non-zero positions in the BG and the shift values ​​for all lift size groups are stored in a single table. When constructing the PC matrix, the lift size is determined first. Then obtain the collection index with the increased size. Finally, the shift value is obtained from the table.

[0157] Typically, PC polar code schemes may require specifying the following parameters:

[0158] ● Whether to perform PC encoding on polar codes.

[0159] ●Which parts of the codeword are PC encoded?

[0160] ●Specific PC encoding methods.

[0161] Some embodiments of this disclosure include methods that first perform PC encoding and then perform polar encoding. These methods also support IR-HARQ retransmission of LDPC codes and polar codes. Some embodiments of this disclosure may include the following objectives:

[0162] ● Achieve stable performance across a wide range of code lengths and bit rates.

[0163] ●Supports multiple transmissions and retransmissions, for example, with multiple redundant versions.

[0164] The method according to embodiments of this disclosure may include one or more of the following features:

[0165] ● Determining whether to perform PC encoding and how to perform PC encoding:

[0166] ● Whether PC encoding is performed based on the physical channel type and / or code parameters and / or application scenario.

[0167] ● How to perform PC encoding (e.g., mark the freeze bit as the PC bit).

[0168] ● The method of performing PC encoding on different parts of the code:

[0169] ● Methods for performing sub-block PC encoding.

[0170] ●Different sub-blocks of the code.

[0171] ●Different redundant versions and transmissions.

[0172] Some embodiments of this disclosure include one or more of the following features, which may be used individually or together as a complete solution.

[0173] The first aspect of this disclosure relates to a method for determining whether to perform PC encoding, comprising one or more of the following features:

[0174] ● Rules for specifying whether PC coding should be performed based on the physical channel type;

[0175] ● This specifies whether to perform PC encoding based on the code parameters;

[0176] ● Rules for specifying whether PC encoding should be performed based on the physical channel type and code parameters;

[0177] ● Rules for specifying whether to perform PC coding based on application scenario and priority;

[0178] ● Rules for specifying different ways to perform PC encoding under different physical channels and encoding parameters, and which method to choose.

[0179] A second aspect of this disclosure relates to a method for performing PC encoding on different portions of a code. The method may include one or more of the following configurations:

[0180] ● Apply PC encoding to different sub-blocks of the code;

[0181] ● Apply PC encoding to different redundant versions and transmissions.

[0182] PC-based polar coding is an effective way to improve coding performance. Similar schemes, such as polarization-adjusted convolutional (PAC) codes, also apply convolutional codes (CC) before the polar coding step to improve performance. These PC-based, PAC, and other methods that generate auxiliary bits from the information block before polar coding belong to the same category. The general term may be "auxiliary bit-based polar coding." However, for convenience, this paper will simply refer to various auxiliary bit-based polar coding schemes as PC-based polar codes.

[0183] PC polarization, PAC, and other auxiliary bit-based polarization coding designs can be generalized to a pre-transform matrix framework, where a pre-transformation step is performed before polarization coding. The pre-transformation step involves multiplying the input vector by an upper triangular matrix, such as... Figure 12 As shown.

[0184] exist Figure 12 In the example, the information bits are transformed by the pre-transformation matrix 1202 to generate information bits with PC bits. Then, the information bits with PC bits are encoded by the polarization transformation matrix 1204 (also simply called the "polarization matrix") to generate PC polar-coded bits (also called pre-transformed polar codes). Figure 12 It is shown as The pre-transformation matrix 1202 and expressed as Example of polarization transformation matrix 1204.

[0185] Mathematically, pretransform polar codes are generated by a generator matrix. Definition, where It is the upper triangular pre-transformation matrix, as shown below.

[0186]

[0187] and It is the polarization matrix, as shown below.

[0188]

[0189] The encoding process can be represented as

[0190]

[0191] in, It is a vector of length N, where the index corresponding to the information bit position is assigned the value of the information bit (or payload bit), and the index corresponding to the freeze bit position is assigned a predefined value (usually zero, i.e., ...). After PC encoding (or pre-transformation), a vector of length N is obtained. The vector can contain both information bits and PC bits, or it can contain only PC bits.

[0192] When the PC code (or by) When the pretransform code defined by the upper triangular pretransform matrix is ​​a systematic code, the vector... It includes both information bits and PC bits;

[0193] When the PC code (or by) When the pretransform code defined by the upper triangular pretransform matrix is ​​a non-systematic code, the vector Only contains the PC bit.

[0194] Typically, for ease of hardware implementation, PC encoding (or pre-transform encoding) (i.e., with the pre-transform matrix) is used. Multiplication is described and implemented by a set of shift registers (e.g., the PC polar-coded shift registers mentioned above), where wiring, connections, and output are defined by a polynomial. This set of shift registers can be collectively referred to as shift registers (where each unit in the shift register can be a single register (i.e., a 1-bit register)). A shift register in which the units (single registers in a set of shift registers) are connected in a circular manner (i.e., the highest index unit is connected to the lowest index unit) can be called a circular shift register or a set of circular shift registers. The input is fed into the shift register, and the value in the register is in a length of... The vector is shifted (or cyclically shifted) one position after each information bit and / or freeze bit. The output can be obtained from the value stored in the shift register.

[0195] It should be understood that the use of shift registers (or circular shift registers) is an exemplary implementation of the circular shift operation used in PC polar coding as disclosed herein. In various examples, the circular shift operation can be implemented using hardware (e.g., using shift registers) or software (e.g., logic). For example, some implementations of the circular shift operation may use hash functions or lookup tables. Various software and / or hardware implementations of the circular shift operation are possible within the scope of this disclosure.

[0196] In some cases, even if a PC bit is added to the polar code, a CRC bit may still be needed for error detection. Therefore, this code can also be called a "PC-CA polar code".

[0197] For simplicity, PC polar codes can be used here to refer to all processes involving the generation of PC bits (e.g., vectors) before polar coding. The concatenated polar code of the PC external encoding (PC bit in the code).

[0198] For the sake of generality, PC polar codes can be used here to refer to all concatenated polar codes that fall within the pre-transformed polar code framework.

[0199] Polar codes can be used as channel coding schemes, suitable for various scenarios requiring a wide range of code lengths and rates. Therefore, it is necessary to configure when and where PC polar codes are applied.

[0200] The first aspect of this disclosure relates to a method for determining whether to perform PC encoding;

[0201] The method may include one or more rules for specifying whether to perform PC coding based on the physical channel type;

[0202] ● Determine whether to apply PC coding based on the physical channel type and uplink / downlink traffic.

[0203] ● One configuration could be: PC polar coding is used for the physical uplink control channel (PUCCH) carrying uplink control information (UCI) including HARQ feedback (ACK / NACK) and scheduling request (SR), and non-PC polar coding is used for all other physical channels.

[0204] ● One configuration could be: PC polar coding is used for PUCCH carrying UCI content including Channel State Information (CSI), and non-PC polar coding is used for all other physical channels;

[0205] ● One configuration could be: PC polar coding for PUCCHs that are not multiplexed on the physical uplink shared channel (PUSCH), and non-PC polar coding for all other physical channels;

[0206] ●Another configuration could be: PC polar coding for PUCCH (including PUCCH multiplexed on PUSCH) and non-PC polar coding for all other physical channels;

[0207] ●Another configuration could be: PC polar coding for PUCCH and PBCH, and non-PC polar coding for all other physical channels;

[0208] ●Another configuration could be: PC polar coding for PUCCH and PDCCH, and non-PC polar coding for all other physical channels;

[0209] ●Another configuration could be: PC polar coding for PUCCH, PBCH, and PDCCH, and non-PC polar coding for all other physical channels;

[0210] ●Another configuration is to use PC polar coding for the first-level PDCCH and non-PC polar coding for the second-level PDCCH; the advantage of the above configuration is that it can improve the performance of shorter polar codes.

[0211] ●Another configuration could be: PC polar coding for all control channels (PUCCH, PBCH, and PDCCH) and non-PC polar coding for all data channels (PUSCH, PDSCH);

[0212] ●Another configuration is to use PC polar coding for all uplink channels (PUCCH and PUSCH) and non-PC polar coding for all downlink channels (PBCH, PDCCH and PDSCH). The advantage of the above configuration is that the design is uniform, the description is simpler, and the performance of shorter polar codes is improved.

[0213] The method may include one or more rules for specifying whether to perform PC encoding based on code parameters;

[0214] ● Determine whether to apply PC encoding based on the encoding parameters.

[0215] ● One configuration could be: for code lengths up to... In this case, PC polar coding is used, where It can be 32, 64, 128, 256, 512, or 1024;

[0216] ● One configuration could be: for information block lengths up to... In this case, PC polar coding is used, where It can be 11, 16, 19, 22, 24, 32, 64, 128, 256, 512;

[0217] ●Another configuration could be: for bitrates up to In this case, PC polar coding is used, where It can be 3 / 4, 2 / 3, 1 / 2, 2 / 5, 3 / 8, 1 / 4, or 1 / 8.

[0218] ●Another configuration could be: simultaneously satisfying the code length reachability requirement And the bitrate can reach In this case, PC polarization coding is used. and The value can be selected from the values ​​above;

[0219] The method may include one or more rules for specifying whether to perform PC coding based on the physical channel type and code parameters;

[0220] ● Determine whether to apply PC coding based on the physical channel type, uplink / downlink traffic, and coding parameters.

[0221] ● One configuration could be: for code lengths up to... The PUCCH uses PC polar coding, where It can be 32, 64, 128, 256, 512, or 1024;

[0222] ● One configuration could be: for information block lengths up to... The PUCCH uses PC polar coding, where It can be 11, 16, 19, 22, 24, 32, 64, 128, 256, 512;

[0223] ● One configuration could be: for code lengths up to... The second-level PDCCH uses PC polar coding, in which It can be 32, 64, 128, 256, 512, or 1024;

[0224] The method may include one or more rules for specifying whether to perform PC coding based on the application scenario and priority;

[0225] ● Determine whether to apply PC encoding based on the application scenario.

[0226] ● In some embodiments, PC polar coding is used for ultra-reliable low-latency communication (URLLC) services, while non-PC polar coding is used for all other physical channels. In practice, the standard specification may not explicitly mention URLLC, but it may associate PC polar coding with services that have certain priority indices (e.g., high-priority (HP) UCI ​​content or high-priority data services).

[0227] ●The method may include one or more rules for specifying different ways to perform PC coding under different physical channels and coding parameters, and for selecting which way to use.

[0228] ● There are two types of PC encoding methods. One is to use a predefined number of PC bits, such as 3, 6, or 8 bits. This can be called Type I PC polarization. The other is to use all frozen bits as PC bits. This can be called Type II PC polarization.

[0229] ● In some embodiments, type I polarization can be used for code lengths up to [amount missing]. PUCCH, of which It can be 32, 64, 128, 256, 512, or 1024; Type II polarization can be used for code lengths greater than... PUCCH.

[0230] ● In some embodiments, type I polarization can be used for information block lengths up to [number missing]. PUCCH, of which The values ​​can be 11, 16, 19, 22, 24, 32, 64, 128, 256, or 512; Type II polarization can be used for information block lengths greater than [a certain value]. PUCCH.

[0231] ● In some embodiments, type I polarization can be used for PUCCH; in some embodiments, type II polarization can be used for PDCCH and / or PBCH.

[0232] The second aspect of this disclosure relates to a method for performing PC encoding on different parts of a code.

[0233] This disclosure may also relate to partial PC polarization coding schemes and segmented PC polarization schemes.

[0234] In the exemplary PC polarization coding method, PC encoding is applied to all information bits before generating the PC bits. Variations of this scheme can apply PC encoding only to a subset of information bits. The advantage of this variation could be simplified implementation or compatibility with other coding features in the coding chain.

[0235] PC encoding can be applied to certain sub-blocks of polar codes. Therefore, PC encoding can be restricted to sub-blocks of length powers of 2, while other sub-blocks can follow non-PC encoding methods.

[0236] For example, a vector of length N The index corresponding to the information bit position is assigned the value of the information bit (or payload bit), and the index corresponding to the freeze bit position is assigned a predefined value (usually zero, i.e., ...). This vector can be represented as a concatenation of two sub-blocks, i.e. .

[0237] In one configuration, only the first sub-block is PC-encoded. The PC encoding matrix (or pre-transform matrix) can be represented as... ,in for The upper triangular submatrix, for The identity submatrix. The encoding process is still... However, it is quite obvious As can be seen, only the first half of the code is PC-encoded; the second half is unaffected by PC encoding. The configuration is as follows... Figure 13A As shown.

[0238] Figure 13AAn example of a polar codeword 1300 is shown, which is logically divided into two sub-blocks called a first sub-block 1302 (or sub-block 1) and a second sub-block 1304 (or sub-block 2). The terms "first" or "second" sub-block are not intended to limit a specific order within codeword 1300. In some examples, the transmission of the first sub-block 1302 may precede the transmission of the second sub-block 1304 (therefore "first" and "second" may refer to the transmission order), but this is not a required or expected limitation. It should be understood that, for simplicity, codeword 1300 is shown as having two sub-blocks 1302 and 1304. Typically, a polar codeword may have two or more sub-blocks, and each sub-block may be generated independently of any other sub-block using (or not using) PC encoding. That is, the PC encoding used for one sub-block does not necessarily affect or depend on whether another sub-block of codeword 1300 uses (or does not use) PC encoding. Polar codewords can be divided into two or more sub-blocks in any suitable manner, such as the manner disclosed herein, and the lengths of the sub-blocks can be equal or unequal. Figure 13A In the example, the first sub-block 1302 is generated by applying PC encoding to the information bits corresponding to the first sub-block 1302 to generate PC bits, and then performing polar encoding to obtain PC polar encoded sub-block 1302 (where PC bit 1306 replaces the frozen bits in some frozen bit positions; although not shown, other frozen bit positions may have frozen bits); and the second sub-block 1304 is generated by polar encoding (without PC encoding) the information bits corresponding to the second sub-block 1304 to obtain non-PC polar encoded sub-block 1304 (only frozen bit 1308 in the frozen bit positions).

[0239] In another configuration, only the second sub-block is PC-encoded. The PC encoding matrix (or pre-transform matrix) can be represented as... ,in for The upper triangular submatrix, for The identity submatrix. The encoding process is still... However, it is quite obvious As can be seen, only the latter half of the code is PC-encoded, while the former half is unaffected by PC encoding.

[0240] Figure 13BAn example is shown. Similarly, polar codeword 1300 is logically divided into a first sub-block 1302 and a second sub-block 1304. In this example, the first sub-block 1302 is generated by polar coding (without PC coding) the information bits corresponding to the first sub-block 1302 to obtain a non-PC polar-coded sub-block 1302 (only the frozen bit 1308 is in the frozen bit position); and the second sub-block 1304 is generated by applying PC coding to the information bits corresponding to the second sub-block 1304 to generate PC bits, and then polar coding to obtain a PC polar-coded sub-block 1304 (where PC bit 1306 replaces the frozen bits in some frozen bit positions; although not shown, other frozen bit positions may have frozen bits).

[0241] In another configuration, both the first and second sub-blocks are PC-encoded. The PC encoding matrix (or pre-transform matrix) can be represented as... ,in and All The upper triangular submatrix. The encoding process is still... However, it is quite obvious As can be seen, both the first and second halves of the code are PC-encoded. However, unlike methods that PC-encode all information bits, this method differs in that the PC encoding between the first and second sub-blocks is independent. The PC bits (i.e., the bit values) in the second half will not depend on the first half. This decoupled PC encoding method can be advantageous for self-decoding in situations where two sub-blocks of a polar code need to be decoded independently without receiving encoded bits (signals) from the other sub-block. IR-HARQ can be an example of this.

[0242] As described above, in the exemplary hardware implementation, PC encoding (or pre-transform encoding), i.e., with the pre-transform matrix... Multiplication is described and implemented using a set of shift registers, where wiring, connections, and outputs are defined by polynomials. This means that before encoding a new sub-block, the values ​​stored in the shift registers need to be cleared (or the shift registers need to be reset) to eliminate coupling effects between sub-blocks. While a single PC polynomial might be easier to describe and implement, different polynomials can be implemented for PC encoding of different sub-blocks due to the decoupling of sub-blocks (i.e., making the PC encoding of sub-blocks independent). This configuration, along with shift register resets, in Figure 13C As shown in the image.

[0243] exist Figure 13CIn this example, codeword 1300 is logically divided into a first sub-block 1302 and a second sub-block 1304. PC encoding is applied to the information bits corresponding to the first sub-block 1302 to generate a first set of PC bits, and PC encoding is applied to the information bits corresponding to the second sub-block 1304 to generate a second set of PC bits. Then, polar encoding is performed such that the first sub-block 1302 is a PC-polar encoded sub-block (PC bit 1306 replaces some frozen bits in frozen bit positions; although not shown, other frozen bit positions may have frozen bits) and the second sub-block 1304 is also a PC-polar encoded sub-block (PC bit 1306 replaces some frozen bits in frozen bit positions; although not shown, other frozen bit positions may have frozen bits). It should be noted that only the information bits of the first sub-block 1302 are used to generate the first set of PC bits in the first sub-block 1302, and only the information bits of the second sub-block 1304 are used to generate the second set of PC bits in the second sub-block 1304. To enable the same set of shift registers to be used for PC encoding of the first subblock 1302 and the second subblock 1304, the shift registers can be reset between the end of PC encoding of the first subblock 1302 and the start of PC encoding of the second subblock 1304 (e.g., as shown). Figure 13C (As indicated in the document). This allows PC encoding to be implemented using a smaller set of shift registers (for example, the shift registers only need to store the length of the information bits in the subvector corresponding to a subblock 1302, 1304, instead of the full length of the bit vector of code 1300), and the same set of shift registers can be reused, thereby saving computational resources (e.g., saving chip area, memory resources, etc.).

[0244] Resetting the shift register between the PC encodings of the first subblock 1302 and the second subblock 1304 also helps decouple the first and second sets of PC bits. This means that the first subblock 1302 can be decoded with the assistance of the first set of PC bits (without the second set of PC bits), and the second subblock 1304 can be decoded with the assistance of the second set of PC bits (without the first set of PC bits). As discussed elsewhere in this application, the decoupling of the first and second sets of PC bits can provide the following technical advantages: if only one PC-polarized codeword subblock is received at the receiver, the receiver can still successfully recover the information bits without receiving the remaining subblocks of the PC-polarized codeword. This enables more flexible and / or more robust wireless communication and may save computational resources at the decoder.

[0245] The above design can also be extended to any sub-block. For example, assuming there are S sub-blocks, a subset of these sub-blocks can be selected for PC encoding. At the beginning of each sub-block, PC encoding is initiated by resetting the shift registers in the corresponding description and implementation, and terminated at the end of the sub-block. Multiple sub-blocks can be bundled together for a single PC encoding instance. Therefore, The length of a subvector in the array can be a power of 2 or a multiple of a power of 2. Figure 14 An example is shown.

[0246] Figure 14 An example is shown where the polar codeword 1400 has an arbitrary number of sub-blocks (e.g., four sub-blocks 1402, 1404, 1406, and 1408). Each sub-block can be generated from a corresponding sub-vector of the bit vector, where PC encoding can be used (or not used) independently in the generation of each sub-block. In the example shown, PC encoding is used in the generation of the first sub-block 1402 and the third sub-block 1406 (such that some frozen bit positions contain PC bit 1410), while PC encoding is not used in the generation of the second sub-block 1404 and the fourth sub-block 1406 (such that all frozen bit positions contain frozen bit 1412). As discussed above, when using a set of shift registers to perform PC encoding, the set of shift registers can be reset between the PC encodings of different sub-blocks (e.g., the shift registers can be cleared at the beginning of the PC encoding of any sub-block; or the shift registers can be cleared at the end of the PC encoding of any sub-block). In other examples, PC encoding can be performed by implementing cyclic shift operations in other ways instead of using shift registers. For example, if logic is used to implement cyclic shift operations in PC encoding, instead of resetting the shift registers between PC encodings of different sub-blocks, the logic can be reinitialized (e.g., the variables can be reinitialized to zero). Although Figure 14 Alternating modes of PC-polarized and non-PC-polarized subblocks are shown, but are merely exemplary. For example, devices or apparatuses may be used to use or not use PC encoding for subblocks based on various settings and / or criteria, some of which are discussed herein.

[0247] Embodiments of this disclosure may include one or more of the following configurations.

[0248] ● Apply PC encoding to different sub-blocks of the code, where:

[0249] ● Divide the code into S sub-blocks of length 2, and apply PC coding to the front. Each block, and . Specifically, It can be 1, 2, or 4. The advantage of doing this is that more frozen bits can be used as PC bits, thus obtaining more coding gain.

[0250] ● Divide the code into S sub-blocks of length 2, and apply PC coding to the first part containing the information bits. Each block, and . Specifically, It can be 1, 2, or 4. The reason is that only the freeze bit after the first information bit can become the PC bit.

[0251] ● Divide the code into S sub-blocks of length 2, and apply PC coding to the subsequent... Each block, and . Specifically, It can be 1, 2, or 4. The advantage of doing this is that by performing PC encoding on the last few sub-blocks, the weight spectrum can be improved to the greatest extent.

[0252] ● Divide the code into powers of 2. Each sub-block, and apply PC encoding to all. Each sub-block is encoded independently or separately. That is, the PC bit in a sub-block serves only as a parity check bit for the information bits within that sub-block. In other words, the PC bit in a sub-block only checks the information bits within the same sub-block. The advantage of this approach is that sub-block SCL decoding can be used to reduce memory usage.

[0253] When IR-HARQ is used for polar codes, multiple shorter polar codes can be further combined and polarized into a longer polar code. For example... Figure 15 As shown, the two shorter polar codes are... and Further polarization to generate and ,in remain unchanged and For IR-HARQ applications, It can be sent as redundant version 0 (RV0) in the initial transmission. It can be sent as another redundant version RV1 in subsequent retransmissions. In one implementation, PC encoding can be performed only on RV0, and PC encoding can be omitted from RV1. That is, Depend on Generate, where the input vector With PC encoding matrix (or upper triangular pre-transformation matrix) Multiply by the product and then multiply by the polarization matrix FN; Depend on Direct generation, where the input vector With polarization matrix Multiply directly.

[0254] ●PC encoding can be applied to different redundant versions and transmissions.

[0255] ● In some embodiments, PC coding is applied only to the first redundant version, and PC coding is not performed on the remaining redundant versions. Figure 16 A diagram is provided. Figure 16 Example code 1600 is shown, which is divided into two sub-blocks. One sub-block 1602 is sent as the initial transmission (first redundancy version, denoted as RV0) and PC encoding is applied, while the second sub-block 1604, sent as a subsequent retransmission (remaining redundancy version, denoted as RV1), is not PC encoded.

[0256] ● In some embodiments, PC encoding is applied only to the front end. There are redundant versions, among which and It represents the total number of redundant versions, and PC encoding is not performed on the remaining redundant versions.

[0257] ● In some embodiments, PC encoding is applied to the redundant version, wherein the transmission length of the redundant version is predefined or fixed.

[0258] ● In some embodiments, PC encoding is applied to redundant versions for retransmissions and / or repetitions of PUCCH / UCI and / or PDCCH / DCI. For each PUCCH / UCI and / or PDCCH / DCI retransmission or repetition, each redundant version is a shorter, self-decoded codeword, and during soft combining, a longer codeword is generated to achieve higher coding gain. For each shorter, self-decoded codeword, PC encoding is performed independently and separately, allowing for self-decoding even when no other redundant versions are available. Figure 17 A diagram is provided. Figure 17 In the example, the shorter codewords 1702 and 1704 (corresponding to redundant versions RV0 and RV1, respectively) are soft-merged to obtain the longer codeword 1700. Each shorter codeword 1702 and 1704 can be PC-encoded independently and separately. A set of shift registers used for PC encoding is reset between PC encodings of different shorter codewords, such as... Figure 17 As shown.

[0259] ● In some embodiments, if a redundant version is defined such that it is sent in a single transmission, PC encoding can be applied to that redundant version. Otherwise, if multiple transmissions within a redundant version are permitted, then PC encoding should not be used for that redundant version.

[0260] ● Alternatively, if a redundant version is defined such that multiple transmissions are allowed within a redundant version, and PC encoding is performed on that redundant version, then the code points associated with each individual transmission should be PC encoded independently or separately.

[0261] Some embodiments of this disclosure additionally relate to determining the number of so-called special auxiliary bits. Special auxiliary bits can have different names or be referred to using different names.

[0262] ●Auxiliary bits can be considered "special" because they are PC bits that are not selected according to reliability order, or PC bits that are not selected solely according to reliability order.

[0263] ●For example, an auxiliary bit could be the PC bit with the smallest row weight in the set of unfrozen bits. The set of unfrozen bits could be... The most reliable bit positions (excluding bit positions corresponding to those that have been punched or truncated), among which It refers to the number of information bits. It refers to the number of auxiliary bits.

[0264] ●Number of special auxiliary positions The output sequence length can be matched according to the rate. and information block length The information is provided in the table below.

[0265] Table 1

[0266]

[0267] ●Number of special auxiliary positions It can be given by a piecewise function, that is, or The input parameters may include the rate-matched output sequence length. and information block length Even including the mother code length For example, when or hour, ,otherwise ,in , and All are constants. In one example, let... =6、 =7 and =4 or 8 or 16 or 20.

[0268] Some embodiments of this disclosure include exemplary methods, represented in pseudocode, for PC encoding of a specific code. The polar code length is... It supports two redundant retransmission versions. Encoded bits Belongs to RV0, used for initial transmission; the input vector contains all information bits. Parameters This indicates that PC encoding is enabled. The encoded bits... Belonging to RV1, it is used for retransmission. The input vector contains partial information bits, and the values ​​of these information bits are assigned to two sets of information bit positions in a certain order. In RV1, PC encoding is not performed.

[0269] For the first redundant version, according to Figure 18 The pseudocode generation shown .

[0270] Figure 18 The pseudocode in the example illustrates how PC coding can be applied. The output of the pseudocode is the PC-coded vector of the bits to be polarized. Then, it is polar encoded to obtain the final PC polar codeword. The first set representing the location of information bits (for ), The set representing the PC bit positions. This represents the bit sequence to be encoded. Represents the XOR operation. Bit sequence It can be an interleaved bit sequence or a non-interleaved bit sequence. For example, the bit positions of the information bits and the PC bits (such as those formed by...) and (Definition) can be selected or defined according to the standard.

[0271] exist Figure 18 In the pseudocode section 1810, it indicates that PC encoding (parameter) is used for application. This indicates the operation of enabling PC encoding.

[0272] Line 1812 represents a circular shift operation on an array of elements of length 5, where the bit values ​​are stored in the elements. In this example, the input to the cyclic shift operation is located at element [element name missing]. At this point, the output of the circular shift operation is also located at element [number]. It should be understood that circular shift operations are not necessarily limited to a length of 5, and can shift along the direction from the most significant bit (MSB) to the least significant bit (LSB) or along the direction from LSB to MSB. Circular shift operations can be implemented in various ways, for example, by using a circular shift register (e.g., such as...). Figure 9 As shown), this can be implemented logically, using a hash function (e.g., a hash function that maps a 5-bit sequence to a PC bit value), a lookup table (e.g., a lookup table that can be used to look up the PC bit value based on a 5-bit sequence), or any other suitable hardware and / or software implementation.

[0273] In this example, yes A subset of. For the current index n, determine whether index n is a subset of. If it is, then further determine whether index n is part of the PC bit set. If index n is part of the PC bit set, then... The value is set to the output bit value of the circular shift operation (in this case, the output of the circular shift operation is located at element). (as indicated in line 1814), otherwise, The value is set to the current information bit value (as shown in line 1816), the index of the information bit is incremented by 1, and the bit value of the information bit is input into the circular shift operation (in this case, the input of the circular shift operation is located at element). (as shown in line 1818). If index n is not... If it is part of the frozen bit set, then it is assumed that the current index n belongs to the frozen bit set, and will The value is set to the freeze bit value 0 (as indicated in line 1820).

[0274] Pseudocode section 1822 indicates how to generate the output vector without PC encoding. The operation.

[0275] For the second redundant version, according to Figure 19 The pseudocode generation shown .

[0276] Figure 19 The pseudocode in the figure illustrates how a vector of bits to be polarized can be generated from another set of information bit positions. Example. In Figure 19 PC encoding is not used in the pseudocode.

[0277] Output bit vector This can be called the vector of bits to be polarized, or the input vector of the polarization encoder. In other words, the polarization matrix is ​​applied to the vector. To obtain polarized codewords.

[0278] Encoded output Depend on Received, among which yes The polarization matrix. Encoding is performed in GF(2).

[0279] The above description is used to determine one or more of the following PC polarization-related parameters:

[0280] ● Whether to perform PC encoding on code blocks (CB) or transport blocks (TB).

[0281] ● Whether to perform PC encoding for specific sub-blocks, redundant versions, or transports.

[0282] ● The type of PC encoding used for a specific sub-block, redundant version, or transmission.

[0283] ● The number of sub-blocks with PC bits is obtained through PC encoding.

[0284] ● Obtain the index of the sub-block with PC bit through PC encoding.

[0285] These parameters can be predefined in standard specifications or transmitted via Radio Resource Control (RRC) messages or UCI signals.

[0286] Now for reference Figures 20A to 20C . Figure 20A Example devices including an encoding unit or module 2010 (hereinafter generally referred to as encoding module 2010), such as the aforementioned ED 110, T-TRP 170, and / or NT-TRP 172, are shown. For example, encoding module 2010 may be in... Figure 4 Provided based on any one or more units or modules shown, but for simplicity, not in... Figure 20A The diagram shows all the units or modules of the device. In some examples, the encoding module 2010 may be provided as a submodule of any of the units or modules described above. Figure 20A Also shown is the transmitting unit or module 2020 (hereinafter generally referred to as transmitting module 2020), which has been previously combined with Figure 4 It was discussed.

[0287] The encoding module 2010 and / or the transmitting module 2020 can be implemented as software, hardware, or a combination of software and hardware. For example, the encoding module 2010 and / or the transmitting module 2020 can be circuits such as integrated circuits. Examples of integrated circuits include programmed FPGAs, GPUs, or ASICs. For example, the encoding module 2010 and / or the transmitting module 2020 can be implemented at least partially as logic, such as logical functions performed by circuits, by a portion of an integrated circuit, or by software instructions executed by a processor, etc.

[0288] The encoding module 2010 and the transmitting module 2020 can be used by the transmitting device to encode the information bits of the bit vector into PC polarization codewords (e.g., using any example of this disclosure) and transmit the PC polarization codewords as wireless communication signals via a communication channel.

[0289] Specifically, the encoding module 2010 can encode information bit vectors into PC polar codewords, where PC encoding is used on a sub-block basis rather than on a codeword basis. Although in Figure 20AAs not shown, encoding module 2010 may include a PC encoding submodule and a polar encoding submodule. The PC encoding submodule can be used to generate a PC-encoded vector from the information bits of the information bit vector. As discussed elsewhere in this disclosure, a cyclic shift operation (which can be implemented using various hardware and / or software techniques, such as using a set of cyclically connected shift registers (also called cyclic shift registers), using hash functions, using lookup tables, using logic, etc.) can be used by the PC encoding submodule to generate PC bits from the information bits. The generated PC bits can be assigned to less reliable bit positions in the PC-encoded vector (e.g., frozen bit positions), while the information bits can be assigned to more reliable bit positions in the PC-encoded vector (e.g., information bit positions). The polar encoding submodule can then be used to generate PC-polarized codewords from the PC-encoded vector.

[0290] Figure 20B Another exemplary device is shown, including a decoding unit or module 2030 (hereinafter generally referred to as decoding module 2030), which may be an example of the ED 110, T-TRP 170, and / or NT-TRP 172 described above. Decoding module 2030 may be in... Figure 4 Provided based on any one or more units or modules shown, but for simplicity, not in... Figure 20B The diagram shows all the units or modules of the device. In some examples, the decoding module 2030 may be provided as a submodule of any of the units or modules described above. Figure 20B Also shown is a receiving unit or module 2040 (hereinafter generally referred to as receiving module 2040), which has been previously combined with Figure 4 It was discussed.

[0291] The decoding module 2030 and / or the receiving module 2040 can be implemented as software, hardware, or a combination of software and hardware. For example, the decoding module 2030 and / or the receiving module 2040 can be circuits such as integrated circuits. Examples of integrated circuits include programmed FPGAs, GPUs, or ASICs. For example, the decoding module 2030 and / or the receiving module 2040 can be implemented at least partially as logic, such as logical functions performed by circuits, by a portion of an integrated circuit, or by software instructions executed by a processor, etc.

[0292] The decoding module 2030 and the receiving module 2040 can be used by a receiving device to receive a wireless communication signal containing at least one sub-block of PC-polarized codewords, and to decode the sub-block to recover the information bits encoded in the sub-block. In particular, the decoding module 2030 can use the PC bits of the sub-block of PC-polarized codewords to decode the sub-block without needing other sub-blocks of PC-polarized codewords.

[0293] It should be understood that Figure 20A and Figure 20BThe same device can be represented. That is, a single device can have an encoding module 2010, a transmitting module 2020, a decoding module 2030, and a receiving module 2040. When the device is in the role of a transmitting device, it can perform encoding and transmitting; when the device is in the role of a receiving device, it can perform receiving and decoding operations. In some examples, the encoding module 2010 and the decoding module 2030 can be implemented together as an encoder / decoder module, and the transmitting module 2020 and the receiving module 2040 can be implemented together as a transceiver module.

[0294] Figure 20C An example of an encoding chain that can be implemented by the encoding module 2010 is shown.

[0295] As previously described, PC encoding can be implemented using a cyclic shift operation of a fixed-length array of elements, shifting by 1 at a time. In some examples, the cyclic shift operation can be implemented using a set of shift registers (e.g., the PC polarization encoding shift register described above), where wiring, connections, and outputs can be defined by polynomials. In other examples, the cyclic shift operation can be implemented using logic. Some implementations of the cyclic shift operation can use hash functions or lookup tables to generate the PC bits for a given fixed-length sequence of previous information bits. Within the scope of this disclosure, various software and / or hardware implementations of the cyclic shift operation are possible.

[0296] like Figure 20C As shown, the encoding process can be represented by three steps or stages.

[0297] The first step or stage is PC encoding 2012, where the length is bit vector (represented as) ) generated by PC encoding 1 auxiliary bit (or PC bit). The output of PC encoding 2012 is of length 1. PC-encoded vector (represented as) The operation of PC encoding 2012 can be represented as follows:

[0298]

[0299] In the above representation, PC encoding is determined by the pretransform matrix. Definition. In this example, PC encoding can be achieved using an upper triangular pretransformation matrix. Definition. Using the cyclic shift operation described above, each PC bit is generated based on the previous information bit with the smaller index. As mentioned above, PC encoding 2012 can be performed using a shift register. For example, the shift register can be a physical circuit or a logic shift register (e.g., implemented using software executed by a processor, as represented by the pseudocode above). In some examples, PC encoding 2012 can be performed without using a shift register, for example, by using a hash function or a lookup table to implement the pre-transform matrix. Other functional equivalents may be used within the scope of this disclosure.

[0300] The sub-channel selection module 2016 can instruct PC encoding 2012 and subsequent bit allocation 2014. Auxiliary bits. The number of auxiliary bits and their positions in the bit vector can be controlled by the sub-channel selection module 2016. The sub-channel selection module 2016 outputs several sub-channel sets, which can be called information sets. PC collection and frozen collection The information set defines the positions of the information bits in the PC-coded vector, the PC set defines the positions of the PC bits in the PC-coded vector, and the freeze set defines the positions of the frozen bits in the PC-coded vector. The information set, freeze set, and PC set can be defined based on the sub-channel reliability (e.g., positions corresponding to more reliable sub-channels can be defined as part of the information set, while positions corresponding to less reliable sub-channels can be defined as part of either the freeze set or the PC set). In some examples, the PC set can be a subset of the freeze set, meaning that some frozen positions can be allocated to carry PC bits, while other frozen positions still carry frozen bits. In some examples, all frozen positions can be allowed (or permitted) to be allocated to PC bits (this can be called "full check"). In some examples, even if all frozen positions are allowed to be allocated to PC bits, only frozen positions with indices greater than the minimum information bit index can be allocated to PC bits. In some examples, the information set, PC set, and freeze set can be defined for the total PC-coded vector. In some examples, the information set, PC set, and freeze set can be additionally or alternatively defined for individual sub-blocks of the PC-coded vector.

[0301] The sub-channel selection module 2016 determines the polar code. In which polarization sub-channel? Each subchannel is used to allocate PC-coded bits (which may include information bits), which One sub-channel is used to freeze bits.

[0302] After PC encoding 2012, a length of [length missing] is obtained. vector The vector can contain both information bits and PC bits, or it can contain only PC bits.

[0303] When the PC code is a system code, the vector It contains both information bits and PC bits, for example, in In the units digit, The units digit is the information digit. The units digit is an auxiliary digit.

[0304] When the PC code is a non-systematic code, the vector It only contains the PC bit; therefore, the input payload bit will not appear at all. middle.

[0305] In-place allocation steps or phases 2014, will The unit digit is allocated to the polarization sub-channel. If necessary, in Insert zeros between the units digit to generate a length of [length to be inserted] for polar coding. A vector. This can be represented as follows, where This represents a PC-encoded vector with zero padding.

[0306] →Zero Fill→

[0307] Zero padding is also controlled by the sub-channel selection module 2016, which inserts zeros with frozen bit values. The units digit (usually zero, and can be masked by the identifier bit).

[0308] Finally, in the polar coding step or stage 2018, the vector... (This can be done with zero padding) polar coding to obtain polar codewords. Polar code 2018 can be represented as follows, where... Indicates polarized codewords, This represents the polarization encoder matrix.

[0309]

[0310] Figure 21 This is a flowchart illustrating an exemplary method 2100 for generating PC-polarized codewords. For example, method 2100 can be implemented by a processor executing instructions of encoding module 2010 (and optionally transmitting module 2020). Method 2100 can be used to perform various examples of PC-polarized encoding described herein. In some examples, method 2100 can be performed by a means acting as a transmitting device.

[0311] Optionally, at operation 2102, a bit vector of the information bits to be encoded can be obtained. For example, the bit vector of the information bits can represent data to be sent to the intended receiving device (which may be generated by the device or received by the device).

[0312] In some examples, the bit vector may include information bits associated with data transmissions having different redundancy versions. For example, the bit vector may include information bits corresponding to a first codeword (e.g., a first short polarization codeword) used for initial data transmission (e.g., RV0) and information bits corresponding to a second codeword (e.g., a second short polarization codeword) used for data retransmission (e.g., RV1).

[0313] At operation 2104, a PC-coded vector is generated based on the bit vector of the information bits to be encoded. The generated PC-coded vector can have multiple sub-blocks, and each sub-block of the PC-coded vector can be generated with or without PC coding. Whether PC coding should be applied can be configured (e.g., based on a standard or by a control signal). For example, as described in this disclosure, a standard can define rules for applying PC coding based on various factors (e.g., based on the type of physical channel, one or more code parameters, one or more application scenarios, etc.).

[0314] As a detailed operation of operation 2104, operation 2106 can be performed on each sub-block using PC encoding. As described in this disclosure, the transmitting device can be used to apply PC encoding to different sub-blocks according to specific rules, such as based on the length of each sub-block. For simplicity, the following will refer to the first sub-block using PC encoding.

[0315] In some examples, PC encoding can be applied to subvectors of an input bit vector, wherein the bit length of the subvector is a power of 2. As described elsewhere in this disclosure, a bit vector can be divided into subvectors of length powers of 2, and PC encoding can be applied to one or more selected subvectors of length powers of 2.

[0316] Optionally, at operation 2108, if the shift register is used to generate the PC bit for the first subblock, the shift register can be reset or cleared first. This can be useful when the same shift register is used to generate PC bits for multiple subblocks. Resetting the shift register between subblocks helps ensure that the PC bit of one subblock is independent of another (e.g., the PC bit of the first subblock does not depend on the information bits of the second subblock, and the PC bit of the first subblock is decoupled from the PC bit of the second subblock). For example, clearing or resetting the shift register could mean resetting all elements of the shift register to have zero values ​​or a predefined set of values. In the example of resetting the shift register using a predefined set of values, the shift register could be reset to contain a set of values ​​based on the Radio Network Temporary Identifier (RNTI), such as a UE-specific RNTI (e.g., the RNTI of the expected receiving device), a public RNTI, or a cell-specific RNTI, etc.

[0317] At operation 2110, the information bits of the first sub-vector of the bit vector are assigned to the information bit positions of the first sub-block. The information bits can be assigned to the information bit positions of the first sub-block based on the information set defining those positions.

[0318] At operation 2112, one or more PC bits generated from the information bits of the first sub-vector are assigned to the corresponding one or more frozen bit positions of the first sub-block. The PC bits can be assigned to the frozen bit positions of the first sub-block based on a frozen set defining the frozen bit positions of the first sub-block or based on a PC set defining the PC positions of the first sub-block (the PC set may be a subset of the frozen set). PC bits can be assigned to frozen bit positions with indices greater than the minimum information bit index. That is, frozen bit positions preceding the first information bit position can carry only the frozen bit value, and PC bits can be assigned to frozen bit positions with indices greater than the index of the first information bit in the first sub-block. In some examples, all frozen bit positions can be allowed to carry PC bits. For example, all frozen bit positions with indices greater than the minimum information bit index can be assigned to carry the corresponding PC bits.

[0319] The PC bit can be generated from information bits using a circular shift operation. This circular shift operation can be implemented using a shift register (specifically a circular shift register), a hash function, a lookup table, software logic, or a pretransform matrix. As mentioned above, if a shift register is used, it can be a circular shift register that is reset between sub-blocks. The pretransform matrix can be an upper triangular matrix, where the dimensions of the matrix match the lengths of the subvectors to which the pretransform matrix is ​​applied. A lookup table may be suitable for generating each PC bit based on a relatively small number of information bits (e.g., fewer than 20 information bits), and may not be suitable for generating a large number of information bits, but it can still be used.

[0320] It is important to note that the PC bits are generated from any other sub-block of the first sub-vector, independent of the information bits of the PC-encoded vector. In other words, the PC bits assigned to the first sub-block are not generated from the information bits of any other sub-block (and similarly, the PC bits assigned to another sub-block are not generated from the information bits of the first sub-block). This means that the PC bits in the first sub-block can be used independently of any other sub-block to assist in decoding the information bits of the first sub-block.

[0321] It can be noted that the bit positions of the first sub-block can be filled bit by bit. For example, by incrementing the index of the first sub-block by 1 one at a time and (e.g., based on a predefined freeze set, information set, and PC set) determining whether the bit position at the current index should carry a freeze bit, information bit, or PC bit. If the current bit position should carry a freeze bit, a freeze bit value can be assigned to that bit position (e.g., a bit value of zero); if the current bit position should carry an information bit, the next information bit in an unassigned subvector can be assigned to that bit position; or, if the current bit position should carry a PC bit, the next PC bit can be assigned to that bit position (e.g., from the output of a circular shift operation, such as from a shift register, hash function, or lookup table, depending on the implementation).

[0322] Therefore, operations 2110 and 2112 can be performed together to assign the appropriate bits to each bit position of the first sub-block.

[0323] Operation 2106 is performed on each sub-block of the PC-encoded vector using PC encoding, including optional operations 2108, 2110, and 2112.

[0324] For a second sub-block of a PC-encoded vector that does not require PC encoding, (e.g., based on the freeze set and information set defined for the second sub-block) the information bits of the second sub-vector of the bit vector are assigned to the information bit positions of the second sub-block, and there are no PC bits in the second sub-block.

[0325] Therefore, a PC-encoded vector may include at least one sub-block that has been PC-encoded (i.e., has PC bits generated from the information bits of that sub-block). A PC-encoded vector may also include or may not include at least one other sub-block that has not been PC-encoded (i.e., no PC bits are generated from the information bits of that sub-block, and that sub-block has no PC bits). In some examples, a PC-encoded sub-block may correspond to a sub-vector with a bit length that is a power of 2, while a non-PC-encoded sub-block may correspond to a sub-vector with a bit length that is not a power of 2.

[0326] After all sub-blocks have been generated for the PC-encoded vector, the complete PC-encoded vector can be provided as input to the polar encoder.

[0327] At operation 2114, PC polar codewords are generated by applying polar codes to the PC-coded vector. For example, a polar coding matrix can be applied to the PC-coded vector.

[0328] At operation 2116, the PC polar codeword is output. For example, the PC polar codeword can be output by the encoding module.

[0329] Optionally, at operation 2118, PC polarization codewords can be transmitted. For example, the transmitting module of the transmitting device can transmit the PC polarization codewords as a wireless communication signal to the intended receiving device via a communication channel.

[0330] As previously mentioned, there can be one or more rules or configurations for generating PC-polarized codewords using PC encoding, depending on various factors such as the type of physical channel through which the codewords are transmitted, the type of traffic on the channel, one or more code parameters, one or more application scenarios, and combinations thereof. Some exemplary configurations are described now, but these examples are not intended to be limiting.

[0331] An exemplary configuration may be to use PC coding based on the type of the physical channel from which codewords are to be transmitted and / or based on the type of uplink / downlink traffic in the channel. For example, when the physical channel is a Physical Uplink Control Channel (PUCCH) carrying uplink control information (UCI) content including feedback (e.g., ACK or NACK feedback for a HARQ retransmission scheme) and scheduling request (SR) information, PC coding can be used to generate codewords, and all other physical channels may not use PC coding. In another example, when the physical channel is a PUCCH carrying UCI content including channel state information (CSI), PC coding can be used to generate codewords, and all other physical channels may not use PC coding. In another example, when the physical channel is a PUCCH not multiplexed on a Physical Uplink Shared Channel (PUSCH), PC coding can be used to generate codewords, and all other physical channels may not use PC coding. In yet another example, when the physical channel is an arbitrary PUCCH (including channels multiplexed on PUSCH), PC coding can be used to generate codewords, and all other physical channels may not use PC coding. In another example, when the physical channel is PUCCH or a physical broadcast channel (PBCH), PC encoding can be used to generate codewords, and all other physical channels may not use PC encoding. In another example, when the physical channel is PUCCH or a physical downlink control channel (PDCCH), PC encoding can be used to generate codewords, and all other physical channels may not use PC encoding. In another example, when the physical channel is a Level 1 PDCCH, PC encoding can be used to generate codewords; when the physical channel is a Level 2 PDCCH, PC encoding may not be used. In another example, when the physical channel is an arbitrary control channel (e.g., PUCCH, PBCH, or PDCCH), PC encoding can be used to generate codewords; when the physical channel is a data channel (e.g., PUSCH, PDSCH), PC encoding may not be used. In another example, when the physical channel is an arbitrary uplink channel (e.g., PUCCH or PUSCH), PC coding can be used to generate codewords; when the physical channel is a downlink channel (e.g., PBCH, PDCCH, or PDSCH), PC coding may not be used. In some of the configurations described above, there may be technical advantages that can improve the performance of shorter polar codes. In some configurations, there may also be technical advantages in terms of design uniformity, making the descriptions in the standard simpler.

[0332] Another exemplary configuration could be to use PC encoding based on one or more code parameters. For example, when the code length is at the maximum code length (which can be represented as...), (For example, the maximum code length can be 32, 64, 128, 256, 512, or 1024, etc.) PC encoding can be used to generate codewords. In another example, when the block length is within the maximum block length (which can be represented as...), PC encoding can be used to generate codewords. (For example, the maximum block length can be within block lengths of 11, 16, 19, 22, 24, 32, 64, 128, 256, or 512, etc.) PC encoding can be used to generate codewords. In another example, when the bitrate is within the maximum bitrate (expressed as...), PC encoding can be used to generate codewords. (For example, the maximum code rate could be 3 / 4, 2 / 3, 1 / 2, 2 / 5, 3 / 8, 1 / 4, or 1 / 8, etc.) PC encoding can be used to generate codewords. In another example, when the code length is within the maximum code length... (For example, the maximum code length as described above) within and also within the maximum code rate When within the maximum bit rate (as described above), PC encoding can be used to generate codewords.

[0333] Another exemplary configuration can be to use PC coding based on a combination of physical channel type and one or more code parameters. For example, any combination of the above configurations based on physical channel type and code parameters can be used. For instance, when the physical channel is PUCCH and the code length is at the maximum code length... (For example, the maximum code length can be within the range of 32, 64, 128, 256, 512, or 1024, etc.) PC encoding can be used to generate codewords. In another example, when the physical channel is PUCCH and the block length is within the maximum block length... (For example, when the maximum block length can be within the range of 11, 16, 19, 22, 24, 32, 64, 128, 256, or 512, etc.), PC coding can be used to generate codewords. In another example, when the physical channel type is Level 2 PDCCH and the codeword length is within the maximum codeword length... When the maximum code length is within the range of 32, 64, 128, 256, 512, or 1024, PC encoding can be used to generate codewords. It should be understood that other combinations of the above configurations can be used.

[0334] Another exemplary configuration could be to use PC encoding based on the priority of certain application scenarios and / or services (e.g., the priority of the data represented by the information bits to be encoded). For example, when the information bits are used for Ultra Reliable Low Latency Communication (URLLC) services, PC encoding can be used to generate codewords, and the PC encoding is not used for other physical channels. In some examples, PC encoding can be used to generate codewords when the information bits are used for high-priority communications (e.g., services associated with a specific priority index or an index indicating high priority), such as high-priority UCI content or high-priority data services.

[0335] Some exemplary configurations may include one or more rules that specify how PC coding should be performed to generate PC polar codewords. Different techniques for PC coding can be specified by combining certain physical channel types and / or coding parameters. For example, a standard may include a table indicating a specific type of PC coding for a particular physical channel and specific coding parameters.

[0336] One type of PC polar coding, which can be called Type I PC polar coding (or Type I PC polarization), can use a set of PC bits for each sub-block or a predefined number of PC bits, such as 3 PC bits, 6 PC bits, or 8 PC bits. Another type of PC polar coding, which can be called Type II PC polar coding (or Type II PC polarization), allows all frozen bits in a sub-block to be used as PC bits (it should be noted that since PC bits are generated from information bits, generally only frozen bit positions with indices greater than the minimum information bit index can be used as PC bit positions).

[0337] For example, when the channel is a PUCCH and the code length is within the maximum code length (e.g., within a maximum code length of 32, 64, 128, 256, 512, or 1024), Type I PC polar coding can be used; when the channel is a PUCCH and the code length is greater than the maximum code length, Type II PC polar coding can be used. In another example, when the channel is a PUCCH and the block length is within the maximum block length (e.g., within a maximum block length of 11, 16, 19, 22, 24, 32, 64, 128, 256, or 512), Type I PC polar coding can be used; when the channel is a PUCCH and the block length is greater than the maximum block length, Type II PC polar coding can be used. In yet another example, when the channel is a PUCCH, Type I PC polar coding can be used; when the channel is a PDCCH and / or PBCH, Type II PC polar coding can be used.

[0338] As mentioned earlier, there can be one or more rules or configurations for applying PC encoding to different sub-blocks, depending on various factors, such as the length of the sub-vectors used to generate the sub-blocks. Some exemplary configurations are described now, but these examples are not intended to be limiting.

[0339] One exemplary configuration could be to divide the bit vector into subvectors of length powers of 2 (in some examples, there may be subvectors of lengths other than powers of 2), and then apply PC encoding to generate the first or more sub-blocks (but fewer than all sub-blocks) from the subvectors. For example, PC encoding could be applied to generate the first, second, or fourth sub-blocks of a codeword. The advantage of this configuration is that more freeze bit positions can be allocated to carry the PC bit, thus contributing to greater coding gain. In another exemplary configuration, the bit vector can be divided into subvectors of length powers of 2 (in some examples, there may be subvectors of lengths other than powers of 2), and then apply PC encoding to generate the first or more sub-blocks (but fewer than all sub-blocks) containing information bits from the corresponding subvectors. For example, PC encoding could be applied to generate the first, second, or fourth sub-blocks containing information bits in a codeword. This configuration can be useful because, in cases where PC bits can only be generated after at least one information bit is present, only freeze bit positions with indices greater than the minimum information bit index can be used to carry the PC bit. In another exemplary configuration, the bit vector can be divided into subvectors of length powers of 2 (in some examples, there may be subvectors of length not powers of 2), and then PC encoding is applied to generate the last one or more sub-blocks (but fewer than all sub-blocks) from the corresponding subvectors. For example, PC encoding can be applied to generate the last sub-block, the last two sub-blocks, or the last four sub-blocks of the codeword. The advantage of this configuration is that the weight spectrum can be improved to a greater extent when PC encoding is used in the last one or more sub-blocks. In another exemplary configuration, the bit vector can be divided into subvectors of length powers of 2 (in some examples, there may be subvectors of length not powers of 2), and then PC encoding is applied to generate all sub-blocks from the corresponding subvectors. PC encoding can be applied independently or separately to generate each sub-block. This means that the PC bits in a given sub-block are generated only from the information bits of that given sub-block. Therefore, the PC bits in a given sub-block can be used only to assist in decoding that sub-block (e.g., to check the information bits of that sub-block). The advantage of this configuration is that sub-block SCL decoding can be used at the decoder of the receiving device, which helps to reduce memory footprint.

[0340] Figure 22This is a flowchart illustrating an exemplary method 2200 for decoding PC-polarized codewords. For example, method 2200 may be implemented by a processor executing instructions of decoding module 2030 (and optionally receiving module 2040). Method 2200 can be used to decode various examples of PC-polarized codewords described herein. In some examples, method 2200 may be executed by a device acting as a receiving device.

[0341] Optionally, at operation 2202, at least a first sub-block of the PC-polarized codeword is received. For example, the receiving module can receive a wireless communication signal via a communication channel, wherein at least a first sub-block of the PC-polarized codeword is carried by the signal. The PC-polarized codeword may include multiple sub-blocks. In some examples, not all sub-blocks of the PC-polarized codeword may be received. For example, only the first sub-block may be received. In some examples, at least another second sub-block and / or another third sub-block of the PC-polarized codeword may be received. In some examples, all sub-blocks of the PC-polarized codeword may be received.

[0342] At operation 2204, the PC bits in the first sub-block are used to decode the first sub-block. The PC bits in the first sub-block can be used to assist in decoding the first sub-block independently of any other sub-block containing the PC polarization codeword. Therefore, the first sub-block can be decoded even if no other sub-blocks containing the PC polarization codeword are received. For example, even if only the first sub-block is received, the first sub-block can be successfully decoded using only the PC bits contained in the first sub-block.

[0343] As discussed above, a PC-polarized codeword can include one or more sub-blocks that are PC-encoded and one or more sub-blocks that are not PC-encoded. Each type of sub-block can be decoded independently.

[0344] Optionally, at operation 2206, the PC bit in the second sub-block can be used to decode the second sub-block containing the PC bit. The PC bit of the second sub-block can be used independently of the first sub-block to assist in decoding, thereby decoding the second sub-block.

[0345] Optionally, at operation 2208, a third sub-block that does not contain a PC bit can be decoded without using the PC bit. The third sub-block can be decoded independently of the first and second sub-blocks.

[0346] At operation 2210, the decoded sub-block is output.

[0347] This disclosure includes various embodiments, not only method embodiments but also other embodiments, such as apparatus embodiments and embodiments related to non-transitory computer-readable storage media. Embodiments may individually or in combination incorporate the features disclosed herein.

[0348] Although this disclosure references illustrative embodiments, it is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of this disclosure, will be apparent to those skilled in the art upon reference to this specification.

[0349] Alternatively or additionally, features disclosed herein in the context of any particular embodiment may be implemented in other embodiments. For example, alternatively or additionally, method embodiments may be implemented in apparatus, system, and / or computer program product embodiments. Furthermore, although embodiments have been described primarily in the context of methods and apparatus, other implementations are contemplated, such as instructions stored on one or more non-transitory computer-readable media. Such media may store programs or instructions to perform any of the various methods consistent with this disclosure.

[0350] It should be understood that the examples disclosed herein can be embodied as a method, apparatus, non-transitory computer-readable medium, processing module, chipset, system chip, or computer program, etc. An apparatus may include a transmitting module for performing the transmitting steps described above and a receiving module for performing the receiving steps described above. An apparatus may include a processing module, processor, or processing unit for controlling or causing the apparatus to perform the examples disclosed herein.

[0351] Although this disclosure describes methods and processes in a specific order, one or more steps in the methods and processes may be omitted or modified as needed. One or more steps may be performed in an order other than that described, as required.

[0352] Although this disclosure describes at least part of the methodological aspects, those skilled in the art will understand that this disclosure also relates to various components, whether hardware components, software, or any combination thereof, for performing at least some aspects and features of the described methods. Therefore, the technical solutions of this disclosure can be embodied in the form of a software product. Suitable software products can be stored in pre-recorded storage devices or other similar non-volatile or non-transitory computer-readable media, including DVDs, CD-ROMs, USB flash drives, removable hard drives, or other storage media. The software product includes instructions tangibly stored thereon that enable a processing device (e.g., a personal computer, server, or network device) to perform the method examples disclosed herein. Machine-executable instructions can be in the form of code sequences, configuration information, or other data that, when executed, cause a machine (e.g., a processor or other processing device) to perform the steps of the methods executable in this disclosure.

[0353] This disclosure may be embodied in other specific forms without departing from the subject matter of the claims. The exemplary embodiments described are illustrative in all respects and not restrictive. Selected features from one or more of the foregoing embodiments may be combined to create alternative embodiments not explicitly described, and features suitable for such combinations are to be understood to fall within the scope of this disclosure.

[0354] Furthermore, all values ​​and sub-ranges within the scope of the disclosure are also disclosed. Additionally, although the systems, devices, and processes disclosed and illustrated herein may include a specific number of elements / components, the systems, devices, and assemblies may be modified to include more or fewer of these elements / components. For example, although any disclosed element / component may be a single quantity, embodiments disclosed herein may be modified to include multiple such elements / components. The subject matter described herein is intended to cover and include all suitable technical changes.

Claims

1. A method for generating codewords, characterized in that, The method includes: A parity check coding vector is generated based on the bit vector of the information bits to be encoded. The parity check coding vector includes multiple sub-blocks. The information bits of the first sub-vector of the bit vector are assigned to the information bit positions of the first sub-block among the multiple sub-blocks, and one or more parity bits generated from the information bits of the first sub-vector are assigned to the frozen bit positions of the first sub-block. Parity-check polar codewords are generated by applying polar codes to the parity-check coding vector; and Output the parity check polarization codeword.

2. The method according to claim 1, characterized in that, The one or more parity bits assigned to the freeze bit position of the first sub-block are generated independently of the second sub-block among the plurality of sub-blocks.

3. The method according to claim 2, characterized in that, The information bits of the second sub-vector of the bit vector are assigned to the information bit positions of the second sub-block, and the second sub-block has no parity bit.

4. The method according to 2, characterized in that: The one or more parity bits generated from the information bits of the first sub-vector form a first set of one or more parity bits; The information bits of the second sub-vector of the bit vector are assigned to the information bit positions of the second sub-block; and A second set of one or more parity bits generated from the information bits of the second sub-vector is assigned to the frozen bit position of the second sub-block, wherein the first set of one or more parity bits is decoupled from the second set of one or more parity bits.

5. The method according to claim 4, characterized in that, A circular shift register is used to generate a first set of the one or more parity bits and a second set of the one or more parity bits, and to clear the circular shift register between generating the first set of the one or more parity bits and generating the second set of the one or more parity bits.

6. The method according to claim 5, characterized in that, The circular shift register is cleared by resetting all bit values ​​stored in the circular shift register to a single predefined value or a set of predefined values.

7. The method according to claim 6, characterized in that, The set of predefined values ​​is based on the Radio Network Temporary Identifier (RNTI).

8. The method according to any one of claims 1 to 4, characterized in that, A circular shift register is used to generate one or more parity bits from the information bits of the first subvector.

9. The method according to any one of claims 1 to 4, characterized in that, The pre-transformation matrix is ​​used to generate the one or more parity bits from the information bits of the first sub-vector.

10. The method according to claim 9, characterized in that, The pre-transformation matrix is ​​an upper triangular square matrix.

11. The method according to any one of claims 1 to 4, characterized in that, The hash function is used to generate one or more parity bits from the information bits of the first subvector.

12. The method according to any one of claims 1 to 4, characterized in that, A lookup table is used to generate the one or more parity bits from the information bits of the first subvector.

13. The method according to any one of claims 1 to 12, characterized in that, The bit length of the first subvector is a power of 2.

14. The method according to any one of claims 1 to 13, characterized in that, The bit vector of the information bits includes a first polarization codeword for data transmission with a first redundancy version and a second polarization codeword for another data transmission with a second redundancy version, and the first sub-vector corresponds to the first polarization codeword.

15. The method according to claim 14, characterized in that, The data transmission with the first redundant version is the initial data transmission, and the data transmission with the second redundant version is the data retransmission.

16. The method according to any one of claims 1 to 15, characterized in that, All frozen bit positions in the first sub-block whose index is greater than the index of the first information bit in the first sub-block are allocated to carry parity bits.

17. The method according to any one of claims 1 to 16, characterized in that, The parity polarization codeword is generated based on the type of the physical channel through which it is to be transmitted.

18. The method according to claim 17, characterized in that, The parity-check polar code is generated based on the following: The physical channel is a physical uplink control channel carrying uplink control containing indication feedback and scheduling request information; The physical channel is a physical uplink control channel carrying uplink control containing information indicating channel status. The physical channel is a physical uplink control channel that is not multiplexed on the physical uplink shared channel; The physical channel is of any physical uplink control channel; The physical channel is either a physical uplink control channel or a physical broadcast channel. The physical channel is of the type of physical uplink control channel or physical downlink control channel; The physical channel is of the type of physical uplink control channel, physical downlink control channel, or physical broadcast channel; The physical channel is of type Level 1 physical downlink control channel; The physical channel is of any physical control channel; or The physical channel is of any physical uplink channel type.

19. The method according to any one of claims 1 to 18, characterized in that, The parity-check polarized codeword is generated based on one or more code parameters.

20. The method according to claim 19, characterized in that, The one or more code parameters include one or more of the following: The length of the code within the maximum code length; The length of the information block within the maximum information block length; Bitrate within the maximum bitrate range; or The code length within the maximum code length and the code rate within the maximum code rate.

21. The method according to any one of claims 1 to 20, characterized in that, The parity-check polarization codeword is generated based on one or more communication scenarios.

22. The method according to claim 21, characterized in that, The one or more communication scenarios include one or more of the following: Communication used for ultra-reliable low-latency communication; or Communication used for high-priority communication.

23. The method according to any one of claims 1 to 22, characterized in that, Also includes: The parity-check polar codeword is transmitted through the communication channel.

24. The method according to any one of claims 1 to 234, characterized in that, Also includes: The bit vector of the information bits is obtained.

25. A method for decoding codewords, characterized in that, The method includes: The first sub-block is decoded by using one or more parity bits in at least a first sub-block of a parity-check polar codeword having multiple sub-blocks to assist in decoding the first sub-block; and Output the first sub-block after decoding.

26. The method according to claim 25, characterized in that, The first sub-block is received in the absence of the second sub-block among the plurality of sub-blocks.

27. The method according to claim 25, characterized in that, The second sub-block among the plurality of sub-blocks does not have a parity bit, and the method further includes: Decoding the second sub-block independently of the first sub-block; and Output the decoded second sub-block.

28. The method according to claim 25, characterized in that, Also includes: Independent of the first sub-block, the second sub-block is decoded by using one or more parity bits from the second sub-block among the plurality of sub-blocks to assist in decoding the second sub-block; as well as Output the decoded second sub-block.

29. The method according to any one of claims 25 to 28, characterized in that, Also includes: Receive at least the first sub-block.

30. An apparatus, characterized in that, include: processor; as well as The memory includes instructions that, when executed by the processor, cause the apparatus to perform the method according to any one of claims 1 to 29.

31. An apparatus, characterized in that, include: An encoding module is configured to perform the method according to any one of claims 1 to 24; or A decoding module for performing the method according to any one of claims 25 to 29.

32. A non-transitory computer-readable medium storing machine-executable instructions, characterized in that, When the instructions are executed by the device, the device performs the method according to any one of claims 1 to 29.

33. A processing module, characterized in that, For controlling the device to cause the device to perform the method according to any one of claims 1 to 29.

34. A chip or chipset, characterized in that, Includes a processor for executing instructions to cause the apparatus to perform the method according to any one of claims 1 to 29.

35. A computer program, characterized in that, When the computer program is run on a computer, it causes the computer to perform the method according to any one of claims 1 to 29.

Images