Signal processing device

Abstract

Combining multiple antenna arrays can sometimes lead to a decrease in transmit and receive performance. A signal processing apparatus converts two polarized waves and corresponding first and second signals, wherein the two polarized waves are modulated by different data and their vibration directions are orthogonal. The signal processing apparatus comprises: a first antenna array and a second antenna array, each including multiple antennas, each having a first feed point and a second feed point; a first signal circuit electrically connected to the multiple first feed points of the first antenna array; a second signal circuit electrically connected to the multiple second feed points of the first antenna array; a third signal circuit electrically connected to the multiple first feed points of the second antenna array; a fourth signal circuit electrically connected to the multiple second feed points of the second antenna array; a first selection circuit selectively connecting one of the nodes of the first signal and the second signal to the first signal circuit, and selectively connecting the other to the second signal circuit; and a second selection circuit selectively connecting one of the nodes of the first signal and the second signal to the third signal circuit, and selectively connecting the other to the fourth signal circuit.

Description

Technical Field

[0001] This disclosure relates to a signal processing apparatus. Background Technology

[0002] Patent document 1 discloses a method for combining multiple antenna arrays.

[0003] Existing technical documents Patent documents Patent Document 1: International Publication WO2022 / 176646. Summary of the Invention

[0004] The problem the invention aims to solve When multiple antenna arrays are combined, the polarization waves radiated from the predetermined antenna array may become noise when the predetermined antenna array is rotated relative to the other antenna arrays, resulting in a decrease in transmission and reception performance.

[0005] Solution for solving the problem One aspect of this disclosure relates to a signal processing apparatus that converts two polarized waves into each other with a first signal and a second signal corresponding to the two polarized waves. The two polarized waves are modulated by different data and their vibration directions are orthogonal to each other. The signal processing apparatus comprises: a first antenna array including a plurality of antennas, each antenna having a first feed point and a second feed point; a second antenna array including a plurality of antennas, each antenna having a first feed point and a second feed point; a first signal circuit electrically connected to the plurality of first feed points of the first antenna array; a second signal circuit electrically connected to the plurality of second feed points of the first antenna array; a third signal circuit electrically connected to the plurality of first feed points of the second antenna array; a fourth signal circuit electrically connected to the plurality of second feed points of the second antenna array; a first selection circuit selectively connecting one of the nodes of the first signal and the second signal to the first signal circuit and selectively connecting the other to the second signal circuit; and a second selection circuit selectively connecting one of the nodes of the first signal and the second signal to the third signal circuit and selectively connecting the other to the fourth signal circuit.

[0006] Invention Effects It can improve the transmission and reception performance of signal processing devices. Attached Figure Description

[0007] Figure 1 This is a schematic diagram showing the structure of the signal processing apparatus according to this embodiment.

[0008] Figure 2 This is a schematic diagram showing the structure of the signal processing apparatus according to this embodiment.

[0009] Figure 3 This is a schematic diagram showing the structure of the signal processing apparatus according to this embodiment.

[0010] Figure 4 This is a top view showing an example of the structure of an antenna array.

[0011] Figure 5 This is a cross-sectional view showing an example of the structure of an antenna array.

[0012] Figure 6 This is a schematic diagram showing the structure of a signal processing device.

[0013] Figure 7 This is a schematic diagram showing the structure of a signal processing device.

[0014] Figure 8 This is a schematic diagram showing the structure of a signal processing device.

[0015] Figure 9 This is a cross-sectional view showing the structure of the signal processing device.

[0016] Figure 10 This is a top view showing the structure of the connector.

[0017] Figure 11 This is a top view showing the signal distribution in the connector.

[0018] Figure 12 This is a top view showing an example of a combination of multiple antenna arrays.

[0019] Figure 13 This is a schematic diagram showing the structure of a signal processing device.

[0020] Figure 14 This is a schematic diagram showing the structure of a signal processing device.

[0021] Figure 15 This is a top view showing an example of a combination of multiple antenna arrays.

[0022] Figure 16 This is a cross-sectional view showing the structure of the signal processing device.

[0023] Figure 17 This is a schematic diagram showing the structure of a signal processing device.

[0024] Figure 18 This is a schematic diagram showing the structure of a signal processing device. Detailed Implementation

[0025] Figures 1 to 3 This is a schematic diagram showing the structure of the signal processing apparatus according to this embodiment. Figure 4This is a top view showing an example of the structure of an antenna array. Figure 5 This is a cross-sectional view showing an example of the structure of an antenna array. For example... Figures 1 to 3 As shown, the signal processing device 10 is a signal processing device that converts two polarized waves into each other with a first signal S1 and a second signal S2 corresponding to the two polarized waves. The two polarized waves are modulated by different data and their vibration directions are orthogonal to each other. The signal processing device 10 includes: a first antenna array T1, which includes multiple antennas JA, JB, JC, and JD (hereinafter referred to as JA~JD), each antenna having a first feed point P1 and a second feed point P2; a second antenna array T2, which includes multiple antennas JA~JD, each antenna having a first feed point P1 and a second feed point P2; a first signal circuit C1, which is electrically connected to the multiple first feed points P1 of the first antenna array T1; and a second signal circuit C2, which is connected to the first antenna array T1. Multiple second feed points P2 are electrically connected; a third signal circuit C3 is electrically connected to multiple first feed points P1 of the second antenna array T2; a fourth signal circuit C4 is electrically connected to multiple second feed points P2 of the second antenna array T2; a first selection circuit X1 selectively connects one of the nodes U1 of the first signal S1 and the node U2 of the second signal S2 to the first signal circuit C1 and selectively connects the other to the second signal circuit C2; and a second selection circuit X2 selectively connects one of the nodes U1 of the first signal S1 and the node U2 of the second signal S2 to the third signal circuit C3 and selectively connects the other to the fourth signal circuit C4. The signal processing device 10 also includes a control unit CS that controls the first and second selection circuits X1 and X2 and the first to fourth signal circuits C1 to C4.

[0026] The signal processing device 10 controls the first and second selection circuits X1 and X2 according to the positional relationship between the first antenna array T1 and the second antenna array T2, thereby improving the transmission and reception performance.

[0027] like Figure 4 and Figure 5As shown, the first antenna array T1 includes: a substrate ST; a ground conductor MG on the substrate ST; an insulating film ZF on the ground conductor MG; and radiating elements MA, MB, MC, and MD (hereinafter referred to as MA to MD) on the insulating film ZF. The ground conductor MG and the radiating elements MA to MD can be rectangular (e.g., square) metal films. The first antenna array T1 includes: an antenna JA containing radiating elements MA and ground conductor MG; an antenna JB containing radiating elements MB and ground conductor MG; an antenna JC containing radiating elements MC and ground conductor MG; and an antenna JD containing radiating elements MD and ground conductor MG. Multiple antennas JA to JD are arranged in a first direction D1. In each antenna JA to JD, a first feed point P1 is located between the antenna center and a side parallel to the first direction D1, and a second feed point P2 is located between the antenna center and a side parallel to the second direction D2 (orthogonal to D1).

[0028] When fed to the first feed point P1, the vibration direction (polarization direction) of the polarized wave radiated is the second direction D2, and when fed to the second feed point P2, the vibration direction (polarization direction) of the polarized wave radiated is the first direction D1. The second antenna array T2 has the same structure as the first antenna array T1. When the second antenna array T2 is rotated 90 degrees relative to the first antenna array T1, ( Figures 1-3 When the polarized wave is fed to the first feed point P1, the vibration direction (polarization direction) of the polarized wave is the first direction D1, and when the polarized wave is fed to the second feed point P2, the vibration direction (polarization direction) of the polarized wave is the second direction D2.

[0029] like Figure 1 and Figure 2 As shown, the first signal circuit C1 includes: amplifiers 18 and 19; a mixer M1; a first phase adjustment circuit (phase shifters 1A to 1D); amplifiers 5A to 5D; and amplifiers 6A to 6D. Amplifiers 18 and 19 are connected to the first selection circuit X1. Amplifiers 5A to 5D and 6A to 6D are connected to the first antenna array T1. Specifically, amplifiers 5A and 6A are connected to the first feed point P1 of antenna JA, amplifiers 5B and 6B are connected to the first feed point P1 of antenna JB, amplifiers 5C and 6C are connected to the first feed point P1 of antenna JC, and amplifiers 5D and 6D are connected to the first feed point P1 of antenna JD.

[0030] like Figure 1 and Figure 2As shown, the second signal circuit C2 includes: amplifiers 28 and 29; mixer M2; second phase adjustment circuit (phase shifters 2A to 2D); amplifiers 7A to 7D; and amplifiers 8A to 8D. Amplifiers 28 and 29 are connected to the first selection circuit X1. Amplifiers 7A to 7D and amplifiers 8A to 8D are connected to the first antenna array T1. Specifically, amplifiers 7A and 8A are connected to the second feed point P2 of antenna JA, amplifiers 7B and 8B are connected to the second feed point P2 of antenna JB, amplifiers 7C and 8C are connected to the second feed point P2 of antenna JC, and amplifiers 7D and 8D are connected to the second feed point P2 of antenna JD.

[0031] like Figure 1 and Figure 3 As shown, the third signal circuit C3 includes: amplifiers 38 and 39; mixer M3; third phase adjustment circuit (phase shifters 3A-3D); amplifiers 5A-5D; and amplifiers 6A-6D. Amplifiers 38 and 39 are connected to the second selection circuit X2. Amplifiers 5A-5D and 6A-6D are connected to the second antenna array T2. Specifically, amplifiers 5A and 6A are connected to the first feed point P1 of antenna JA, amplifiers 5B and 6B are connected to the first feed point P1 of antenna JB, amplifiers 5C and 6C are connected to the first feed point P1 of antenna JC, and amplifiers 5D and 6D are connected to the first feed point P1 of antenna JD.

[0032] like Figure 1 and Figure 3 As shown, the fourth signal circuit C4 includes: amplifiers 48 and 49; mixer M4; fourth phase adjustment circuit (phase shifters 4A-4D); amplifiers 7A-7D; and amplifiers 8A-8D. Amplifiers 48 and 49 are connected to the second selection circuit X2. Amplifiers 7A-7D and 8A-8D are connected to the second antenna array T2. Specifically, amplifiers 7A and 8A are connected to the second feed point P2 of antenna JA, amplifiers 7B and 8B are connected to the second feed point P2 of antenna JB, amplifiers 7C and 8C are connected to the second feed point P2 of antenna JC, and amplifiers 7D and 8D are connected to the second feed point P2 of antenna JD.

[0033] The first signal S1 can be an intermediate frequency (IF) signal or a baseband signal; similarly, the second signal S2 can also be an IF signal or a baseband signal. The first to fourth signal circuits C1 to C4 each include a mixer (M1 to M4) for mixing the local oscillator signal LO with the IF signal. For example, the mixer M1 of the first signal circuit C1 is configured on the signal path between the first selection circuit X1 and the first antenna array T1. For example, in the first signal circuit C1, the mixer M1 is connected to multiple signal paths, and in each signal path, a phase shifter 1A, an amplifier 5A, and an amplifier 6A are configured between the mixer M1 and the first feed point P1.

[0034] Figure 6 This is a schematic diagram showing the structure of a signal processing device. For example... Figure 6 As shown, the transmission function of the first selection circuit X1 when it connects node U1 of the first signal S1 to the first signal circuit C1 and node U2 of the second signal S2 to the second signal circuit C2 is as follows.

[0035] The first signal S1 (IF signal or baseband signal) is input to mixer M1 via amplifier 18. Mixer M1 multiplies the first signal S1 with the LO signal (local oscillator signal) used for up-conversion and outputs a high-frequency signal. This high-frequency signal is divided into four paths: the first branch signal is supplied to the first feed point P1 of antenna JA via phase shifter 1A and amplifier 5A; the second branch signal is supplied to the first feed point P1 of antenna JB via phase shifter 1B and amplifier 5B; the third branch signal is supplied to the first feed point P1 of antenna JC via phase shifter 1C and amplifier 5C; and the fourth branch signal is supplied to the first feed point P1 of antenna JD via phase shifter 1D and amplifier 5D. Thus, a polarized wave corresponding to the first signal S1 is radiated from the first antenna array T1 (antennas JA to JD). The LO signal is converted into a desired integer multiple frequency signal via frequency multiplier circuit (harmonic generation circuit) 85 and amplifier 95, and this integer multiple frequency signal is input to mixer M1.

[0036] The second signal S2 (IF signal or baseband signal) is input to mixer M2 via amplifier 28. Mixer M2 multiplies the second signal S2 with the LO signal (local oscillator signal) used for up-conversion and outputs a high-frequency signal. This high-frequency signal is divided into four paths: the first branch signal is supplied to the second feed point P2 of antenna JA via phase shifter 2A and amplifier 7A; the second branch signal is supplied to the second feed point P2 of antenna JB via phase shifter 2B and amplifier 7B; the third branch signal is supplied to the second feed point P2 of antenna JC via phase shifter 2C and amplifier 7C; and the fourth branch signal is supplied to the second feed point P2 of antenna JD via phase shifter 2D and amplifier 7D. Thus, a polarized wave corresponding to the second signal S2 is radiated from the first antenna array T1 (antennas JA to JD). The LO signal is converted into a desired integer multiple frequency signal via frequency multiplier circuit (harmonic generation circuit) 85 and amplifier 95, and this integer multiple frequency signal is input to mixer M2.

[0037] Figure 6The receiving function in the illustrated case is as follows: The high-frequency signal received by antenna JA is input to mixer M1 via the first feed point P1, amplifier 6A, and phase shifter 1A. The high-frequency signal received by antenna JB is input to mixer M1 via the first feed point P1, amplifier 6B, and phase shifter 1B. The high-frequency signal received by antenna JC is input to mixer M1 via the first feed point P1, amplifier 6C, and phase shifter 1C. The high-frequency signal received by antenna JD is input to mixer M1 via the first feed point P1, amplifier 6D, and phase shifter 1D. Mixer M1 multiplies the high-frequency signal with the LO signal (local oscillator signal) used for down-conversion and outputs an intermediate frequency (IF) signal or a baseband signal. This IF signal or baseband signal is extracted as the first signal S1 via the first selection circuit X1.

[0038] The high-frequency signal received by antenna JA is input to mixer M2 via the second feed point P2, amplifier 8A, and phase shifter 2A. The high-frequency signal received by antenna JB is input to mixer M2 via the second feed point P2, amplifier 8B, and phase shifter 2B. The high-frequency signal received by antenna JC is input to mixer M2 via the second feed point P2, amplifier 8C, and phase shifter 2C. The high-frequency signal received by antenna JD is input to mixer M2 via the second feed point P2, amplifier 8D, and phase shifter 2D. Mixer M2 multiplies the high-frequency signal with the LO signal (local oscillator signal) used for down-conversion and outputs an intermediate frequency (IF) signal or baseband signal. This IF signal or baseband signal is extracted as the second signal S2 via the first selection circuit X1.

[0039] like Figure 1 As shown, in the signal processing device 10, let m be an integer greater than or equal to 2, and n be a natural number less than m. The first antenna array T1 arranges m antennas (e.g., m=4) in the first direction D1 and n antennas (e.g., n=1) in the second direction D2, which is orthogonal to the first direction D1. The second antenna array T2 arranges n antennas (e.g., n=1) in the first direction D1 and m antennas (e.g., m=4) in the second direction D2. Alternatively, the first antenna array T1 and the second antenna array T2 can have the same structure, with the second antenna array T2 rotated 90 degrees relative to the first antenna array T1. The first antenna array T1 and the second antenna array T2 can also be arranged on the same plane.

[0040] Figure 7 and Figure 8 A schematic diagram showing the structure of a signal processing device is provided. Figure 8 As shown, the first antenna array T1 and the second antenna array T2 have the same structure. When the second antenna array T2 is rotated 90 degrees relative to the first antenna array T1, as shown... Figures 6 to 8As shown, the first selection circuit X1 inputs the first signal S1 to the first signal circuit C1 and the second signal S2 to the second signal circuit C2; the second selection circuit X2 inputs the first signal S1 to the fourth signal circuit C4 and the second signal S2 to the third signal circuit C3. Therefore, the vibration direction corresponding to the first signal S1 of the first antenna array T1 is orthogonal to the vibration direction corresponding to the second signal S2 of the second antenna array T2, preventing them from becoming parallel (and thus becoming noise).

[0041] like Figure 2 , Figure 3 and Figure 6 , Figure 7 As shown, the first signal circuit C1 includes a first phase adjustment circuit containing multiple phase shifters 1A to 1D, the second signal circuit C2 includes a second phase adjustment circuit containing multiple phase shifters 2A to 2D, the third signal circuit C3 includes a third phase adjustment circuit containing multiple phase shifters 3A to 3D, and the fourth signal circuit C4 includes a fourth phase adjustment circuit containing multiple phase shifters 4A to 4D.

[0042] exist Figure 1 In this case, one of the third phase adjustment circuits (3A-3D) and the fourth phase adjustment circuit (4A-4D) performs a 180° phase shift, while the other does not. For example, the third phase adjustment circuit (3A-3D) of the third signal circuit C3 may not perform a phase shift, while the fourth phase adjustment circuit (4A-4D) of the fourth signal circuit C4 may perform a 180° phase shift. Alternatively, the first phase adjustment circuit (1A-1D) of the first signal circuit C1 and the second phase adjustment circuit (2A-2D) of the second signal circuit C2 may both not perform a phase shift.

[0043] Figure 9 This is a cross-sectional view showing the structure of the signal processing device. Figure 10 This is a top view showing the structure of the connector. Figure 11 This is a top view showing the signal distribution within the connector. (Example) Figure 9 As shown, the first antenna array T1 and the second antenna array T2 can be connected to the same plane via connecting member Y. A connector 21 is disposed on the bottom (back) surface of the first antenna array T1. Connector 21 can be electrically connected to the distribution board DS via connector 31, wiring W, connector 41, and connector 51. Connectors 31 and 41 can be connected to both sides of wiring W. Connector 51 can be disposed on the upper surface of the distribution board DS.

[0044] The bottom (back) surface of the first antenna array T1 is equipped with an RFIC 11, a power IC 90, and a connector 21 electrically connected to the RFIC 11. First and second signals S1, S2, and LO signals can be input and output between the distribution board DS and the RFIC 11. The RFIC 11 includes first and second signal circuits C1 and C2, and a first selection circuit X1. Similarly, the bottom (back) surface of the second antenna array T2 is equipped with an RFIC 12, a power IC, and a connector 22 electrically connected to the RFIC 12. First and second signals S1, S2, and LO signals can be input and output between the distribution board DS and the RFIC 12. The RFIC 12 includes third and fourth signal circuits C3 and C4, and a second selection circuit X2. A connector 52 electrically connected to the connector 22 via wiring is disposed on the upper surface of the distribution board DS.

[0045] like Figure 10 and Figure 11 As shown, the signal assignments for each pin in connector 51 (first connector) and connector 52 (second connector) can be the same. Figure 11 In allocation type 101, pin a is assigned IF2 (second signal S2), pin b is assigned GND, pin c is assigned Ctrl1 (control signal), pin d is assigned GND, pin e is assigned VDD, pin f is assigned GND, pin g is assigned GND, pin h is assigned Ctrl2 (control signal), pin i is assigned GND, and pin j is assigned IF1 (first signal S1) and the LO signal. Allocation type 101 is one example; allocation types 102 to 104 are also possible. For example, the control signals (Ctrl1, Ctrl2) in RFIC 11 can be input from the control unit CS to the first and second signal circuits C1 and C2, and the first and second selection circuits X1 and X2, etc.

[0046] Figure 12 This is a top view showing an example of a combination of multiple antenna arrays. (Example) Figure 12 As shown, a second antenna array T2 (1×4 antennas) rotated 90 degrees to the left and a sixth antenna array T6 (1×4 antennas) rotated 90 degrees to the right can be configured adjacent to the first antenna array T1 (4×1 antennas), the third antenna array T3 (4×1 antennas), the fourth antenna array T4 (4×1 antennas), and the fifth antenna array T5 (4×1 antennas) arranged along the second direction D2.

[0047] Let λ be the wavelength of the two polarized waves radiated or absorbed from the antenna array. One antenna JD in the first antenna array T1 and one antenna JA in the second antenna array T2 can be adjacent in the first direction D1 with a spacing PT of half wavelength (λ / 2).

[0048] In the first antenna array T1, two adjacent antennas (e.g., antenna JC and antenna JD) in the first direction D1 can be adjacent in the first direction D1 with a spacing of half a wavelength (λ / 2) PT. When the wavelengths of the two polarized waves are different, the wavelength of one of them can be used as λ for design.

[0049] Figure 13 and Figure 14 This is a schematic diagram showing the structure of a signal processing device. For example... Figure 12 and Figure 13 As shown, the signal processing device 10 may further include: a third antenna array T3 comprising a plurality of antennas, each antenna having a first feed point P1 and a second feed point P2; a fifth signal circuit C5 electrically connected to the plurality of first feed points P1 of the third antenna array T3; a sixth signal circuit C6 electrically connected to the plurality of second feed points P2 of the third antenna array T3; and a third selection circuit X3 that selectively inputs one of a first signal S1 and a second signal S2 to the fifth signal circuit C5 and selectively inputs the other to the sixth signal circuit C6. In the third antenna array T3, m antennas (e.g., m=4) can be arranged in the first direction D1, and n antennas (e.g., n=1) can be arranged in the second direction D2, such as... Figure 14 As shown, the third selection circuit X3 can connect node U1 of the first signal S1 to the fifth signal circuit C5, and connect node U2 of the second signal S2 to the sixth signal circuit C6.

[0050] Figure 15 This is a top view showing an example of a combination of multiple antenna arrays. (Example) Figure 15 As shown, the first antenna array T1 and the third antenna array T3 have the same structure, with the third antenna array T3 rotated 180 degrees relative to the first antenna array T1. In this case, as... Figure 14 As shown, the fifth signal circuit C5 includes a fifth phase adjustment circuit containing multiple phase shifters (15A to 15D), and the sixth signal circuit C6 includes a sixth phase adjustment circuit containing multiple phase shifters (16A to 16D). The fifth phase adjustment circuit (15A to 15D) and the sixth phase adjustment circuit (16A to 16D) respectively perform a 180° phase shift.

[0051] Figure 16 This is a cross-sectional view showing the structure of the signal processing device. For example... Figure 16 As shown, the connector 21, which is configured on the back of the first antenna array T1 and is electrically connected to the RFIC 11, and the connector 51 on the distribution board DS can be directly fitted together without wiring, thereby realizing the electrical connection between the RFIC 11 and the distribution board DS.

[0052] Figure 17 and Figure 18This is a schematic diagram showing the structure of a signal processing device. For example... Figure 17 As shown, when the mixed signal of the first signal S1 and the LO signal (refer to...) Figure 11 When the signal is input to RFIC11, the first signal S1 and the LO signal can be separated by the separation circuit 88, allowing only the first signal S1 to be input to the first selection circuit X1. The LO signal is input to the frequency multiplier circuit (harmonic generator circuit) 85. Figure 18 As shown, in the first signal circuit C1, a phase shifter 91 can be configured between the mixer M1 and the first phase adjustment circuit containing multiple phase shifters (1A to 1D), thereby allowing phase setting of the four-way branch portion to be performed in the phase shifter 91. Similarly, in the second signal circuit C2, a phase shifter 92 can be configured between the mixer M2 and the second phase adjustment circuit containing multiple phase shifters (2A to 2D).

[0053] The above embodiments are provided for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art can make various modified embodiments based on the above examples and descriptions.

[0054] (Mutual citation of related applications) This application incorporates the entire contents of Japanese Patent Application No. 2024-053882.

[0055] Explanation of reference numerals in the attached figures 10. Signal Processing Device 11 RFIC 12 RFIC X1 First Selection Circuit X2 Second Selection Circuit C1 First Signal Circuit C2 Second Signal Circuit C3 Third Signal Circuit C4 Fourth Signal Circuit CS Control Department JA~JD antenna P1 First feed point P2 Second Feed Point T1 First Antenna Array T2 Second Antenna Array.

Claims

1. A signal processing apparatus that converts two polarized waves into each other with a first signal and a second signal corresponding to the two polarized waves, wherein the two polarized waves are modulated by different data and their vibration directions are orthogonal to each other, characterized in that, The signal processing device includes: The first antenna array includes multiple antennas, each of which has a first feed point and a second feed point; The second antenna array includes multiple antennas, each of which has a first feed point and a second feed point. A first signal circuit is electrically connected to a plurality of first feed points of the first antenna array; The second signal circuit is electrically connected to multiple second feed points of the first antenna array; The third signal circuit is electrically connected to multiple first feed points of the second antenna array; The fourth signal circuit is electrically connected to multiple second feed points of the second antenna array; A first selection circuit selectively connects one of the nodes of the first signal and the second signal to the first signal circuit, and selectively connects the other to the second signal circuit. as well as The second selection circuit selectively connects one of the nodes of the first signal and the second signal to the third signal circuit, and selectively connects the other to the fourth signal circuit.

2. The signal processing apparatus according to claim 1, characterized in that, Let m be an integer greater than or equal to 2, and n be a natural number less than m. The first antenna array has m antennas arranged in a first direction and n antennas arranged in a second direction orthogonal to the first direction. The second antenna array has n antennas arranged in the first direction and m antennas arranged in the second direction.

3. The signal processing apparatus according to claim 2, characterized in that, The first antenna array and the second antenna array have the same structure. The second antenna array is configured with its orientation rotated 90 degrees relative to the first antenna array.

4. The signal processing apparatus according to claim 2, characterized in that, The first selection circuit inputs the first signal to the first signal circuit and inputs the second signal to the second signal circuit. The second selection circuit inputs the first signal to the fourth signal circuit and the second signal to the third signal circuit.

5. The signal processing apparatus according to claim 1, characterized in that, The first antenna array and the second antenna array are arranged on the same plane.

6. The signal processing apparatus according to claim 2, characterized in that, Let the wavelengths of the two polarization waves be λ. One antenna in the first antenna array is adjacent to one antenna in the second antenna array in the first direction at a distance of λ / 2.

7. The signal processing apparatus according to claim 6, characterized in that, In the first antenna array, two adjacent antennas in the first direction are arranged with a half-wavelength spacing.

8. The signal processing apparatus according to claim 2, characterized in that, It also has: The third antenna array includes multiple antennas, each of which has a first feed point and a second feed point. The fifth signal circuit is electrically connected to multiple first feed points of the third antenna array; The sixth signal circuit is electrically connected to multiple second feed points of the third antenna array; as well as The third selection circuit selectively inputs one of the nodes of the first signal and the second signal to the fifth signal circuit, and selectively inputs the other to the sixth signal circuit.

9. The signal processing apparatus according to claim 8, characterized in that, The third antenna array has m antennas arranged in the first direction and n antennas arranged in the second direction.

10. The signal processing apparatus according to claim 8, characterized in that, The third selection circuit inputs the first signal to the fifth signal circuit and the second signal to the sixth signal circuit.

11. The signal processing apparatus according to claim 2, characterized in that, The first signal circuit includes a first phase adjustment circuit containing multiple phase shifters. The second signal circuit includes a second phase adjustment circuit containing multiple phase shifters. The third signal circuit includes a third phase adjustment circuit containing multiple phase shifters. The fourth signal circuit includes a fourth phase adjustment circuit containing multiple phase shifters.

12. The signal processing apparatus according to claim 11, characterized in that, One of the third phase adjustment circuit and the fourth phase adjustment circuit performs a 180° phase shift, while the other does not perform a phase shift.

13. The signal processing apparatus according to claim 12, characterized in that, Neither the first phase adjustment circuit nor the second phase adjustment circuit performs phase shifting.

14. The signal processing apparatus according to claim 9, characterized in that, The first antenna array and the third antenna array have the same structure. The third antenna array is configured with its orientation rotated 180 degrees relative to the first antenna array.

15. The signal processing apparatus according to claim 14, characterized in that, The fifth signal circuit includes a fifth phase adjustment circuit containing multiple phase shifters. The sixth signal circuit includes a sixth phase adjustment circuit containing multiple phase shifters. Both the fifth phase adjustment circuit and the sixth phase adjustment circuit perform a 180° phase shift.

16. The signal processing apparatus according to any one of claims 1 to 15, characterized in that, It also has: A first connector, which is electrically connected to the first signal circuit and the first selection circuit; and The second connector is electrically connected to the second signal circuit and the second selection circuit. In both the first and second connectors, the signal assignments for each pin are the same.

17. The signal processing apparatus according to any one of claims 1 to 15, characterized in that, The first signal is an intermediate frequency signal or a baseband signal.

18. The signal processing apparatus according to claim 17, characterized in that, The first to fourth signal circuits each include a mixer, which mixes the local oscillator signal with the intermediate frequency signal or the baseband signal.

19. The signal processing apparatus according to claim 18, characterized in that, The mixer of the first signal circuit is configured on the signal path between the first selection circuit and the first antenna array.

20. The signal processing apparatus according to claim 18, characterized in that, In the first signal circuit, the mixer is connected to multiple signal paths. In each signal path, a phase shifter and an amplifier are arranged between the mixer and the first feed point.

21. The signal processing apparatus according to any one of claims 1 to 15, characterized in that, The signal processing device includes: An RFIC comprising the first selection circuit and the first and second signal circuits; and An RFIC comprising the second selection circuit and the third and fourth signal circuits.

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