Solid-state imaging device and electronic apparatus

Abstract

The present application relates to a solid-state imaging device and an electronic apparatus capable of further improving image quality. The solid-state imaging device includes a pixel having a first capacitor that holds a voltage of a pixel signal at a reset level output by a pixel circuit, a second capacitor that holds a voltage of the pixel signal at a pixel signal level output by the pixel circuit, a first gate that connects the first capacitor and a node connected to an amplification gate that outputs the pixel signal, and a second gate that connects the second capacitor and the node. Then, a difference between a first parasitic capacitance caused by a capacitive coupling occurring between the first gate and the node and a second parasitic capacitance caused by a capacitive coupling occurring between the second gate and the node is less than a predetermined value. The present technology can be applied, for example, to a global-shutter type solid-state imaging device using a voltage domain type structure.

Description

Technical Field

[0001] This disclosure relates to solid-state imaging devices and electronic devices, and more particularly to solid-state imaging devices and electronic devices capable of further improving image quality. Background Technology

[0002] In recent years, with the increase in the number of pixels, there is a need for global shutter complementary metal-oxide-semiconductor (CMOS) image sensors to achieve finer pixel sizes. Such image sensors do not produce focal plane distortion during imaging.

[0003] For example, in global shutter complementary metal-oxide-semiconductor (CMOS) image sensors, representative methods employ a charge-domain-type structure that temporarily holds the signal generated in the photodiode as a charge and a voltage-domain-type structure that temporarily holds the signal generated in the photodiode as a voltage.

[0004] In a charge-domain configuration, the memory cell mounted on the same semiconductor substrate as the photodiode serves as a signal holding unit, while in a voltage-domain configuration, the capacitor mounted outside the semiconductor substrate serves as the signal holding unit. Therefore, the signal holding unit in a charge-domain configuration encroaches on the photodiode's area, while the signal holding unit in a voltage-domain configuration does not. This is advantageous for miniaturization from the perspective of saturated signal strength.

[0005] For example, Patent Document 1 discloses a global shutter type image sensor that reduces coupling noise and produces a clear image by surrounding a first capacitor and a second capacitor, which temporarily hold the signal generated in the photodiode as a voltage, with a shielding structure. Reference List Patent documents

[0006] Patent Document 1: U.S. Patent Application Publication No. 2020 / 0058688 Summary of the Invention The problem to be solved by the present invention

[0007] However, while the voltage-domain global shutter complementary metal-oxide-semiconductor (CMOS) image sensor described above is advantageous for miniaturization from the perspective of saturated signal quantity, there are concerns that image quality may be degraded in sample-and-hold circuits with signal holding units due to capacitive coupling between wirings.

[0008] For example, in a voltage-domain configuration, since the signal is written to the capacitor in voltage form, the signal holding node is in a floating state from the end of the signal writing to the start of the reading. Therefore, it can be assumed that the read signal fluctuates due to the capacitive coupling between the signal holding node and the control line performing the reading operation, resulting in a degraded image quality.

[0009] This disclosure is made in view of the foregoing and is intended to further improve image quality. Solution to the problem

[0010] According to one aspect of the present disclosure, a solid-state imaging device includes a pixel, the pixel comprising: a pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; and a sample-and-hold circuit having at least: a first capacitor, one end of which is connected to the first node and holds a voltage of a pixel signal output from the pixel circuit at a reset level; a second capacitor, one end of which is connected to the first node and holds a voltage of a pixel signal output from the pixel circuit at a pixel signal level; an amplifying gate that generates a pixel signal corresponding to a charge accumulated in a second node connected to its gate; a first gate that connects a third node and the second node, the third node serving as a connection point between the first gate and the other end of the first capacitor; and a second gate that connects a fourth node and the second node, the fourth node serving as a connection point between the second gate and the other end of the second capacitor, wherein the difference between parasitic capacitances caused by capacitive coupling between the two nodes of the sample-and-hold circuit and corresponding one of the two gates of the sample-and-hold circuit is less than a predetermined value.

[0011] An electronic device according to one aspect of this disclosure includes a solid-state imaging device, the solid-state imaging device including a pixel, the pixel including: a pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; and a sample-and-hold circuit having at least: a first capacitor having one end connected to the first node and holding a voltage of a pixel signal output from the pixel circuit at a reset level; a second capacitor having one end connected to the first node and holding a voltage of a pixel signal output from the pixel circuit at a pixel signal level; an amplifying gate that generates a pixel signal corresponding to a charge accumulated in a second node connected to its gate; a first gate connecting a third node and the second node, the third node serving as a connection point between the first gate and the other end of the first capacitor; and a second gate connecting a fourth node and the second node, the fourth node serving as a connection point between the second gate and the other end of the second capacitor, wherein the difference between parasitic capacitances caused by capacitive coupling occurring between the two nodes of the sample-and-hold circuit and corresponding one of the two gates of the sample-and-hold circuit is less than a predetermined value.

[0012] In one aspect of this disclosure, a pixel includes: a pixel circuit having at least a photoelectric conversion unit and outputting a pixel signal to a first node; and a sample-and-hold circuit having at least: a first capacitor, one end of which is connected to the first node and holds a voltage of a pixel signal output from the pixel circuit at a reset level; a second capacitor, one end of which is connected to the first node and holds a voltage of a pixel signal output from the pixel circuit at a pixel signal level; an amplifying gate that generates a pixel signal corresponding to a charge accumulated in a second node connected to its gate; a first gate that connects a third node and the second node, the third node serving as a connection point between the first gate and the other end of the first capacitor; and a second gate that connects a fourth node and the second node, the fourth node serving as a connection point between the second gate and the other end of the second capacitor, wherein the difference between parasitic capacitances caused by capacitive coupling between the two nodes of the sample-and-hold circuit and a corresponding one of the two gates of the sample-and-hold circuit is less than a predetermined value. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating a construction example of an imaging device applying the present technology. Figure 2 This is a circuit diagram showing a first example of pixel construction. Figure 3 It is shown Figure 2 A circuit diagram illustrating the construction example of a four-pixel shared structure. Figure 4 This is a diagram illustrating a planar layout example used to explain the capacitive coupling between the SR gate and the V2 node. Figure 5 This is a diagram illustrating a planar layout example used to explain the capacitive coupling between the SR gate and the VCR node. Figure 6 This is a diagram showing an example of a wiring layout with RB wiring and SEL wiring. Figure 7 This is a circuit diagram showing a second example of pixel construction. Figure 8 This is a diagram showing an example of a wiring layout with SR wiring, SD wiring and VREG wiring. Figure 9 It is shown Figure 7 A circuit diagram illustrating the construction example of a four-pixel shared structure. Figure 10 This is a diagram showing an example of a wiring layout with SR wiring, SD wiring and VREG wiring. Figure 11This is a diagram showing an example of a grid layout. Figure 12 This is a diagram showing an example layout of the capacitor and the V1 node. Figure 13 This is a circuit diagram illustrating a third example of pixel construction. Figure 14 This is a circuit diagram illustrating a fourth example of pixel construction. Figure 15 This is a circuit diagram showing a fifth example of pixel construction. Figure 16 This is a circuit diagram showing a sixth example of pixel construction. Figure 17 This is a circuit diagram illustrating a seventh example of pixel construction. Figure 18 This is a circuit diagram illustrating an eighth example of pixel construction. Figure 19 This is a circuit diagram illustrating a ninth example of pixel construction. Figure 20 This is a circuit diagram illustrating the tenth construction example of a pixel. Figure 21 This is a diagram illustrating an example of a first cross-sectional structure of a solid-state imaging device. Figure 22 This is a diagram illustrating an example of a second cross-sectional structure of a solid-state imaging device. Figure 23 This is a diagram illustrating an example of a third cross-sectional structure of a solid-state imaging device. Figure 24 This is a diagram illustrating an example of a fourth cross-sectional structure of a solid-state imaging device. Figure 25 This is a diagram illustrating an example of an image sensor application. Detailed Implementation

[0014] The specific embodiments of this technology will be described in detail below with reference to the accompanying drawings.

[0015] <Example of Imaging Device Construction> Figure 1 This is a block diagram illustrating a construction example of an imaging device applying the present technology.

[0016] like Figure 1 As shown, the imaging device 11 includes an optical system 12, a solid-state imaging device 13, an imaging control circuit 14, a signal processing circuit 15, a monitor 16, and a memory 17. For example, the imaging device 11 can be applied to various electronic devices, such as imaging systems including digital cameras and digital video cameras, mobile phones with imaging capabilities, or other devices with imaging capabilities, and can capture still images and moving images.

[0017] The optical system 12 includes one or more lenses that collect incident light from the subject entering the imaging device 11, guide the light to the solid-state imaging device 13, and form an image of the subject on the light receiving surface (sensor unit) of the solid-state imaging device 13.

[0018] Under the control of the imaging control circuit 14, the solid-state imaging device 13 captures the image of the subject formed on the light receiving surface through the optical system 12, and provides the image signal obtained by the capture to the signal processing circuit 15.

[0019] The imaging control circuit 14 controls the solid-state imaging device 13 to capture images. For example, the imaging control circuit 14 provides the solid-state imaging device 13 with imaging control signals including a vertical synchronization signal VSYNC, wherein the vertical synchronization signal VSYNC is a periodic signal with a constant frequency (e.g., 60 Hz) that indicates the timing of the images.

[0020] The signal processing circuit 15 performs various signal processing on the image signal output from the solid-state imaging device 13, and provides the processed image data to the monitor 16 or the memory 17.

[0021] The monitor 16 displays images based on the image data provided by the signal processing circuit 15, and the memory 17 stores (records) the image data provided by the signal processing circuit 15. Note that if the solid-state imaging device 13 includes a communication interface, the image data can be transmitted externally.

[0022] The solid-state imaging device 13 includes a pixel array unit 21, a timing control circuit 22, a vertical scanning circuit 23, a digital-to-analog converter (DAC) 24, a load complementary metal-oxide (MOS) circuit block 25, and a column signal processing circuit 26.

[0023] In pixel array unit 21, multiple pixels 31 are arranged in an array. Hereinafter, a group of pixels 31 arranged in the horizontal direction is referred to as a "row", and a group of pixels 31 arranged in the direction perpendicular to the row is referred to as a "column". In pixel array unit 21, each pixel 31 performs photoelectric conversion on the incident light to generate an analog pixel signal, and for each row selected by vertical scanning circuit 23, the pixel signal is output in parallel in the column direction.

[0024] The timing control circuit 22 controls the operating timing of each of the vertical scanning circuit 23, DAC 24 and column signal processing circuit 26 in a manner synchronized with the vertical synchronization signal VSYNC provided from the imaging control circuit 14.

[0025] The vertical scanning circuit 23 sequentially selects the rows to be scanned along the vertical direction, provides various control signals to the pixels 31 set in each selected row, and causes the pixels 31 to output analog pixel signals.

[0026] DAC 24 generates a sawtooth waveform ramp signal through digital-to-analog conversion and provides the ramp signal to column signal processing circuit 26.

[0027] Load MOS circuit block 25 is equipped with MOS transistors that can provide a constant current to each column (e.g., Figure 2 (44) Constant current source in the middle.

[0028] The column signal processing circuit 26 references the ramp signal provided by the DAC 24, performs analog-to-digital conversion (AD) on the analog pixel signal output from the pixel 31 through the load MOS circuit block 25, and eliminates noise by performing correlated double sampling (CDS) processing on the digital pixel signal.

[0029] Then, the image data obtained by the pixel signal processing circuit 26 after processing the pixel signal is output from the solid-state imaging device 13.

[0030] <Example of the first construction of a pixel> Reference Figures 2 to 6 The first construction example describes pixel 31.

[0031] Figure 2 A circuit diagram example for pixel 31 is shown as a first construction example.

[0032] like Figure 2 As shown, pixel 31 includes pixel circuit 41 and sample-and-hold circuit 42, and is connected to constant current source 44 through vertical signal line 43; pixel circuit 41 generates pixel signal corresponding to incident light amount, and sample-and-hold circuit 42 samples the pixel signal generated in pixel circuit 41 and holds the pixel signal at a constant voltage level.

[0033] Pixel circuit 41 includes a photoelectric conversion unit 51, a transmission gate 52, an FD gate 53, a reset gate 54, a capacitor 55, an amplification gate 56, and a switching gate 57. Sample-and-hold circuit 42 includes a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an RB gate 65, an amplification gate 66, a selection gate 67, and a constant current source 68. Furthermore, when pixel 31 is constructed from a semiconductor substrate with a double-layer structure, pixel circuit 41 is disposed in the first semiconductor substrate, while sample-and-hold circuit 42 is disposed in the second semiconductor substrate. Figure 2 In the diagram, the rectangle shown between pixel circuit 41 and sample-and-hold circuit 42 represents the connection point (e.g., Cu-Cu connection) where the two-layer semiconductor substrates are connected to each other.

[0034] The anode of photoelectric conversion unit 51 is grounded, and the cathode of photoelectric conversion unit 51 is connected to the source of transmission gate 52. The drain of transmission gate 52 is connected to the source of FD gate 53 and the gate of amplification gate 56, and this connection point is called the floating diffusion (FD) node. The drain of FD gate 53 is connected to the source of reset gate 54 and one end of capacitor 55. The drain of reset gate 54 is connected to power supply VDD, and the other end of capacitor 55 is grounded. The drain of amplification gate 56 is connected to power supply AMD, and the source of amplification gate 56 is connected to the drain of switching gate 57. The source of switching gate 57 is connected to the constant current source 68 of sample-and-hold circuit 42.

[0035] The connection point between one end of capacitor 61 and one end of capacitor 62 is called node V1, and the source of switching gate 57 and constant current source 68 are connected to node V1. The other end of capacitor 61 is connected to the source of SR gate 63, and the other end of capacitor 62 is connected to the source of SD gate 64. The drain of SR gate 63 is connected to the drain of SD gate 64, and this connection point is called node V2. The gate of amplifying gate 66 and the source of RB gate 65 are connected to node V2. The drain of RB gate 65 is connected to power supply VREG, and the drain of amplifying gate 66 is connected to power supply VDD. The source of amplifying gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43.

[0036] The photoelectric conversion unit 51 includes a photodiode that performs photoelectric conversion on incident light entering the pixel 31 and accumulates the charge generated by the photoelectric conversion.

[0037] The transmission gate 52 is driven by the control signal TRG provided from the vertical scanning circuit 23, and the charge accumulated in the photoelectric conversion unit 51 is transferred to the FD node at the moment when the transmission gate 52 is turned on.

[0038] The FD gate 53 is driven according to the control signal FDG provided from the vertical scanning circuit 23, and the capacitor 55 is connected to the FD node during the conduction period of the transmission gate 52. For example, the capacitor 55 can be connected to the FD node through the FD gate 53, thereby increasing the holding capacitance for holding the charge transferred from the photoelectric conversion unit 51, so that imaging with high dynamic range (HDR) is possible.

[0039] The reset gate 54 is driven by the control signal RST provided from the vertical scan circuit 23, and at the moment the reset gate 54 is turned on, the charge accumulated in the capacitor 55 and the charge accumulated in the FD node through the FD gate 53 are released to the power supply VDD to reset the charge.

[0040] During the period when capacitor 55 is connected to the FD node through FD gate 53, capacitor 55 and FD node together retain the charge transferred from photoelectric conversion unit 51.

[0041] Amplifying gate 56 generates a pixel signal corresponding to the charge accumulated in the FD node or the charge accumulated in the FD node and capacitor 55. Amplifying gate 56 and constant current source 68 connected through switching gate 57 together form a source follower circuit and output the generated pixel signal to V1 node.

[0042] The switching gate 57 is driven according to the control signal SW provided from the vertical scanning circuit 23, and the amplifying gate 56 is connected to the V1 node during the on-time of the switching gate 57. Then, the pixel signal generated in the amplifying gate 56 is output to the V1 node through the switching gate 57.

[0043] Capacitor 61 uses the signal holding capacitor C to maintain the voltage of the pixel signal (hereinafter also referred to as the P-phase signal) at the reset level after the FD node is reset. The signal holding node between capacitor 61 and SR gate 63 that holds the charge corresponding to the P-phase signal is called the VCR node.

[0044] Capacitor 62 uses signal holding capacitor C to maintain the voltage of the pixel signal (hereinafter also referred to as the D-phase signal) by using the pixel signal level corresponding to the charge generated in photoelectric conversion unit 51 and held in FD node (or FD node and capacitor 55). The signal holding node between capacitor 62 and SD gate 64 that holds the charge corresponding to the D-phase signal is called VCD node.

[0045] The SR gate 63 is driven by the control signal SR provided from the vertical scanning circuit 23, and when the SR gate 63 is turned on, the VCR node is connected to the V2 node. Using this arrangement, the charge corresponding to the P-phase signal held in the VCR node is maintained through the VCR node and the V2 node.

[0046] The SD gate 64 is driven according to the control signal SD provided from the vertical scanning circuit 23, and when the SD gate 64 is turned on, the VCD node is connected to the V2 node. Therefore, the charge corresponding to the D-phase signal held in the VCD node is maintained through the VCD node and the V2 node.

[0047] The RB gate 65 is driven by the control signal RB provided from the vertical scanning circuit 23, and at the moment the RB gate 65 is turned on, the charge held by the VCR node and the V2 node and the charge held by the VCD node and the V2 node are released to the power supply VREG to reset the charge.

[0048] Amplifying gate 66 generates P-phase and D-phase signals; the P-phase signal is the pixel signal corresponding to the charge held by the VCR node and V2 node, while the D-phase signal is the pixel signal corresponding to the charge held by the VCD node and V2 node. Amplifying gate 56 and constant current source 44 connected through selection gate 67 together form a source follower circuit, and output the P-phase and D-phase signals to vertical signal line 43.

[0049] The selection gate 67 is driven by the control signal SEL provided from the vertical scanning circuit 23, and during the period when a row is selected as the pixel signal read row and the selection gate 67 is turned on, the amplification gate 66 is connected to the vertical signal line 43. Then, the pixel signals (P-phase signals and D-phase signals) generated in the amplification gate 66 are read onto the vertical signal line 43 through the selection gate 67.

[0050] The constant current source 68 forms the load of the amplification gate 56 and provides a sink current as a constant current to the V1 node.

[0051] In the solid-state imaging device 13, the operation of reading pixel signals (P-phase signals and D-phase signals) from pixels 31 of a selected row is as follows.

[0052] First, after resetting node V2 by turning on gate 65, gate 63 is turned on, causing nodes VCR and V2 to retain charges corresponding to the P-phase signal voltage charged in capacitor 61, and the P-phase signal is read through amplification gate 66. Next, after resetting node V2 by turning on gate 65, gate 64 is turned on, causing nodes VCD and V2 to retain charges corresponding to the D-phase signal voltage charged in capacitor 62, and the D-phase signal is read through amplification gate 66.

[0053] In this way, when the P-phase signal is read from pixel 31, charge sharing occurs at the VCR node and the V2 node, and when the D-phase signal is read from pixel 31, charge sharing occurs at the VCD node and the V2 node.

[0054] Therefore, in order to obtain good image quality in the solid-state imaging device 13, it is preferable that the parasitic capacitance C SR-V2 With parasitic capacitance C SD-V2 The difference between them is small, where the parasitic capacitance C SR-V2 This is caused by capacitive coupling between the SR gate 63 and the V2 node, and the parasitic capacitance C SD-V2 This is caused by capacitive coupling between the SD gate 64 and the V2 node. Therefore, the following construction is preferred: by controlling the parasitic capacitance C... SR-V2 With parasitic capacitance C SD-V2The first capacitance ratio C1 is obtained by dividing the difference between them by the signal holding capacitor C. ratio In practical applications, it is less than 1 / 1000, that is, pixel 31 is constructed to satisfy the following expression (1).

[0055] [Mathematical Formula 1]

[0056] Furthermore, in order to obtain good image quality in the solid-state imaging device 13, it is preferable that the parasitic capacitance C SR-VCR With parasitic capacitance C SD-VCD The difference between them is small, where the parasitic capacitance C SR-VCR This is caused by capacitive coupling between the SR gate 63 and the VCR node, and the parasitic capacitance C SD-VCD This is caused by capacitive coupling between the SD gate 64 and the VCD node. Therefore, the following construction is preferred: by controlling the parasitic capacitance C... SR-VCR With parasitic capacitance C SD-VCD The second capacitance ratio C2 is obtained by dividing the difference between them by the signal holding capacitor Cs. ratio In practical applications, it is less than 1 / 1000, that is, pixel 31 is constructed to satisfy the following expression (2).

[0057] [Mathematical Formula 2]

[0058] Furthermore, in order to obtain good image quality in the solid-state imaging device 13, it is preferable that the parasitic capacitance C RB-VCR With parasitic capacitance C RB-VCD The difference between them is small, where the parasitic capacitance C RB-VCR This is caused by capacitive coupling between the RB gate 65 and the VCR node, and the parasitic capacitance C RB-VCD This is caused by capacitive coupling between the RB gate 65 and the VCD node. Therefore, the following construction is preferred: by controlling the parasitic capacitance C... RB-VCR With parasitic capacitance C RB-VCD The third capacitance ratio C3 is obtained by dividing the difference between them by the signal holding capacitor C. ratio In practical applications, it is less than 1 / 1000, that is, pixel 31 is constructed to satisfy the following expression (3).

[0059] [Mathematical Formula 3]

[0060] Furthermore, in order to obtain good image quality in the solid-state imaging device 13, it is preferable that the parasitic capacitance C SEL-VCR and parasitic capacitance C SEL-VCDThe difference between them is small, where the parasitic capacitance C SEL-VCR This is caused by capacitive coupling between the select gate 67 and the VCR node, and the parasitic capacitance C SEL-VCD This is caused by capacitive coupling between the select gate 67 and the VCD node. Therefore, it is preferable to adopt the following construction: by controlling the parasitic capacitance C SEL-VCR With parasitic capacitance C SEL-VCD The fourth capacitance ratio C4 is obtained by dividing the difference between them by the signal holding capacitor C. ratio In practical applications, it is less than 1 / 1000, that is, pixel 31 is constructed to satisfy the following expression (4).

[0061] [Mathematical Formula 4]

[0062] As described above, the solid-state imaging device 13 can construct the pixel 31 to satisfy the above expressions (1) to (4) and suppress pixel signal fluctuations caused by the corresponding capacitive coupling, thereby suppressing image quality degradation and further improving image quality. Note that the solid-state imaging device 13 does not need to satisfy all of the above expressions (1) to (4), and satisfying any one of them is sufficient to improve image quality.

[0063] In addition, such as Figure 3 As shown, the solid-state imaging device 13 may employ a 4-pixel sharing structure; in this sharing structure, four pixels 31[0] to 31[3] with a 2×2 arrangement share the V2 node. Note that the pixel circuit 41 is omitted in the following figures of the 4-pixel sharing structure. Furthermore, i is used to identify a specific pixel 31 among the plurality of pixels 31, and in the 4-pixel sharing structure, each pixel 31 is distinguished by i = 1, 2, 3 or 4.

[0064] Figure 4 and Figure 5 An example of a planar layout of pixels 31[0] to 31[3] with a four-pixel shared structure is shown.

[0065] like Figure 4 As shown, in pixel 31[i], there is a parasitic capacitance C between SR gate 63[i] and node V2. SR[i]-V2 Furthermore, there is a parasitic capacitance C between SD gate 64[i] and node V2. SD[i]-V2 .like Figure 5 As shown, in pixel 31[i], there is a parasitic capacitance C between SR gate 63[i] and VCR node [i]. SR[i]-VCR[i] Furthermore, there is a parasitic capacitance C between SD gate 64[i] and VCD node [i].SD[i]-VCD[i] Here, Figure 4 and Figure 5 The following description shows the setup. Figure 14 The diagram shows the planar layout of the DIFF gate 75, and the dashed rectangles represent contacts used to connect the semiconductor substrate or gate to the wiring layer.

[0066] In the above four-pixel shared structure, the following construction is preferred: by controlling the parasitic capacitance C SR[i]-V2 With parasitic capacitance C SD[i]-V2 The first capacitance ratio C1 is obtained by dividing the difference between them by the signal holding capacitor C. ratio [i] is less than 1 / 1000. Furthermore, it is preferable that the first capacitance is less than C1. ratio [0] to C1 ratio The maximum value in [3] is maxC1 ratio [i] and the minimum value minC1 ratio The difference between [i] is less than 1 / 1000. That is, preferably, pixels 31[0] to 31[3] are constructed to satisfy the following expression (5).

[0067] [Mathematical Formula 5]

[0068] Similarly, in the above four-pixel shared structure, the following construction is preferred: by controlling the parasitic capacitance C SR[i]-VCR[i] With parasitic capacitance C SD[i]-VCD[i] The second capacitance ratio C2 is obtained by dividing the difference between them by the signal holding capacitor C. ratio [i] is less than 1 / 1000. Furthermore, it is preferable that the second capacitance is less than C2. ratio [0] to C2 ratio The maximum value in [3] is maxC2. ratio [i] and the minimum value minC2 ratio The difference between [i] is less than 1 / 1000. That is, preferably, pixels 31[0] to 31[3] are constructed to satisfy the following expression (6).

[0069] [Mathematical Formula 6]

[0070] Furthermore, in the aforementioned four-pixel shared structure, the following construction is preferred: by controlling the parasitic capacitance C RB-VCR[i] With parasitic capacitance C RB-VCD[i] The third capacitance ratio C3 is obtained by dividing the difference between them by the signal holding capacitor C. ratio [i] is less than 1 / 1000. Furthermore, it is preferable that the third capacitor is less than C3. ratio [0] to C3ratio The maximum value in [3] is maxC3. ratio [i] and the minimum value minC3 ratio The difference between [i] is less than 1 / 1000. That is, preferably, pixels 31[0] to 31[3] are constructed to satisfy the following expression (7).

[0071] [Mathematical Formula 7]

[0072] Furthermore, in the aforementioned four-pixel shared structure, the following construction is preferred: by controlling the parasitic capacitance C SEL-VCR[i] With parasitic capacitance C SEL-VCD[i] The fourth capacitance ratio C4 is obtained by dividing the difference between them by the signal holding capacitor C. ratio [i] is less than 1 / 1000. Furthermore, it is preferable that the fourth capacitor is equal to C4. ratio [0] to C4 ratio The maximum value in [3] is maxC4. ratio [i] and the minimum value minC4 ratio The difference between [i] is less than 1 / 1000. That is, preferably, pixels 31[0] to 31[3] are constructed to satisfy the following expression (8).

[0073] [Mathematical Formula 8]

[0074] As described above, the solid-state imaging device 13 employing a four-pixel shared structure can construct pixel 31[i] to satisfy the above expressions (5) to (8) and suppress pixel signal fluctuations caused by individual capacitive coupling, thereby suppressing image quality degradation and further improving image quality. Note that the solid-state imaging device 13 does not need to satisfy all of the above expressions (5) to (8), and satisfying any one of them is sufficient to improve image quality.

[0075] To satisfy these constraints of capacitive coupling, it is preferable to, for example... Figure 3 and Figure 4 The planar layout shown adopts the following wiring layout: as mentioned above, the wiring to reduce parasitic capacitance differences has a relative positional relationship (symmetry) with each other, and the shortest distance between these wirings is equal.

[0076] Figure 6 An example plan view of the wiring layer is shown, in which RB wiring providing control signals to RB gate 65 for resetting the V2 node and SEL wiring providing control signals to select gate 67 for row selection are arranged in a four-pixel shared structure. Furthermore, as... Figure 6As shown, in addition to the RB wiring and SEL wiring, this wiring layer also has other wiring, such as the VSSHPS wiring that supplies power to the VSS power supply.

[0077] Then, as described above, the solid-state imaging device 13 needs to satisfy the coupling constraint (expression (3) above), that is, reduce the parasitic capacitance C caused by the capacitive coupling between the RB gate 65 and the VCR node. RB-VCR Parasitic capacitance C caused by capacitive coupling between RB gate 65 and VCD node RB-VCD The difference between them. For this purpose, it is preferable that the solid-state imaging device 13 adopts the following wiring layout: wiring other than the RB wiring, VCR wiring [2], VCR wiring [3], VCD wiring [2], and VCD wiring [3] is arranged between the RB wiring and the VCR wiring [2], VCR wiring [3], VCD wiring [2], and VCD wiring [3]. Figure 6 In the example shown, the wiring is a VSSHPS wiring.

[0078] Similarly, as described above, the solid-state imaging device 13 needs to satisfy the coupling constraint (expression (4) above), that is, to reduce the parasitic capacitance C caused by the capacitive coupling between the selection gate 67 and the VCR node. SEL-VCR Parasitic capacitance C caused by capacitive coupling between select gate 67 and VCD node SEL-VCD The difference between them. Therefore, it is preferable that the solid-state imaging device 13 adopts the following wiring layout: wiring other than the SEL wiring, VCR wiring [0], VCR wiring [1], VCD wiring [0], and VCD wiring [1] is arranged between the SEL wiring and the VCR wiring [0], VCR wiring [1], VCD wiring [0], and VCD wiring [1]. Figure 6 In the example shown, the wiring is a VSSHPS wiring.

[0079] By satisfying these coupling constraints, the solid-state imaging device 13 can suppress the occurrence of offset between the P-phase signal and the D-phase signal in the pixel-sharing structure and the occurrence of differences between the pixel signals of each pixel 31[i] when performing the operation of reading pixel signals from pixel 31[i].

[0080] Note that, although Figure 6 An example is shown where the RB wiring and SEL wiring are arranged in the same wiring layer, but the RB wiring and SEL wiring can also be arranged in different wiring layers, for example. Furthermore, this wiring layout is also applicable to a single pixel 31 that does not employ a four-pixel shared structure.

[0081] As described above, the global shutter solid-state imaging device 13, which utilizes a voltage domain type structure and includes pixels 31 constructed as described above, can suppress image quality degradation and capture images with better image quality by using pixels 31 that satisfy the above-described coupling constraints.

[0082] <Example of the second construction of a pixel> The following will refer to Figures 7 to 12 A second construction example describing pixel 31.

[0083] Figure 7 A circuit diagram example for pixel 31a is shown as a second construction example. Note that in Figure 7 In pixel 31a shown, with Figure 2 The same components as those in pixel 31 are indicated by the same reference numerals, and therefore will not be described further.

[0084] like Figure 7 As shown, the construction of pixel 31a is similar to... Figure 2 The common feature of the construction of the pixels 31 is that the pixel 31a includes a pixel circuit 41a and a sample and hold circuit 42a, and is connected to a constant current source 44 via a vertical signal line 43.

[0085] The construction method of pixel circuit 41a and Figure 2 The pixel circuit 41 is similar in construction to the pixel circuit 41a in that it includes a photoelectric conversion unit 51, a transmission gate 52, an FD gate 53, a reset gate 54, a capacitor 55, an amplification gate 56, and a switching gate 57. Furthermore, the pixel circuit 41a also includes an overflow gate 73.

[0086] An overflow gate 73 is connected between the photoelectric conversion unit 51 and the power supply VDD, and releases the charge overflowing from the photoelectric conversion unit 51 to the power supply VDD. In addition, the overflow gate 73 is driven according to the control signal OFG provided from the vertical scanning circuit 23, and at the moment when the overflow gate 73 is turned on, the charge accumulated in the photoelectric conversion unit 51 is released to the power supply VDD to reset the charge and start the exposure of pixel 31a.

[0087] The construction method of sample-and-hold circuit 42a and Figure 2 The sample-and-hold circuit 42a is similar in construction to the sample-and-hold circuit 42a in that it includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, RB gate 65, amplification gate 66, and selection gate 67. Furthermore, the sample-and-hold circuit 42a also includes PC gate 71 and VB gate 72, instead of... Figure 2 The constant current source in the middle is 68.

[0088] The drain of gate PC 71 is connected to node V1, the source of gate PC 71 is connected to the drain of gate VB 72, and the source of gate VB 72 is grounded. Gate PC 71 provides a constant current to node V1 corresponding to the bias voltage PC applied to the gate, and gate VB 72 provides a constant current to node V1 corresponding to the bias voltage VB applied to the gate. In this way, by cascading gate VB 72 with gate PC 71 as a current source, and applying different bias voltages PC and VB to each gate, noise in the constant current supplied to node V1 can be reduced, and fluctuations in the constant current due to power supply voltage fluctuations can be minimized.

[0089] Figure 8 An example wiring layout for the wiring layer is shown, wherein SR wiring is provided for providing the control signal SR to the gate of SR gate 63, SD wiring is provided for providing the control signal SD to the gate of SD gate 64, and VREG wiring is provided for supplying power to power supply VREG. Here, the longitudinal direction of the wiring is perpendicular to the vertical signal line 43, and this direction is referred to as the horizontal direction.

[0090] As shown in the figure, there is a parasitic capacitance C between adjacent SR wiring and VREG wiring. SR-VREG Furthermore, there is a parasitic capacitance C between adjacent SD wiring and VREG wiring. SD-VREG Therefore, the global shutter solid-state imaging device 13 utilizing a voltage domain structure can suppress image quality degradation by employing a wiring layout that takes into account these capacitive couplings.

[0091] In other words, such as Figure 8 As shown, preferably, pixel 31a adopts the following wiring layout: the SD wiring and SR wiring are symmetrical about the dotted-dash line passing through the center of pixel 31a in the horizontal direction, and the VREG wiring is symmetrical about the dotted-dash line.

[0092] Therefore, in pixel 31a, when the VCR node or VCD node is connected to the V2 node, the voltage fluctuation of the power supply VREG during voltage changes at the SR gate 63 (from low to high and from high to low) is consistent with the voltage fluctuation of the power supply VREG during voltage changes at the SD gate 64 (from low to high and from high to low). Thus, pixel 31a can match the voltage level caused by charge sharing between the VCR node and V2 node with the voltage level caused by charge sharing between the VCD node and V2 node, thereby reducing output fluctuations when reading P-phase or D-phase signals from pixel 31.

[0093] Furthermore, in order to obtain good image quality in the solid-state imaging device 13, it is preferable that the parasitic capacitance C SR-VREG With parasitic capacitance C SD-VREGThe difference between them is small, where the parasitic capacitance C SR-VREG This is caused by capacitive coupling between the SR wiring and the VREG wiring, and the parasitic capacitance C SD-VREG This is caused by capacitive coupling between the SD wiring and the VREG wiring. Therefore, it is preferable that pixel 31a is configured such that the parasitic capacitance C is reduced. SR-VREG With parasitic capacitance C SD-VREG The fifth capacitance ratio C5 is obtained by dividing the difference between them by the signal holding capacitor C. ratio In practical applications, it is less than 1 / 1000, that is, pixel 31a is constructed to satisfy the following expression (9).

[0094] [Mathematical Formula 9]

[0095] In addition, such as Figure 9 As shown, the solid-state imaging device 13 can also adopt a four-pixel shared structure, in which the four pixels 31a[0] to 31a[3] arranged in a 2×2 arrangement share the V2 node.

[0096] Figure 10 An example wiring layout of the wiring layer is shown, wherein in the four-pixel shared structure, there are SR[i] wirings that provide control signals SR to the gate of SR gate 63[i], SD[i] wirings that provide control signals SD to the gate of SD gate 64[i], and VREG wirings that supply power to the power supply VREG.

[0097] Similarly, in pixels 31a[0] to 31a[3] with this four-pixel shared structure, similar to the single pixel 31a mentioned above, it is preferable to adopt the following wiring layout: the SD[i] wiring and the SR[i] wiring are symmetrical about the dotted-dash line that passes through the center of the 2×2 arrangement structure in the horizontal direction, and the VREG wiring is symmetrical about the dotted-dash line.

[0098] With this arrangement, in pixels 31a[0] to 31a[3], when the VCR node[i] or VCD node[i] is connected to the V2 node, the voltage fluctuation of the power supply VREG during the voltage change (from low to high and from high to low) at the SR gate 63[i] is consistent with the voltage fluctuation of the power supply VREG during the voltage change (from low to high and from high to low) at the SD gate 64[i]. Therefore, pixels 31a[0] to 31a[3] can match the voltage level caused by the charge sharing between the VCR node[i] and the V2 node with the voltage level caused by the charge sharing between the VCD node[i] and the V2 node, thereby reducing the output fluctuation when reading the P-phase signal or D-phase signal from pixels 31a[0] to 31a[3].

[0099] In other words, in order to obtain good image quality in the solid-state imaging device 13, it is preferable that the parasitic capacitance C SR[i]-VREG With parasitic capacitance C SD[i]-VREG The total value of the differences between them is small, among which the parasitic capacitance C SR[i]-VREG This is caused by capacitive coupling between the i-th SR wiring and the VREG wiring, and the parasitic capacitance C SD[i]-VREG This is caused by capacitive coupling between the i-th SD wiring and the VREG wiring. Therefore, it is preferable that pixel 31a is configured such that the parasitic capacitance C is reduced. SR[i]-VREG With parasitic capacitance C SD[i]-VREG The total capacitance ratio C6 obtained by dividing the difference between them by the signal holding capacitor C ratio In practical applications, it is less than 1 / 1000, that is, pixel 31a is constructed to satisfy the following expression (10).

[0100] [Mathematical Formula 10]

[0101] Therefore, the solid-state imaging device 13 can suppress image quality degradation and capture images with better image quality.

[0102] Figure 11 An example of a gate layout is shown where pixels 31a[0] to 31a[3] are arranged in a 2×2 arrangement.

[0103] like Figure 11 In the 2×2 arrangement shown, pixels 31a[0] and 31a[1] are arranged to be adjacent in the horizontal direction, and pixels 31a[2] and 31a[3] are arranged to be adjacent in the horizontal direction. In addition, pixels 31a[0] to 31a[3] are constructed with the following gate layout: among the horizontally adjacent pixels 31a[i], SR gate 63[i] and SD gate 64[i] have a translationally symmetric relationship (symmetric about parallel translation), and PC gate 71[i] and VB gate 72[i] have a line symmetric relationship.

[0104] In this gate layout, in pixel 31a[0] located in the lower left corner, VB gate 72[0] is adjacent to SR gate 63[0], and in pixel 31a[1] located in the lower right corner, VB gate 72[1] is adjacent to SD gate 64[1]. Therefore, when focusing along the row direction, the parasitic capacitance C caused by the capacitive coupling between SR gate 63[0] and VB gate 72[0] is... SR[0]-VB Parasitic capacitance C caused by capacitive coupling between SD gate 64[1] and VB gate 72[1]SD[1]-VB Consistent.

[0105] Similarly, in pixel 31a[2] located in the upper left corner, VB gate 72[2] is adjacent to SR gate 63[2], and in pixel 31a[3] located in the upper right corner, VB gate 72[3] is adjacent to SD gate 64[3]. Therefore, when focusing along the row direction, the parasitic capacitance C caused by the capacitive coupling between SR gate 63[2] and VB gate 72[2] is... SR[2]-VB Parasitic capacitance C caused by capacitive coupling between SD gate 64[3] and VB gate 72[3] SD[3]-VB Consistent.

[0106] Therefore, when VCR node[i] or VCR node[i] is connected to V2 node simultaneously in all pixels 31a and when they are disconnected, the voltage fluctuation in VB gate 72[i] caused by the voltage change of SR gate 63[i] and the voltage fluctuation in VB gate 72[i] caused by the voltage change of SD gate 64[i] are kept consistent, thereby suppressing the degradation of image quality.

[0107] Furthermore, it is preferable that the parasitic capacitance C SR[i]-VB With parasitic capacitance C SD[i]-VB The total value of the differences between them is small, among which the parasitic capacitance C SR[i]-VB This is caused by capacitive coupling between SR gate 63[i] and VB gate 72[i], and the parasitic capacitance C SD[i]-VB This is caused by capacitive coupling between SD gate 64[i] and VB gate 72[i]. Therefore, it is preferable that pixel 31a is configured such that the parasitic capacitance C is reduced by the capacitance C. SR[i]-VB With parasitic capacitance C SD[i]-VB The total capacitance ratio C7 obtained by dividing the difference between them by the signal holding capacitor C ratio In practical applications, it is less than 1 / 1000, that is, pixel 31a is constructed to satisfy the following expression (11).

[0108] [Mathematical Formula 11]

[0109] Therefore, the solid-state imaging device 13 can suppress image quality degradation and capture images with better image quality.

[0110] Figure 12 An example layout of capacitor 61, capacitor 62 and V1 nodes is shown in pixels 31a[0] to 31a[3] arranged in a 2×2 arrangement.

[0111] like Figure 12In the 2×2 arrangement shown, there is a parasitic capacitance C between the capacitor 61 of pixel 31a[i] and the V1 node of another pixel 31a[j] that is vertically adjacent to pixel 31a[i]. V1[i]-VCR[j] The capacitor is capacitively coupled, and there is a parasitic capacitance C between capacitor 62 of pixel 31a[i] and V1 node of another pixel 31a[j]. V1[i]-VCD[j] Capacitive coupling.

[0112] Therefore, as Figure 12 As shown, pixels 31a[0] to 31a[3] adopt the following layout: among the adjacent pixels 31a[i] in the vertical direction, the V1 node[i], which serves as the drain node of the constant current source, is arranged at a position far away from each other, and capacitors 61[i] and 62[i] are arranged between the V1 nodes[i].

[0113] That is, in pixel 31a[0] located in the lower left corner, V1 node[0] is located on the bottom side, and in pixel 31a[2] located in the upper left corner, V1 node[2] is located on the top side, and capacitors 61[0] and 62[0], as well as capacitors 61[2] and 62[2], are located between V1 node[0] and V1 node[2]. Similarly, in pixel 31a[1] located in the lower right corner, V1 node[1] is located on the bottom side, and in pixel 31a[3] located in the upper right corner, V1 node[3] is located on the top side, and capacitors 61[1] and 62[1], as well as capacitors 61[3] and 62[3], are located between V1 node[1] and V1 node[3].

[0114] Furthermore, it is preferred that pixels 31a[0] to 31a[3] adopt the following layout: the V1 node[i] of adjacent pixels 31a[i] in the vertical direction is symmetrical about the dashed line passing through the center of the 2×2 arrangement structure in the horizontal direction, and the capacitors 61[i] and 62[i] of adjacent pixels 31a[i] in the vertical direction are symmetrical about the dashed line.

[0115] By adopting this layout, the parasitic capacitance C can be reduced. V1[i]-VCR[j] and parasitic capacitance C V1[i]-VCD[j] This suppresses the fluctuations in the holding potential of pixel 31a[i] caused by the potential fluctuations of pixel 31a[j] adjacent to pixel 31a[i] in the vertical direction. Therefore, the output fluctuations of each pixel 31a[i] can be reduced.

[0116] In other words, in order to reduce the output fluctuation of each pixel 31a[i] and obtain good image quality in the solid-state imaging device 13, it is preferable that, in the 2×2 arrangement structure, the parasitic capacitance C caused by the capacitive coupling between the capacitors 61 and 62 of pixel 31a[i] and the V1 node of another pixel 31a[j] adjacent to pixel 31a[i] in the vertical direction is reduced. V1[i]-VCR[j] and parasitic capacitance C V1[i]-VCD[j] Smaller. Therefore, preferably, pixel 31a[i] is constructed such that the parasitic capacitance C is reduced. V1[i]-VCR[j] The capacitance ratio C8 obtained by dividing by the signal holding capacitor C ratio And by controlling the parasitic capacitance C V1[i]-VCD[j] The capacitance ratio C9 obtained by dividing by the signal holding capacitor C ratio In practical applications, it is less than 1 / 1000, that is, pixel 31a[i] is constructed to satisfy the following expression (12).

[0117] [Mathematical Formula 12]

[0118] As described above, the global shutter solid-state imaging device 13, which utilizes a voltage domain type structure and includes pixels 31a constructed as described above, can suppress image quality degradation and capture images with better image quality by satisfying predetermined conditions for the layout of control lines, including the aforementioned gate, and the coupling between the control lines and the power lines.

[0119] <Examples of the third to tenth pixel constructions> Reference Figures 13 to 20 Describe the third through tenth construction examples for pixel 31.

[0120] Figure 13 A circuit diagram example for pixel 31b is shown as a third construction example. Note that in Figure 13 In pixel 31b shown, with Figure 2 Pixel 31 and Figure 7 The components of pixel 31a are represented by the same reference numerals, and therefore will not be described further.

[0121] like Figure 13 As shown, the construction of pixel 31b is similar to... Figure 2 The common feature of the construction of pixel 31b is that pixel 31b includes pixel circuit 41b and sample-and-hold circuit 42b, and is connected to constant current source 44 through vertical signal line 43. The construction method of sample-and-hold circuit 42b is similar to... Figure 7The sample-and-hold circuit 42a is similar in construction to the sample-and-hold circuit 42b, which includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, RB gate 65, amplification gate 66, selection gate 67, PC gate 71 and VB gate 72.

[0122] The construction method of pixel circuit 41b and Figure 2 The pixel circuit 41b is similar in construction to the pixel circuit 41b in that it includes a photoelectric conversion unit 51, a transmission gate 52, a reset gate 54, an amplification gate 56, and a switching gate 57. Furthermore, the pixel circuit 41a also includes an overflow gate 73 and a CLP gate 74.

[0123] like Figure 13 As shown, the CLP gate 74 is connected in parallel with the amplification gate 56, and the CLP gate 74 forms a source follower circuit in a manner similar to that of the amplification gate 56.

[0124] The global shutter solid-state imaging device 13, which utilizes a voltage domain type structure and includes pixels 31b constructed as described above, can capture images with better image quality by satisfying the coupling constraints of the above expressions (1) to (4).

[0125] Figure 14 A circuit diagram example for pixel 31c is shown as a fourth construction example. Note that in Figure 14 In pixel 31c shown, with Figure 2 Pixel 31 and Figure 7 The components of pixel 31a are represented by the same reference numerals, and therefore will not be described further.

[0126] like Figure 14 As shown, the construction of pixel 31c is similar to... Figure 2 The common feature of the construction of pixel 31 is that pixel 31c includes pixel circuit 41 and sample-and-hold circuit 42c, and is connected to constant current source 44 through vertical signal line 43.

[0127] The construction method of the sample-and-hold circuit 42c and Figure 2 The sample-and-hold circuit 42c is similar in construction to the sample-and-hold circuit 42c in that it includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, RB gate 65, amplification gate 66, and selection gate 67. Furthermore, the sample-and-hold circuit 42c also includes a DIFF gate 75 and capacitor 76, instead of... Figure 2 The constant current source in the middle is 68.

[0128] like Figure 14As shown, the drain of DIFF gate 75 is connected to node V1, which is the connection point between the source of switch gate 57 and one end of capacitor 61. The source of DIFF gate 75 is connected to the connection point between one end of capacitor 62 and one end of capacitor 76, and this connection point is referred to as node V3. The other end of capacitor 76 is connected to the signal line used to provide the ramp signal RAMP.

[0129] In the pixel 31c constructed as described above, when charge is accumulated in the capacitor 76 at a constant rate according to the sawtooth ramp signal RAMP, the capacitor 76 acts as a constant current source, which provides sink current as a constant current to the V1 node.

[0130] Furthermore, pixel 31c can reduce pixel signal leakage during the hold period in capacitors 61 and 62 by setting the DIFF gate 75. For example, the DIFF gate 75 is driven by the control signal DIFF, and capacitors 61 and 62 can be isolated by turning off the DIFF gate 75 during the read standby period after the global operation period. On the other hand, capacitors 61 and 62 can be connected by turning on the DIFF gate 75 during the read period, the entire global operation period, and / or the entire line read period.

[0131] The global shutter solid-state imaging device 13, which utilizes a voltage domain type structure and includes pixels 31c constructed as described above, can capture images with better image quality by satisfying the coupling constraints of the above expressions (1) to (4).

[0132] Figure 15 A circuit diagram example for pixel 31d is shown as a fifth construction example. Note that in Figure 15 In pixel 31d shown, with Figure 2 Pixel 31 and Figure 7 The components of pixel 31a are represented by the same reference numerals, and therefore will not be described further.

[0133] like Figure 15 As shown, the construction of pixel 31d is similar to... Figure 2 The common feature of the construction of pixel 31 is that pixel 31d includes pixel circuit 41d and sample-and-hold circuit 42d, and is connected to constant current source 44 through vertical signal line 43.

[0134] The construction method of pixel circuit 41d and Figure 2 The pixel circuit 41d is similar in construction to the pixel circuit 41d in that it includes a photoelectric conversion unit 51, a transmission gate 52, an FD gate 53, a reset gate 54, a capacitor 55, and an amplification gate 56, and is similar to... Figure 2 The difference between pixel circuit 41 and pixel circuit 41 is that the switching gate 57 is not provided. Note that pixel circuit 41d is different from... Figure 2 The difference in the pixel circuit 41 is that the drain of the amplification gate 56 and the drain of the reset gate 54 are connected to the power supply VDD.

[0135] The sample-and-hold circuit 42d includes a switching gate 57, a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an amplification gate 66, a selection gate 67, a PC gate 71, and a VB gate 72.

[0136] The drain of switch gate 57 is connected to the source of amplifier gate 56 and the drain of PC gate 71, and this connection point serves as node V1. The source of switch gate 57 is connected to node V2, and the drains of SR gate 63, SD gate 64, and the gate of amplifier gate 66 are also connected to node V2. The source of SR gate 63 is connected to one end of capacitor 61, and the other end of capacitor 61 is grounded. The source of SD gate 64 is connected to one end of capacitor 62, and the other end of capacitor 62 is grounded. The drain of amplifier gate 66 is connected to power supply VDD, the source of amplifier gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43. The drain of PC gate 71 is connected to node V1, the source of PC gate 71 is connected to the drain of VB gate 72, and the source of VB gate 72 is grounded.

[0137] The global shutter solid-state imaging device 13, which utilizes a voltage domain type structure and includes pixels 31d constructed as described above, can capture images with better image quality by satisfying the coupling constraints of the above expressions (1), (2) and (4).

[0138] Figure 16 A circuit diagram example for pixel 31e is shown as the sixth construction example. Note that in Figure 16 In pixel 31e shown, with Figure 2 Pixel 31 and Figure 7 The components of pixel 31a are all represented by the same reference numerals, so they will not be described again.

[0139] like Figure 16 As shown, the construction of pixel 31e is similar to... Figure 2 The common feature of the construction of pixel 31 is that pixel 31e includes pixel circuit 41 and sample-and-hold circuit 42e. In addition, pixel 31e is connected to constant current source 44-1 through vertical signal line 43-1 and to constant current source 44-2 through vertical signal line 43-2.

[0140] The sample-and-hold circuit 42e includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, amplification gate 66-1 and amplification gate 66-2, selection gate 67-1 and selection gate 67-2, and PC gate 71.

[0141] The drain of SR gate 63 is connected to node V1, and the source of SR gate 63 is connected to one end of capacitor 61 and the gate of amplification gate 66-1. The drain of amplification gate 66-1 is connected to power supply VDD, and the source of amplification gate 66-1 is connected to the drain of select gate 67-1, and the source of select gate 67-1 is connected to vertical signal line 43-1. The drain of SD gate 64 is connected to node V1, and the source of SD gate 64 is connected to one end of capacitor 62 and the gate of amplification gate 66-2. The drain of amplification gate 66-2 is connected to power supply VDD, and the source of amplification gate 66-2 is connected to the drain of select gate 67-2, and the source of select gate 67-2 is connected to vertical signal line 43-2. ​​The drain of PC gate 71 is connected to node V1, and the source of PC gate 71 is grounded.

[0142] Similarly, a global shutter solid-state imaging device 13, which utilizes a voltage-domain structure and includes pixels 31e constructed as described above, can also capture images with better image quality.

[0143] Figure 17 A circuit diagram example for pixel 31f is shown as the seventh construction example. Note that in Figure 17 In pixel 31f shown, with Figure 2 Pixel 31 and Figure 7 The components of pixel 31a are represented by the same reference numerals, and therefore will not be described further.

[0144] like Figure 17 As shown, the construction of pixel 31f is similar to... Figure 2 The common feature of the construction of pixel 31 is that pixel 31f includes pixel circuit 41 and sample-and-hold circuit 42f, and is connected to constant current source 44 through vertical signal line 43.

[0145] The sample-and-hold circuit 42f includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, amplification gate 66, selection gate 67, and PC gate 71.

[0146] The drain of SR gate 63 is connected to node V1, and the source of SR gate 63 is connected to one end of capacitor 61 and one end of capacitor 62. The other end of capacitor 62 is connected to node V2, and the drain of SD gate 64 and the gate of amplification gate 66 are connected to node V2. The drain of amplification gate 66 is connected to power supply VDD, the source of amplification gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43. The drain of PC gate 71 is connected to node V1, and the source of PC gate 71 is grounded.

[0147] Similarly, a global shutter solid-state imaging device 13, which utilizes a voltage-domain structure and includes pixels 31f constructed as described above, can also capture images with better image quality.

[0148] Figure 18 A circuit diagram example for pixel 31g is shown as an example of the eighth construction. Note that in Figure 18 In the pixel 31g shown, with Figure 2 Pixel 31 and Figure 7 The components of pixel 31a are represented by the same reference numerals, and therefore will not be described further.

[0149] like Figure 18 As shown, the structure of pixel 31g is similar to... Figure 2 The common feature of the construction of the pixels 31 is that the pixels 31g include pixel circuit 41g and sample-and-hold circuit 42g, and are connected to constant current source 44 through vertical signal line 43.

[0150] The construction method of pixel circuit 41g and Figure 2 The pixel circuit 41 in the image is similar in that it includes a photoelectric conversion unit 51, a transmission gate 52, an FD gate 53, a reset gate 54, a capacitor 55, and an amplification gate 56, and is similar to... Figure 2 The difference in pixel circuit 41 is that it does not have a switch gate 57.

[0151] The sample-and-hold circuit 42g includes a switch gate 57, a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an amplification gate 66, a selection gate 67, a PC gate 71, and a VB gate 72.

[0152] The drain of switch gate 57 is connected to the source of amplifier gate 56 and the drain of PC gate 71, and this connection point serves as node V1. The source of switch gate 57 is connected to node V2, and the drains of SR gate 63, SD gate 64, and the gate of amplifier gate 66 are also connected to node V2. The source of SR gate 63 is connected to one end of capacitor 61, and the other end of capacitor 61 is grounded. The source of SD gate 64 is connected to one end of capacitor 62, and the other end of capacitor 62 is grounded. The drain of amplifier gate 66 is connected to power supply VDD, the source of amplifier gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43. The drain of PC gate 71 is connected to node V1, the source of PC gate 71 is connected to the drain of VB gate 72, and the source of VB gate 72 is grounded.

[0153] Similarly, a global shutter solid-state imaging device 13, which utilizes a voltage-domain structure and includes pixels 31g constructed as described above, can also capture images with better image quality.

[0154] Figure 19 A circuit diagram example for pixel 31h is shown as a ninth construction example. Note that in Figure 19In pixel 31h shown, with Figure 2 Pixel 31 and Figure 7 The components of pixel 31a are represented by the same reference numerals, and therefore will not be described further.

[0155] like Figure 19 As shown, the construction of pixel 31h is similar to... Figure 2 The common feature of the construction of the pixels 31 is that the pixels 31h include pixel circuit 41 and sample-and-hold circuit 42h, and are connected to constant current source 44 through vertical signal line 43.

[0156] The sample-and-hold circuit 42h includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, amplification gate 66, selection gate 67, and PC gate 71.

[0157] The drain of SR gate 63 is connected to node V1, and the source of SR gate 63 is connected to the drain of SD gate 64 and one end of capacitor 61. The source of SD gate 64 is connected to the gate of amplifying gate 66 and one end of capacitor 62. The drain of amplifying gate 66 is connected to power supply VDD, the source of amplifying gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43. The drain of PC gate 71 is connected to node V1, and the source of PC gate 71 is grounded.

[0158] Similarly, a global shutter solid-state imaging device 13, which utilizes a voltage-domain structure and includes pixels 31h constructed as described above, can also capture images with better image quality.

[0159] Figure 20 A circuit diagram example for pixel 31i is shown as the tenth construction example. Note that in Figure 20 In the pixel 31i shown, with Figure 2 Pixel 31 and Figure 7 The components of pixel 31a are represented by the same reference numerals, and therefore will not be described further.

[0160] like Figure 20 As shown, the construction of pixel 31i is similar to... Figure 2 The common feature of the construction of the pixels 31 is that the pixels 31i include pixel circuit 41 and sample-and-hold circuit 42i, and are connected to constant current source 44 through vertical signal line 43.

[0161] The sample-and-hold circuit 42i includes capacitor 61, capacitor 62, RB gate 65, amplification gate 66, selection gate 67 and PC gate 71.

[0162] One end of capacitor 61 is connected to node V1, and the other end of capacitor 61 is connected to one end of capacitor 62, the source of RB gate 65, and the gate of amplifying gate 66. The drain of RB gate 65 is connected to power supply VREG, and the drain of amplifying gate 66 is connected to power supply VDD. The source of amplifying gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43. The drain of PC gate 71 is connected to node V1, and the source of PC gate 71 is grounded.

[0163] Similarly, a global shutter solid-state imaging device 13, which utilizes a voltage domain type structure and includes pixels 31i constructed as described above, can also capture images with better image quality.

[0164] Note that pixel 31 can be divided by... Figures 13 to 20 Various constructs other than those shown are permitted, and any construct that satisfies the above coupling constraints and other conditions may be used.

[0165] <Example of cross-sectional structure of solid-state imaging device> Reference Figures 21 to 24 An example of the cross-sectional structure of the solid-state imaging device 13 is described.

[0166] Figure 21 A cross-sectional structure of the solid-state imaging device 13 is shown as a first example of its construction.

[0167] like Figure 21 As shown, the solid-state imaging device 13 has a double-layer structure formed by stacking a first semiconductor substrate 101 and a second semiconductor substrate 102, and a plurality of pixels 31 are arranged in the pixel array unit 21.

[0168] The first semiconductor substrate 101 is constructed by stacking a wiring layer 112 on the semiconductor layer 111, and the on-chip lens 113 for converging light of each pixel 31 is stacked on the light receiving side of the semiconductor layer 111.

[0169] The semiconductor layer 111 is provided with a photoelectric conversion unit 51 for each pixel 31 and various components constituting the pixel circuit 41 (e.g., a transmission gate 52 and an FD gate 53). In addition, the semiconductor layer 111 is also provided with a component isolation unit 121 for optically and electrically isolating adjacent pixels 31 from each other.

[0170] The wiring layer 112 is provided with a plurality of wirings and a plurality of through electrodes for electrical connection to the second semiconductor substrate 102 for each pixel. In addition, pads 122 for connecting the solid-state imaging device 13 to the outside are arranged in the peripheral region of the wiring layer 112 (the region outside the pixel array unit 21) and are provided with openings 123 for wiring bonding with the pads 122.

[0171] The second semiconductor substrate 102 is constructed by stacking a wiring layer 132 on the semiconductor layer 131.

[0172] The semiconductor layer 131 is provided with various elements constituting the sample-and-hold circuit 42 (e.g., SR gate 63 and SD gate 64, etc.). In addition, the semiconductor layer 131 is also provided with various elements constituting, for example, logic circuits for driving the solid-state imaging device 13.

[0173] The wiring layer 132 is provided with a plurality of wires and a plurality of through electrodes for electrically connecting each pixel 31 to the first semiconductor substrate 101. In addition, the wiring layer 132 is also provided with a metal-insulator-metal (MIM) structure 143 constituting capacitor 61 and capacitor 62 for each pixel 31.

[0174] The solid-state imaging device 13 with this stacked structure can have the following configuration: as in Figure 21 In the illustrated construction example, the wiring layer 112 of the first semiconductor substrate 101 and the wiring layer 132 of the second semiconductor substrate 102 are bonded to each other.

[0175] Figure 22 A cross-sectional structure of the solid-state imaging device 13A is shown as a second structural example. Note that in Figure 22 In the solid-state imaging device 13A shown, with Figure 21 The same components of the solid-state imaging device 13 shown are indicated by the same reference numerals and therefore will not be described again.

[0176] like Figure 22 As shown, the solid-state imaging device 13A has a two-layer structure formed by stacking a first semiconductor substrate 101A and a second semiconductor substrate 102A. Then, in the solid-state imaging device 13A, with... Figure 21 Similar to the solid-state imaging device 13, each pixel 31 is provided with a photoelectric conversion unit 51 in the semiconductor layer 111 of the first semiconductor substrate 101A, and a MIM structure 143 is provided in the wiring layer 132A of the second semiconductor substrate 102A.

[0177] In addition, the solid-state imaging device 13A and Figure 21 The difference between the solid-state imaging device 13 and the solid-state imaging device 13A is that, in the construction of the solid-state imaging device 13A, the wiring layer 112A of the first semiconductor substrate 101A and the semiconductor layer 131A of the second semiconductor substrate 102A are bonded to each other. In addition, in the solid-state imaging device 13A, a pad 122A is arranged on the wiring layer 132A, and the opening 123A is configured to pass through the first semiconductor substrate 101A and communicate with the pad 122.

[0178] Figure 23A cross-sectional structure of the solid-state imaging device 13B is shown as a third structural example. Note that in Figure 23 In the solid-state imaging device 13B shown, with Figure 21 The same components of the solid-state imaging device 13 shown are indicated by the same reference numerals and therefore will not be described again.

[0179] like Figure 23 As shown, the solid-state imaging device 13B has a three-layer structure formed by stacking a first semiconductor substrate 101, a second semiconductor substrate 102, and a third semiconductor substrate 103, and the wiring layer 112 of the first semiconductor substrate 101 and the wiring layer 132 of the second semiconductor substrate 102 are bonded to each other. That is, in the construction of the solid-state imaging device 13B, the third semiconductor substrate 103, constructed by stacking the wiring layer 152 on the semiconductor layer 151, is stacked to... Figure 21 The solid-state imaging device 13 is constructed on a first semiconductor substrate 101 and a second semiconductor substrate 102 in a similar manner.

[0180] For example, in the solid-state imaging device 13B, various components constituting the pixel circuit 41 are disposed in the first semiconductor substrate 101, and various components constituting the sample-and-hold circuit 42 are disposed in the second semiconductor substrate 102. Then, various components constituting the logic circuit for driving the solid-state imaging device 13 are disposed in the third semiconductor substrate 103.

[0181] Figure 24 A cross-sectional structure of the solid-state imaging device 13C is shown as a fourth construction example. Note that in Figure 23 In the solid-state imaging device 13C shown, with Figure 21 The same components of the solid-state imaging device 13 shown are indicated by the same reference numerals and therefore will not be described again.

[0182] like Figure 24 As shown, the solid-state imaging device 13C has a three-layer structure formed by stacking a first semiconductor substrate 101C, a second semiconductor substrate 102C, and a third semiconductor substrate 103, and the wiring layer 112C of the first semiconductor substrate 101C and the semiconductor layer 131C of the second semiconductor substrate 102C are bonded to each other. That is, in the construction of the solid-state imaging device 13C, the third semiconductor substrate 103, constructed by stacking a wiring layer 152 on the semiconductor layer 151, is stacked to... Figure 22 The solid-state imaging device 13A is constructed on a first semiconductor substrate 101A and a second semiconductor substrate 102A in a manner similar to that of the solid-state imaging device 13A.

[0183] For example, in the solid-state imaging device 13C, various components constituting the pixel circuit 41 are disposed in the first semiconductor substrate 101C, and various components constituting the sample-and-hold circuit 42 are disposed in the second semiconductor substrate 102C. Then, various components constituting the logic circuit for driving the solid-state imaging device 13 are disposed in the third semiconductor substrate 103.

[0184] Note that the solid-state imaging device 13 can employ a method other than... Figures 21 to 24 Stacking structures other than those shown.

[0185] <Examples of Image Sensor Applications> Figure 25 This is a diagram illustrating an example of using the aforementioned image sensor (solid-state imaging device).

[0186] The image sensor described above can be used in various situations for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, as described below.

[0187] • Devices used to capture images for viewing, such as digital video cameras and mobile devices with camera functionality; • Equipment for transportation purposes, including onboard sensors for capturing images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and for identifying driver status, surveillance cameras for monitoring vehicles and roads, and distance measurement sensors for measuring distances between vehicles. • Devices used in household appliances such as televisions, refrigerators, and air conditioners to capture user gestures and enable the appliances to operate according to those gestures; • Devices used in medical and health care, such as endoscopes and devices that perform vascular imaging by receiving infrared light; • Devices used for security, such as security surveillance cameras and authentication cameras; • Devices used in beauty, such as dermatographs for skin imaging and microscopes for scalp imaging; • Equipment used for sports, such as sports cameras or wearable cameras; • Equipment used in agriculture, such as cameras used to monitor the condition of fields and crops.

[0188] <Examples of constructed combinations> Note that this technology can also have the following configuration. (1) A solid-state imaging device, comprising: Pixels, which include: A pixel circuit, having at least a photoelectric conversion unit, outputs pixel signals to a first node; and A sample-and-hold circuit has at least the following features: A first capacitor, one end of which is connected to the first node, maintains the voltage of the pixel signal output from the pixel circuit at the reset level; A second capacitor, one end of which is connected to the first node, maintains the voltage of the pixel signal output from the pixel circuit at the pixel signal level; An amplifying gate generates a pixel signal corresponding to the charge accumulated in a second node connected to its gate. A first gate, which connects a third node and a second node, wherein the third node serves as a connection point between the first gate and the other end of the first capacitor; and A second gate connects the fourth node and the second node, wherein the fourth node serves as a connection point between the second gate and the other end of the second capacitor. The difference between the parasitic capacitances caused by the capacitive coupling between the two nodes of the sample-and-hold circuit and one of the two gates of the sample-and-hold circuit is less than a predetermined value. (2) The solid-state imaging device according to (1), wherein, The difference between the first parasitic capacitance and the second parasitic capacitance is less than the predetermined value. The first parasitic capacitance is caused by capacitive coupling between the first gate and the second node, and the second parasitic capacitance is caused by capacitive coupling between the second gate and the second node. (3) The solid-state imaging device according to (2), wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The first capacitance ratio obtained by dividing the difference between the first parasitic capacitance and the second parasitic capacitance by the signal holding capacitance is less than 1 / 1000. (4) The solid-state imaging device according to (3), wherein, The following pixel-sharing structure is adopted: multiple pixels share the second node, and The difference between the maximum and minimum values ​​of the first capacitance ratio of each pixel is less than 1 / 1000. (5) The solid-state imaging device according to any one of (1) to (4), wherein, The difference between the third parasitic capacitance and the fourth parasitic capacitance is less than the predetermined value. The third parasitic capacitance is caused by capacitive coupling between the first gate and the third node, and the fourth parasitic capacitance is caused by capacitive coupling between the second gate and the fourth node. (6) The solid-state imaging device according to (5), wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The second capacitance ratio obtained by dividing the difference between the third parasitic capacitance and the fourth parasitic capacitance by the signal holding capacitance is less than 1 / 1000. (7) The solid-state imaging device according to (6), wherein, The following pixel-sharing structure is adopted: multiple pixels share the second node, and The difference between the maximum and minimum values ​​of the second capacitance ratio of each pixel is less than 1 / 1000. (8) The solid-state imaging device according to any one of (1) to (7), further comprising: The third gate resets the charge accumulated in the second, third, and fourth nodes, wherein... The difference between the fifth parasitic capacitance and the sixth parasitic capacitance is less than the predetermined value. The fifth parasitic capacitance is caused by capacitive coupling between the third gate and the second node, and the sixth parasitic capacitance is caused by capacitive coupling between the third gate and the second node. (9) The solid-state imaging device according to (8), wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The third capacitance ratio, obtained by dividing the difference between the fifth parasitic capacitance and the sixth parasitic capacitance by the signal holding capacitance, is less than 1 / 1000. (10) The solid-state imaging device according to (9), wherein, The following pixel-sharing structure is adopted: multiple pixels share the second node, and The difference between the maximum and minimum values ​​of the third capacitance ratio of each pixel is less than 1 / 1000. (11) The solid-state imaging device according to (10), wherein, In the wiring layer provided with a first control signal line for providing control signals to the third gate, the wiring layout is as follows: other wiring is arranged between the first control signal line and the wiring connected to the third node and the fourth node. (12) The solid-state imaging device according to any one of (1) to (11), further comprising: The fourth gate selects the pixels from which the pixel signal generated by the amplifying gate is to be output, wherein, The difference between the seventh parasitic capacitance and the eighth parasitic capacitance is less than the predetermined value. The seventh parasitic capacitance is caused by capacitive coupling between the fourth gate and the second node, and the eighth parasitic capacitance is caused by capacitive coupling between the fourth gate and the second node. (13) The solid-state imaging device according to (12), wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The fourth capacitance ratio obtained by dividing the difference between the seventh parasitic capacitance and the signal holding capacitance is less than 1 / 1000. (14) The solid-state imaging device according to (13), wherein, The following pixel-sharing structure is adopted: multiple pixels share the second node, and The difference between the maximum and minimum values ​​of the fourth capacitance ratio of each pixel is less than 1 / 1000. (15) The solid-state imaging device according to (14), wherein, In the wiring layer provided with a second control signal line for providing control signals to the fourth gate, the wiring layout is as follows: other wiring is arranged between the second control signal line and the wiring connected to the third node and the fourth node. (16) The solid-state imaging device according to (8), wherein, In a wiring layer containing a third control signal line for providing control signals to the first gate, a fourth control signal line for providing control signals to the second gate, and a fifth and sixth control signal line for providing control signals to the third gate, extending in the same direction, a wiring layout is provided as follows: the third and fourth control signal lines are symmetrical about the same direction line, and the fifth and sixth control signal lines are also symmetrical about the same direction line. (17) The solid-state imaging device according to (16), wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The fifth capacitance ratio, obtained by dividing the difference between the eighth and ninth parasitic capacitances by the signal holding capacitance, is less than 1 / 1000. The eighth parasitic capacitance is caused by capacitive coupling between the third and fifth control signal lines, and the ninth parasitic capacitance is caused by capacitive coupling between the fourth and sixth control signal lines. (18) The solid-state imaging device according to (17), wherein, The following pixel-sharing structure is adopted: multiple pixels share the second node, and The difference between the total value of the eighth parasitic capacitance of each pixel and the total value of the ninth parasitic capacitance of each pixel is less than 1 / 1000. (19) The solid-state imaging device according to (16), wherein, The following pixel-sharing structure is adopted: multiple pixels with a 2×2 arrangement share the second node. The first gate and the second gate have a translational symmetry relationship, and The first current source gate and the second current source gate, which are used to provide a constant current to the first node and are cascaded together, have a linear symmetric relationship. (20) The solid-state imaging device according to (19), wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The sixth capacitance ratio, obtained by dividing the difference between the total value of the tenth parasitic capacitance and the total value of the eleventh parasitic capacitance by the signal holding capacitance, is less than 1 / 1000. The tenth parasitic capacitance is caused by capacitive coupling between the first gate and the first current source gate in each of the pixels, and the eleventh parasitic capacitance is caused by capacitive coupling between the second gate and the first current source gate in each of the pixels. (21) The solid-state imaging device according to any one of (1) to (20), wherein, The following pixel-sharing structure is adopted: multiple pixels with a 2×2 arrangement share the second node. The first nodes of the pixels that are adjacent in the vertical direction are linearly symmetrical to each other, and the first capacitor and the second capacitor of each pixel are arranged between the first nodes. (22) The solid-state imaging device according to (21), wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The sixth capacitance ratio, obtained by dividing the twelfth parasitic capacitance by the signal holding capacitance, is less than 1 / 1000. The twelfth parasitic capacitance is caused by capacitive coupling between the first node of one pixel and the first capacitor of another pixel in a vertically adjacent pixel. The seventh capacitance ratio, obtained by dividing the thirteenth parasitic capacitance by the signal holding capacitance, is less than 1 / 1000. The thirteenth parasitic capacitance is caused by capacitive coupling between the first node of one pixel and the second capacitor of another pixel in the vertically adjacent pixels. (23) An electronic device including a solid-state imaging device, the solid-state imaging device comprising: Pixels, which include: A pixel circuit, having at least a photoelectric conversion unit, outputs pixel signals to a first node; and A sample-and-hold circuit has at least the following features: A first capacitor, one end of which is connected to the first node, maintains the voltage of the pixel signal output from the pixel circuit at the reset level; A second capacitor, one end of which is connected to the first node, maintains the voltage of the pixel signal output from the pixel circuit at the pixel signal level; An amplifying gate generates a pixel signal corresponding to the charge accumulated in a second node connected to its gate. A first gate, which connects a third node and a second node, wherein the third node serves as a connection point between the first gate and the other end of the first capacitor; and A second gate connects the fourth node and the second node, wherein the fourth node serves as a connection point between the second gate and the other end of the second capacitor. The difference between the parasitic capacitances caused by the capacitive coupling between the two nodes of the sample-and-hold circuit and one of the two gates of the sample-and-hold circuit is less than a predetermined value.

[0189] Note that this embodiment is not limited to the above embodiment, and various modifications can be made without departing from the essence of this disclosure. Furthermore, the effects described herein are merely illustrative and not intended to limit the invention; other effects can also be achieved. List of reference numerals

[0190] 11 Imaging Device 12 Optical System 13 Solid-state imaging devices 14 Imaging Control Circuit 15. Signal Processing Circuit 16 monitors 17. Memory 21-pixel array unit 22 Timing Control Circuit 23 Vertical Scanning Circuit 24 DAC 25 Load MOS circuit block 26-column signal processing circuits 31 pixels 41-pixel circuit 42 Sample and Hold Circuit 43 Vertical signal line 44 Constant Current Source 51 Photoelectric Conversion Unit 52 Transmission Gate 53 FD gate 54 Reset Gate 55 capacitor 56 Magnifying Grid 57 switch gate 61 Capacitor 62 capacitors 63 SR gate 64 SD gate 64 65 RB gate 66 Magnifying Grid 67 Selection Gate 68 Constant Current Source

Claims

1. A solid-state imaging device, the solid-state imaging device comprising pixels, the pixels comprising: A pixel circuit, which has at least a photoelectric conversion unit and outputs pixel signals to a first node; and A sample-and-hold circuit has at least the following features: A first capacitor, one end of which is connected to the first node, maintains the voltage of the pixel signal output from the pixel circuit at the reset level; A second capacitor, one end of which is connected to the first node, maintains the voltage of the pixel signal output from the pixel circuit at the pixel signal level; An amplifying gate generates a pixel signal corresponding to the charge accumulated in a second node connected to its gate. A first gate, which connects a third node and a second node, wherein the third node serves as a connection point between the first gate and the other end of the first capacitor; and A second gate connects the fourth node and the second node, wherein the fourth node serves as a connection point between the second gate and the other end of the second capacitor. The difference between the parasitic capacitances caused by the capacitive coupling between the two nodes of the sample-and-hold circuit and one of the two gates of the sample-and-hold circuit is less than a predetermined value.

2. The solid-state imaging device according to claim 1, wherein, The difference between the first parasitic capacitance and the second parasitic capacitance is less than the predetermined value. The first parasitic capacitance is caused by capacitive coupling between the first gate and the second node, and the second parasitic capacitance is caused by capacitive coupling between the second gate and the second node.

3. The solid-state imaging device according to claim 2, wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The first capacitance ratio obtained by dividing the difference between the first parasitic capacitance and the second parasitic capacitance by the signal holding capacitance is less than 1 / 1000.

4. The solid-state imaging device according to claim 3, wherein, The following pixel-sharing structure is adopted: multiple pixels share the second node, and The difference between the maximum and minimum values ​​of the first capacitance ratio of each pixel is less than 1 / 1000.

5. The solid-state imaging device according to claim 1, wherein, The difference between the third parasitic capacitance and the fourth parasitic capacitance is less than the predetermined value. The third parasitic capacitance is caused by capacitive coupling between the first gate and the third node, and the fourth parasitic capacitance is caused by capacitive coupling between the second gate and the fourth node.

6. The solid-state imaging device according to claim 5, wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The second capacitance ratio obtained by dividing the difference between the third parasitic capacitance and the fourth parasitic capacitance by the signal holding capacitance is less than 1 / 1000.

7. The solid-state imaging device according to claim 6, wherein, The following pixel-sharing structure is adopted: multiple pixels share the second node, and The difference between the maximum and minimum values ​​of the second capacitance ratio of each pixel is less than 1 / 1000.

8. The solid-state imaging device according to claim 1, further comprising: The third gate resets the charge accumulated in the second, third, and fourth nodes, wherein... The difference between the fifth parasitic capacitance and the sixth parasitic capacitance is less than the predetermined value. The fifth parasitic capacitance is caused by capacitive coupling between the third gate and the second node, and the sixth parasitic capacitance is caused by capacitive coupling between the third gate and the second node.

9. The solid-state imaging device according to claim 8, wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The third capacitance ratio, obtained by dividing the difference between the fifth parasitic capacitance and the sixth parasitic capacitance by the signal holding capacitance, is less than 1 / 1000.

10. The solid-state imaging device according to claim 9, wherein, The following pixel-sharing structure is adopted: multiple pixels share the second node, and The difference between the maximum and minimum values ​​of the third capacitance ratio of each pixel is less than 1 / 1000.

11. The solid-state imaging device according to claim 10, wherein, In the wiring layer provided with a first control signal line for providing control signals to the third gate, the wiring layout is as follows: other wiring is arranged between the first control signal line and the wiring connected to the third node and the fourth node.

12. The solid-state imaging device according to claim 1, further comprising: The fourth gate selects the pixels from which the pixel signal generated by the amplifying gate is to be output, wherein, The difference between the seventh parasitic capacitance and the eighth parasitic capacitance is less than the predetermined value. The seventh parasitic capacitance is caused by capacitive coupling between the fourth gate and the second node, and the eighth parasitic capacitance is caused by capacitive coupling between the fourth gate and the second node.

13. The solid-state imaging device according to claim 12, wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The fourth capacitance ratio obtained by dividing the difference between the seventh parasitic capacitance and the signal holding capacitance is less than 1 / 1000.

14. The solid-state imaging device according to claim 13, wherein, The following pixel-sharing structure is adopted: multiple pixels share the second node, and The difference between the maximum and minimum values ​​of the fourth capacitance ratio of each pixel is less than 1 / 1000.

15. The solid-state imaging device according to claim 14, wherein, In the wiring layer provided with a second control signal line for providing control signals to the fourth gate, the wiring layout is as follows: other wiring is arranged between the second control signal line and the wiring connected to the third node and the fourth node.

16. The solid-state imaging device according to claim 8, wherein, In a wiring layer containing a third control signal line for providing control signals to the first gate, a fourth control signal line for providing control signals to the second gate, and a fifth and sixth control signal line for providing control signals to the third gate, extending in the same direction, a wiring layout is provided as follows: the third and fourth control signal lines are symmetrical about the same direction line, and the fifth and sixth control signal lines are also symmetrical about the same direction line.

17. The solid-state imaging device according to claim 16, wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The fifth capacitance ratio, obtained by dividing the difference between the eighth and ninth parasitic capacitances by the signal holding capacitance, is less than 1 / 1000. The eighth parasitic capacitance is caused by capacitive coupling between the third and fifth control signal lines, and the ninth parasitic capacitance is caused by capacitive coupling between the fourth and sixth control signal lines.

18. The solid-state imaging device according to claim 17, wherein, The following pixel-sharing structure is adopted: multiple pixels share the second node, and The difference between the total value of the eighth parasitic capacitance of each pixel and the total value of the ninth parasitic capacitance of each pixel is less than 1 / 1000.

19. The solid-state imaging device according to claim 16, wherein, The following pixel-sharing structure is adopted: multiple pixels with a 2×2 arrangement share the second node. The first gate and the second gate have a translational symmetry relationship, and The first current source gate and the second current source gate, which are used to provide a constant current to the first node and are cascaded together, have a linear symmetric relationship.

20. The solid-state imaging device according to claim 19, wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The sixth capacitance ratio, obtained by dividing the difference between the total value of the tenth parasitic capacitance and the total value of the eleventh parasitic capacitance by the signal holding capacitance, is less than 1 / 1000. The tenth parasitic capacitance is caused by capacitive coupling between the first gate and the first current source gate in each of the pixels, and the eleventh parasitic capacitance is caused by capacitive coupling between the second gate and the first current source gate in each of the pixels.

21. The solid-state imaging device according to claim 1, wherein, The following pixel-sharing structure is adopted: multiple pixels with a 2×2 arrangement share the second node. The first nodes of the pixels that are adjacent in the vertical direction are linearly symmetrical to each other, and the first capacitor and the second capacitor of each pixel are arranged between the first nodes.

22. The solid-state imaging device according to claim 21, wherein, The first capacitor and the second capacitor have substantially the same signal holding capacitance, and The sixth capacitance ratio, obtained by dividing the twelfth parasitic capacitance by the signal holding capacitance, is less than 1 / 1000. The twelfth parasitic capacitance is caused by capacitive coupling between the first node of one pixel and the first capacitor of another pixel in a vertically adjacent pixel. The seventh capacitance ratio, obtained by dividing the thirteenth parasitic capacitance by the signal holding capacitance, is less than 1 / 1000. The thirteenth parasitic capacitance is caused by capacitive coupling between the first node of one pixel and the second capacitor of another pixel in the vertically adjacent pixels.

23. An electronic device including a solid-state imaging device, the solid-state imaging device including pixels, the pixels comprising: A pixel circuit, which has at least a photoelectric conversion unit and outputs pixel signals to a first node; and A sample-and-hold circuit has at least the following features: A first capacitor, one end of which is connected to the first node, maintains the voltage of the pixel signal output from the pixel circuit at the reset level; A second capacitor, one end of which is connected to the first node, maintains the voltage of the pixel signal output from the pixel circuit at the pixel signal level; An amplifying gate generates a pixel signal corresponding to the charge accumulated in a second node connected to its gate. A first gate, which connects a third node and a second node, wherein the third node serves as a connection point between the first gate and the other end of the first capacitor; and A second gate connects the fourth node and the second node, wherein the fourth node serves as a connection point between the second gate and the other end of the second capacitor. The difference between the parasitic capacitances caused by the capacitive coupling between the two nodes of the sample-and-hold circuit and one of the two gates of the sample-and-hold circuit is less than a predetermined value.

Images