Semiconductor device

Abstract

A semiconductor device that is easily miniaturized is provided. The semiconductor device includes first to fourth conductive layers, a semiconductor layer, and first to fourth insulating layers. The first insulating layer is on the first conductive layer and includes a first slit reaching the first conductive layer. The second conductive layer is on the first insulating layer. The semiconductor layer has a portion in contact with the second conductive layer, a side surface of the first insulating layer, and the first conductive layer. The second insulating layer covers the semiconductor layer inside the first slit, the third conductive layer covers the second insulating layer inside the first slit, the third insulating layer is below the first insulating layer and includes a second slit. The fourth conductive layer has a portion along a side surface of the third insulating layer inside the second slit. The first conductive layer has a portion inside the second slit. The fourth insulating layer is between the first conductive layer and the fourth conductive layer inside the second slit.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. One aspect of the present invention relates to a transistor. One aspect of the present invention relates to a memory device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving these devices, and methods for manufacturing these devices. A semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Background Technology

[0003] In recent years, semiconductor devices have been developed, with CPUs (Central Processing Units), memory, or LSIs (other components) primarily used in semiconductor devices. A CPU is an assembly of semiconductor integrated circuits (including at least transistors and memory) formed by processing semiconductor wafers to create chips, and semiconductor elements having electrodes formed as connection terminals.

[0004] CPUs, memory, or other LSI semiconductor circuits (IC chips) are mounted on circuit boards, such as printed circuit boards, and used as components of various electronic devices.

[0005] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted considerable attention. These transistors are widely used in electronic devices such as integrated circuits and image display devices (simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. Among other materials, oxide semiconductors have also garnered attention.

[0006] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely small in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current. Additionally, for example, Patent Document 2 discloses a storage device that achieves long-term retention of stored content.

[0007] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 discloses a technique in which multiple memory cells are stacked in an overlapping manner by layering a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of the integrated circuit. For example, Patent Document 4 discloses a vertical transistor in which the gate electrode covers the sidewall of the oxide semiconductor through a gate insulator.

[0008] [Preliminary Technology Documents]

[0009] [Patent Literature]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0011] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0012] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0013] [Patent Document 4] Japanese Patent Application Publication No. 2013-211537 Summary of the Invention

[0014] The technical problem that the invention aims to solve

[0015] One objective of this invention is to provide a semiconductor device that is easily miniaturized. Another objective is to provide a semiconductor device capable of achieving high integration. Additionally, one objective is to provide a semiconductor device with reduced wiring load. Furthermore, one objective is to provide a semiconductor device with high reliability. Furthermore, one objective is to provide a semiconductor device with good electrical characteristics. Finally, one objective is to provide a semiconductor device with high operating speed.

[0016] One objective of this invention is to provide a semiconductor device, memory device, or electronic device with a novel structure. Another objective of this invention is to improve at least one of the problems of the prior art.

[0017] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Note that objectives other than those described above can be extracted from the description in the specification, drawings, claims, etc.

[0018] means of solving technical problems

[0019] One aspect of the present invention is a semiconductor device comprising: a first conductive layer; a second conductive layer; a third conductive layer; a fourth conductive layer; a semiconductor layer; a first insulating layer; a second insulating layer; a third insulating layer; and a fourth insulating layer. The first insulating layer is located on the first conductive layer and has a first slit reaching the first conductive layer. The second conductive layer is located on the first insulating layer. The semiconductor layer has a portion contacting the second conductive layer, a portion inside the first slit along a side of the first insulating layer, and a portion inside the first slit contacting the first conductive layer. The second insulating layer covers the semiconductor layer inside the first slit, and the third conductive layer covers the second insulating layer inside the first slit, the third insulating layer being located below the first insulating layer and having the second slit. The fourth conductive layer has a portion inside the second slit along a side of the third insulating layer. The first conductive layer has a portion located inside the second slit. The fourth insulating layer is located inside the second slit between the first conductive layer and the fourth conductive layer.

[0020] Furthermore, in the aforementioned semiconductor device, both the first slit and the second slit preferably extend in the first direction. The third conductive layer preferably extends in the first direction inside the first slit. And, the fourth conductive layer preferably extends in the first direction inside the second slit.

[0021] Furthermore, in the aforementioned semiconductor device, the first slit preferably extends in a first direction. The second slit preferably extends in a second direction intersecting the first direction. The third conductive layer preferably extends inside the first slit in the first direction. And, the fourth conductive layer preferably extends inside the second slit in the second direction.

[0022] Furthermore, the semiconductor device described above preferably includes a fifth conductive layer and a connecting electrode. In this case, the first slit preferably extends in a first direction. The third conductive layer preferably extends inside the first slit in the first direction. The fifth conductive layer is preferably located on the third conductive layer and extends in a second direction intersecting the first direction. And the connecting electrode preferably connects the fifth conductive layer and the second conductive layer.

[0023] Furthermore, the semiconductor device described above preferably includes a fifth conductive layer. In this case, the first slit preferably extends in the first direction. The second conductive layer preferably extends in the first direction. Furthermore, the fifth conductive layer preferably contacts the third conductive layer and extends in a second direction intersecting the first direction.

[0024] Furthermore, the semiconductor device described above preferably includes a pair of semiconductor layers, a pair of second insulating layers, and a pair of third conductive layers. In this case, the pair of semiconductor layers, the pair of second insulating layers, and the pair of third conductive layers are all symmetrically arranged along a pair of side surfaces of the first insulating layer within the first slit.

[0025] Furthermore, in the aforementioned semiconductor device, the first conductive layer preferably has a recess in the region overlapping with the first slit. Additionally, the bottom of each of the semiconductor layer, the second insulating layer, and the third conductive layer is preferably disposed along the recess.

[0026] Furthermore, the semiconductor device described above preferably includes a sixth conductive layer. In this case, the second slit preferably reaches the sixth conductive layer. Additionally, the fourth conductive layer contacts the sixth conductive layer inside the second slit.

[0027] Furthermore, in the aforementioned semiconductor device, it is preferable that the semiconductor layer comprises a first metal oxide and the first conductive layer comprises a second metal oxide. In this case, both the first metal oxide and the second metal oxide preferably comprise In.

[0028] Furthermore, in the aforementioned semiconductor device, it is preferable that the semiconductor layer comprises a first metal oxide and the second conductive layer comprises a third metal oxide. In this case, both the first metal oxide and the third metal oxide preferably comprise In.

[0029] Furthermore, in the aforementioned semiconductor device, the fourth insulating layer preferably comprises a ferroelectric film. In this case, the ferroelectric film is preferably a film comprising hafnium oxide, zirconium oxide, or hafnium zirconium oxide.

[0030] Furthermore, in the aforementioned semiconductor device, the top surfaces of the semiconductor layer, the second insulating layer, and the third conductive layer are preferably planarized. Also, the semiconductor layer is preferably in contact with the side surface of the second conductive layer.

[0031] Invention Effects

[0032] According to one aspect of the present invention, a semiconductor device that is easily miniaturized can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of achieving high integration can be provided. Additionally, according to one aspect of the present invention, a semiconductor device with reduced wiring load can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high operating speed can be provided.

[0033] According to one aspect of the present invention, a semiconductor device, memory device, or electronic device with a novel structure can be provided. According to one aspect of the present invention, at least one of the problems in the prior art can be improved.

[0034] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the invention does not necessarily require all of the above-described effects. Note that effects other than those described above can be extracted from the description in the specification, drawings, claims, etc. Attached Figure Description

[0035] Figure 1A and Figure 1B This is an example of the structure of a semiconductor device.

[0036] Figure 2 This is an example of the structure of a semiconductor device.

[0037] Figure 3A and Figure 3B This is an example of the structure of a semiconductor device.

[0038] Figure 4 This is an example of the structure of a semiconductor device.

[0039] Figure 5 This is an example of the structure of a semiconductor device.

[0040] Figure 6A and Figure 6B This is an example of the structure of a semiconductor device.

[0041] Figure 7 This is an example of the structure of a semiconductor device.

[0042] Figure 8 This is an example of the structure of a semiconductor device.

[0043] Figure 9 This is an example of the structure of a semiconductor device.

[0044] Figure 10A and Figure 10B This is an example of the structure of a semiconductor device.

[0045] Figure 11A and Figure 11B This is an example of the structure of a semiconductor device.

[0046] Figure 12A and Figure 12B This is an example of the structure of a semiconductor device.

[0047] Figure 13A and Figure 13B This is an example of the structure of a semiconductor device.

[0048] Figure 14A and Figure 14B This is an example of the structure of a semiconductor device.

[0049] Figure 15A and Figure 15B This is an example of the structure of a semiconductor device.

[0050] Figure 16A and Figure 16B This is an example of the structure of a semiconductor device.

[0051] Figures 17A to 17CThis is a diagram illustrating an example of a semiconductor device manufacturing method.

[0052] Figures 18A to 18C This is a diagram illustrating an example of a semiconductor device manufacturing method.

[0053] Figure 19A and Figure 19B This is a diagram illustrating an example of a semiconductor device manufacturing method.

[0054] Figure 20A and Figure 20B This is a diagram illustrating an example of a semiconductor device manufacturing method.

[0055] Figure 21A and Figure 21B This is a diagram illustrating an example of a semiconductor device manufacturing method.

[0056] Figure 22A and Figure 22B This is a diagram illustrating an example of a semiconductor device manufacturing method.

[0057] Figure 23A and Figure 23B This is a diagram illustrating an example of a semiconductor device manufacturing method.

[0058] Figure 24 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0059] Figures 25A to 25H This is a diagram illustrating an example of the circuit structure of a memory cell.

[0060] Figure 26A and Figure 26B This is a three-dimensional diagram illustrating an example of the structure of a semiconductor device.

[0061] Figure 27 This is a block diagram illustrating the CPU.

[0062] Figure 28A and Figure 28B It is a 3D diagram of a semiconductor device.

[0063] Figure 29A and Figure 29B It is a 3D diagram of a semiconductor device.

[0064] Figure 30A and Figure 30B This is a structural example of an electronic component.

[0065] Figures 31A to 31C This is an example of the architecture of a mainframe computer.

[0066] Figure 32A This is an example of the structure of space equipment. Figure 32B This is an example of a storage system structure.

[0067] Figures 33A to 33C This is a structural example of the model according to the embodiment.

[0068] Figure 34 This is the result of transistor density calculation. Detailed Implementation

[0069] The embodiments will now be described with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments shown below.

[0070] Note that in the structure of the invention described below, the same symbols are used in different figures to represent the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when representing parts with the same function, the same shading lines are sometimes used without additional symbols.

[0071] Note that in the various figures described in this specification, the size of the constituent elements, the thickness of the layers, and the area are sometimes exaggerated for clarity. Therefore, the present invention is not limited to the dimensions shown in the figures.

[0072] The ordinal numbers such as "first" and "second" used in this specification are appended to avoid confusion of the constituent elements, and are not intended to limit the quantity.

[0073] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning on or off), etc. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0074] Furthermore, in cases where transistors with different polarities are used or the direction of current changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be used interchangeably.

[0075] Furthermore, in this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, and other elements with various functions.

[0076] Note that in this specification, the connection between two nodes via insulators such as the dielectric of a capacitor, the gate insulating film of a transistor, or the interlayer insulating film is not included in the "electrical connection" section.

[0077] Note that in this specification, etc., "generally consistent top surface shape" means that at least a portion of the edges of each layer in the stack overlaps. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, strictly speaking, there are cases where the edges do not overlap, such as when the upper layer is inside or outside the lower layer; in these cases, it can sometimes be said that the "generally consistent top surface shape" also applies.

[0078] Note that in this specification, the top surface shape of a constituent element refers to the outline shape of the constituent element when viewed from a plane. Furthermore, "viewed from a plane" means the view taken from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0079] Note that the directions such as "up" and "down" will be used in accordance with the directions in the accompanying drawings in the following description. However, for the sake of simplicity, the directions indicated by "up" or "down" in the specification may sometimes differ from those in the accompanying drawings. As an example, when describing the stacking order (or formation order) of laminates, etc., even if the surface of one side of the laminate (the surface to be formed, the supporting surface, the adhesive surface, the flat surface, etc.) is located on the upper side of the laminate in the accompanying drawings, there may be cases where the surface to be formed is shown as "down" and the laminate side is shown as "up".

[0080] Note that in this specification, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source and drain regions with the shortest distance. That is, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the on state. Furthermore, the channel width direction refers to a direction orthogonal to the channel length direction. In addition, depending on the structure or shape of the transistor, the channel length direction and channel width direction are sometimes not limited to one direction.

[0081] Furthermore, in this specification and other materials, the terms "film" and "layer" may be interchanged. For example, sometimes "insulating layer" and "insulating film" may be interchanged.

[0082] Furthermore, unless otherwise specified in this specification, the off-state current refers to the drain current when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the state where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, Vgs is higher than Vth).

[0083] (Implementation Method 1)

[0084] This embodiment illustrates a structural example of a semiconductor device according to one aspect of the present invention and an example of its manufacturing method. The semiconductor device shown below can be used as a storage device.

[0085] One aspect of the semiconductor device of the present invention includes a plurality of memory cells. Each memory cell includes a transistor and a memory element. As the memory element, various elements capable of holding stored data can be used, such as capacitors, variable resistors, ferroelectric elements, charge-trapping elements, and floating-gate elements.

[0086] The source and drain electrodes of the transistors included in the memory cell are located at different heights, and current flows through the semiconductor layer in the height direction. That is to say, the channel length direction has a height (vertical) component, so one aspect of the present invention can also be called VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, etc.

[0087] More specifically, a first insulating layer serving as a spacer is disposed above the lower electrode (first conductive layer) of one of the source and drain electrodes, and an upper electrode (second conductive layer) of the other of the source and drain electrodes is disposed above the first insulating layer. A slit (first slit) extending in a first direction and reaching the lower electrode is disposed in the first insulating layer. The slit has a side surface that is substantially perpendicular to the substrate surface. The semiconductor layer has a portion that contacts the upper electrode, a portion that contacts the side surface of the first insulating layer inside the slit, and a portion that contacts the lower electrode inside the slit. Furthermore, a gate insulating layer (second insulating layer) is disposed inside the slit in a manner that covers the semiconductor layer. Additionally, a gate electrode (third conductive layer) is disposed inside the slit in a manner that covers the gate insulating layer. The gate electrode is preferably disposed in a manner that fills the slit.

[0088] The capacitor included in the memory cell can be positioned below the transistor. By stacking transistors and capacitors, memory cells can be configured with high density. The capacitor can be a so-called MIM (Metal-Insulator-Metal) capacitor, which includes a dielectric material between a pair of electrodes. In this case, it is preferable to use a structure where the lower electrode of the transistor also serves as the upper electrode of the capacitor. Furthermore, the upper electrode of the transistor is preferably used as a bit line. Additionally, by using a ferroelectric material as the dielectric material included in the capacitor, a ferroelectric capacitor can be realized. Thus, a non-volatile memory device can be realized.

[0089] The capacitor has a portion located inside a slit (second slit) in a third insulating layer, which is situated below the aforementioned first insulating layer. Specifically, the capacitor includes a lower electrode (fourth conductive layer) disposed along the side and bottom surfaces inside the slit of the third insulating layer, a portion of a first conductive layer located inside the slit and serving as the upper electrode of the capacitor, and an insulating layer (fourth insulating layer) sandwiched between them and covering the lower electrode inside the slit, serving as a dielectric. By employing this three-dimensional structure instead of a parallel planar type, the capacitor achieves both large capacity and a small footprint, thereby enabling high-density storage cells.

[0090] As the semiconductor layer, metal oxides (oxide semiconductors) that exhibit semiconductor properties are preferred. For example, silicon, a typical semiconductor material, requires doping with impurities that act as donors or acceptors in order to form the source and drain regions. However, in a vertical transistor according to one aspect of the present invention, due to the difference in height between the source and drain, the channel formation region is located vertically relative to the substrate surface, making it sometimes difficult to precisely dope the semiconductor layer with impurities. On the other hand, oxide semiconductors can be well connected to the source and drain electrodes even without such impurity doping, so transistors with three-dimensional structures, such as those according to one aspect of the present invention, can be manufactured with high yield.

[0091] Here, both the upper and lower electrodes of the transistor preferably have a stacked structure with a first conductive film and a second conductive film stacked thereon. The second conductive film is in contact with the semiconductor layer. Furthermore, the second conductive film preferably comprises a conductive metal oxide (oxide conductor). Using a metal oxide in the conductive film that contacts the semiconductor layer containing the metal oxide reduces their contact resistance and lowers the wiring load, which is preferred. In particular, when the second conductive film contains the same metal element as the semiconductor layer, the contact resistance can be further reduced, which is also preferred. Specifically, the semiconductor layer and the second conductive film preferably contain one or more of In, Sn, Zn, Ga, and Ti, with In being particularly preferred. Furthermore, the first conductive film can be made of a low-resistance metal material. This reduces both the contact resistance and the wiring resistance, thereby further reducing the wiring load.

[0092] The following illustrations provide more specific examples.

[0093] [Structure Example]

[0094] Figure 1A A top view schematic diagram of semiconductor device 50 is shown. Figure 2 A perspective view of the semiconductor device 50 is shown. Furthermore, Figure 3A , Figure 3B and Figure 4 Show along Figure 1A The diagram shows cross-sectional views of cut-off lines AB, CD, and EF. Note that in... Figure 1A and Figure 2 Some components (such as insulating layers) are omitted. Furthermore, each figure shows arrows indicating intersecting X, Y, and Z directions.

[0095] Semiconductor device 50 has a structure in which a plurality of memory cells 15 are arranged in the X and Y directions. In semiconductor device 50, a conductive layer 26 serving as bit lines extends in the X direction, and a conductive layer 23 serving as word lines extends in the Y direction. Figure 2 As shown, the storage cell 15 includes a transistor 10 and a capacitor 30 below it.

[0096] Figure 1B A circuit diagram corresponding to semiconductor device 50 is shown. Figure 1B This shows multiple routing lines BL used as bit lines, multiple routing lines WL orthogonal to each bit line and used as word lines, and routing line CL. Although Figure 1B The example shown illustrates wiring CL parallel to wiring BL, but wiring CL can be parallel to wiring WL or configured in a grid pattern. Alternatively, wiring CL can also be a flat conductive film.

[0097] The memory cell 15 consists of a transistor 10 and a capacitor 30. The gate of the transistor 10 is connected to wiring WL, one of its source and drain is connected to wiring BL, and the other of its source and drain is connected to one electrode of the capacitor 30. The other electrode of the capacitor 30 is connected to wiring CL.

[0098] Wiring BL is used for writing and reading data. Wiring WL is used to control the switching on or off (conducting or de-conducting) of transistor 10, which acts as a switch. Wiring CL is used as a constant potential line connected to capacitor 30.

[0099] like Figure 2 As shown, transistor 10 and capacitor 30 are disposed on insulating layer 11 disposed on substrate (not shown). Insulating layer 11 serves as a base insulating layer.

[0100] Transistor 10 includes a semiconductor layer 21, an insulating layer 22 serving as a gate insulating layer, a conductive layer 23 serving as a gate electrode, a conductive layer 24 serving as one of a source electrode and a drain electrode, and a conductive layer 25 serving as the other of a source electrode and a drain electrode. Here, an example is shown where conductive layer 24 includes a conductive film 24a and a conductive film 24b thereon, and conductive layer 25 includes a conductive film 25a and a conductive film 25b thereon.

[0101] A capacitor 30 is disposed on a conductive layer 55, which serves as a wiring CL. The capacitor 30 includes a conductive layer 51 serving as a lower electrode, a conductive layer 24 serving as an upper electrode, and an insulating layer 52 located between them and serving as a dielectric. Thus, the conductive layer 24 preferably serves as both the lower electrode of the transistor 10 and the upper electrode of the capacitor 30. Therefore, the manufacturing process can be simplified, thereby reducing manufacturing costs. Figure 2 As shown, when the conductive layer 24 has a stacked structure of conductive film 24a and conductive film 24b, the lower conductive film 24a can be used as the upper electrode of the capacitor 30. In this case, the upper conductive film 24b can also be used as a connecting electrode connecting the conductive film 24a and the semiconductor layer 21.

[0102] A conductive layer 55 is disposed on the insulating layer 11. Although an example of a two-dimensional flat plate shape is shown here, wiring extending in the X, Y, or other directions may also be used. Alternatively, a grid-like shape combining two or more portions extending in different directions may also be used.

[0103] An insulating layer serving as a protective insulating layer may also be provided between the insulating layer 11 and the conductive layer 55. Alternatively, the insulating layer 11 may also be used as a protective insulating layer. This insulating layer has the function of preventing impurities such as hydrogen from diffusing from the insulating layer 11 or below the insulating layer 11 to the semiconductor layer 21. For example, films that are less prone to hydrogen diffusion (having hydrogen-blocking properties) compared to silicon oxide films, such as silicon nitride films, silicon oxynitride films, aluminum oxide films, magnesium oxide films, hafnium oxide films, gallium oxide films, etc., can be used. Silicon nitride films or silicon oxynitride films are particularly preferred.

[0104] In this specification, etc., "oxynitride" refers to a material in which the content of oxygen atoms is greater than the content of nitrogen atoms in its composition, while "nitrogen oxide" refers to a material in which the content of nitrogen atoms is greater than the content of oxygen atoms in its composition. For example, when described as "silicon oxynitride", it refers to a material in which the content of oxygen atoms is greater than the content of nitrogen atoms in its composition, while when described as "silicon oxynitride", it refers to a material in which the content of nitrogen atoms is greater than the content of oxygen atoms in its composition.

[0105] An insulating layer 46 is disposed on the conductive layer 55. The insulating layer 46 serves as an interlayer insulating layer. A plurality of slits 40 are provided in the insulating layer 46 to reach the conductive layer 55. The slits 40 extend in the Y direction. A plurality of capacitors 30 corresponding to a plurality of memory cells 15 arranged in the Y direction are disposed in the slits 40. The side surfaces within the slits 40 of the insulating layer 46 are preferably substantially perpendicular to the substrate surface. The height of the insulating layer 46 is preferably greater than its width in the X direction.

[0106] In this specification, two surfaces being perpendicular means that their interior angles are 80 degrees or more and 100 degrees or less. Furthermore, two surfaces being substantially perpendicular means that their interior angles are 60 degrees or more and 120 degrees or less (including perpendicularity). In this specification, two surfaces being parallel means that their interior angles are -10 degrees or more and 10 degrees or less. Furthermore, two surfaces being substantially parallel means that their interior angles are -30 degrees or more and 30 degrees or less (including parallelism).

[0107] The conductive layer 51 has a portion disposed along the side of the slit 40 of the insulating layer 46 and a portion in contact with the top surface of the conductive layer 55. The conductive layer 51 has a U-shaped recess in its cross-section parallel to the XZ plane. The insulating layer 52 has a portion disposed along the recess of the conductive layer 51, a portion in contact with the top surface of the conductive layer 51, and a portion in contact with the top surface of the insulating layer 46. The conductive layer 24 is disposed such that it fills the recess of the conductive layer 51 through the insulating layer 52. Additionally, the conductive layer 24 has a portion disposed on the insulating layer 46 through the insulating layer 52. The conductive layer 51 extends in the Y direction inside the slit 40. That is, multiple capacitors 30 located in the Y direction share the conductive layer 51. On the other hand, the conductive layer 24 is disposed in each memory cell 15.

[0108] Figure 5It shows the view from the Z direction along the parallel Figure 4 The cross-sectional view is shown when plane G of the XY plane is cut off. (See diagram below.) Figure 5 As shown, the conductive layer 51 is provided in the extending direction (Y direction) of the slit 40. Within the slit 40, the conductive films 24a are provided at equal intervals in the Y direction. Furthermore, by providing the conductive layer 51 and the insulating layer 52 along the side of the insulating layer 44 (not shown) at the end of the slit 40 in the Y direction, the conductive layer 51 and the insulating layer 52 each have an annular cross-sectional shape.

[0109] Figure 2 and Figure 3B An example is shown where the bottom of the conductive layer 51 has an arc shape (a concave surface). Furthermore, the bottoms of the insulating layer 52 and the conductive layer 24 formed along the insulating layer 52 also have an arc shape (a convex surface). Thus, by employing a structure where the conductive layer 51 forming the insulating layer 52 does not have corners, localized thinning of the insulating layer 52 can be prevented. Furthermore, by eliminating corners at the bottom of the conductive layer 51, localized concentration of the electric field can be prevented. Therefore, leakage current in the capacitor can be suppressed, thereby improving reliability.

[0110] Furthermore, an arc-shaped recess is provided on the top surface of the conductive layer 55, and the bottom of the conductive layer 51 is embedded in this recess. By adopting this structure, the contact area between the conductive layer 55 and the conductive layer 51 is increased compared to the case where the contact surface between the conductive layer 55 and the conductive layer 51 is planar, thereby reducing the contact resistance between them. The recess of the conductive layer 55 can be formed by etching a portion of the upper part of the conductive layer 55 when forming the slit 40 in the insulating layer 46.

[0111] The conductive film 24a is preferably made of a conductive material with a lower resistance than the conductive film 24b. In particular, it is preferably made of a metallic material. The conductive film 24b is preferably made of a conductive metal oxide (oxide conductor).

[0112] Using a conductive metal oxide as the conductive film 24b in contact with the semiconductor layer 21 containing the metal oxide reduces their contact resistance and thus lowers the wiring load, which is preferred. In particular, it is preferred that the contact resistance be further reduced when the conductive film 24b contains the same metal element as the semiconductor layer 21. Specifically, the semiconductor layer 21 and the conductive film 24b preferably contain one or more of In, Sn, Zn, Ga, and Ti as common elements. In particular, the semiconductor layer 21 and the conductive film 24b preferably contain In. Furthermore, by using a metal material with a lower resistance than the conductive film 24b as the conductive film 24a, both the contact resistance and the wiring resistance can be reduced, thereby further lowering the wiring load.

[0113] An insulating layer 41 is disposed above the conductive layer 24 and the insulating layer 52. The insulating layer 41 includes a strip-shaped slit 20 extending in the Y direction. The side surfaces of the slit 20 in the insulating layer 41 are preferably substantially perpendicular to the substrate surface. The height of the insulating layer 41 is preferably greater than its width in the X direction.

[0114] A conductive layer 25 is disposed on the insulating layer 41. Here, an example is shown of a laminated structure where the conductive layer 25 has a conductive film 25a and a conductive film 25b thereon. Furthermore, the conductive layer 25 is provided with a slit overlapping the slit 20, and the conductive layer 25 is separated into two parts by this slit. That is, a pair of conductive layers 25 are disposed on the insulating layer 41 such that they sandwich a slit 20. Additionally, as... Figure 2 As shown, island-shaped conductive layers 25 are arranged at equal intervals along the extension direction (Y direction) of slit 20.

[0115] The semiconductor layer 21, insulating layer 22, and conductive layer 23 include portions located within the slit 20. The semiconductor layer 21 and insulating layer 22 are disposed along the side surface of the insulating layer 41 and the top surface of the conductive layer 24 in the slit 20. In addition, the conductive layer 23 is disposed in a manner that fills the recess of the insulating layer 22.

[0116] The semiconductor layer 21 includes portions that contact the top and side surfaces of the conductive layer 25, portions that contact the side surfaces of the insulating layer 41 in the slit 20, and portions that contact the top surface of the conductive film 24b. Here, it is preferable to use the same conductive metal oxide as the conductive film 24b as one of the conductive films 25a and 25b included in the conductive layer 25. Furthermore, it is preferable to use a low-resistance metal material as the other of the conductive films 25a and 25b. By stacking a conductive film with low contact resistance to the semiconductor layer 21 and a conductive film with low wiring resistance, both the contact resistance and wiring resistance can be reduced, thereby further reducing the wiring load.

[0117] Since the semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the slit 20 of the insulating layer 41, the thickness of this portion may be reduced depending on the deposition method. For example, in deposition methods such as sputtering or plasma CVD (Chemical Vapor Deposition), the thickness of the film deposited on a surface inclined to or perpendicular to the substrate surface tends to be thinner than the thickness of the film deposited on a surface parallel to the substrate surface. On the other hand, when using deposition methods such as atomic layer deposition (ALD) or thermal CVD, a film with uniform thickness can be deposited regardless of the angle of the formed surface. For example, when the angle of the sidewall of the slit 20 of the insulating layer 41 is 75 degrees or more, 80 degrees or more, or 85 degrees or more relative to the substrate, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0118] When the conductive film 25b contains the same metal element as the semiconductor layer 21, the contact resistance can be further reduced, which is therefore preferred. Specifically, the conductive film 25b and the semiconductor layer 21 preferably contain one or more of In, Sn, Zn, Ga, and Ti as common elements. In particular, the conductive film 25b and the semiconductor layer 21 preferably contain In.

[0119] The source and drain electrodes of transistor 10 are located at different heights, so the current flowing through the semiconductor flows in the height direction. That is, the channel length direction can have a height (vertical) component, so the transistor of one embodiment of the present invention can also be called a VFET, a vertical transistor, a vertical channel transistor, etc. In the transistor 10 described above, two or more of the source electrode, semiconductor, and drain electrode can be stacked, so the occupied area can be significantly reduced compared to so-called planar transistors (also called lateral transistors, LFETs, etc.) where the semiconductor is arranged on a plane.

[0120] Furthermore, the channel length of the transistor 10 can be precisely controlled according to the thickness of the insulating layer 41 used as a spacer, thus significantly reducing channel length non-uniformity compared to planar transistors. Moreover, by thinning the insulating layer 41, transistors with extremely short channel lengths can be manufactured. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less but greater than 5 nm, 7 nm or more, or 10 nm or more can be manufactured. Thus, transistors with extremely small channel lengths that cannot be achieved with mass production exposure equipment can be realized. Furthermore, transistors with channel lengths less than 10 nm can be achieved without the very expensive exposure equipment used in state-of-the-art LSI technology.

[0121] Semiconductor layer 21 can be made of various semiconductor materials, with oxide semiconductors, including metal oxides, being particularly preferred. By using oxide semiconductors formed under appropriate conditions, transistors with both high on-state current and extremely low off-state current can be realized at low cost. Below, unless otherwise emphasized, a structural example of using oxide semiconductors as semiconductor layer 21 will be described.

[0122] Here, Figure 2An example is shown where the top surface of the region of the conductive film 24b overlapping with the slit 20 has an arc-shaped concave portion (concave surface). Thus, inside the slit 20, the bottoms of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are respectively disposed along the concave surface of the conductive film 24b and have arc-shaped convex portions (convex surfaces). Therefore, similar to the conductive layer 51 in the capacitor 30, a structure where the electric field is not easily concentrated can be achieved. Therefore, a transistor with low leakage current and high reliability can be realized.

[0123] An insulating layer 44 serving as an interlayer insulating layer is provided covering the insulating layer 22 and the conductive layer 23. Furthermore, a conductive layer 26 serving as a bit line is provided on the insulating layer 44. A connector 27 for connecting the conductive layer 25 and the conductive layer 26 is provided within an opening in the insulating layer 44, the insulating layer 22, and the semiconductor layer 21. Thus, multiple conductive layers 25 arranged in the X direction, sandwiching the slit 20, can be connected by the conductive layer 26.

[0124] Here, an example is shown where the plug 27 passes through the conductive film 25b and contacts the conductive film 25a. Thus, by employing a structure where the low-resistance conductive film 25a contacts the plug 27, the contact resistance between them can be reduced, thereby reducing the wiring load, which is therefore preferred. Alternatively, a structure can be adopted where the bottom surface of the plug 27 contacts the conductive film 25b or contacts the semiconductor layer 21.

[0125] Here, the conductive layer 51 extends in the Y direction, so the conductive layer 55 does not necessarily need to cover the entire bottom surface of the conductive layer 51. Figure 6A and Figure 6B In this configuration, the conductive layer 55 extending in the X direction is disposed only near the end of the slit 40, and the conductive layer 55 is connected to the plurality of conductive layers 51 disposed in each slit 40. Figure 6A and Figure 6B They correspond to respectively Figure 1A The diagram shows cross-sectional views of cut lines AB and EF. In this case, conductive layer 51 is used as wiring extending in the Y direction, and conductive layer 55 is used as wiring extending in the X direction. In all memory cells 15, conductive layer 51 is connected to conductive layer 55 near the end of slit 40.

[0126] An insulating layer 35 is provided on the insulating layer 11, and an insulating layer 46 is provided on the insulating layer 35. The slit 40 is provided in such a way that it reaches the insulating layer 35. A recess is formed in the insulating layer 35 that overlaps with the slit 40. The conductive layer 51 is in contact with the top surface of the insulating layer 35 at the bottom of the slit 40.

[0127] like Figure 6BAs shown, a conductive layer 55 is disposed at the end of the slit 40 (the end in the Y direction). The conductive layer 55 is located between the insulating layer 35 and the insulating layer 46. Furthermore, a portion of the conductive layer 55 overlaps with the slit 40. Therefore, the conductive layer 51 and the conductive layer 55 are in contact within the slit 40.

[0128] Here, Figure 6A and Figure 6B An example is shown where the insulating layer 41 has a stacked structure in which insulating layers 41a, 41b and 41c are stacked sequentially from one side of the insulating layer 52.

[0129] The semiconductor layer 21 is disposed in contact with the inner wall of the slit 20 within the insulating layer 41. The insulating layer 41b is preferably made of an oxide insulating film. In particular, an oxide insulating film that releases oxygen upon heating is preferred. Furthermore, the insulating layer 41b is preferably sandwiched between the oxygen-barrier insulating layers 41a and 41c. This confines the oxygen in the insulating layer 41b within the region surrounded by the insulating layers 41a, 41c, and the semiconductor layer 21. It also prevents the oxygen in the insulating layer 41b from escaping and diminishing during processing. Consequently, oxygen can be supplied to the semiconductor layer 21 more efficiently.

[0130] The portion of semiconductor layer 21 that contacts insulating layer 41b is a region where oxygen vacancies are reduced, which can be considered an i-type region. On the other hand, the portion that does not contact insulating layer 41b is preferably an n-type region containing multiple charge carriers. That is, the portion of semiconductor layer 21 that contacts insulating layer 41b can be referred to as a channel formation region, and the region outside it can be referred to as a low-resistance region (also called a source region or drain region).

[0131] Since the insulating layer 41b is in contact with the semiconductor layer 21, it is preferably a film that contains as little hydrogen as possible. Oxygen vacancies in the semiconductor layer 21 bond with hydrogen to generate charge carriers, which can sometimes affect, for example, the threshold voltage of the transistor 10. Therefore, an insulating film other than an oxide insulating film, which is not easily diffused by hydrogen, can also be used as the insulating layer 41b. For example, a single layer of an insulating film that blocks hydrogen and oxygen can also be used as the insulating layer 41.

[0132] The insulating layer 41b can be used as an interlayer insulating film. For example, deposition methods such as sputtering or plasma CVD are preferred. In particular, when using sputtering, hydrogen is not required as the deposition gas, thereby achieving a film with extremely low hydrogen content. This suppresses the supply of hydrogen to the semiconductor layer 21, thus stabilizing the electrical characteristics of the transistor 10.

[0133] Since the insulating layer 41b contacts the channel formation region of the semiconductor layer 21, an oxide insulating film is preferably used. In particular, an oxide insulating film that releases oxygen upon heating is preferred. As the insulating layer 41b, the oxide insulating film described above, which can be used as a gate insulating layer, can be used.

[0134] Furthermore, since insulating layer 41b is used as an interlayer insulating layer, a deposition method that can be used to deposit it at a higher deposition rate than other insulating layers is preferred. For example, as insulating layer 41, an insulating film formed using plasma CVD and TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) can also be used. This can improve the yield.

[0135] The insulating layers 41a and 41c are preferably made of films that are not easily diffused by hydrogen. By sandwiching the insulating layer 41b between the upper and lower parts of the insulating layer 41b by the insulating layers 41a and 41c, which are not easily diffused by hydrogen, hydrogen can be prevented from mixing into the insulating layer 41b that is in contact with the semiconductor layer 21 from the outside.

[0136] As insulating layers 41a and 41c, one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used, for example. In particular, silicon nitride and silicon oxynitride have the characteristics of releasing very few impurities (such as water and hydrogen) and not easily allowing oxygen and hydrogen to permeate, so they can be suitably used as insulating layers 41a and 41c.

[0137] Furthermore, an insulating layer 32 is provided between the side of the insulating layer 46 and the conductive layer 51 within the slit 40. The insulating layer 32 serves as a barrier film to prevent the diffusion of impurities such as hydrogen. For example, when a ferroelectric material is used as the insulating layer 52 in the capacitor 30, the crystallinity decreases when impurities (typically hydrogen) are introduced, and sometimes the ferroelectricity decreases. Therefore, by providing an insulating layer 32, which serves as a barrier film, between the insulating layer 46, which serves as an interlayer insulating film, and the capacitor 30, a ferroelectric capacitor with good electrical characteristics can be realized.

[0138] As a barrier film to prevent the diffusion of hydrogen and the like, films that are less susceptible to hydrogen diffusion (and have hydrogen-blocking properties) compared to silicon oxide films can be used, such as silicon nitride films, silicon oxynitride films, aluminum oxide films, magnesium oxide films, hafnium oxide films, gallium oxide films, etc. Silicon nitride films or silicon oxynitride films are particularly preferred.

[0139] Furthermore, as the insulating layer 32, it is preferable to laminate the aforementioned insulating film used as a barrier film and an insulating film with hydrogen trapping or fixing function on one side of the insulating layer 52 of the insulating film. Thus, due to heat or other factors applied during the manufacturing process of the transistor 10 or the memory cell 15, hydrogen can be trapped or fixed by the insulating film, thereby reducing the hydrogen concentration contained in the insulating layer 52. This allows for the realization of a memory cell 15 with good electrical characteristics and high reliability. Hafnium oxide film, hafnium silicate film, alumina film, hafnium zirconium oxide film, etc., are preferably used as the insulating film for trapping or fixing hydrogen.

[0140] Here, the material used as a ferroelectric material for the insulating layer 52 that can be used in the capacitor 30 will be described.

[0141] Examples of materials exhibiting ferroelectric properties include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, materials containing Group IIIa elements are preferred. For example, materials containing scandium, yttrium, and one or more lanthanide elements are preferred. In particular, yttrium, lanthanum, or scandium are easier to process and have high affinity for semiconductor manufacturing processes, thus being preferred. Adding these elements not only ensures stable ferroelectricity but also suppresses characteristic degradation during repeated rewriting, thereby improving reliability. Furthermore, it improves the withstand voltage of the insulating layer 52. For example, these elements are preferably added at a ratio of 0.5 at% to 10 at%. Other additive elements include silicon, aluminum, gadolinium, and scandium. In addition to materials exhibiting ferroelectricity, materials exhibiting antiferroelectricity can also be used for the insulating layer 52.

[0142] Oxides containing one or both of hafnium and zirconium tend to exhibit ferroelectricity even when formed into extremely thin films using thin film deposition methods such as sputtering and atomic layer deposition. Therefore, they have high affinity with semiconductor manufacturing processes and can reduce manufacturing costs.

[0143] In addition, piezoelectric ceramics with perovskite structures, such as barium titanate, lead titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), and bismuth ferrite (BFO), can also be used as the insulating layer 52.

[0144] Alternatively, organic ferroelectric materials such as polyvinylidene fluoride (PVDF) or copolymers of polyvinylidene fluoride (VDF) and trifluoroethylene (TrFE) can also be used as the insulating layer 52.

[0145] Furthermore, as a material exhibiting ferroelectric properties, a mixture or compound formed from a plurality of materials selected from the above-mentioned materials can be used, for example. Alternatively, the insulating layer 52 may have a laminated structure composed of a plurality of materials selected from the above-mentioned materials.

[0146] Among these, hafnium oxide, materials containing hafnium oxide and zirconium oxide (HZO), and materials containing yttrium in HZO (HZYO) are preferred as materials exhibiting ferroelectricity, because even thin films of a few nm exhibit ferroelectricity. When using films containing hafnium oxide, HZO, or HZYO, the thickness of the insulating layer 52 can be 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 3 nm or more and 20 nm or less, and even more preferably 4 nm or more and 10 nm or less.

[0147] Furthermore, when hafnium zirconium oxide (HfZrO) is used as a material exhibiting ferroelectric properties... X When X is a real number greater than 0, ALD method is preferred, and thermal ALD method is particularly preferred for deposition. In addition, ALD method (including thermal ALD method) that utilizes plasma to enhance reactivity is preferred (PEALD method: Plasma Enhanced ALD).

[0148] Furthermore, when using the thermal ALD method, materials containing organometallic compounds can be used as precursors. For example, when using hafnium zirconium oxide, tetra(ethylmethylamide)hafnium (TEMAHf) can be used as a hafnium-containing precursor, and tetra(ethylmethylamide)zirconium (TEMAZr) and other organometallic compounds can be used as zirconium-containing precursors. Alternatively, materials that do not contain hydrocarbons (also known as hydrocarbon carbons) can be used. For example, chlorine-based materials can be used as hydrocarbon-free precursors. Note that when using hafnium zirconium oxide, chlorine-based precursors such as HfCl4 and ZrCl4 can be used as precursors.

[0149] Note that when oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide are used as the insulating layer 52, the residual polarization can sometimes be increased by including an appropriate amount of carbon. In this case, these elements are preferably added at a ratio of 0.5 at% to 10 at%.

[0150] In addition, when using hafnium zirconium oxide in insulating layer 52, it is preferable to alternately deposit hafnium and zirconium with a 1:1 composition using thermal ALD or plasma ALD.

[0151] Furthermore, H2O or O3 can be used as the oxidant in thermal ALD or plasma-based ALD processes. However, the oxidant is not limited to these; O2, O3, N2O, NO2, H2O, H2O2, etc., or two or more of the above materials can be used. In particular, O2 or O3 is preferred as the oxidant to reduce the hydrogen and nitrogen concentrations in the membrane, and O3 is especially preferred.

[0152] The hydrogen concentration in the film used for insulating layer 52 is preferably low. This prevents hydrogen from diffusing from insulating layer 52 to semiconductor layer 21, thus preventing an increase in carrier concentration in semiconductor layer 21. Specifically, the hydrogen concentration in the film is preferably 5 × 10⁻⁶. 20 atoms / cm 3 Hereinafter, 1×10 is more preferred. 20 atoms / cm 3 the following.

[0153] Furthermore, there are no particular restrictions on the crystalline structure of the film used for the insulating layer 52, as long as it is a crystalline structure without centrosymmetry and possessing polarity. For example, a crystal system other than cubic can be used. In addition, the film used for the insulating layer 52 can have a single-crystal structure or a polycrystalline structure, or it can have a composite structure including amorphous and crystalline structures.

[0154] The conductive layer 51 and conductive film 24a, which are in contact with or near the insulating layer 52, are preferably made of conductive materials that have the function of absorbing oxygen. This allows oxygen to be absorbed from the insulating layer 52, thereby increasing the oxygen vacancy concentration in the insulating layer 52. Therefore, the remanent polarization of the insulating layer 52 can be increased. Metals or alloys are preferably used as conductive materials with the function of absorbing oxygen. In particular, tungsten, molybdenum, titanium, tantalum, etc., are preferred. Furthermore, from a stress point of view, tungsten readily increases the remanent polarization of the insulating layer 52, and is therefore particularly preferred.

[0155] Furthermore, conductive layer 51 and conductive film 24a are preferably made of conductive materials that do not readily diffuse with oxygen. This improves the withstand voltage of insulating layer 52, thereby enhancing the rewrite durability of the ferroelectric capacitor. In particular, nitride metals such as titanium nitride and tantalum nitride are preferably used.

[0156] The conductive film 24a may also have a multilayer structure. In this case, it is preferable to use a low-resistance conductive material on the side that does not contact the insulating layer 52. For example, a metal or alloy containing one or more of the following can be used: aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. In particular, when using high-melting-point materials such as tungsten, molybdenum, tantalum, ruthenium, and hafnium, the temperature of the subsequent heat treatment can be increased, which is preferred. In addition to the low-resistance conductive materials mentioned above, oxide materials such as indium tin oxide, silicon-added indium tin oxide, indium zinc oxide, and indium gallium zinc oxide can also be used.

[0157] Here, the above shows an example where slit 20 and slit 40 extend in the same direction (here, the Y direction), but slit 20 and slit 40 can also extend in different directions. Figure 7 An example is shown when slit 40 extends in the Y direction, which intersects the X direction.

[0158] By employing this structure, even with the reduction in minimum processing size due to the improvement in the performance of the exposure apparatus, the capacitance of capacitor 30 can remain constant. Therefore, it is not necessary to increase the depth of slit 40 to maintain the capacitance, thereby suppressing the decrease in yield. This is because the capacitance of capacitor 30 depends on the width in the X direction of the portion located within slit 40 of conductive film 24a, which is limited by the width of slit 20. The width of slit 20 is limited by the width (thickness) in the X direction of the semiconductor layer 21, insulating layer 22, and conductive layer 23 disposed inside slit 20. Therefore, even when the minimum processing size is reduced, the width of slit 20 remains at a predetermined size, and thus the capacitance of capacitor 30 can also be maintained in the same way.

[0159] Here, the semiconductor device 50 preferably has a layer on which the memory cell 15 is stacked and a layer on which the functional circuit is disposed. The functional circuit may include, for example, an arithmetic circuit, a power supply circuit, etc., in addition to a drive circuit for driving the memory cell 15. The drive circuit may include, for example, one or more of a row decoder, column decoder, row driver, column driver, input circuit, output circuit, and sense amplifier. This reduces the footprint of the semiconductor chip including the semiconductor device 50, and compared to arranging the functional circuit and the memory cell 15 in a single configuration, shortens the wiring length, thereby enabling high-speed operation and low power consumption.

[0160] Figure 8 An example is shown of a layer 80 on which memory cells 15 are disposed and a transistor 90 constituting a functional circuit disposed below the layer 80. Here, an example is shown where one of the source electrode and drain electrode of the transistor 90 is connected to a conductive layer 26 serving as a bit line.

[0161] Transistor 90 is a transistor whose channel is formed in a portion of substrate 91, which is a single-crystal semiconductor substrate. Substrate 91 can typically be single-crystal silicon. Alternatively, substrate 91 can be a semiconductor composed of a single element such as germanium, or a compound semiconductor composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, gallium nitride, etc. Alternatively, substrate 91 can also be a semiconductor substrate having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.

[0162] Transistor 90 is disposed on substrate 91 and includes a conductive layer 94 serving as a gate, an insulating layer 93 serving as a gate insulating layer, a semiconductor region 92 formed by a portion of substrate 91, and low-resistance regions 95a and 95b serving as source or drain regions. Transistor 90 can be a p-channel transistor or an n-channel transistor. A device separation layer 98 is disposed in substrate 91 between two adjacent transistors 90.

[0163] In transistor 90, the semiconductor region 92 forming the channel has a convex shape (fin shape). Additionally, although in Figure 8 Not shown in the diagram, but a conductive layer 94 is provided in the Y direction such that it covers the sides and top surface of the semiconductor region 92 through an insulating layer 93. This transistor 90 is also called a FIN-type transistor.

[0164] An insulating layer 96 is provided to cover the transistor 90. An insulating layer 86 and an insulating layer 87 are provided on the insulating layer 96. A conductive layer 81 is embedded in the insulating layer 87. An insulating layer 88 is provided to cover the conductive layer 81 and the insulating layer 87. An insulating layer 45 and an insulating layer 11 are provided on the insulating layer 45. A connector 82 is provided inside the openings in the insulating layers 96 and 86, through which the conductive layer 81 is connected to the low-resistance region 95b. A conductive layer 84 is provided on the insulating layer 45, and is connected to the conductive layer 81 through connectors 83 provided inside the openings in the insulating layers 45 and 88. The conductive layer 84 and the conductive layer 26 are connected through connectors 85 inside the openings in the insulating layers between them. Thus, one of the source and drain terminals of the transistor 90 is connected to the conductive layer 26.

[0165] Note that although an example of a conductive layer 81 being provided as a wiring layer is shown here, a structure in which interlayer insulating layers and wiring layers are alternately stacked between the layer where transistors 90 are provided and the layer 80 where memory cells 15 are provided (also known as a multilayer wiring layer) can also be adopted.

[0166] Here, in the region outside the memory cell array including memory cells 15 or outside the functional circuit including transistors 90, each insulating layer constituting layer 80 is etched to provide an insulating layer 47 that covers its top and side surfaces. The insulating layer 47 is in contact with the top surface of the insulating layer 45. Thus, all memory cells 15 included in layer 80 can be surrounded by the insulating layers 47 and 45.

[0167] The insulating layers 45 and 47 may use the aforementioned hydrogen-barrier films. Silicon nitride films or silicon oxynitride films are particularly preferred.

[0168] Furthermore, insulating layer 45 and insulating layer 47 preferably have a laminated structure in which the insulating film used as a barrier film is stacked with an insulating film on its inner side (on the side of transistor 10) that has the function of trapping or fixing hydrogen. For example, hafnium oxide film, hafnium silicate film, aluminum oxide film, hafnium zirconium oxide film, etc. are preferably used.

[0169] This suppresses hydrogen diffusion from the outside into the region surrounded by insulating layers 45 and 47, and reduces the hydrogen concentration contained within. Consequently, the amount of hydrogen that could potentially diffuse into the semiconductor layer 21 of the transistor 10 can be effectively reduced, thereby enabling a highly reliable transistor 10.

[0170] Figure 9 An example is shown when a layer 80, including storage cells 15, is stacked. Although Figure 9 An example of a three-layer stacked layer 80 (layers 80[1] to 80[3] stacked from one side of substrate 91) is shown, but it may also be two or four or more layers.

[0171] Connector 85 connects conductive layer 84 to conductive layer 26 included in layer 80[1]. Additionally, connector 89 connects the conductive layers 26 included in the two layers 80 to each other. Thus, the three conductive layers 26 included in layers 80[1] to 80[3] are connected to one of the source and drain of transistor 90.

[0172] The insulating layer 47 is provided around layers 80[1] to 80[3]. Note that it is not limited to this, and a structure in which the insulating layer 47 is provided in each layer 80 may also be adopted.

[0173] Note that although a structure in which the layer 80 is directly stacked on the substrate 91 where the transistor 90 is disposed is shown here, it is not limited to this. For example, the substrate 91 where the transistor 90 is disposed may be bonded to the substrate where the memory cell 15 is disposed. For example, the two substrates may be bonded by direct bonding (hybrid bonding) using a direct bonding technology represented by Cu-Cu bonding. Alternatively, two or more layers may be bonded in such a way that the insulating films are in contact with each other, and then through electrodes are formed to connect the electrodes disposed in each layer. In particular, by using direct bonding or through electrodes, the spacing between the connecting electrodes can be made extremely small, thereby allowing a large number of connecting electrodes to be disposed at high density, which increases the amount of data transmitted between layers, and is therefore preferred.

[0174] When bonding two layers, any of the following can be used: CoC (Chip on Chip), CoW (Chip on Wafer), and WoW (Wafer on Wafer). While WoW bonding offers high productivity by bringing wafers together, it can sometimes reduce yield due to bonding a mixture of good and defective chips. On the other hand, CoW bonding (bonding chips to wafers) and CoC bonding (bonding chips together) have lower productivity than WoW bonding, but they significantly improve yield by bonding good chips together. Furthermore, although CoC bonding has lower productivity than the other two bonding methods, it is highly versatile because it can bond even layers with significantly different dimensions.

[0175] Alternatively, wiring layers such as interposers can be placed between two layers. This eliminates the need for alignment of electrode positions in adjacent layers, increasing design freedom for each layer and enabling higher-performance semiconductor devices.

[0176] [Regarding the constituent elements]

[0177] <Substrate>

[0178] Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can also be used. Furthermore, examples of insulating substrates with conductive or semiconductor layers, semiconductor substrates with conductive or insulating layers, and conductive substrates with semiconductor or insulating layers can also be used. Alternatively, substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements (including transistors), light-emitting elements, and memory elements.

[0179] <Semiconductor layer> Semiconductor layer 21 preferably comprises metal oxide (oxide semiconductor).

[0180] Examples of metal oxides that can be used in semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. Furthermore, the metal oxide preferably contains two or three elements selected from In, element M, and Zn. Note that element M is a metallic or half-metallic element with a high bond energy with oxygen, such as a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specific examples of element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Note that metal oxides containing In, M, and Zn are sometimes referred to below as In-M-Zn oxides. Note that in this specification, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification may sometimes include half-metallic elements.

[0181] When using In-M-Zn oxides as metal oxides, the atomic ratio of In in the In-M-Zn oxide is preferably greater than or equal to the atomic ratio of M. Examples of such atomic ratios of the metal elements in In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions close to these. Note that "close to" includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in metal oxides, the on-state current or field-effect mobility of transistors can be improved.

[0182] In In-M-Zn oxides, the atomic ratio of In can also be less than the atomic ratio of element M. For example, examples of such In-M-Zn oxides include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or compositions close to these ratios. By increasing the atomic ratio of M in the metal oxide, the formation of oxygen vacancies can be suppressed.

[0183] The semiconductor layer 21 can be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, etc. Additionally, Ga-Zn oxide can also be used. Using a Zn-free material such as indium oxide improves the affinity with the LSI manufacturing process, making it preferred. On the other hand, using a Zn-containing material easily improves crystallinity, making it preferred as well.

[0184] Note that metal oxides can also replace indium or contain one or more metals with high period numbers in the periodic table besides indium. The greater the overlap of the orbitals of the metal element, the greater the carrier conduction in the metal oxide. Therefore, including metals with high period numbers can sometimes improve the field-effect mobility of transistors. Examples of metals with high period numbers include those belonging to period 5 and period 6. Specific examples of such metals include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0185] Furthermore, metal oxides can also contain one or more non-metallic elements. The inclusion of non-metallic elements in metal oxides can sometimes improve the field-effect mobility of transistors. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0186] Metal oxides can be formed appropriately using sputtering or atomic layer deposition (ALD). In particular, ALD is preferred for depositing metal oxides due to its excellent coverage. Note that when metal oxides are formed using sputtering, the composition of the deposited metal oxide sometimes differs from that of the target material. In particular, the zinc content in the deposited metal oxide sometimes decreases to about 50% of the zinc content in the target material.

[0187] In this specification, the content of a certain metal element in a metal oxide refers to the proportion of the number of atoms of that element relative to the total number of atoms of the metal element contained in the metal oxide. For example, in a metal oxide containing metal elements X, Y, and Z, the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A. X A Y A ZWhen the content of metallic element X is such that it can be expressed as A, the percentage of X in the composition of metal can be expressed as A. X / (A X +A Y +A Z Furthermore, when the ratio of the number of atoms of metal elements X, Y, and Z in a metal oxide (atomic ratio) is expressed as B... X B Y B Z When the content of metallic element X is such that B is used, the percentage of X can be expressed as B. X / (B) X +B Y +B Z ).

[0188] For example, when using metal oxides containing In, transistors with high on-state current can be achieved by increasing the In content.

[0189] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability under forward bias can be realized. That is, a transistor with small fluctuations in the threshold voltage during PBTS (Positive Bias Temperature Stress) testing can be achieved. Furthermore, when using a Ga-containing metal oxide, the Ga content is preferably lower than the In content. Thus, a transistor with both high mobility and high reliability can be realized.

[0190] On the other hand, by increasing the Ga content, transistors with high reliability for light can be achieved. In other words, transistors with small threshold voltage variations during NBTIS (Negative Bias Temperature Illumination Stress) testing can be realized. Specifically, metal oxides with a higher Ga atomic number than those with a higher In atomic number have a larger band gap, which reduces the threshold voltage variation during NBTIS testing of the transistor.

[0191] Furthermore, by increasing the zinc content to create a highly crystalline metal oxide, the diffusion of impurities in the metal oxide can be suppressed. This suppresses variations in the electrical characteristics of the transistor, thereby improving reliability.

[0192] Semiconductor layer 21 may also have a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers included in semiconductor layer 21 may be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs. Note that a stacked structure of two or more oxide semiconductor layers with different compositions can also be used. Furthermore, by utilizing the ALD method, a metal oxide layer with a composition that continuously varies in the thickness direction can be formed. Therefore, compared to using a film with a predetermined composition, not only can the range of design choices be expanded, but the generation of interface states, etc., between two layers with different compositions can also be prevented, thus improving electrical characteristics and reliability. Furthermore, a metal oxide layer with a stacked structure can be formed using both sputtering and ALD methods.

[0193] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (high conductivity) than the first layer in the second layer, i.e., the layer closest to the gate electrode. This allows for the formation of a normally-off transistor with a large on-state current. Therefore, both low power consumption and high performance can be achieved. Alternatively, a material with higher mobility than the second layer can be used in the first layer, i.e., the layer in contact with the source and drain electrodes. This reduces the contact resistance between the semiconductor layer 21 and the source or drain electrode, thereby reducing parasitic resistance and enabling the formation of a transistor with a large on-state current.

[0194] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material in the second layer with a higher mobility than that in the first and third layers. This allows for the realization of transistors with high on-state current and high reliability.

[0195] For example, the aforementioned mobility or conductivity can be replaced by the indium content. In addition, the following factors also affect mobility and conductivity: the presence or content of elements other than indium that contribute to improved conductivity. Examples of high-mobility materials include those with an In:Ga:Zn ratio of 4:3:2 or similar, In:Zn ratio of 1:1 or similar, In:Zn ratio of 2:1 or similar, In:Zn ratio of 4:1 or similar, and In:Sn:Zn ratio of 40:X:10 (where X is 0.1 or higher and 5 or lower, typically X=1) or similar. On the other hand, materials with lower mobility or conductivity than the aforementioned materials include those with an atomic ratio of 1:3:2 or similar, In:Ga:Zn = 1:3:4 or similar, In:Ga:Zn = 2:2:1 or similar, In:Ga:Zn = 1:1:1 or similar, and In:Ga:Zn = 1:1:2 or similar.

[0196] A crystalline metal oxide layer is preferably used as the semiconductor layer 21. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a nano-crystal (nc: nano-crystal) structure, etc., as described later, can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect state density in the semiconductor layer 21 can be reduced, thereby enabling a highly reliable semiconductor device.

[0197] The higher the crystallinity of the metal oxide layer used for semiconductor layer 21, the lower the defect state density in semiconductor layer 21 can be. On the other hand, by using a metal oxide layer with low crystallinity, transistors capable of carrying large currents can be realized.

[0198] Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have a very high field-effect mobility. Furthermore, the leakage current between the source and drain of an OS transistor in the off-state (hereinafter also called off-state current) is extremely low, allowing it to retain the charge stored in the capacitor connected in series with the transistor for extended periods. Additionally, the power consumption of semiconductor devices can be reduced by using OS transistors.

[0199] A semiconductor device according to one aspect of the present invention can be applied, for example, to processors, memory devices, or various ICs. A transistor according to one aspect of the present invention has the characteristics of being able to carry large currents and having extremely low off-state currents, thus enabling both high-speed circuit operation and low power consumption.

[0200] One aspect of the semiconductor device of the present invention can also be applied to a display device. When increasing the luminous brightness of the light-emitting device included in the pixel circuit of a display device, it is necessary to increase the current flowing through the light-emitting device. For this purpose, it is necessary to increase the source-drain voltage of the driving transistor included in the pixel circuit. Because the source-drain breakdown voltage of an OS transistor is higher than that of a silicon transistor (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, the current flowing through the light-emitting device can be increased, thereby improving the luminous brightness of the light-emitting device.

[0201] When operating in the saturation region, OS transistors, compared to Si transistors, allow for smaller changes in source-drain current in response to variations in the gate-source voltage. Therefore, by using OS transistors as driving transistors within pixel circuits, the amount of current flowing through the light-emitting device can be precisely controlled. This, in turn, increases the grayscale of the pixel circuit. Furthermore, a stable current can flow even when variations or inhomogeneities occur in the electrical characteristics of the light-emitting device (e.g., resistance).

[0202] As described above, by using OS transistors as driving transistors included in pixel circuits, it is possible to achieve "suppression of black blur", "increase in luminous brightness", "multi-grayscale conversion", and "suppression of the effects of manufacturing non-uniformity of light-emitting devices".

[0203] OS transistors exhibit minimal changes in electrical characteristics due to radiation exposure, meaning they possess high radiation tolerance and can therefore be appropriately used in environments where radiation exposure is possible. OS transistors can also be described as having high reliability against radiation. For example, OS transistors can be appropriately used as pixel circuits in X-ray flat panel detectors. Furthermore, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0204] Note that the semiconductor material that can be used in semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors composed of a single element or compound semiconductors can be used. Examples of semiconductors composed of a single element include silicon (including monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) or germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, or oxide semiconductors. Note that these semiconductor materials may also contain impurities as dopants.

[0205] Alternatively, semiconductor layer 21 may also have a layered material that serves as a semiconductor. Layered materials are a general term for materials with a layered crystalline structure. A layered crystalline structure is a structure formed by layers of covalent or ionic bonds stacked together through bonds weaker than covalent and ionic bonds, such as van der Waals bonds. Layered materials exhibit high conductivity per unit layer, i.e., high two-dimensional conductivity. By using a material with high two-dimensional conductivity, intended to be used as a semiconductor, in the channel formation region, transistors with large on-state currents can be provided.

[0206] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (elements belonging to Group 16). Furthermore, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0207] There are no particular restrictions on the crystallinity of the semiconductor material used for semiconductor layer 21; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystals (polycrystalline semiconductors, microcrystalline semiconductors, or semiconductors in which a portion has crystalline regions) can be used. When using a crystalline semiconductor, the degradation of transistor characteristics can be suppressed, so it is preferred.

[0208] <Gate insulating layer>

[0209] The insulating layer 22 is used as the gate insulating layer of the transistor. When an oxide semiconductor is used for the semiconductor layer 21, an oxide insulating film is preferably used as the film in the insulating layer 22 that is at least in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga-Zn oxide can be used as the insulating layer 22. In addition, nitride insulating films such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride can also be used as the insulating layer 22. Furthermore, the insulating layer 22 can also have a stacked structure, for example, it can also have a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0210] Furthermore, the insulating layer 22 is preferably used by laminating an insulating material composed of a high-k material, and preferably uses a laminate structure of a material with a high relative permittivity (high-k) and a material with a dielectric strength greater than that high-k material. For example, as the insulating layer 22, an insulating film (also known as ZAZ) sequentially laminated with zirconium oxide, alumina, and zirconium oxide can be used. Alternatively, an insulating film (also known as ZAZA) sequentially laminated with zirconium oxide, alumina, zirconium oxide, and alumina can be used. Furthermore, an insulating film sequentially laminated with hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina can be used. By using an insulator with high dielectric strength, such as alumina, the dielectric strength can be increased, thereby suppressing electrostatic discharge damage to the capacitor.

[0211] Furthermore, ferroelectric materials can also be used as the insulating layer 22. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO. X (X is a real number greater than 0) and other metal oxides. Alternatively, HfZrO can also be used. X Metal oxides with added Y (yttrium). This was achieved through the addition of Y to HfZrO. X Adding Y can improve ferroelectricity.

[0212] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film with hydrogen trapping or fixing function as the film in contact with the semiconductor layer 21, and an insulating film that blocks hydrogen as the film located on the side of the conductive layer 23 used as the gate electrode. This suppresses hydrogen diffusion from the conductive layer 23 side to the semiconductor layer 21, thereby enabling a highly reliable transistor.

[0213] Hafnium oxide films, hafnium silicate films, and aluminum oxide films are preferred as insulating films for capturing or fixing hydrogen. Furthermore, silicon nitride films, silicon oxynitride films, aluminum oxide films, magnesium oxide films, hafnium oxide films, and gallium oxide films are preferred as insulating films that block hydrogen.

[0214] Alternatively, an insulating film that releases oxygen upon heating can be used as a film in contact with the semiconductor layer 21, and an insulating film that blocks hydrogen can be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen upon heating can be used as a film in contact with the semiconductor layer 21, and an insulating film that traps or fixes hydrogen can be used as a film located on the conductive layer 23 side.

[0215] When the insulating layer 22 has a three-layer structure, it is preferable that the insulating film in contact with the semiconductor layer 21 is made of a material that readily diffuses oxygen, the insulating film on one side of the conductive layer 23 is made of a material that blocks hydrogen and oxygen, and the insulating film between them is made of a material that traps or fixes hydrogen. Silicon oxide or silicon oxynitride can be used as the material that readily diffuses oxygen. With this structure, oxygen can be supplied to the semiconductor layer 21 from the film in contact with it. Furthermore, the film on one side of the conductive layer 23 prevents oxygen from diffusing to that side, thus suppressing oxidation of the conductive layer 23.

[0216] As an insulating film that blocks oxygen, aluminum oxide film, silicon nitride film, hafnium oxide film, hafnium silicate film, etc. are preferred. As an insulating film that blocks both oxygen and hydrogen, aluminum oxide film, silicon nitride film, hafnium oxide film, etc. are preferred.

[0217] When the insulating layer 22 has a four-layer structure, an insulating film that blocks oxygen is used as the film in contact with the semiconductor layer 21. Then, from the side closest to the semiconductor layer 21, an insulating film made of a material that allows oxygen to diffuse easily, an insulating film that traps or fixes hydrogen, and an insulating film that blocks both hydrogen and oxygen are used respectively. That is, a structure can be adopted that adds a film in contact with the semiconductor layer 21 in addition to the above three-layer structure. By using an insulating film that blocks oxygen as the film in contact with the semiconductor layer 21, oxygen can be suppressed from escaping from the semiconductor layer 21. In this case, an alumina film is preferably used as the film in contact with the semiconductor layer 21. Alumina not only blocks oxygen but also traps or fixes hydrogen, thus preventing hydrogen diffusion into the semiconductor layer 21.

[0218] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, by setting the thickness of the insulating layer 22 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also known as the S-value) of the transistor can be reduced. In addition, the thickness of each insulating film is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, even more preferably 0.5 nm or more and 5 nm or less, even more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less.

[0219] As a specific example, a four-layer structure is preferably adopted in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked sequentially from one side of the semiconductor layer 21, and their thicknesses are set to 1nm, 2nm, 2nm, and 1nm from one side of the semiconductor layer 21.

[0220] Note that in this specification, etc., barrier properties refer to the property that the corresponding substance does not easily diffuse (or, in other words, the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Furthermore, hydrogen, referred to as the corresponding substance, includes, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel-forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc.

[0221] Here, by surrounding a transistor using a metal oxide film with an insulating film that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. The insulating film that suppresses the permeation of impurities and oxygen can be, for example, a single layer or a stack of insulating films selected from one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the material used for the insulating film that suppresses the permeation of impurities and oxygen can be metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0222] Specifically, materials for insulating films that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, materials for insulating films that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include, for example, oxides containing aluminum and hafnium (hafnium aluminate). Additionally, materials for insulating films that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include, for example, nitrides such as aluminum nitride, titanium aluminum nitride, silicon oxynitride, and silicon nitride.

[0223] Materials used as insulating films with the function of trapping or fixing hydrogen include metal oxides such as hafnium oxides, magnesium oxides, aluminum oxides, and oxides containing both aluminum and hafnium (hafnium aluminate). Furthermore, these metal oxides may also contain zirconium; for example, oxides containing both hafnium and zirconium can be cited. In metal oxides with amorphous structures, the ability to trap or fix hydrogen is high because some oxygen atoms have dangling bonds. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure can be achieved by including silicon in these oxides. For example, oxides containing both hafnium and silicon (hafnium silicate) are preferred. Note that sometimes metal oxides have one or both of a crystalline region and a grain boundary in a portion of their structure.

[0224] <Conductive Layer> Conductive layers 24 and 25 are in contact with the semiconductor layer 21. Here, when an oxide semiconductor is used as the semiconductor layer 21, there is a concern that if a metal that is easily oxidized, such as aluminum, is used for the portion of conductive layer 24 or conductive layer 25 that contacts the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may form between the conductive layer 24 or conductive layer 25 and the semiconductor layer 21, hindering conduction between them. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductive material for at least the portion of conductive layer 24 and conductive layer 25 that contacts the semiconductor layer 21.

[0225] The conductive film in contact with the semiconductor layer 21 is preferably made of materials such as titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. These materials are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even when oxidized.

[0226] In addition, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. In particular, conductive oxides containing indium have high conductivity and are therefore preferred. Furthermore, oxide materials such as In-Ga-Zn oxide, which can be applied to the aforementioned semiconductor layer 21, can also be used in the conductive layer by increasing the carrier concentration.

[0227] For example, conductive layers 24 and 25 can be either a single-layer structure of the conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked sequentially, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on a tungsten film, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the conductive oxide film, or a two-layer structure in which the conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0228] The conductive layer 23 is used as the gate electrode and various conductive materials can be used. For example, the conductive layer 23 preferably uses a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing that metal element. Alternatively, nitrides or oxides of the aforementioned metals or alloys can be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferred. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used.

[0229] Alternatively, the conductive layer 23 may also use the nitrides and oxides that are applicable to the conductive layers 24 and 25 as described above.

[0230] Conductive layers 23, 24, and 25 are also used for wiring, and therefore preferably are made of low-resistance conductive materials. For example, conductive films 24a and 25b can also be made of low-resistance conductive materials that are suitable for conductive layer 23.

[0231] <Insulating layer>

[0232] The insulating layer 41 can be used as an interlayer insulating film. For example, deposition methods such as sputtering or plasma CVD are preferred. In particular, when using sputtering, hydrogen is not required as the deposition gas, thereby achieving a film with extremely low hydrogen content. This suppresses the supply of hydrogen to the semiconductor layer 21, thus stabilizing the electrical characteristics of the transistor 10.

[0233] Since the insulating layer 41 contacts the channel formation region of the semiconductor layer 21, an oxide insulating film is preferably used. In particular, an oxide insulating film that releases oxygen upon heating is preferred. As the insulating layer 41, the oxide insulating film described above, which can be used as a gate insulating layer, can be used.

[0234] Furthermore, since insulating layer 41 is used as an interlayer insulating layer, it is preferable to use a deposition method that can be deposited at a higher deposition rate than other insulating layers. For example, as insulating layer 41, a silicon oxide film (also known as a TEOS film) deposited using plasma CVD and TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) can also be used. This can improve the yield.

[0235] Insulating layers 11, 35, 42, 44, 46, and 47 are all used as interlayer insulating layers. Insulating layers 11, 35, 42, 44, 46, and 47 can be made of insulating materials suitable for insulating layer 41.

[0236] The insulating layer 52 serves as the dielectric of the capacitor 30. The same insulating material as the insulating layer 22 described above can be used as the insulating layer 52. Furthermore, by using the aforementioned ferroelectric material as the insulating layer 52, the capacitor 30 can be used as a ferroelectric capacitor, thereby realizing a non-volatile storage device. Additionally, the capacitor 30 can also be a resistance-changing type storage element that utilizes the colossal electro-resistance (CER) effect induced by an electric field.

[0237] The above is an explanation of the constituent elements.

[0238] [Example of variation]

[0239] Below are examples where a portion of the structure differs from the examples described above. Note that the same symbols are used for parts that are repeated above, and explanations are omitted.

[0240] [Example 1 of the variation]

[0241] Figure 10A and Figure 10B The following diagrams show cross-sectional and three-dimensional views of the semiconductor device. Figure 10A and Figure 10B The main difference between the structure shown and the above-described structural example is the shape of the top of each of the semiconductor layer 21, the insulating layer 22 and the conductive layer 23; and the former includes the insulating layer 43.

[0242] The upper portions of semiconductor layer 21, insulating layer 22, and conductive layer 23 are planarized, and the height of their top surfaces (e.g., their height from the substrate surface) is approximately the same. Furthermore, the height of the top surfaces of semiconductor layer 21, insulating layer 22, and conductive layer 23 is approximately the same as the height of the top surface of conductive layer 25 (specifically, conductive film 25b). By employing this structure, conductive layer 25 does not overlap with conductive layer 23 when viewed from a planar perspective, thereby reducing the parasitic capacitance between conductive layer 25 and conductive layer 23. This enables the realization of a semiconductor device capable of high-speed operation.

[0243] An insulating layer 43 is provided in contact with the top surface of the conductive layer 25, the top surface of the semiconductor layer 21, the top surface of the insulating layer 22, and the top surface of the conductive layer 23. The insulating layer 43 functions as a barrier film to prevent impurities such as hydrogen from diffusing from above into the semiconductor layer 21. For example, films that are less prone to hydrogen diffusion (have hydrogen-blocking properties) compared to silicon oxide films, such as silicon nitride films, silicon oxynitride films, aluminum oxide films, magnesium oxide films, hafnium oxide films, and gallium oxide films, can be used. Silicon nitride films or silicon oxynitride films are particularly preferred.

[0244] Furthermore, as the insulating layer 43, it is preferable to laminate the aforementioned insulating film used as a barrier film and an insulating film with the function of trapping or fixing hydrogen on the semiconductor layer 21 side of the insulating film. Thus, due to heat or other factors applied during the manufacturing process of the transistor 10 or memory cell 15, hydrogen that would diffuse into the semiconductor layer 21 can be trapped or fixed by the insulating film, thereby reducing the hydrogen concentration contained in the semiconductor layer 21. Therefore, a transistor 10 or semiconductor device 50 with good electrical characteristics and high reliability can be realized. Hafnium oxide film, hafnium silicate film, alumina film, hafnium zirconium oxide film, etc., are preferably used as the insulating film for trapping or fixing hydrogen.

[0245] An insulating layer 44, which serves as an interlayer insulating film, is provided on the insulating layer 43. If it is not required, the insulating layer 44 may be omitted.

[0246] A conductive layer 26 serving as a bit line is provided on the insulating layer 44. Additionally, a plug 27 is provided to connect the conductive layer 25 and the conductive layer 26 through openings provided in the insulating layers 44 and 43. Thus, multiple conductive layers 25 arranged in the X direction, sandwiching the slit 20, can be connected by the conductive layer 26.

[0247] [Example 2]

[0248] Figure 11A and Figure 11B The main difference between the structure shown and the example above is that the extension directions of the word lines and bit lines are reversed.

[0249] The conductive layer 23 is processed into an island shape and connected to the conductive layer 29 located above it and used as a word line. The conductive layer 29 extends in the X direction. On the other hand, the conductive layer 25 extends in the same direction as the slit 20, i.e., in the Y direction. The conductive layer 25 is used as a bit line.

[0250] An insulating layer 44 is disposed on the insulating layer 41, and a portion of the conductive layer 23 is embedded in the insulating layer 44. Furthermore, the top surface of the conductive layer 23 is planarized, and the height of the substrate surface is approximately the same as the height of the top surface of the insulating layer 44. In addition, a conductive layer 29 is disposed on the conductive layer 23 and the insulating layer 44.

[0251] Furthermore, the top surface shapes of the insulating layer 22 and the semiconductor layer 21 are substantially the same as those of the conductive layer 23. For example, the insulating layer 22 and the semiconductor layer 21 can be processed using the same etching mask as the conductive layer 23.

[0252] In addition, an insulating layer 43 is provided between each of the semiconductor layer 21, the insulating layer 22, the conductive layer 23, the conductive layer 25, and the insulating layer 41 and the insulating layer 44. By providing the insulating layer 43, impurities such as hydrogen can be prevented from diffusing from the insulating layer 44 to the semiconductor layer 21.

[0253] [Example 3]

[0254] Figure 12A and Figure 12B The main difference between the structure shown and the modified example 2 above is that two transistors (transistor 10a) are arranged in a slit 20 in the former.

[0255] Semiconductor layer 21, insulating layer 22, conductive layer 23, and conductive layer 24 are separated into two within the slit 20 along its extension direction. Semiconductor layer 21 and insulating layer 22 are disposed along one of a pair of side surfaces within the slit 20 of insulating layer 41. That is, a pair of semiconductor layers 21, a pair of insulating layers 22, and a pair of conductive layers 23 are symmetrically disposed within the slit 20 along a pair of side surfaces of insulating layer 41.

[0256] Each of the separated pair of conductive layers 24 is provided with a capacitor 30. This allows two memory cells 15 to share a single slit 20. In this case, two slits 40 are provided within one slit 20. The slits 40 are positioned offset in the X direction relative to the center of the slit 20.

[0257] Additionally, an insulating layer 48 is provided along the side surfaces of the conductive layer 23, insulating layer 22, semiconductor layer 21, and conductive layer 24, and the top surface of the insulating layer 52. A recess is formed on the top surface of the insulating layer 48, and an insulating layer 44a is provided on the insulating layer 48 to fill this recess. The insulating layer 44a can be made of the same material as the insulating layer 44. The insulating layer 48 is preferably used as an impurity barrier film, similar to the insulating layer 43. This prevents impurities such as hydrogen contained in the insulating layer 44a from diffusing into the semiconductor layer 21.

[0258] [Example 4]

[0259] Figure 13A and Figure 13B The main difference between the structure shown and the modified example 3 above is that, in the former, two capacitors (capacitor 30a) are provided in a slit 40.

[0260] Within the slit 40, the conductive film 24a is divided into two. An insulating layer 46a is provided to fill the gap between the two conductive films 24a within the slit 40. The insulating layer 48 is disposed in contact with a portion of the conductive film 24a and the top surface of the insulating layer 46a, but not in contact with the insulating layer 52.

[0261] By adopting this structure, two memory cells 15 can share slits 20 and 40. Thus, compared with the structure shown in FIG11, memory cells 15 can be integrated at a higher density.

[0262] [Example 5]

[0263] Figure 14A and Figure 14B The structure shown is an example of applying the structure of placing two transistors in the slit 20 shown in the above modified example 3 to the structure shown in the above structural example.

[0264] Two transistors 10b are disposed within a slit 20. A pair of conductive layers 23 disposed within the slit 20 extend in the Y direction and are used as word lines. In addition, a conductive layer 26 extending in the X direction is used as a bit line.

[0265] Insulating layer 48 is provided such that it covers the sides and top surface of conductive layer 23 and the top surface of insulating layer 22. Insulating layer 44 is provided such that it covers insulating layer 48. A portion of insulating layer 44 is provided such that it fills the gap between a pair of conductive layers 23.

[0266] also, Figure 15A and Figure 15B An example is shown where the structure shown in the above structural example is applied to the structure shown in the above modified example 4, in which two capacitors 30a are provided in the slit 40. Figure 15A and Figure 15B The structure shown includes a pair of capacitors 30a sharing a common slit 40 and a pair of transistors 10b sharing a common slit 20.

[0267] [Example 6]

[0268] Figure 16A and Figure 16B The structure shown is an example of transistor 10 and capacitor 30b arranged side by side.

[0269] Transistor 10 has the same structure as the example described above. In addition, capacitor 30b is disposed in insulating layers 44, 22, 43 and 41 (insulating layers 41c, 41b, 41a) and is located inside the slit 40a leading to conductive layer 24.

[0270] Capacitor 30b includes a conductive layer 51, an insulating layer 52, and a conductive layer 53. The conductive layer 53 is used as wiring extending in the Y direction (e.g., wiring CL). Figure 16B As shown, within the slit 40a, the conductive layer 51 is divided according to each capacitor. The conductive layer 51 contacts the conductive layer 24 at the bottom of the slit 40a. One conductive layer 51 and one conductive layer 24 are disposed in each memory cell 15.

[0271] Insulating layer 52 is provided to cover insulating layer 44. Furthermore, insulating layer 33 is provided to cover insulating layer 52 and conductive layer 53, and insulating layer 49 is provided on insulating layer 33. Conductive layer 26 is provided on insulating layer 49, and conductive layer 26 is connected to conductive layer 25 (conductive film 25a) via connector 27. Insulating layer 33, like insulating layer 43, serves as a barrier film. Insulating layer 49, like insulating layer 44, serves as an interlayer insulating film. By providing insulating layer 33, impurities such as hydrogen contained in insulating layer 49 can be prevented from diffusing to semiconductor layer 21.

[0272] By adopting this structure, transistor 10 and capacitor 30b can share some components, thus reducing manufacturing costs compared to a structure that stacks transistors and capacitors.

[0273] The above is an explanation of the examples of the variations.

[0274] [Example of manufacturing method]

[0275] The following describes an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. Here, a semiconductor device including the memory cell 15 illustrated in the above structural example will be used as an example for description.

[0276] Note that the thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition, and other methods.

[0277] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, and doctor blade coating.

[0278] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is preferred for deposition using insulating targets. DC sputtering is primarily used when depositing conductive targets. Furthermore, conductive films can be formed during DC sputtering, and insulating films can be formed during reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0279] CVD methods can be categorized into plasma-enhanced chemical vapor deposition (PECVD), thermal CVD (TCVD), and photochemical CVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0280] By utilizing plasma-enhanced CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because plasma is not used in thermal CVD, plasma damage to the workpiece is reduced. Additionally, since no plasma damage occurs during deposition in thermal CVD, films with fewer defects can be obtained.

[0281] As ALD methods, there are thermal ALD methods that use only thermal energy to react the precursors and reactants, and PEALD methods that use reactants excited by plasma.

[0282] Unlike sputtering, CVD and ALD are deposition methods with good step coverage and are less affected by the shape of the substrate. In particular, ALD offers excellent step coverage and thickness uniformity, making it suitable for forming films covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0283] When using CVD (Continuous Chemical Deposition), films of arbitrary composition can be deposited based on the source gas flow rate ratio. For example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. Since the time required for transfer or pressure adjustment is eliminated when deposition is performed simultaneously with changing the source gas flow rate ratio, deposition time can be shortened compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0284] When using the ALD method, films of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, by controlling the number of cycles for each precursor while introducing multiple different precursors, films of arbitrary composition can be deposited. Furthermore, similar to the CVD method, films with continuously varying compositions can be deposited.

[0285] When processing thin films constituting semiconductor devices, photolithography and other methods can be used. Besides these methods, nanoimprint lithography, sandblasting, and lift-off methods can also be used to process thin films. Furthermore, island-shaped thin films can be directly formed using deposition methods that utilize metal masks or similar masking techniques.

[0286] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, processing the film through etching, and then removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to process the film into the desired shape.

[0287] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these rays. Alternatively, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can be employed. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Electron beams can also be used instead of the light used for exposure. When using EUV light, X-rays, or electron beams, extremely fine processing can be achieved, making them preferred. Additionally, when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0288] For thin film etching, dry etching, wet etching, sandblasting, and other methods can be used.

[0289] Figures 17A to 23B These are cross-sectional schematic diagrams corresponding to each step in the manufacturing method illustrated below. The left side of the dashed line in each figure shows the corresponding... Figure 3A The cross section, with the right side of the dotted line showing the corresponding section. Figure 3B The cross section.

[0290] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0291] As a substrate, a substrate with heat resistance that can withstand the degree of subsequent heat treatment can be used.

[0292] As the insulating layer 11, inorganic insulating films such as silicon oxide films and silicon oxynitride films can be used. The deposition of the insulating layer 11 can be performed using sputtering, CVD, MBE, PLD, ALD, etc. If the surface on which the insulating layer 11 is formed is not flat, it is preferable to perform planarization treatment after depositing the insulating layer 11 to make the top surface of the insulating layer 11 flat.

[0293] Next, a conductive film, which will become the conductive layer 55, is deposited on the insulating layer 11. The conductive film can be formed by deposition methods such as sputtering, ALD, or CVD. Then, a photoresist mask is formed on the conductive film, and unwanted portions of the conductive film are removed by etching, thereby forming the conductive layer 55. The conductive layer 55 can have a plate-like, linear, or lattice-like shape.

[0294] Next, after depositing an insulating film covering the conductive layer 55, planarization can be performed until the top surface of the conductive layer 55 is exposed. This allows the conductive layer 55 to be embedded within an insulating layer (not shown). Note that an example of forming an insulating layer (not shown) after the conductive layer 55 is shown here; however, it is also possible to deposit a conductive film that will become the conductive layer 55 after depositing the insulating film and forming openings (or recesses) in the insulating film for embedding the conductive layer 55, and then perform planarization until the surface of the insulating film is exposed, thereby forming the conductive layer 55 and the insulating layer. Planarization can be performed, for example, using CMP (Chemical Mechanical Polishing), dry etching, etc.

[0295] Next, an insulating layer 46 is formed on the conductive layer 55. Figure 17A The insulating layer 46 is preferably formed using deposition methods such as sputtering, ALD, or CVD.

[0296] Note that, without embedding the conductive layer 55 within an insulating layer (not shown), after forming the insulating layer 46, it is possible to form an uneven shape reflecting the shape of the conductive layer 55 on the top surface of the insulating layer 46. In this case, it is preferable to planarize the top surface of the insulating layer 46.

[0297] Next, a slit 40 is formed in the insulating layer 46 to reach the conductive layer 55. Figure 17B At this time, a portion of the top surface of the conductive layer 55 is sometimes etched. In this case, it is preferable to etch in a manner that forms a curved surface on the upper part of the conductive layer 55.

[0298] Next, a conductive film 51f, which will become the conductive layer 51, is deposited in a manner that covers the top surface of the insulating layer 46, the side surface of the insulating layer 46 within the slit 40, and the top surface of the conductive layer 55. Figure 17C The conductive film 51f can be deposited using methods such as CVD, ALD, and sputtering. From the viewpoint of coverage, formation by CVD is particularly preferred.

[0299] A sacrificial layer is formed on the conductive film in such a way that it covers the recess of the slit 40, and planarization is performed until the top surface of the insulating layer 46 is exposed. The sacrificial layer is then removed, thereby forming a conductive layer 51 located only inside the slit 40. Figure 18A ).

[0300] Here, during planarization or removal of the sacrificial layer, the height of the top surface of the conductive layer 51 is sometimes lower than the top surface of the insulating layer 46. In addition, sometimes the corners of the upper end of the conductive layer 51 and the upper end of the slit 40 in the insulating layer 46 are rounded off.

[0301] Next, an insulating layer 52 is formed along the surface of the insulating layer 46 and the conductive layer 51. The insulating layer 52 can be formed by deposition methods such as sputtering, ALD, and CVD, but ALD is preferred from the viewpoint of coverage. Next, a conductive film 24af, which will become a conductive film 24a, is deposited on the insulating layer 52 in a recessed manner within the slit 40 of the insulating layer 46. Then, the top surface of the conductive film 24af can be planarized as needed. Next, a conductive film 24bf, which will become a conductive film 24b, is deposited on the conductive film 24af. Figure 18B The conductive films 24af and 24bf can be formed by deposition methods such as sputtering, ALD, and CVD.

[0302] Next, a photoresist mask is formed on the conductive film 24bf, and unwanted portions of each conductive film are removed by etching, thereby forming a conductive layer 24 including conductive films 24a and 24b. Figure 18C At this point, capacitor 30 can be formed.

[0303] Next, an insulating layer 41 is formed by covering the conductive layer 24, and its top surface is planarized. The insulating layer 41 can be formed using deposition methods such as sputtering, ALD, and CVD.

[0304] The insulating layer 41 is preferably an oxide film containing oxygen to the extent that oxygen is released upon heating and has a low hydrogen content. The insulating layer 41 can be deposited using deposition methods such as PECVD, sputtering, and ALD, with sputtering being particularly preferred. In particular, by depositing the insulating layer 41 using an oxygen-containing gas instead of a hydrogen-containing gas, an insulating film with extremely low hydrogen content and excess oxygen can be deposited. By depositing the insulating layer 41 in this way, oxygen can be supplied from the insulating layer 41 to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0305] Next, heat treatment can be performed. The heat treatment can be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. Furthermore, the heat treatment can be performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing heat treatment in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio can be set to approximately 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the released oxygen, it can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above-described heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 can be reduced before the deposition of the oxide semiconductor film, which will become the semiconductor layer.

[0306] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content of the gas used in the heat treatment is 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulating layer 41 can be prevented as much as possible.

[0307] After the insulating layer 41 is deposited, an oxygen supply process is performed. Thus, oxygen can be supplied from the insulating layer 41 to the semiconductor film 21f by heat or the like applied after the semiconductor film 21f is formed.

[0308] Examples of oxygen supply methods include heating treatment in an oxygen-containing atmosphere or plasma treatment (including microwave plasma) in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method. The deposited oxide film can be removed immediately or remain as a residue. Furthermore, the oxygen-containing atmosphere includes, in addition to oxygen gas (O2), atmospheres containing oxygen-containing compounds such as ozone (O3) and nitrous oxide (N2O).

[0309] Next, conductive film 25af, which will become conductive film 25a, and conductive film 25bf, which will become conductive film 25b, are stacked on insulating layer 41. Figure 19A The conductive films 25af and 25bf can be formed by deposition methods such as sputtering, ALD, and CVD.

[0310] Next, a photoresist mask is formed on the conductive film 25bf to remove unwanted portions of each conductive film, thereby forming conductive films 25a and 25b. Then, a conductive film that will become the insulating layer 42 is formed, and planarization is performed until the top surface of the conductive film 25b is exposed, thereby forming the insulating layer 42. Figure 19B Therefore, conductive films 25a and 25b can be embedded in the insulating layer 42.

[0311] Note that if it is not needed, the insulation layer 42 can be omitted.

[0312] Next, a photoresist mask is formed on the conductive film 25b and the insulating layer 42, and slits 20 are formed in the conductive film 25b, the conductive film 25a, the insulating layer 42, and the insulating layer 41. Figure 20A When forming the slit 20, it is preferable to etch a portion of the conductive film 24a located at the bottom of the slit 20 to form a recess in the conductive film 24b. At this time, it is preferable to etch in a manner that forms a concave curved surface on the upper part of the conductive film 24a. Additionally, as... Figure 20A As shown on the right, in the portion where the conductive film 24a is not provided, it is preferable to also form a concave curved surface on the top surface of the insulating layer 41.

[0313] When forming the slit 20, it is preferable to use anisotropic dry etching to process the slit 20 in a manner in which the sidewalls of the slit 20 (the sidewalls of the conductive film 25b, conductive film 25a, insulating layer 42, and insulating layer 41) are all substantially perpendicular. In addition, depending on the processing conditions, sometimes the sidewalls of the slit 20 are inclined in a direction perpendicular to the surface being formed, thus becoming a conical shape.

[0314] Next, a semiconductor film 21f, which will become the semiconductor layer 21, is formed by covering the top and side surfaces of the conductive film 25b, the side surface of the conductive film 25a, and the side and top surfaces of the insulating layer 41. Figure 20B ).

[0315] As the semiconductor film 21f, a metal oxide (oxide semiconductor) film with semiconductor properties can be used. When depositing this metal oxide film, sputtering, CVD, MBE, PLD, ALD, and other methods can be appropriately employed. Here, the metal oxide film is preferably formed in contact with a side surface that is substantially perpendicular to the insulating layer 41. Therefore, when depositing this metal oxide film, a deposition method with good coverage is preferred, and the ALD method is more preferably employed.

[0316] The metal oxide film preferably has crystallinity. In one aspect of the invention, the metal oxide film particularly preferably comprises a metal oxide having a CAAC structure.

[0317] During or after the deposition of a metal oxide film, it is preferable to perform a treatment to improve the crystallinity of the metal oxide film. Examples of such treatments include heat treatment, plasma treatment, microwave treatment (typically 2.45 GHz), microwave plasma treatment, and light (e.g., ultraviolet light) irradiation. Note that multiple treatments can be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment can be performed simultaneously. Alternatively, microwave plasma treatment can be performed after heat treatment.

[0318] Furthermore, it is more preferable to perform multiple treatments to improve the crystallinity of the metal oxide film during deposition. For example, when forming a metal oxide film by the ALD method, it is preferable to perform microwave plasma treatment after each atomic layer is formed. Alternatively, it is preferable to perform treatments to improve crystallinity after each metal oxide film with a predetermined thickness is formed, as this can improve productivity. Specifically, it is preferable to form a first metal oxide film of 1 nm or more and 10 nm or less and perform a first microwave plasma treatment, and then form a second metal oxide film of 1 nm or more and 10 nm or less and perform a second microwave plasma treatment.

[0319] Note that there are no particular limitations on the deposition methods for the first and second metal oxide films; either ALD (Alternating Deposition) or sputtering can be used. In particular, depositing the first metal oxide film using ALD prevents elements constituting the layer forming the surface from mixing into both the first and second metal oxide films (also known as mixing). This is especially suitable when the element in the layer forming the surface blocks the crystallization of the metal oxide (e.g., when it contains silicon, carbon, etc.). Furthermore, the first and second metal oxide films can have different compositions. While a stacked structure of the first and second metal oxide films is shown here, the method is not limited to this. The same treatment can be applied when the metal oxide films have a single-layer structure or a stacked structure of three or more layers.

[0320] Furthermore, treatments to improve the crystallinity of metal oxide films can be performed after the deposition of the metal oxide film. Specifically, this treatment can be performed directly on the deposited metal oxide film or on a film separated from it by other films, such as an insulating film deposited on the metal oxide film. For example, microwave plasma treatment can be performed after the deposition of the metal oxide film, or an insulating film (e.g., silicon nitride film, silicon oxide film, aluminum oxide film, etc.) can be deposited after the deposition of the metal oxide film, and then the metal oxide film can be subjected to heat treatment or microwave plasma treatment on the film separated from it.

[0321] Note that the above-described treatment to improve the crystallinity of metal oxide films can also be used to remove impurities from the metal oxide films. For example, carbon, hydrogen, nitrogen, etc., can be appropriately removed from the metal oxide films. Alternatively, by performing the treatment to improve the crystallinity of the metal oxide films under an oxygen gas atmosphere, oxygen vacancies in the metal oxide films can be reduced.

[0322] When performing a process to improve the crystallinity of a metal oxide film, it is preferable to set the heat treatment temperature (or substrate temperature) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0323] By increasing the crystallinity of metal oxide films, transistors with high reliability can be achieved.

[0324] Metal oxide films can be formed, for example, by sputtering using a metal oxide target.

[0325] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film, wherein impurities such as hydrogen and water are minimized. In particular, a crystalline metal oxide film is preferred as the metal oxide film.

[0326] When depositing metal oxide films, oxygen gas and inert gases (e.g., helium, argon, xenon, etc.) can also be mixed. Note that the higher the proportion of oxygen gas in the overall deposition gas (hereinafter also referred to as the oxygen flow ratio) during metal oxide film deposition, the higher the crystallinity of the metal oxide film can be, enabling the realization of transistors with high reliability. Conversely, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, enabling the realization of transistors with high on-state current.

[0327] When the substrate temperature is high during the deposition of metal oxide films, a denser metal oxide film with higher crystallinity can be formed. On the other hand, when the substrate temperature is low, a metal oxide film with lower crystallinity and higher conductivity can be formed.

[0328] The metal oxide film is deposited at a substrate temperature above room temperature and below 250°C, preferably above room temperature and below 200°C, and more preferably above room temperature and below 140°C. For example, the substrate temperature is preferably above room temperature and below 140°C, which improves productivity. When the metal oxide film is deposited at a substrate temperature of room temperature or without intentional heating, crystallinity can be reduced.

[0329] When using the ALD method, thermal ALD or PEALD deposition methods are preferred. Thermal ALD has extremely high step coverage, so it is preferred. In addition, PEALD not only has high step coverage but also allows for low-temperature deposition, so it is also preferred.

[0330] For example, when using a metal oxide for semiconductor layer 21, a precursor containing the metal element constituting the metal oxide and an oxidant can be deposited using the ALD method.

[0331] For example, when depositing In-Ga-Zn oxide, three precursors can be used: one containing indium, one containing gallium, and one containing zinc. Alternatively, two precursors can be used: one containing indium and one containing both gallium and zinc.

[0332] As indium-containing precursors, trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, etc. can be used.

[0333] In addition, as gallium-containing precursors, trimethylgallium, triethylgallium, tris(dimethylamide)gallium(III), gallium(III)acetylacetone, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)gallium, dimethylgallium chloride, diethylgallium chloride, gallium(III) chloride, etc. can be used.

[0334] In addition, zinc-containing precursors such as dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptadecanoic acid) zinc, and zinc chloride can be used.

[0335] As an oxidant, ozone, oxygen, water, etc. can be used, for example.

[0336] Methods for controlling the composition of the resulting membrane include adjusting the flow rate ratio of the source gas, the time the source gas flows through, and the order in which the source gas flows through. By adjusting these parameters, membranes with continuously varying compositions can be deposited. Furthermore, two or more membranes with different compositions can be deposited consecutively.

[0337] After depositing the metal oxide film, a heat treatment is preferably performed. The heat treatment can be performed within a temperature range that does not cause polycrystalline formation of the metal oxide film, preferably between 250°C and 650°C, and more preferably between 400°C and 600°C. Furthermore, the heat treatment can be performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm, 1%, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio can be set to approximately 20%. Additionally, the heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the released oxygen, in an atmosphere containing 10 ppm, 1%, or 10% or more of an oxidizing gas.

[0338] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content of the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the metal oxide film can be prevented as much as possible.

[0339] In the accompanying drawings, the semiconductor film 21f has a single-layer structure, but it can also have a multilayer structure. For example, it can have a two-layer structure formed by ALD, a three-layer structure formed by ALD, a two-layer structure where the first layer is formed by ALD and the second layer is formed by sputtering, or a three-layer structure where the first layer is formed by ALD, the second layer is formed by sputtering, and the third layer is formed by either ALD or sputtering. Forming the first layer by ALD can suppress mixing, so it is preferred, but it can also be formed by sputtering. Furthermore, the semiconductor film 21f can also have a multilayer structure with four or more layers.

[0340] Next, a photoresist mask is formed on the semiconductor film 21f. At this time, in order to suppress uneven thickness of the photoresist mask, an organic or inorganic material formed by a coating method can be placed between the photoresist mask and the semiconductor film 21f as a planarization film filling the slits 20. More specifically, coating-type insulating films such as SOC (Spin On Carbon) films and SOG (Spin On Glass) films can be used.

[0341] Next, the portion of the semiconductor film 21f not covered by the resist mask is removed by etching, and then the resist mask is removed, thereby forming the semiconductor layer 21. Figure 21AIn the etching of semiconductor layer 21, since it is difficult to remove the portion in contact with the side of insulating layer 41 when only anisotropic dry etching is performed, it is preferable to combine isotropic dry etching or wet etching. Alternatively, the area of ​​semiconductor film 21f not covered by the resist mask may be pre-treated to degrade a portion of semiconductor film 21f to facilitate etching. Examples of such treatments include plasma treatment, doping (including ion implantation), and wet treatment.

[0342] Next, an insulating layer 22 is formed in such a way that it covers the semiconductor layer 21 and the insulating layer 41. Figure 21B The insulating layer 22 can be formed using deposition methods such as sputtering, ALD, and CVD. The insulating layer 22 is preferably formed on the surface of the vertical portion of the semiconductor layer 21 with the most uniform thickness possible. Therefore, it is particularly preferred to form the insulating layer 22 using the ALD method, which is a deposition method with excellent coverage. Note that when the sidewalls of the insulating layer 41 have a tapered shape, the insulating layer 22 can be deposited using deposition methods such as sputtering and CVD.

[0343] Next, a conductive film 23f, which will later become the conductive layer 23, is deposited in a manner that covers the insulating layer 22. Figure 22A The conductive film 23f can be formed using methods such as CVD, ALD, and sputtering. From the viewpoint of coverage, formation by CVD is particularly preferred.

[0344] Next, by etching the top of the conductive film 23f without using a photomask until the top surface of the insulating layer 22 is exposed, a conductive layer 23 embedded inside the slit 20 can be formed. Figure 22B ).

[0345] At this time, it is preferable to process the conductive film 23f such that the top surface of the conductive layer 23 is above the bottom surface of the conductive film 25a. When the height of the top surface of the conductive layer 23 is lower than the height of the bottom surface of the conductive film 25a, a so-called bias region in the semiconductor layer 21 is formed where no gate electric field is applied. On the other hand, when the height of the top surface of the conductive layer 23 is higher than the bottom surface of the conductive layer 25a, no bias region is formed, and thus a transistor with high on-state current can be realized.

[0346] Transistor 10 can be formed at this time.

[0347] Next, an insulating layer 44 is formed by covering the conductive film 25b, the semiconductor layer 21, the insulating layer 22, and the conductive layer 23. Figure 23A The insulating layer 44 can be formed using methods such as CVD, ALD, and sputtering.

[0348] Next, an opening leading to the conductive film 25a is formed in the insulating layer 44, the insulating layer 22, the semiconductor layer 21, and the conductive film 25b. Then, a conductive film filling the opening is deposited until the top surface of the insulating layer 44 is exposed, and a planarization process is performed, thereby forming the plug 27.

[0349] Next, a conductive film is deposited on the insulating layer 44 and the plug 27, and unwanted parts are removed by etching, thereby forming the conductive layer 26. Figure 23B ).

[0350] Through the above-described process, a semiconductor device including a memory cell 15 having a transistor 10 and a capacitor 30 can be manufactured.

[0351] The above is an explanation of examples of manufacturing methods.

[0352] (Implementation Method 2)

[0353] In this embodiment, a semiconductor device 900 according to one aspect of the present invention, different from the embodiments described above, is described. The semiconductor device 900 can be used as a storage device.

[0354] Figure 24 This is a block diagram illustrating a structural example of a semiconductor device 900. Figure 24 The semiconductor device 900 shown includes a driving circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Figure 24 An example of a memory array 920 including multiple memory cells 950 configured in a matrix is ​​shown.

[0355] As storage unit 950, the above-described embodiment can be used.

[0356] Examples include storage unit 15.

[0357] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and peripheral circuit 915. The peripheral circuit 915 includes peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0358] In the semiconductor device 900, the aforementioned circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0359] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Alternatively, signals PON1 and PON2 can also be generated in the control circuit 912.

[0360] The control circuit 912 is a logic circuit that controls the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 to execute the aforementioned operating mode.

[0361] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 928. For example, when a signal of level H is applied as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0362] The peripheral circuit 911 is used to write and read data from the storage unit 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0363] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row specified by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0364] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data written to memory cell 950 (Din). The data read from memory cell 950 by column driver 924 (Dout) is output to output circuit 926. Output circuit 926 has the function of holding Dout. In addition, output circuit 926 has the function of outputting Dout to the outside of semiconductor device 900. The data output from output circuit 926 is signal RDA.

[0365] PSW931 controls the supply of VDD to the peripheral circuit 915. PSW932 controls the supply of VHM to the row driver 923. Here, the high supply voltage of the semiconductor device 900 is VDD, and the low supply voltage is GND (ground potential). Furthermore, VHM is a high supply voltage used to make the word line high, which is higher than VDD. Signal PON1 controls the on / off state of PSW931, and signal PON2 controls the on / off state of PSW932. Figure 24 In the peripheral circuit 915, the number of power supply domains supplied with VDD is 1, but it can also be multiple. In this case, it is preferable to set a power switch for each power supply domain.

[0366] Reference Figures 25A to 25H This section describes structural examples of other storage units that can be used in storage unit 950.

[0367] The following discussion of connecting two components includes cases where they are electrically connected via circuit elements (transistors, switches, diodes, resistors, etc.). An electrical connection refers to a state where current can flow between two components. Furthermore, when two components are connected via a switch or transistor, current can flow even when the switch or transistor is in the ON state, and therefore this is also included in the scope of an electrical connection.

[0368] [DOSRAM]

[0369] Figure 25A An example circuit structure of a DRAM (Dynamic Random Access Memory) type memory cell is shown. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 951 includes transistor M1 and capacitor CA.

[0370] Transistor M1 may also include a front gate (sometimes simply referred to as the gate) and a back gate. In this case, the back gate may also be connected to a wiring supplied with a constant potential or signal, and the front gate and the back gate may also be connected.

[0371] The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitor CA is connected to wiring CAL.

[0372] The BIL (Bite Line) is used as the bit line, and the WOL (Word Line) is used as the word line. The CAL (Chip Line) is used to apply a specified potential to the second terminal of the capacitor CA. During data writing and reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to the CAL.

[0373] Data writing and reading are performed by applying a high-level potential to the wiring WOL to turn on the transistor M1, thereby making the wiring BIL and the first terminal of the capacitor CA conductive (allowing current to flow).

[0374] Furthermore, the memory cell that can be used as memory cell 950 is not limited to memory cell 951, and the circuit structure can be changed. For example, it can also be used as... Figure 25B The structure of memory cell 952 is shown. Memory cell 952 is an example excluding capacitor CA and wiring CAL. The first terminal of transistor M1 is in a floating state.

[0375] In memory cell 952, the potential written by transistor M1 is maintained in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0376] An OS transistor is preferably used as transistor M1. OS transistors have the characteristic of extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. That is, transistor M1 can hold written data for a long time, thereby reducing the refresh frequency of the memory cell. Furthermore, the memory cell refresh operation can be omitted. In addition, due to the very low leakage current, multi-valued data or analog data can be held in memory cells 951 and 952.

[0377] [NOSRAM]

[0378] Figure 25C An example circuit structure of a gain-cell type memory cell including two transistors and one capacitor is shown. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and the like, a memory device including a gain-cell type memory cell that uses transistor OS for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0379] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; and transistor M2's gate is connected to wiring WOL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0380] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a predetermined potential to the second terminal of capacitor CB. During data writing, data holding, and data reading, it is preferable to apply a low-level potential (sometimes called the reference potential) to wiring CAL.

[0381] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M2 and thus connects wiring WBL to the first terminal of capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL to write that potential to the first terminal of capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL, which turns off transistor M2, thereby maintaining the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3.

[0382] Data is read out by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate and the second terminal of transistor M3, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0383] For example, a structure that combines the wiring WBL and wiring RBL into a single wiring BIL can also be adopted. Figure 25D An example of the circuit structure of the memory cell in this case is shown. In memory cell 954, the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. That is, memory cell 954 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0384] Figure 25E The memory cell 955 shown is an example where the capacitor CB and wiring CAL of memory cell 953 are omitted. Furthermore, Figure 25FThe memory cell 956 shown is an example of omitting the capacitor CB and wiring CAL found in memory cell 954. This structure improves the integration density of the memory cells.

[0385] Note that it is preferable to use the OS transistor as at least as transistor M2. In particular, it is preferable to use the OS transistor as both transistor M2 and transistor M3.

[0386] Because the OS transistor has extremely low off-state current, transistor M2 can hold written data for an extended period, thereby reducing the refresh frequency of the memory cells. Furthermore, the memory cell refresh operation can be omitted. Additionally, due to the very low leakage current, multi-valued or analog data can be held in memory cells 953, 954, 955, and 956.

[0387] The memory cells 953, 954, 955, and 956, which use OS transistors as transistor M2, are a type of NOSRAM.

[0388] Si transistors can also be used as transistor M3. Si transistors can improve field-effect mobility and can be p-channel transistors, thus increasing the freedom of circuit design.

[0389] Furthermore, when an OS transistor is used as transistor M3, the memory cell can be composed of only n-type transistors.

[0390] also, Figure 25G A gain-cell type memory cell 957 with three transistors and one capacitor is shown. The memory cell 957 includes transistors M4 to M6 and capacitor CC.

[0391] Transistor M4's first terminal is connected to capacitor CC's first terminal; transistor M4's second terminal is connected to wiring BIL; and transistor M4's gate is connected to wiring WOL. Capacitor CC's second terminal is connected to transistor M5's first terminal and wiring GNDL. Transistor M5's second terminal is connected to transistor M6's first terminal; transistor M5's gate is connected to capacitor CC's first terminal. Transistor M6's second terminal is connected to wiring BIL; and transistor M6's gate is connected to wiring RWL.

[0392] The BIL (Bite Line) is used as the bit line, the WOL (Write Word Line) is used as the write word line, and the RWL (Read Word Line) is used as the read word line. The GNDL (Ground Node Line) is used to supply a low-level potential.

[0393] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M4 and connects wiring BIL to the first terminal of capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to wiring BIL to write that potential to the first terminal of capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to wiring WOL, which turns off transistor M4, thereby maintaining the potential of the first terminal of capacitor CC and the potential of the gate of transistor M5.

[0394] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high-level potential to the wiring RWL. By making the wiring RWL high, transistor M6 is turned on, and the wiring BIL and the second terminal of transistor M5 are connected. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL will change correspondingly to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0395] Note that it is preferable to use the OS transistor as at least transistor M4.

[0396] Si transistors can also be used as transistors M5 and M6. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystal state of the silicon used in the semiconductor layer.

[0397] Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be composed of only n-type transistors.

[0398] [OS-SRAM]

[0399] Figure 25H An example of SRAM (Static Random Access Memory) using OS transistors is shown. In this specification, etc., SRAM using OS transistors will be referred to as OS-SRAM (Oxide Semiconductor-SRAM). Furthermore, Figure 25H The storage unit 958 shown is an SRAM-type storage unit capable of backup.

[0400] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, capacitor CD1, and capacitor CD2. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0401] Transistor M7's first terminal is connected to wiring BIL. Transistor M7's second terminal is connected to the first terminal of transistors MS1 and MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. Transistor M7's gate is connected to wiring WOL. Transistor M8's first terminal is connected to wiring BILB. Transistor M8's second terminal is connected to the first terminal of transistors MS2 and MS4, the gate of transistor MS1 and MS3, and the first terminal of transistor M9. Transistor M8's gate is connected to wiring WOL.

[0402] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0403] The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, and the gate of transistor M9 is connected to the wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, and the gate of transistor M10 is connected to the wiring BRL.

[0404] The second terminal of capacitor CD1 is connected to wiring GNDL, and the second terminal of capacitor CD2 is also connected to wiring GNDL.

[0405] The BIL and BILB wirings are used as bit lines, the WOL wiring is used as word lines, and the BRL wiring is used to control the on and off states of transistors M9 and M10.

[0406] Wiring VDL provides a high-level potential, and wiring GNDL provides a low-level potential.

[0407] Data is written by applying a high-level potential to the wiring WOL and the wiring BRL. Specifically, when transistor M10 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the second terminal side of transistor M10.

[0408] Storage cell 958 uses transistors MS1 to MS2 to form an inverter loop, so the inverted signal of the data signal corresponding to this potential is input to the second terminal of transistor M8. Since transistor M8 is in the on state, the potential applied to wiring BIL, that is, the inverted signal of the signal input to wiring BIL, is output to wiring BILB. In addition, since transistors M9 and M10 are in the on state, the potentials of the second terminals of transistor M7 and transistor M8 are maintained by the first terminals of capacitor CD2 and capacitor CD1, respectively. Then, by applying a low-level potential to wiring WOL and a low-level potential to wiring BRL to turn off transistors M7 to M10, the potentials of the first terminals of capacitor CD1 and capacitor CD2 are maintained.

[0409] The following describes the data readout process. First, the wiring BIL and wiring BILB are pre-charged to a predetermined potential. Next, a high-level potential is applied to wiring WOL and wiring BRL. At this time, the potential of the first terminal of capacitor CD1 is refreshed by the inverter loop of memory cell 958 and output to wiring BILB. Furthermore, the potential of the first terminal of capacitor CD2 is refreshed by the inverter loop of memory cell 958 and output to wiring BIL. Since wiring BIL and wiring BILB change from the pre-charged potential to the potential of the first terminal of capacitor CD2 and the first terminal of capacitor CD1, respectively, the potential held by the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0410] Transistors M7 to M10 are preferably OS transistors. This allows transistors M7 to M10 to hold written data for an extended period, thus reducing the refresh frequency of the memory cell. Alternatively, the refresh operation of the memory cell can be omitted.

[0411] Furthermore, Si transistors are preferably used as transistors MS1 to MS4.

[0412] The driving circuitry 910 and the memory array 920 included in the semiconductor device 900 are disposed on the same plane. Furthermore, as... Figure 26A As shown, the driving circuit 910 and the memory array 920 can also overlap. By overlapping the driving circuit 910 and the memory array 920, the signal transmission distance can be shortened. Figure 26B As shown, multiple memory arrays 920 can also be stacked on the drive circuit 910.

[0413] Next, an example of an arithmetic processing device that may include the aforementioned storage device or other semiconductor device will be described.

[0414] Figure 27This is a block diagram of the arithmetic unit 960. Figure 27 The computing device 960 shown can be used, for example, as a CPU. Furthermore, the computing device 960 can also be used with processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units), which have more (tens to hundreds) processor cores than a CPU capable of parallel processing.

[0415] Figure 27 The illustrated arithmetic unit 960, on a substrate 990, includes: an ALU 991 (ALU: Arithmetic Logic Unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also include a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be located on different chips.

[0416] Cache 999 is connected to the main memory located on different chips via cache interface 989. Cache interface 989 has the function of supplying a portion of the data stored in the main memory to cache 999. In addition, cache interface 989 has the function of outputting a portion of the data held in cache 999 to ALU 991 or register 996, etc., via bus interface 998.

[0417] As described later, the memory array 920 can be arranged in a manner that stacks on the computing device 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 can have the function of supplying data held in the memory array 920 to the cache 999. Furthermore, in this case, it is preferable that a portion of the cache interface 989 includes a drive circuit 910.

[0418] Note that you can also use memory array 920 as a cache instead of setting cache 999.

[0419] Figure 27 The arithmetic device 960 shown is merely an example with a simplified structure; therefore, the actual arithmetic device 960 has various structures depending on its application. For example, it is preferable to include... Figure 27The computing device 960 shown has a multi-core structure, which consists of a single core and multiple cores that operate simultaneously. The more cores, the better the computing performance. More cores are preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, and sixteen cores or more are even more preferred. Furthermore, when used in servers or other applications requiring very high computing performance, a multi-core structure with 16 or more cores is preferred, more preferably 32 or more cores, and more preferably 64 or more cores. Additionally, the number of bits that can be processed in the internal computing circuitry, data bus, etc., of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0420] Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993 and, after being decoded, are input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0421] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing the program of the arithmetic unit 960, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority, mask state, etc. The register controller 997 generates the address of register 996 and performs read, write, and other operations on register 996 according to the state of the arithmetic unit 960.

[0422] Furthermore, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0423] exist Figure 27 In the illustrated arithmetic unit 960, the register controller 997 selects the holding operation of register 996 according to instructions from ALU 991. In other words, the register controller 997 selects whether data is held in the memory cells included in register 996 by flip-flops or by capacitors. When data is held by flip-flops, a power supply potential is supplied to the memory cells in register 996. When data is held by capacitors, the data is overwritten to the capacitors, and the power supply potential to the memory cells in register 996 can be stopped.

[0424] The memory array 920 and the arithmetic unit 960 can be arranged overlappingly. Figure 28A and Figure 28B This is a perspective view of semiconductor device 970A. Semiconductor device 970A includes a layer 930 on a computing device 960, on which memory arrays are disposed. Layer 930 houses memory arrays 920L1, 920L2, and 920L3. The computing device 960 and each memory array have overlapping areas. To facilitate understanding of the structure of semiconductor device 970A, in... Figure 28B The computing device 960 and the layer 930 are shown separately in the middle.

[0425] By overlapping the layer 930, which includes the memory array, and the computing device 960, the connection distance between them can be shortened. This improves the communication speed between them. Furthermore, the shorter connection distance reduces power consumption.

[0426] As a stacking method for the layer 930 including the memory array and the computing device 960, the following methods can be used: directly stacking the layer 930 including the memory array on the computing device 960 (also known as monolithic stacking); or forming the computing device 960 and the layer 930 on different substrates, bonding the two substrates together, and connecting them using bonding techniques such as through-holes or conductive films (Cu-Cu bonding, etc.). The former method does not require consideration of misalignment during bonding, thus reducing both chip size and manufacturing costs.

[0427] Here, the memory arrays 920L1, 920L2, and 920L3, which do not include cache 999 in the arithmetic unit 960 and are disposed in layer 930, can all be used as caches. For example, memory arrays 920L1, 920L2, and 920L3 can be used as L1 cache (also called level 1 cache), L2 cache (also called level 2 cache), and L3 cache (also called level 3 cache), respectively. Among the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, memory array 920L1 has the smallest capacity and the highest access frequency.

[0428] Note that when the cache 999 in the arithmetic unit 960 is used as an L1 cache, the memory arrays in layer 930 can be used as lower-level caches or main memory. Main memory is memory with a larger capacity and lower access frequency than cache.

[0429] In addition, such as Figure 28BAs shown, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

[0430] Note that although the case shown here is a three-array memory array used as a cache, it can also be one, two, or more than four.

[0431] When the memory array 920L1 is used as a cache, the driver circuit 910L1 can also be used as part of the cache interface 989, and the driver circuit 910L1 can also be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 can also be used as part of the cache interface 989 or connected to a part of the cache interface 989.

[0432] Whether the memory array 920 is used as a cache or as main memory depends on the control circuit 912 included in each drive circuit 910. The control circuit 912 can use a portion of the multiple memory cells 950 contained in the semiconductor device 900 as RAM based on signals supplied from the arithmetic unit 960.

[0433] In the semiconductor device 900, a portion of the multiple storage cells 950 can be used as a cache and the remainder as main memory. That is, the semiconductor device 900 can function as both a cache and main memory. The semiconductor device 900 according to one embodiment of the invention can, for example, be used as a general-purpose memory.

[0434] Alternatively, a layer 930 including a memory array 920 may be provided in a manner that overlaps with the computing device 960. Figure 29A This is a 3D view of the semiconductor device 970B.

[0435] In the semiconductor device 970B, a memory array 920 can be divided into multiple regions and assigned different functions for use. Figure 29A This shows an example of using region L1, region L2, and region L3 as L1 cache, L2 cache, and L3 cache, respectively.

[0436] Furthermore, in the semiconductor device 970B, the capacity of each of regions L1 to L3 can be changed according to the situation. For example, the capacity of the L1 cache can be increased by increasing the area of ​​region L1. By adopting this structure, efficient computational processing can be achieved, thereby increasing processing speed.

[0437] In addition, multiple memory arrays can be stacked. Figure 29B This is a 3D view of the semiconductor device 970C.

[0438] Semiconductor device 970C includes a layer 930L1 comprising a memory array 920L1, a layer 930L2 comprising a memory array 920L2, and a layer 930L3 comprising a memory array 920L3. The memory array 920L1, physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, furthest from the arithmetic unit 960, can be used as a lower-level cache or main memory. By employing this structure, the capacity of each memory array can be increased, thus further improving processing power.

[0439] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0440] (Implementation Method 3)

[0441] In this embodiment, an application example of a semiconductor device according to one aspect of the present invention is described. For example, the semiconductor device according to one aspect of the present invention can be used in electronic components, electronic devices, mainframe computers, space equipment, and data centers (also known as DCs). Electronic components, electronic devices, mainframe computers, space equipment, and data centers using the semiconductor device according to one aspect of the present invention are highly effective in achieving high performance such as low power consumption.

[0442] [Electronic Components]

[0443] Figure 30A A perspective view of a substrate (circuit board 704) on which electronic components 700 are mounted is shown. Figure 30A The electronic component 700 shown includes a semiconductor device 710 within the mold 711. Figure 30A In this description, a portion of the electronic component 700 is omitted to indicate its internal structure. The electronic component 700 includes a connecting pad 712 on the outside of the mold 711. The connecting pad 712 is electrically connected to an electrode pad 713, which is electrically connected to a semiconductor device 710 via a lead 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. By combining multiple such electronic components and electrically connecting them individually on the printed circuit board 702, a circuit board 704 is completed.

[0444] Furthermore, the semiconductor device 710 includes a driver circuit layer 715 and a memory layer 716. The memory layer 716 has a structure with multiple memory cell arrays stacked on top of each other. The stacked structure of the driver circuit layer 715 and the memory layer 716 can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without through-hole electrode technologies such as TSVs (Through Silicon Vias) or bonding technologies such as Cu-Cu direct bonding. When the driver circuit layer 715 and the memory layer 716 are stacked monolithically, for example, a so-called on-chip memory structure in which memory is directly formed on the processor can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0445] Furthermore, by employing an on-chip memory structure, the size of interconnect wiring can be reduced compared to techniques using through electrodes such as TSVs, thus allowing for an increase in the number of pins. Increasing the number of pins enables parallel operation, thereby improving the memory's bandwidth.

[0446] Furthermore, it is preferable to use OS transistors to form multiple memory cell arrays in memory layer 716, and to stack these multiple memory cell arrays monolithically. When multiple memory cell arrays are stacked monolithically, one or both of the memory bandwidth and memory access latency can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between accessing and starting data exchange. When using Si transistors in memory layer 716, it is more difficult to stack them monolithically compared to OS transistors. Therefore, in a monolithically stacked structure, OS transistors are superior to Si transistors.

[0447] Furthermore, the semiconductor device 710 may be referred to as a bare die. In this specification, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into rectangular pieces during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0448] then, Figure 30B A perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is disposed on a package substrate 732 (printed circuit board), and semiconductor devices 735 and multiple semiconductor devices 710 are disposed on the interposer 731.

[0449] Electronic component 730 illustrates an example of using semiconductor device 710 as high-bandwidth memory (HBM). Furthermore, semiconductor device 735 can be used in integrated circuits such as CPUs, GPUs, NPUs, or FPGAs (Field Programmable Gate Arrays).

[0450] The packaging substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The through-hole plate 731 can be, for example, a silicon through-hole plate or a resin through-hole plate.

[0451] The through-hole board 731 has multiple wirings and multiple integrated circuits with different spacing between their electrical connection terminals. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 has the function of electrically connecting the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 732. Therefore, the through-hole board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". Additionally, sometimes a through electrode is provided in the through-hole board 731, through which the integrated circuit is electrically connected to the package substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0452] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0453] Furthermore, in SiP and MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally on the interposer.

[0454] On the other hand, when multiple integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSVs, space is required for the width of these terminal pitches. Therefore, when the size of the electronic component 730 is to be reduced, the width of the aforementioned terminal pitch becomes a problem, and it is sometimes difficult to set to achieve the required amount of wiring to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array can also be used.

[0455] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the integrated circuits provided on the insert 731 have the same height. For example, in the electronic component 730 shown in this embodiment, it is preferable that the semiconductor device 710 and the semiconductor device 735 have the same height.

[0456] In order to mount the electronic component 730 on other substrates, an electrode 733 may also be provided on the bottom of the package substrate 732. Figure 30B An example of forming electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0457] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0458] [Mainframe Computer]

[0459] then, Figure 31A A perspective view of a mainframe computer 5600 is shown. In the mainframe computer 5600, multiple rack-mounted computers 5620 are housed in racks 5610. Alternatively, the mainframe computer 5600 can also be referred to as a supercomputer.

[0460] Figure 31B A perspective view of an example of a computer 5620 is shown. The computer 5620 includes a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slots 5631. Furthermore, the personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0461] Figure 31CAn example of a personal computer card 5621 is shown. The personal computer card 5621 is, for example, a processing board including a CPU, GPU, storage device, etc. The personal computer card 5621 includes a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and connection terminals 5629 mounted on the board 5622. Furthermore, Figure 31C Components other than electronic component 5626, electronic component 5627 and electronic component 5628 are shown.

[0462] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 on the motherboard 5630. The connection terminal 5629 is used as an interface for connecting the personal computer card 5621 to the motherboard 5630. Examples of specifications for the connection terminal 5629 include PCIe.

[0463] Connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for powering or inputting signals to the personal computer card 5621. Furthermore, they can be used, for example, as interfaces for outputting signals calculated by the personal computer card 5621. Examples of the specifications for connection terminals 5623, 5624, and 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of the specifications include HDMI (registered trademark).

[0464] Electronic component 5626 includes terminals (not shown) for signal input and output. By inserting these terminals into a socket (not shown) included in board 5622, electronic component 5626 and board 5622 can be electrically connected.

[0465] Electronic components 5627 and 5628 include multiple terminals, which can be mounted, for example, by reflow soldering these terminals to wiring included in board 5622. Examples of electronic components 5627 include, for example, an FPGA, GPU, or CPU. Examples of electronic components 5627 include, for example, electronic component 730. Examples of electronic components 5628 include, for example, a storage device. Examples of electronic components 5628 include, for example, electronic component 700.

[0466] The 5600 mainframe computer can be used as a parallel computer. By using the 5600 mainframe computer as a parallel computer, large-scale computations required for artificial intelligence learning and inference can be performed, for example.

[0467] [Space Equipment]

[0468] The semiconductor device of one aspect of the present invention can be applied to space equipment.

[0469] One aspect of the semiconductor device of the present invention includes an OS transistor. The OS transistor exhibits minimal change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, and therefore can be suitably used in environments where radiation is likely to occur. For example, the OS transistor can be suitably used in applications involving space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device disposed in a space shuttle, satellite, or space probe. Examples of radiation include, for instance, X-rays and neutron radiation. Note that space, for example, refers to altitudes above 100 km, but the space described in this specification includes one or more of the thermosphere, mesosphere, and stratosphere.

[0470] exist Figure 32A The image shows an artificial satellite 6800 as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control unit 6807. Furthermore, Figure 32A This example shows a planet 6804 in outer space.

[0471] In addition, although Figure 32A Although not illustrated, a battery management system (also known as a BMS) or battery control circuit can also be configured for the secondary battery 6805. When the OS transistor is used in the aforementioned battery management system or battery control circuit, low power consumption and high reliability are achieved, even in space, making it a preferred option.

[0472] Furthermore, outer space is an environment where the radiation dose is more than 100 times that of the Earth's surface. Examples of radiation include electromagnetic waves (electromagnetic radiation), represented by X-rays and gamma rays; and particle radiation, represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0473] The solar panel 6802 generates the power required for the satellite 6800 to operate when sunlight shines on it. However, the generated power decreases, for example, when sunlight does not reach the solar panel or when the amount of sunlight reaching the solar panel is low. Therefore, it is possible that the power required for the satellite 6800 to operate may not be generated. In order to enable the satellite 6800 to operate even when the generated power is low, it is preferable to provide a secondary battery 6805 in the satellite 6800. Furthermore, the solar panel is sometimes referred to as a solar cell module.

[0474] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received, for example, by a ground receiver or other satellites. By receiving the signal transmitted by satellite 6800, the position of the receiver can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0475] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 may use one or more components selected from CPU, GPU, and storage devices. Moreover, the control device 6807 preferably uses a semiconductor device including an OS transistor according to one aspect of the present invention. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to radiation exposure. In other words, OS transistors have high reliability and can be appropriately used even in environments where radiation may be incident.

[0476] Furthermore, satellite 6800 may include sensors. For example, by including a visible light sensor, satellite 6800 may be able to detect sunlight reflected from objects on the ground. Alternatively, by including a thermal infrared sensor, satellite 6800 may be able to detect thermal infrared radiation emitted from the Earth's surface. Thus, satellite 6800 can be used, for example, as an Earth observation satellite.

[0477] Note that in this embodiment, an artificial satellite is shown as an example of a space device, but the invention is not limited thereto. For example, a semiconductor device according to one aspect of the invention can be suitably applied to space devices such as spacecraft, space capsules, and space probes.

[0478] As explained above, OS transistors offer superior performance compared to Si transistors, such as enabling wider memory bandwidth and higher radiation resistance.

[0479] [Data Center]

[0480] For example, the semiconductor device of one aspect of the present invention can be applied to storage systems used in data centers, etc. Data centers are required to manage data over long periods, ensuring data immutability, etc. Long-term data management necessitates large-scale facilities, such as installing storage and servers to store massive amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment is available for data retention.

[0481] By using the semiconductor device of one aspect of the present invention in a storage system employed in a data center, it is possible to reduce the power required to retain data and to miniaturize the semiconductor device used to retain data. Therefore, it is possible to miniaturize the storage system, reduce the size of the power supply used to retain data, and decrease the size of the cooling equipment. This, in turn, enables space-saving in data centers.

[0482] Furthermore, the semiconductor device according to one aspect of the present invention has low power consumption, thus reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Moreover, by using the semiconductor device according to one aspect of the present invention, data centers can operate stably even in high-temperature environments. Therefore, the reliability of data centers can be improved.

[0483] Figure 32B This illustrates a storage system that can be used in a data center. Figure 32B The storage system 6000 shown includes multiple servers 6001sb as a host 6001 (illustrated as a main computer). Furthermore, it includes multiple storage devices 6003md as storage (illustrated as storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as a SAN) and a storage control circuit 6002 (illustrated as a storage controller).

[0484] Host 6001 is equivalent to a computer that accesses data stored in storage 6003. Hosts 6001 can also connect to each other via a network.

[0485] In the Memory 6003, flash memory is used to reduce data access speed, i.e., to shorten the time required for data storage and output. However, this time is much longer than that required by DRAM, which can be used as a cache memory in the storage. In storage systems, to address the issue of the long access speed of the Memory 6003, a cache memory is generally incorporated into the storage to further reduce the time required for data storage and output.

[0486] The aforementioned cache memory is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is output to the host 6001 or the storage 6003 after being stored in the cache memory in the storage control circuit 6002 and the storage 6003.

[0487] When OS transistors are used to maintain the voltage corresponding to the data in the aforementioned cache memory, the refresh frequency can be reduced to lower power consumption. Furthermore, miniaturization can be achieved through stacked memory cell arrays.

[0488] Note that by using the semiconductor device of one aspect of the present invention in one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers, a reduction in power consumption can be expected. Therefore, it is currently believed that with the increasing energy demands of high-performance or highly integrated semiconductor devices, the use of the semiconductor device of one aspect of the present invention can also reduce emissions of greenhouse gases, such as carbon dioxide (CO2). Furthermore, the semiconductor device of one aspect of the present invention has low power consumption, and is therefore effective as a measure against global warming.

[0489] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0490] [Example]

[0491] In this embodiment, the results of estimating the integration level of a semiconductor device (memory device) including a memory cell according to one aspect of the present invention will be described.

[0492] Figures 33A to 33C A top view schematic diagram of a storage device used for computation is shown. Figure 33A The storage device shown in Embodiment 1 includes a transistor (transistor Tr1) (referred to as UFET) disposed in a slit of a spacer. Figure 33A The conductive layer 23, which corresponds to the wiring WL used as a word line, the conductive layer 26, which corresponds to the wiring BL used as a bit line, the insulating layer 22, and the semiconductor layer 21 are shown.

[0493] also, Figure 33A The minimum processing size F (F stands for "Feature Size") and the size F' are shown. F is a value determined by the exposure apparatus, processing apparatus, etc., and is a size that can be reduced through the development of processing technology. On the other hand, F' is a value determined by the structure. Here, F' is determined by the width of the semiconductor layer 21, insulating layer 22, and conductive layer 23 provided inside the slit in the direction orthogonal to the slit, and is consistent with the width of the slit 20.

[0494] exist Figure 33A In the structure shown, the area S of a storage cell is 2F×(F+F'). The smaller S is, the higher the integration density of the storage cell can be.

[0495] Figure 33B A memory device is shown that includes a transistor (transistor Tr2) (referred to as VFET) that uses a cylindrical opening instead of a slit. Figure 33B The diagram shows wiring WL, wiring BL, conductive layer 23 disposed in the opening, insulating layer 22 and semiconductor layer 21.

[0496] exist Figure 33B In this diagram, the diameter of the opening is equivalent to F'. The width of the wiring WL is F'. On the other hand, the wiring BL needs to include the opening, so the width of the wiring BL needs to be greater than the diameter F' of the opening. Here, the width of the wiring BL is F' + α (α > 0). Therefore, the area S of a memory cell is (F + F') × (F + F' + α).

[0497] Figure 33C This shows a DRAM memory cell. Figure 33C The diagram shows wiring WL, wiring SL, semiconductor AL, capacitor CAP, and the contact CON between wiring SL and semiconductor AL. A transistor Tr3 and a capacitor CAP are configured in the area indicated by the dotted line. Figure 33C The area of ​​one memory cell is 6F. 2 .

[0498] Figure 34 This shows the estimated transistor integration (transistor density) when the minimum fabrication size F and size F' of the three models described above are changed. Figure 34 In the diagram, the horizontal axis represents the dimension F [nm], and the vertical axis represents the transistor density [μm]. -2 ].exist Figure 34 In the middle, only Figure 33A The model shown (UFET) has estimation results for three conditions: F' = 35nm, 30nm, and 25.5nm. Note that in... Figure 33B In the model shown (VFET), α is estimated with a value of 20 nm. For example... Figure 34 As shown, among all models, the smaller the minimum fabrication size F, the higher the transistor density. Furthermore, it was confirmed that... Figure 33A The model shown (UFET) can improve transistor density compared to the other two models.

[0499] According to this embodiment, it can be seen that by employing a storage device according to one aspect of the present invention, storage cells can be configured with extremely high density.

[0500] [Symbol Explanation]

[0501] 10: Transistor, 10a: Transistor, 10b: Transistor, 11: Insulating layer, 15: Memory cell, 20: Slit, 21: Semiconductor layer, 21f: Semiconductor film, 22: Insulating layer, 23: Conductive layer, 23f: Conductive film, 24: Conductive layer, 24a: Conductive film, 24af: Conductive film, 24b: Conductive film, 24bf: Conductive film, 25: Conductive layer, 25a: Conductive film, 25af: Conductive film, 25b: Conductive film, 25bf: Conductive film, 26: Conductive layer, 27: Plug, 29: Conductive layer, 30: Capacitor, 30a: Capacitor, 30b: Capacitor, 32: Insulating layer, 33: Insulating layer, 35: Insulating layer, 40: Slit, 40a: Slit, 41: Insulating layer 41a: Insulating layer, 41b: Insulating layer, 41c: Insulating layer, 42: Insulating layer, 43: Insulating layer, 44: Insulating layer, 44a: Insulating layer, 45: Insulating layer, 46: Insulating layer, 46a: Insulating layer, 47: Insulating layer, 48: Insulating layer, 49: Insulating layer, 50: Semiconductor device, 51: Conductive layer, 51f: Conductive film, 52: Insulating layer, 53: Conductive layer, 55: Conductive layer, 80: Layer, 81: Conductive layer, 82: Plug, 83: Plug, 84: Conductive layer, 85: Plug, 86: Insulating layer, 87: Insulating layer, 88: Insulating layer, 89: Plug, 90: Transistor, 91: Substrate, 92: Semiconductor region, 93: Insulating layer, 94: Conductive layer, 95a: Low resistance region 95b: Low resistance region; 96: Insulating layer; 98: Component separation layer; 700: Electronic component; 702: Printed circuit board; 704: Mounting substrate; 710: Semiconductor device; 711: Mold; 712: Connecting pad; 713: Electrode pad; 714: Lead; 715: Driver circuit layer; 716: Memory layer; 730: Electronic component; 731: Through-hole board; 732: Packaging substrate; 733: Electrode; 735: Semiconductor device; 900: Semiconductor device; 910: Driver circuit; 911: Peripheral circuit; 912: Control circuit; 915: Peripheral circuit; 920: Memory array; 923: Row driver; 924: Column driver; 925: Input circuit; 926: Output circuit. 927: Readout Amplifier; 928: Voltage Generation Circuit; 930: Layer; 931: PSW; 932: PSW; 941: Row Decoder; 942: Column Decoder; 950: Memory Cell; 951: Memory Cell; 952: Memory Cell; 953: Memory Cell; 954: Memory Cell; 955: Memory Cell; 956: Memory Cell; 957: Memory Cell; 958: Memory Cell; 960: Arithmetic Logic Unit; 970A: Semiconductor Device; 970B: Semiconductor Device; 970C: Semiconductor Device; 989: Buffer Interface; 990: Substrate; 991: ALU; 992: ALU Controller; 993: Instruction Decoder; 994: Interrupt Controller; 995: Timing Controller.996: Register, 997: Register Controller, 998: Bus Interface, 999: Cache, 5600: Mainframe Computer, 5610: Rack, 5620: Computer, 5621: Personal Computer Card, 5622: Board, 5623: Connection Terminal, 5624: Connection Terminal, 5625: Connection Terminal, 5626: Electronic Component, 5627: Electronic Component, 5628: Electronic Component, 5629: Connection Terminal, 5630: Motherboard, 5631: Slot, 6000: Storage System, 6001: Host, 6001sb: Server, 6002: Storage Control Circuit, 6003: Storage, 6003md: Storage Device, 6800: Satellite, 6801: Main Body, 6802: Solar Panel, 6803: Antenna, 6804: Planet, 6805: Secondary Battery, 6807: Control Device

Claims

1. A semiconductor device, comprising: First conductive layer; Second conductive layer; Third conductive layer; Fourth conductive layer; Semiconductor layer; First insulating layer; Second insulating layer; Third insulating layer; as well as Fourth insulating layer, The first insulating layer is located on the first conductive layer and has a first slit reaching the first conductive layer. The second conductive layer is located on the first insulating layer. The semiconductor layer has a portion that contacts the second conductive layer, a portion inside the first slit along the side of the first insulating layer, and a portion inside the first slit that contacts the first conductive layer. The second insulating layer covers the semiconductor layer inside the first slit. The third conductive layer covers the second insulating layer inside the first slit. The third insulating layer is located below the first insulating layer and has a second slit. The fourth conductive layer has a portion inside the second slit that runs along the side of the third insulating layer. The first conductive layer has a portion located inside the second slit. Furthermore, the fourth insulating layer is located inside the second slit between the first conductive layer and the fourth conductive layer.

2. The semiconductor device according to claim 1, Both the first slit and the second slit extend in the first direction. The third conductive layer extends in the first direction inside the first slit. Furthermore, the fourth conductive layer extends in the first direction inside the second slit.

3. The semiconductor device according to claim 1, The first slit extends in the first direction. The second slit extends in a second direction that intersects the first direction. The third conductive layer extends in the first direction inside the first slit. Furthermore, the fourth conductive layer extends in the second direction inside the second slit.

4. The semiconductor device according to claim 1, further comprising: Fifth conductive layer; as well as Connect the electrodes. The first slit extends in the first direction. The third conductive layer extends in the first direction inside the first slit. The fifth conductive layer is located on the third conductive layer and extends in a second direction that intersects the first direction. Furthermore, the connecting electrode connects the fifth conductive layer and the second conductive layer.

5. The semiconductor device according to claim 1, further comprising: Fifth conductive layer The first slit extends in the first direction. The second conductive layer extends in the first direction. Furthermore, the fifth conductive layer is in contact with the third conductive layer and extends in a second direction that intersects the first direction.

6. The semiconductor device according to claim 1, further comprising: A pair of semiconductor layers; A pair of second insulating layers; as well as A pair of the third conductive layers, The pair of semiconductor layers, the pair of second insulating layers, and the pair of third conductive layers are all symmetrically arranged along a pair of side surfaces of the first insulating layer within the first slit.

7. The semiconductor device according to claim 1, The first conductive layer has a recess in the region overlapping with the first slit. Furthermore, the bottom of each of the semiconductor layer, the second insulating layer, and the third conductive layer is disposed along the recess.

8. The semiconductor device according to claim 1, further comprising: The sixth conductive layer, The second slit reaches the sixth conductive layer. Furthermore, the fourth conductive layer is in contact with the sixth conductive layer inside the second slit.

9. The semiconductor device according to claim 1, The semiconductor layer comprises a first metal oxide. The first conductive layer comprises a second metal oxide. Furthermore, both the first metal oxide and the second metal oxide contain In.

10. The semiconductor device according to claim 1, The semiconductor layer comprises a first metal oxide. The second conductive layer comprises a third metal oxide. Furthermore, both the first metal oxide and the third metal oxide contain In.

11. The semiconductor device according to claim 1, The fourth insulating layer includes a ferroelectric film. Furthermore, the ferroelectric film is a film containing hafnium oxide, zirconium oxide, or hafnium zirconium oxide.

12. The semiconductor device according to claim 1, The top surfaces of the semiconductor layer, the second insulating layer, and the third conductive layer are planarized. Furthermore, the semiconductor layer is in contact with the side of the second conductive layer.

Images