Self-aligned memory node contacts in dynamic random access memory (DRAM) devices
Patent Information
- Application Number
- CN202580015963.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-02-19
- Filing Date
- 2025-01-17
- Publication Date
- 2026-09-22
Smart Images
Figure CN122804497A_ABST
Abstract
Description
Technical Field
[0001] The embodiments described herein generally relate to the fabrication of semiconductor devices, and more specifically, to the fabrication of 4F semiconductor devices. 2 (Feature Square) A method for forming self-aligned memory node contacts in a dynamic random access memory (DRAM) element. Background Technology
[0002] The production of silicon integrated circuits places stringent demands on manufacturing processes to increase component count while reducing the minimum feature size on the chip. These requirements have extended to manufacturing processes, including depositing multiple layers on challenging configurations while maintaining component reliability. For example, 4F... 2 (Feature squared) Dynamic random access memory (DRAM) elements may include memory node contacts that require extreme ultraviolet (EUV) lithography or dual 193nm immersion self-aligned quadruple patterning (SAQP) for patterning.
[0003] Therefore, there is a need for improved processes for forming storage node contacts that do not require complex and expensive photolithography processes during manufacturing. Summary of the Invention
[0004] The embodiments disclosed in this case provide a method for forming storage node contacts in a dynamic random access memory (DRAM) element. The method includes: performing an array wafer polishing process to polish the array wafer from the top side, the array wafer including a bit line layer, a channel pillar located above the bit line layer and surrounded by a gate oxide layer, character line layers located on both sides of the channel pillar, and a bottom source / drain (S / D) junction electrically connecting the channel pillar to the bit line layer, disposed within a shallow trench isolation (STI); performing a junction implantation and activation process to dope the top of the channel pillar and form a top S / D junction; performing a selective dielectric deposition process to selectively form an interlayer dielectric (ILD) on the STI relative to the top S / D junction; performing a silicide process to form an interface layer on the exposed surface of the top S / D junction; performing a contact metal deposition process to deposit a contact metal layer on the ILD and the interface layer; performing a storage node landing pad (SNLP) photolithography and etching process to form a storage node landing pad in the contact metal layer; and performing an insulator filling process to fill the gap between the storage node landing pad and adjacent storage node landing pads with an insulator filling material.
[0005] The embodiments disclosed in this application also provide a method for forming a self-aligned interlayer dielectric (ILD) in a vertical channel structure. The method includes selectively depositing the ILD on a dielectric region without depositing the ILD on the exposed surface of a channel pillar located within the dielectric region, wherein the dielectric region comprises silicon oxide (SiO2) and the channel pillar comprises silicon (Si).
[0006] The embodiments disclosed in this application further provide a vertical channel structure. This vertical channel structure includes: a bit line layer extending along a first direction; a character line layer extending along a second direction orthogonal to the first direction; and a vertical array transistor disposed within a shallow trench isolation (STI). The vertical array transistor includes channel pillars, a bottom source / drain (S / D) junction electrically connected to the bit line layer, and a top S / D junction connectable to a storage capacitor via storage node contacts. The storage node contacts include: an interface layer located on the surface of the top S / D junction, surrounded by a self-aligned interlayer dielectric (ILD) located on the surface of the STI; the interface layer and a contact metal layer on the ILD; and a landing pad within the contact metal layer. Attached Figure Description
[0007] To gain a more detailed understanding of the features of this disclosure, a more specific description of the disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should not be considered as limiting its scope, as this disclosure allows for other equally effective embodiments.
[0008] Figure 1 This is a schematic top view of a multi-chamber cluster tool according to one embodiment.
[0009] Figure 2 This is a process flow diagram of a method for forming self-aligned memory node contacts (SNCs) in a vertical channel structure according to one embodiment.
[0010] Figure 3A , 3A' 3B, 3B', 3C, 3C', 3D, 3D', 3E, 3E', 3F, 3F', 3G, 3G', 3H and 3H' are schematic diagrams of a portion of a vertical channel structure according to one embodiment.
[0011] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further detail. In the figures and the following description, an orthogonal coordinate system comprising the X, Y, and Z axes is used. For convenience, the directions indicated by arrows in the figures are assumed to be positive. Elements disclosed in some embodiments may be advantageously used in other embodiments without further description. Detailed Implementation
[0012] The implementation methods described herein are for use in 4F 2 A method for forming self-aligned memory node contacts (SNCs) in a vertical channel structure used in dynamic random access memory (DRAM) devices. The interlayer dielectric (ILD) surrounding the surface of the vertical array transistors is formed in a self-aligned process through selective dielectric deposition, and therefore the fabrication of memory node contacts (SNCs) including such ILDs does not require complex and expensive photolithography processes or selective epitaxial growth of silicon.
[0013] Figure 1 This is a schematic top view of a multi-chamber cluster tool 100 according to one or more embodiments of the disclosure herein. The multi-chamber cluster tool 100 typically includes a factory interface 102, load-locking chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described herein, substrates in the multi-chamber cluster tool 100 can be processed in and transferred between individual chambers without exposing the substrates to the surrounding environment outside the multi-chamber cluster tool 100 (e.g., the atmospheric environment that may exist in a semiconductor foundry). For example, substrates can be processed in and transferred between individual chambers under low-pressure (e.g., less than or equal to about 300 tors) or vacuum conditions without disrupting the low-pressure or vacuum environment between the various processes performed on the substrates in the multi-chamber cluster tool 100. Therefore, the multi-chamber cluster tool 100 can provide an integrated solution for certain substrate processing.
[0014] Examples of processing systems that can be appropriately modified based on the teachings provided in this article include Endura. ® Producer ® Or Centura ® An integrated processing system or other suitable processing systems may be purchased from Applied Materials, Inc., located in Santa Clara, California, USA. Other processing systems, including those from other manufacturers, may also be adapted to benefit from the aspects described herein.
[0015] exist Figure 1 In the example shown, the fab interface 102 includes a docking station 132 and a fab interface robot 134 to facilitate substrate transfer. The docking station 132 is adapted to receive one or more front-opening wafer cassettes (FOUPs) 136. In some examples, each fab interface robot 134 typically includes blades 138 disposed at one end of the respective fab interface robot 134, adapted to transfer the substrate from the fab interface 102 to the load-locking chambers 104, 106.
[0016] Load-locking chambers 104 and 106 have respective ports 140 and 142 coupled to the factory interface 102 and respective ports 144 and 146 coupled to the transfer chamber 108. The transfer chamber 108 also has respective ports 148 and 150 coupled to the holding chambers 116 and 118 and respective ports 152 and 154 coupled to the processing chambers 120 and 122. Similarly, the transfer chamber 110 has respective ports 156 and 158 coupled to the holding chambers 116 and 118 and respective ports 160, 162, 164, and 166 coupled to the processing chambers 124, 126, 128, and 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 can be, for example, slit valve openings with slit valves that allow the substrate to pass through via transfer robots 112 and 114 and provide a seal between the individual chambers to prevent gas from passing between them. Typically, any port is open to allow the substrate to be transferred through it. Otherwise, the port is closed.
[0017] Load locking chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 are fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryogenic pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the respective chambers. In operation, a factory interface robot 134 transfers a substrate from FOUP 136 through port 140 or 142 to load locking chambers 104 or 106. The gas and pressure control system then depressurizes load locking chambers 104 or 106 by evacuating gas. The gas and pressure control system further maintains a low-pressure or vacuum environment (which may include an inert gas) inside transfer chambers 108, 110, and holding chambers 116, 118. Therefore, evacuating and depressurizing the load-locking chambers 104 or 106 facilitates the transfer of the substrate between the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.
[0018] With the substrate located in a load-locked chamber 104 or 106 that has been depressurized by vacuuming, the transfer robot 112 transfers the substrate from the load-locked chamber 104 or 106 to the transfer chamber 108 through ports 144 or 146. The transfer robot 112 can then transfer the substrate to or between processing chambers 120, 122 (for processing through respective ports 152, 154) and holding chambers 116, 118 (for holding and awaiting further transfer through respective ports 148, 150). Similarly, the transfer robot 114 can access substrates in holding chambers 116 or 118 through ports 156 or 158, and can transfer substrates to or between processing chambers 124, 126, 128, and 130 (for processing through respective ports 160, 162, 164, and 166) and holding chambers 116 and 118 (for holding through respective ports 156 and 158 for further transfer). The transfer and holding of substrates within and between the chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.
[0019] Processing chambers 120, 122, 124, 126, 128, and 130 can be any chamber suitable for processing the substrate. In some examples, processing chamber 120 can perform etching processes, processing chamber 122 can perform cleaning processes, and processing chambers 126, 128, and 130 can perform individual epitaxial growth processes. Processing chamber 120 can be a Selectra™ etching chamber from Applied Materials (Santa Clara, California). Processing chamber 122 can be an Aktiv™ pre-clean (APC) chamber, a pre-clean XT (MCxT-2) chamber, or a SiCoNi™ pre-clean chamber from Applied Materials (Santa Clara, California). Processing chambers 124, 126, 128, or 130 can be Centura™ Epi chambers, Volta™ CVD / ALD chambers, Encore™ PVD chambers, selective tungsten deposition chambers, ionized metal plasma physical vapor deposition (IMP PVD) chambers, rapid thermal processing (RTP) chambers, or plasma etching (PE) chambers supplied by Applied Materials (Santa Clara, California). System controller 168 is coupled to the multi-chamber cluster tool 100 and is used to control the multi-chamber cluster tool 100 or its components. For example, system controller 168 can control the operation of the multi-chamber cluster tool 100 by using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130 of the multi-chamber cluster tool 100, or by controlling a controller associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130. During operation, system controller 168 can collect and provide feedback data from individual chambers to coordinate the performance of the multi-chamber cluster tool 100. System controller 168 is configured to cause the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130 of the multi-chamber cluster tool 100 to perform actions targeting… Figure 2 All the operations described.
[0020] System controller 168 typically includes a central processing unit (CPU) 170, memory 172, and support circuitry 174. CPU 170 can be one of any type of general-purpose processor capable of use in an industrial environment. Memory 172, or a non-transitory computer-readable medium, is accessible by CPU 170 and can be one or more types of memory, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage (local or remote). Support circuitry 174 is coupled to CPU 170 and may include cache memory, frequency circuitry, input / output subsystems, power supply, etc. The various methods disclosed herein can generally be implemented by CPU 170 executing computer instruction code (e.g., software routines) stored in memory 172 (or the memory of a specific processing chamber) under the control of CPU 170. When CPU 170 executes the computer instruction code, CPU 170 controls the chamber to perform the process according to various methods.
[0021] Other processing systems may employ different configurations. For example, more or fewer processing chambers may be coupled to the transport device. In the illustrated example, the transport device includes transport chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transport chambers (e.g., one transport chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transport device in the processing system.
[0022] Figure 2 This is a process flow diagram of a method 200 for forming a self-aligned storage node contact (SNC) in a vertical channel structure 300 according to one or more embodiments of the disclosure in this case. Figure 3A , 3B 3C, 3D, 3E, 3F, 3G, and 3H are cross-sectional views of a portion of the vertical channel structure 300 corresponding to the various stages of method 200. Figure 3A' , 3B' 3C', 3D', 3E', 3F', 3G', and 3H' are top views of this portion of the vertical channel structure 300. The vertical channel structure 300 may be 4F. 2 The vertical array transistor section of a dynamic random access memory (DRAM) element. It should also be understood that... Figure 2 The operations shown can be performed simultaneously and / or with Figure 2 The different sequences shown will be executed.
[0023] 4F 2In the vertical array transistors used in dynamic DRAM devices, the source / drain (S / D) junctions are located at the top and bottom of the channel pillars, and adjacent vertical array transistors are filled with dielectric material as shallow trench isolation (STI). The bottom S / D junction is electrically connected to the bit line, and the top S / D junction is electrically connected to the 4F through the memory node contact (SNC). 2 Storage capacitors in DRAM devices.
[0024] like Figure 3A and 3A' As shown, the vertical channel structure 300 includes an array wafer 302, which includes a bit line layer 304 extending in the X direction, a channel pillar 306 located above the bit line layer 304 and surrounded by a gate oxide layer 308, character line layers 310 extending in the Y direction on both sides of the channel pillar 306 in the X direction, and a bottom source / drain (S / D) junction 312 disposed within a shallow trench isolation (STI) 314 (also referred to as a "dielectric region"), electrically connecting the channel pillar 306 to the bit line layer 304. A carrier wafer (not shown) can be bonded to the bottom side 302B of the array wafer 302.
[0025] Bit line layer 304 and character line layer 310 may be formed of the following materials: tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), titanium nitride (TiN), iridium (Ir), tantalum (Ta), tantalum nitride (TaN), platinum (Pt), rhodium (Rh), or conductive oxides or nitrides of the foregoing, or any combination thereof. The thickness of character line layer 310 on each side of channel pillar 306 may be between about 4 nm and about 6 nm, for example, about 4 nm.
[0026] The channel pillar 306 may be made of silicon (Si), germanium (Ge), silicon-germanium (SiGe), or indium gallium zinc oxide (IGZO), and may have a diameter between approximately 5 nm and approximately 10 nm, for example, approximately 10 nm. The channel pillar 306 may be spaced apart from adjacent channel pillars (not shown) by a spacing between approximately 18 nm and approximately 25 nm, for example, approximately 20 nm.
[0027] The gate oxide layer 308 may be formed of silicon oxide (SiO2), silicon oxynitride (SiON), high-k dielectric materials, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), tantalum pentoxide (Ta2O5), tantalum silicon oxide (TaSiO), or any combination thereof; and the thickness of the gate oxide layer 308 in the X direction is between about 3 nm and about 4 nm.
[0028] The bottom S / D junction 312 can be formed of silicon (Si), germanium (Ge), silicon-germanium (SiGe), or indium gallium zinc oxide (IGZO). These materials are doped with n-type or p-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb) for n-type dopants, and boron (B) or gallium (Ga) for p-type dopants, at a concentration of approximately 10. 19 cm -3 Up to 5x10 20 cm -3 The depth of the bottom S / D junction 312 in the Z direction can be between approximately 15 nm and approximately 35 nm, depending on the desired conductivity characteristics of the bottom S / D junction 312.
[0029] STI 314 can be formed from silicon oxide (SiO2).
[0030] Method 200 begins at block 210, wherein an array wafer polishing process is performed to polish the array wafer 302 from its top side 302T, as follows: Figure 3B As shown. The array wafer polishing process may include a chemical mechanical polishing (CMP) process to thin the array wafer 302 to a desired height relative to the bit line layer 304, for example, between about 180 nm and about 200 nm.
[0031] In block 220, a junction implantation and activation process is performed to dope the top of channel pillar 306 and form a top S / D junction 316, as follows. Figure 3C As shown. The top S / D junction 316 is electrically connected to 4F via storage node contacts (SNCs) formed in subsequent manufacturing steps. 2 Storage capacitors in DRAM devices. Junction implantation and activation processes may include ion implantation of n-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb), from the top side 302T of the array wafer 302. The depth of the top S / D junction 316 in the Z direction may be between approximately 15 nm and approximately 35 nm.
[0032] In block 230, a selective dielectric deposition process is performed to selectively form an interlayer dielectric (ILD) 318 on STI 314 (e.g., silicon oxide (SiO2)) relative to the top S / D junction 316 (e.g., silicon (Si)), as... Figure 3D As shown.
[0033] ILD 318 can be formed from dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zinc oxide (ZnO) or indium oxide (In2O3), and can have a thickness between about 20 nm and about 30 nm.
[0034] Selective dielectric deposition processes may include: in a processing chamber (e.g., Figure 1 In the processing chambers 126, 128, or 130 shown, any suitable deposition process (e.g., atomic layer deposition (ALD)) is performed, and before depositing ILD 318 on the exposed surface of STI 314 (e.g., silicon oxide (SiO2)), surface termination and passivation of the top S / D junction 316 (e.g., silicon (Si)) are performed. Surface termination and passivation may be hydrogen termination of the top S / D junction 316 (e.g., silicon (Si)) to suppress the growth of oxides (e.g., silicon oxide (SiO2)) on the surface of the top S / D junction 316 (e.g., silicon (Si)). Any growth of ILD 318 on unwanted areas (e.g., on the top S / D junction 316) is removed by a post-deposition cleaning process (e.g., wet etching).
[0035] In some embodiments, the selective dielectric deposition process includes the following cycle: in a processing chamber (e.g., Figure 1 The conformal chemical vapor deposition (CVD) of ILD 318 performed in the processing chambers 126, 128, or 130 shown, and in the processing chamber (e.g., Figure 1 An etching process (e.g., wet etching) is performed in the processing chamber 122 shown to remove any growth of ILD 318 on unwanted areas (e.g., on the top S / D junction 316). The conformal deposition and etching processes can be cycled as needed to obtain the desired thickness of ILD 318 on the STI 314 surface.
[0036] In some embodiments, the selective dielectric deposition process includes inhibitor adsorption and re-adsorption to deposit a thin layer of inhibitor or dielectric material on the exposed surface of the top S / D junction 316 (e.g., silicon (Si)) to prevent the growth of any ILD 318 on the top S / D junction 316. The inhibitor is, for example, a self-assembled monolayer (SAM) of an organic molecule, such as methane (CH4), and the dielectric material is, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide nitride (SiCN), silicon oxycarbide (SiOC), or silicon oxynitride (SiON), or a combination of the above materials.
[0037] In block 240, a silicide process is performed to form an interface layer 320 on the exposed surface of the top S / D junction 316, such as... Figure 3E As shown.
[0038] The interface layer 320 can be formed of metal silicides, such as nickel silicide (NiSi), tungsten silicide (WSi2), molybdenum silicide (MoSi2), titanium silicide (TiSi2), cobalt silicide (CoSi2), tantalum silicide (TaSi2), or any combination thereof, with a thickness between about 5 nm and about 10 nm. The interface layer 320 can reduce the resistance of the top S / D junction 316.
[0039] The siliconization process may include any suitable deposition process, such as in a processing chamber (e.g., Figure 1 Chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., are performed in the processing chambers 126, 128, or 130 shown.
[0040] In block 250, a contact metal deposition process is performed to deposit a contact metal layer 322 on ILD 318 and interface layer 320, such as Figure 3F As shown.
[0041] The contact metal layer 322 may be formed of tungsten (W), titanium (Ti), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), conductive oxides or nitrides of the above materials, or any combination of the above materials, and may have a thickness between about 20 nm and about 30 nm.
[0042] Contact metal deposition processes can include any suitable deposition process, such as in a processing chamber (e.g., Figure 1 Chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., are performed in the processing chambers 126, 128, or 130 shown.
[0043] In block 260, a storage node landing pad (SNLP) photolithography and etching process is performed to form a storage node landing pad 324 in the contact metal layer 322, such as... Figure 3G As shown.
[0044] The storage node landing pad 324 may have a width of less than about 20 nm and be spaced apart from adjacent storage node landing pads 324 with a spacing of more than about 14 nm.
[0045] SNLP lithography and etching processes can include any patterning technique, such as lithography and etching processes within a processing chamber, for example... Figure 1 The processing chambers shown are 120, 122, or 124.
[0046] In block 270, an insulator filling process is performed to fill the gap between the storage node landing pad 324 and the adjacent storage node landing pad 324 using insulator filling material 326, such as Figure 3H and 3H' As shown. An interface layer 320, surrounded by an ILD 318, a contact metal layer 322, and a storage node landing pad 324, forms a storage node contact (SNC), which electrically connects the top S / D junction 316 to the 4F. 2 Storage capacitors in DRAM devices.
[0047] The insulator filler material 326 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbonitride (SiCN), or any combination of the above materials.
[0048] Metal filling processes may include processing chambers (e.g., Figure 1 Any suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc., can be performed in the processing chambers 126, 128, or 130 shown.
[0049] In the embodiments described herein, a method for forming self-aligned memory node contacts (SNCs) in a semiconductor device is provided, for example, 4F. 2 Vertical channel structures used in dynamic random access memory (DRAM) devices. In the method described herein, an interlayer dielectric (ILD) is formed around the surface of the vertical array transistors in a self-aligned process via selective dielectric deposition, thus fabricating memory node contacts (SNCs) including such ILDs does not require complex and expensive photolithography processes or selective epitaxial growth of silicon.
[0050] Although the foregoing describes the implementation of the disclosure in this case, other and further implementations of the disclosure can be devised without departing from the basic scope of the disclosure, and the scope of the disclosure is defined by the appended claims.
Claims
1. A method for forming memory node contacts in a dynamic random access memory (DRAM) element, the method comprising: An array wafer polishing process is performed to polish the array wafer from the top side. The array wafer includes a bit line layer, a channel pillar located above the bit line layer and surrounded by a gate oxide layer, a character line layer located on both sides of the channel pillar, and a bottom source / drain (S / D) junction electrically connecting the channel pillar to the bit line layer. The bottom source / drain (S / D) junction is disposed within a shallow trench isolation (STI). Perform junction implantation and activation processes to dope the top of the channel pillar and form a top S / D junction; A selective dielectric deposition process is performed to selectively form an interlayer dielectric (ILD) on the STI relative to the top S / D junction. A silicide process is performed to form an interface layer on the exposed surface of the top S / D junction; A contact metal deposition process is performed to deposit a contact metal layer on the ILD and the interface layer; Perform a SNLP (Storage Node Landing Pad) photolithography and etching process to form a storage node landing pad in the contact metal layer; and An insulator filling process is performed to fill the gap between the storage node landing pad and the adjacent storage node landing pad with an insulating filling material.
2. The method of claim 1, wherein the channel pillar comprises silicon (Si), and the STI comprises silicon oxide (SiO2).
3. The method of claim 1, wherein the diameter of the channel pillar is between 5 nm and 10 nm, and it is spaced apart from adjacent channel pillars at a distance between 18 nm and 25 nm.
4. The method of claim 1, wherein the ILD comprises aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zinc oxide (ZnO) or indium oxide (In2O3).
5. The method of claim 1, wherein the ILD has a thickness between about 20 nm and about 30 nm.
6. The method of claim 1, wherein the selective dielectric deposition process comprises: Hydrogen termination of the exposed surface of the top S / D junction and atomic layer deposition (ALD) of the ILD on the exposed surface of the STI.
7. The method of claim 1, wherein the selective dielectric deposition process comprises conformal chemical vapor deposition (CVD) and etching processes of the ILD to remove any growth of the ILD on the top S / D junction.
8. The method of claim 1, wherein the interface layer comprises nickel silicide (NiSi), tungsten silicide (WSi2), molybdenum silicide (MoSi2), titanium silicide (TiSi2), cobalt silicide (CoSi2), tantalum silicide (TaSi2), or any combination thereof.
9. The method of claim 1, wherein the contact metal layer and the landing pad each comprise: Tungsten (W), titanium (Ti), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), indium (Ta), platinum (Pt), conductive oxides or nitrides of the above materials, or any combination of the above materials.
10. The method of claim 1, wherein the width of the storage node landing pad is less than 20 nm and is spaced apart from the adjacent storage node landing pads at a spacing of greater than 14 nm.
11. A method for forming a self-aligned interlayer dielectric (ILD) in a vertical channel structure, the method comprising: ILDs are selectively deposited on dielectric regions, without depositing the ILDs on the exposed surfaces of channel pillars located within the dielectric regions, wherein: The dielectric region includes silicon oxide (SiO2), and The channel pillars comprise silicon (Si).
12. The method of claim 11, wherein the diameter of the channel pillars is between 5 nm and 10 nm, and they are spaced apart from adjacent channel pillars at a spacing between 18 nm and 25 nm.
13. The method of claim 11, wherein the ILD comprises aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zinc oxide (ZnO) or indium oxide (In2O3).
14. The method of claim 11, wherein the ILD has a thickness between about 20 nm and about 30 nm.
15. The method of claim 11, wherein the deposition of the ILD comprises: Hydrogen-sealed ends of the exposed surface of the channel pillar, atomic layer deposition (ALD) of the ILD on the exposed surface of the dielectric region, and wet etching are performed to remove any growth of the ILD on the exposed surface of the channel pillar.
16. The method of claim 11, wherein the deposition of the ILD comprises a cycle of conformal chemical vapor deposition (CVD) of the ILD and an etching process to remove any growth of the ILD on the exposed surface of the channel pillar.
17. The method of claim 11, wherein the deposition of the ILD comprises: Inhibitor adsorption and re-adsorption are performed to deposit the inhibitor on the exposed surface of the channel column.
18. A vertical channel structure, the vertical channel structure comprising: Bit line layer, the bit line layer extending along a first direction; A character line layer, the character line layer extending along a second direction orthogonal to the first direction; A vertical array transistor disposed within shallow trench isolation (STI), the vertical array transistor including channel pillars, a bottom source / drain (S / D) junction electrically connected to the bit line layer, and a top S / D junction connectable to a storage capacitor via storage node contacts, wherein the storage node contacts include: An interface layer, located on the surface of the top S / D junction, is surrounded by a self-aligned interlayer dielectric (ILD) located on the surface of the STI; Contact metal layer, the contact metal layer being on the interface layer and the ILD; and A landing pad, the landing pad being located within the metal layer of the contact element.
19. The vertical channel structure as described in claim 18, wherein: The channel pillar comprises silicon (Si), and the STI comprises silicon oxide (SiO2). The diameter of the channel pillars is between 5 nm and 10 nm, and they are spaced apart from adjacent channel pillars at a distance between 18 nm and 25 nm.
20. The vertical channel structure as described in claim 18, wherein, The self-aligned ILD includes aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zinc oxide (ZnO) or indium oxide (In2O3).