Logic semiconductor device

Abstract

Provided is a semiconductor device capable of reducing the distance between a semiconductor chip and a trench capacitor. In a logic semiconductor device (1), a silicon substrate portion (12), a transistor layer (14), a wiring layer (16), and a capacitor portion (50) in which a through hole (53) and a capacitor (60) are formed are formed in this order.

Description

Technical Field

[0001] This invention relates to logic semiconductor devices. Background Technology

[0002] Deep trench capacitors are known as capacitors that achieve high capacitance while minimizing the area occupied on the substrate surface. Patent Document 1 discloses a method for manufacturing a deep trench capacitor used in a DRAM (Dynamic Random Access Memory) cell.

[0003] Existing technical documents

[0004] Patent Document 1: Japanese Patent Application Publication No. 2004-103777 Summary of the Invention

[0005] However, in the past, when deep trench capacitors were fabricated within semiconductor devices, they were fabricated on a silicon interposer. Furthermore, the semiconductor chip and the silicon interposer were bonded together via bumps. Therefore, in conventional semiconductor packaging, there was a problem of a large distance between the transistors formed on the semiconductor chip and the deep trench capacitors.

[0006] Therefore, the object of the present invention is to provide a semiconductor device capable of shortening the distance between a semiconductor chip and a trench capacitor.

[0007] The logic semiconductor device of the present invention comprises a silicon substrate portion, a transistor layer, a wiring layer, and a capacitor portion having through vias and capacitors formed therein.

[0008] According to the present invention, a semiconductor device capable of shortening the distance between a semiconductor chip and a trench capacitor can be provided. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view showing the logic semiconductor device of this embodiment.

[0010] Figure 2 This is a diagram showing an outline of the semiconductor package of the logic semiconductor device using this embodiment.

[0011] Figure 3 This is a diagram showing how chip wafers and capacitor wafers are bonded together.

[0012] Figure 4A This is a diagram showing the capacitor wafer bonding surface of a capacitor wafer.

[0013] Figure 4B This is a diagram showing the chip wafer bonding surface of a chip wafer.

[0014] Figure 5This diagram shows the state of the silicon chip section and the capacitor section before they are bonded together.

[0015] Figure 6 This is a diagram showing the joint surface of the capacitor section.

[0016] Figure 7 This is a diagram showing the bonding surface of the chip section.

[0017] Figure 8 This is a cross-sectional view of a trench capacitor.

[0018] Figure 9 This is a diagram showing an overview of conventional semiconductor packaging. Detailed Implementation

[0019] (Logic semiconductor device)

[0020] Referring to the accompanying drawings, a method for carrying out the invention will be described. First, referring to... Figure 1 This describes the logic semiconductor device 1 according to an embodiment of the present invention. Figure 1 This is a cross-sectional view showing the logic semiconductor device 1. Hereinafter, in the accompanying drawings, the X, Y, and Z directions will sometimes be shown. The X, Y, and Z directions are mutually orthogonal. The Z direction is the direction in which the silicon chip portion 10 and the capacitor portion 50, described later, are stacked. Figure 1 A cross-section of the logic semiconductor device 1 on a plane parallel to the X and Z directions is shown.

[0021] In the logic semiconductor device 1 of this embodiment, a silicon substrate portion 12, a transistor layer 14, a wiring layer 16, and a capacitor portion 50 are sequentially formed. These will be described sequentially below.

[0022] (Silicon chip division and capacitor division)

[0023] The logic semiconductor device 1 includes a silicon chip portion 10 and a capacitor portion 50. The silicon chip portion 10 and the capacitor portion 50 are integrated by direct bonding. Direct bonding refers to bonding without using materials other than the silicon chip portion 10 and the capacitor portion 50, such as adhesives, solder bumps, underfill, or other liquid curable resins. An example of direct bonding is hybrid bonding (hybrid bonding).

[0024] (Chip bonding surface and capacitor bonding surface)

[0025] The surface of the silicon chip portion 10 that is bonded to the capacitor portion 50 is referred to as the chip portion bonding surface 11. The surface of the capacitor portion 50 that is bonded to the silicon chip portion 10 is referred to as the capacitor portion bonding surface 51. In the logic semiconductor device 1 of this embodiment, the logic semiconductor device 1 is formed by directly bonding the chip portion bonding surface 11 and the capacitor portion bonding surface 51 using hybrid bonding. Furthermore, the direct bonding of the chip portion bonding surface 11 and the capacitor portion bonding surface 51 is not limited to bonding using hybrid bonding.

[0026] (Silicon Chip Division)

[0027] The silicon chip section 10 includes a silicon substrate section 12, a transistor layer 14, and a wiring layer 16. The silicon substrate section 12, the transistor layer 14, and the wiring layer 16 are sequentially stacked in the Z direction. The silicon chip section 10 can function as a logic semiconductor.

[0028] (Silicon substrate and transistor layer)

[0029] The silicon substrate portion 12 is a substrate for forming transistors on at least one side thereon. The transistor layer 14 is a layer containing transistors formed on the surface of the silicon substrate portion 12. The number of transistors contained in the transistor layer 14 is not limited.

[0030] (Wiring layer)

[0031] Wiring layer 16 is a layer used to connect transistors included in transistor layer 14 to electrodes formed in capacitor section 50. Wiring layer 16 includes chip insulating portion 18 and wiring portions. The wiring portions are not shown. The wiring portions include wiring for electrically connecting transistors included in transistor layer 14 to electrodes formed in capacitor section 50. Chip insulating portion 18 is an insulating portion formed between wiring portions in the wiring portion. In addition, when the surface of wiring layer 16 that is in contact with capacitor section 50 is used as wiring layer bonding surface, the wiring layer bonding surface is the same as chip bonding surface 11.

[0032] (Capacitor Section)

[0033] Next, the capacitor section 50 will be described. The capacitor section 50 includes a through hole 53, a trench capacitor 60, and a capacitor section insulation section 52. In the capacitor section 50, the surface opposite to the capacitor section mating surface 51 is referred to as the capacitor section back surface 58.

[0034] (Through hole)

[0035] The through-hole 53 is a conductive through-hole that extends from the capacitor part bonding surface 51 to the back surface 58 of the capacitor part. The through-hole 53 is also referred to as a TSV (Through Silicon Via).

[0036] (Groove capacitor)

[0037] The trench capacitor 60 can be a so-called deep trench capacitor. Figure 1 In this design, the length of the capacitor section 50 in the Z direction is denoted as length 160. Length 160 represents the thickness of the capacitor section 50 in the Z direction. Similarly, the length of the trench capacitor 60 in the Z direction is denoted as length 162. Length 162 represents the depth of the trench capacitor 60. Length 160 is, for example, 100 μm. In contrast, length 162 is, for example, 20 μm or more and 40 μm or less. Furthermore, the lengths 160 and 162 described above are examples. The lengths of 160 and 162 are not specifically limited.

[0038] The capacitor section insulation portion 52 is an insulating part that fills the spaces between through holes 53 and between through holes 53 and the trench capacitor 60. The material of the capacitor section insulation portion 52 can be silicon.

[0039] (Semiconductor packaging)

[0040] Before describing the logic semiconductor device 1 in detail, an example of how the logic semiconductor device 1 is used will be given. Figure 2 This is a diagram showing an outline of semiconductor package 100. Logic semiconductor device 1 can form part of semiconductor package 100.

[0041] like Figure 2 As shown, the semiconductor package 100 includes a logic semiconductor device 1 and a package substrate 110. Package wiring 112 is formed on the package substrate 110. Package insulating portions 114 are formed between the package wiring 112, etc. In addition, in the semiconductor package 100, spherical package solder portions 116 (solder bumps) are formed on the surface facing the surface on which the logic semiconductor device 1 is disposed.

[0042] The logic semiconductor device 1 is connected to one side of the package substrate 110 via the device solder section 59 (solder bump).

[0043] (Semiconductor packaging)

[0044] Here, refer to Figure 9 This illustrates the previous semiconductor packaging 200. Figure 9 This is a diagram showing an outline of a conventional semiconductor package 200. Furthermore, references are omitted in the following description. Figure 2 Explanation of the matters described. In the conventional semiconductor package 200, it has the same... Figure 2The logic semiconductor device 1 shown is composed of two components, a silicon chip 210 and an interposer 220, which perform the same functions. Through-holes 222 and trench capacitors 224 are formed in the interposer 220. The silicon chip 210 and the interposer 220 are connected via spherical silicon chip solder bumps 212. The interposer 220 is connected to the package substrate 110 via spherical interposer solder bumps 226.

[0045] like Figure 2 as well as Figure 9 As shown, in the logic semiconductor device 1 of this embodiment, the conventional silicon chip 210 and the interposer 220 can be integrated into a single component. Therefore, the logic semiconductor device 1 of this embodiment can shorten the distance between the semiconductor chip and the trench capacitor. Furthermore, the logic semiconductor device 1 of this embodiment can reduce the thickness of the semiconductor package 100 and simplify its structure.

[0046] Specifically, the logic semiconductor device 1 is described. Figure 3 This diagram shows how chip wafer 310 and capacitor wafer 350 are bonded together. Figure 3 The figure shown by arrow 301 illustrates an outline of the chip wafer bonding surface 311 of the chip wafer 310. The chip wafer 310 is a silicon wafer on which a plurality of silicon chip portions 10 are formed. The chip wafer 310 is bonded to the capacitor wafer 350, which will be described later. The surface of the chip wafer 310 bonded to the capacitor wafer 350 is referred to as the chip wafer bonding surface 311. The surface of the chip wafer 310 opposite to the chip wafer bonding surface 311 is referred to as the back surface of the chip wafer 312.

[0047] Figure 3 The diagram indicated by arrow 302 shows the state of the chip wafer 310 and the capacitor wafer 350 before they are bonded. The capacitor wafer 350 is a silicon wafer with multiple capacitor sections 50 formed thereon. The surface of the capacitor wafer 350 that is bonded to the chip wafer 310 is called the capacitor wafer bonding surface 351.

[0048] When bonding the chip wafer 310 and the capacitor wafer 350, the chip wafer bonding surface 311 of the chip wafer 310 is aligned with the capacitor wafer bonding surface 351 of the capacitor wafer 350. Figure 3 In the example shown, as indicated by arrow 361, the chip wafer 310 is flipped so that the chip wafer bonding surface 311 of the chip wafer 310 is opposite to the capacitor wafer bonding surface 351 of the capacitor wafer 350.

[0049] The silicon chip portion 10 and the capacitor portion 50 are formed in corresponding positions on each wafer in such a way that the individual silicon chip portions 10 and capacitor portions 50 are bonded without positional offset when the chip wafer 310 and capacitor wafer 350 are overlapped. (Refer to...) Figure 4A as well as Figure 4B Please provide an explanation. Figure 4A This is a diagram showing the capacitor wafer bonding surface 351 of the capacitor wafer 350. Figure 4B This illustrates the chip wafer bonding surface 311 of the chip wafer 310 in... Figure 3 The image shows a perspective view along the direction of arrow 363. (See image.) Figure 4A as well as Figure 4B As shown, the capacitor section 50 and the silicon chip section 10 are arranged on each wafer in such a way that they are connected to each other without any positional shift when the capacitor wafer 350 and the chip wafer 310 are overlapped. Furthermore, regarding the... Figure 4A as well as Figure 4B For symbols not explained in the diagram, please refer to [reference needed]. Figure 6 as well as Figure 7 This will be explained later.

[0050] Return to Figure 3 After flipping the chip wafer 310 as shown by arrow 361, at least one of the chip wafer 310 and the capacitor wafer 350 is moved relative to each other as shown by arrow 363, so that the chip wafer bonding surface 311 and the capacitor wafer bonding surface 351 come into contact.

[0051] In this way, the silicon chip portion 10 formed on the chip wafer 310 and the capacitor portion 50 formed on the capacitor wafer 350 come into contact and are bonded.

[0052] The bonding of the silicon chip portion 10 and the capacitor portion 50 will be explained in detail below. In the following description, the bonding of the silicon chip portion 10 and the capacitor portion 50 will be explained with regard to one of the plurality of silicon chip portions 10 formed on the chip wafer 310 and one of the plurality of capacitor portions 50 formed on the capacitor wafer 350.

[0053] (Before joining)

[0054] Figure 5 This diagram shows the state of the silicon chip section 10 and the capacitor section 50 before they are bonded together. Figure 5 The directions indicated by arrows 151 and 152 are both along the Z-direction. The directions indicated by arrows 151 and 152 are opposite to each other.

[0055] By moving the silicon chip portion 10 relative to the capacitor portion 50 in the direction of arrow 151, and by moving the capacitor portion 50 relative to the silicon chip portion 10 in the direction of arrow 151, the silicon chip portion 10 and the capacitor portion 50 are joined together. Thus, a logic semiconductor device 1 is formed.

[0056] The capacitor portion 50 and the silicon chip portion 10 are joined by the capacitor portion bonding surface 51 and the chip portion bonding surface 11. Therefore, referring to Figure 6 as well as Figure 7 This explains the capacitor part bonding surface 51 and the chip part bonding surface 11. Figure 6 This is a diagram showing the capacitor part joint surface 51. Figure 7 This is a diagram showing the chip bonding surface 11. Figure 6 as well as Figure 7 All are shown in Figure 5 The direction of arrow 153 shows the view of the object. Arrow 153 is the direction from the (+) side of the Z direction to the (-) side. Furthermore, Figure 7 The chip bonding surface 11 shown is viewed through the silicon substrate 12, transistor layer 14, and wiring layer 16 in the direction of arrow 153. That is, as... Figure 5 Arrow 154 shows the appearance of the chip bonding surface 11 as viewed from inside the wiring layer 16, or in other words from the back side 11R of the chip bonding surface 11.

[0057] (Capacitor joint surface)

[0058] First, refer to Figure 6 The capacitor section bonding surface 51 is described. The capacitor section insulation portion 52 is exposed on the capacitor section bonding surface 51. Furthermore, a through electrode 54, a capacitor electrode 62, and a connecting wire 77 are disposed on the capacitor section bonding surface 51. In other words, the through electrode 54, the capacitor electrode 62, and the connecting wire 77 are disposed within the capacitor section insulation portion 52 in the capacitor section bonding surface 51. The capacitor section bonding surface 51 is covered by the capacitor section insulation portion 52, the through electrode 54, the capacitor electrode 62, and the connecting wire 77.

[0059] (Through electrode)

[0060] The through electrode 54 is an electrode electrically connected to the through hole 53 formed in the capacitor section 50. The through electrode 54 is the portion of the end of the through hole 53 that is exposed at the capacitor section mating surface 51.

[0061] A plurality of through electrodes 54 are disposed on the capacitor section mating surface 51. The number of through electrodes 54 corresponds to the number of through holes 53 formed in the capacitor section 50. Typically, one through electrode 54 is formed for one through hole 53.

[0062] The arrangement of the through electrodes 54 corresponds to the arrangement of the through holes 53 formed in the capacitor section 50. Figure 6 In the example shown, the through electrodes 54 are arranged in a matrix, but there are no particular restrictions on the arrangement of the through electrodes.

[0063] The planar shape of the through electrode 54 is circular. This is because the through hole 53 has a cylindrical shape. The cross-sectional shape of the through hole is not limited to a circle; it can also be annular, rectangular, etc.

[0064] The material of the through electrode 54 can be the same as the material forming the through hole 53. An example of the material for the through electrode 54 is copper. However, the material of the through electrode 54 is not limited to copper. Alternatively, the material of the through electrode 54 can be different from the material forming the through hole 53.

[0065] (Capacitor electrodes)

[0066] The capacitor electrode 62 is the electrode portion of the trench capacitor 60 formed in the capacitor section 50.

[0067] (Groove capacitor)

[0068] Here, a general outline of the structure of the trench capacitor 60 is described. Figure 8 This is a cross-sectional view of the trench capacitor 60. Figure 8 The position of line segment 155-156 and Figure 6 The positions of line segments 155-156 correspond to this. The trench capacitor 60 includes capacitor electrodes 62, a dielectric layer 66, a first electrode layer 68, and a second electrode layer 69. The capacitor electrodes 62 include a first capacitor electrode 64 and a second capacitor electrode 65.

[0069] The dielectric layer 66 is sandwiched between the first electrode layer 68 and the second electrode layer 69. The material of the dielectric layer 66 is not particularly limited. Capacitance can be increased by using a material with a high dielectric constant; silicon oxide, silicon nitride, tantalum oxide, titanium oxide, hafnium oxide, hafnium silicate, HfSiON, HfAlON, etc., can be used. A capacitor is formed in the dielectric layer 66. The first capacitor electrode 64 is the capacitor electrode 62 connected to the first electrode layer 68. The second capacitor electrode 65 is the capacitor electrode 62 connected to the second electrode layer 69.

[0070] The first electrode layer 68, the dielectric layer 66, and the second electrode layer 69 extend in the Z direction to form a trench capacitor.

[0071] The first capacitor electrode 64 and the second capacitor electrode 65 are exposed at the capacitor portion bonding surface 51. A capacitor portion insulating portion 52 is disposed between the first capacitor electrode 64 and the second capacitor electrode 65 at the capacitor portion bonding surface 51. For example, by using the first capacitor electrode 64 as a (+) electrode and the second capacitor electrode 65 as a (-) electrode, a capacitor can be formed in the dielectric layer 66.

[0072] also, Figure 8 The schematic structure of the trench capacitor 60 shown is merely illustrative. The structure of the trench capacitor 60 can be modified appropriately.

[0073] (Capacitor electrodes)

[0074] Return to Figure 6 Next, the capacitor electrode 62 will be described. Figure 6 The first capacitor electrode 64 and the second capacitor electrode 65 shown are for reference. Figure 8 The portions of the first capacitor electrode 64 and the second capacitor electrode 65 of the trench capacitor 60 that are exposed at the capacitor section joint surface 51. The first capacitor electrode 64 and the second capacitor electrode 65 are separated in the capacitor section joint surface 51 by the capacitor section insulation portion 52.

[0075] exist Figure 6 In the example shown, the first capacitor electrode 64 and the second capacitor electrode 65 are quadrilateral in shape. However, the shapes of the first capacitor electrode 64 and the second capacitor electrode 65 are not limited to quadrilaterals. Furthermore, in... Figure 6 In the example shown, the size of the first capacitor electrode 64 is smaller than the size of the second capacitor electrode 65. However, the sizes of the first capacitor electrode 64 and the second capacitor electrode 65 are not limited to... Figure 6 The example shown.

[0076] The material of capacitor electrode 62 is, for example, copper. However, the material of capacitor electrode 62 is not limited to copper.

[0077] (Connection wiring)

[0078] The connecting wiring 77 is a wiring that electrically connects the through electrode 54 and the capacitor electrode 62. The connecting wiring 77 includes a first connecting wiring 78 and a second connecting wiring 79.

[0079] The through electrode 54 closest to the first capacitor electrode 64 is referred to as the first through electrode 55. The first connection wiring 78 is the connection wiring 77 that connects the first through electrode 55 and the first capacitor electrode 64.

[0080] The through electrode 54 near the second capacitor electrode 65 is referred to as the second through electrode 56. The second connection wiring 79 is the connection wiring 77 that connects the second through electrode 56 and the second capacitor electrode 65.

[0081] (Power cord and grounding wire)

[0082] exist Figure 6 In the example shown, for instance, the first through electrode 55 can be aligned with a power line (electric field line), and the second through electrode 56 can be aligned with a ground line (ground wire). Thus, a trench capacitor 60 can be connected between the power line and the ground wire.

[0083] Here, the operation of the transistor is accompanied by the supply and release of charge to and from the transistor. Therefore, switching noise occurs in the power lines. To achieve stable, high-speed operation of the transistor, it is important to reduce switching noise. To achieve this, it is effective to place a capacitor with a large capacitance capable of retaining charge as close as possible to the transistor. In the logic semiconductor device 1 of this embodiment, power lines from the transistor layer 14 can be connected to the trench capacitor 60 without passing through bumps. Therefore, the connection distance of several hundred micrometers to millimeters that was previously incurred due to bumps can be saved.

[0084] Furthermore, the method of connecting the trench capacitor 60 and the wire described above is merely an example. The method of connecting the trench capacitor 60 and the wire is not limited to this.

[0085] The material of the connecting wiring 77 is, for example, copper. However, the material of the connecting wiring 77 is not limited to copper.

[0086] (Chip bonding surface)

[0087] Next, refer to Figure 7 The chip bonding surface 11 is described below. The chip insulating portion 18 is exposed on the chip bonding surface 11. Furthermore, wiring electrodes 26 and pads are disposed on the chip bonding surface 11. In this embodiment, the pads are dummy pads 20. In other words, wiring electrodes 26 and dummy pads 20 are disposed within the chip insulating portion 18 on the chip bonding surface 11. The chip bonding surface 11 is covered by the chip insulating portion 18, the wiring electrodes 26, and the dummy pads 20.

[0088] (Wired electrode)

[0089] Wiring electrode 26 is an electrode electrically connected to the wiring portion formed on the wiring layer 16. Wiring electrode 26 is the portion of the wiring portion that is exposed at the chip bonding surface 11.

[0090] The wiring electrode 26 is engaged with the through electrode 54 of the capacitor part bonding surface 51. That is, the wiring electrode 26 is electrically connected to the through electrode 54 of the capacitor part bonding surface 51.

[0091] Wiring electrode 26 has the same planar shape as through electrode 54. Figure 6 as well as Figure 7 In the example shown, both the planar shape of the wiring electrode 26 and the planar shape of the through electrode 54 are circular. Furthermore, the position of the wiring electrode 26 in the chip bonding surface 11 is the same as the position of the through electrode 54 in the capacitor bonding surface 51.

[0092] By making the planar shape of the wiring electrode 26 and configuring it as described above, the wiring electrode 26 and the through electrode 54 can be fully coupled to each other.

[0093] The material of the wiring electrode 26 can be the same as the material forming the wiring portion. An example of the material for the wiring electrode 26 is copper. However, the material of the wiring electrode 26 is not limited to copper. Furthermore, the material of the wiring electrode 26 can also be different from the material forming the wiring portion.

[0094] (Dummy pads)

[0095] The dummy pad 20 is a pad formed by a conductor at the chip bonding surface 11. The dummy pad 20 can also be a floating pad (island pad) not connected to other conductors. The dummy pad 20 is bonded to the capacitor electrode 62. The planar shape of the dummy pad 20 is the same as the planar shape of the capacitor electrode 62. Furthermore, the position of the dummy pad 20 in the chip bonding surface 11 is the same as the position of the capacitor electrode 62 in the capacitor bonding surface 51.

[0096] The dummy pad 20 includes a first dummy pad 21 and a second dummy pad 22. The first dummy pad 21 is a dummy pad 20 that is bonded to the first capacitor electrode 64. The second dummy pad 22 is a dummy pad 20 that is bonded to the second capacitor electrode 65.

[0097] The material of the dummy pad 20 can be the same as the material of the capacitor electrode 62. For example, if the material of the capacitor electrode 62 is copper, the material of the dummy pad 20 is also preferably copper. Furthermore, the pad formed on the chip bonding surface 11 and bonded to the capacitor electrode 62 is not limited to a floating pad, but can also be a pad connected to wiring. For example, this pad can also be connected to the wiring electrode 26 of the chip bonding surface 11 via connection wiring (not shown). In this case, connection wiring 77 may not be formed on the capacitor bonding surface 51.

[0098] (Jointing of the capacitor part bonding surface and the chip part bonding surface)

[0099] Here, the bonding between the capacitor part bonding surface 51 and the chip part bonding surface 11 will be described. The capacitor part bonding surface 51 and the chip part bonding surface 11 are directly bonded. Direct bonding means that, as described above, they are bonded in a state of mutual contact without any other materials such as adhesives, solder bumps, underfill, or liquid curable resins sandwiched between them.

[0100] (Mixed bonding)

[0101] An example of direct bonding is mixed bonding. The case of mixed bonding between capacitor part bonding surface 51 and chip part bonding surface 11 is illustrated. For mixed bonding to be performed, the two surfaces to be bonded are preferably formed of the same material.

[0102] (Insulation section of capacitor part and insulation section of chip part)

[0103] The capacitor insulating portion 52 of the capacitor bonding surface 51 is an insulating portion made of silicon. Therefore, the chip insulating portion 18 of the chip bonding surface 11 is made of the same silicon as the capacitor insulating portion 52. As a result, the capacitor insulating portion 52 and the chip insulating portion 18 are mixed and bonded.

[0104] The capacitor portions are bonded together as described below. First, the terminal hydroxyl groups of the silicon constituting the capacitor portion insulating portion 52 and the chip portion insulating portion 18 are bonded together by hydrogen bonds. Therefore, the interface between the capacitor portion bonding surface 51 and the chip portion bonding surface 11 is heated. Due to this heating, dehydration occurs from the hydrogen bonds, and the capacitor portion insulating portion 52 and the chip portion insulating portion 18 are bonded together by siloxane bonds.

[0105] Furthermore, the materials of the capacitor insulation portion 52 and the chip insulation portion 18 are not limited to the materials described above. For example, the materials of the capacitor insulation portion 52 and the chip insulation portion 18 can also be silicon oxide or silicon carbonitride. These materials can also be used as insulating materials for hybrid bonding.

[0106] (Through-through electrode and wiring electrode)

[0107] Next, the bonding of the through electrode 54 and the wiring electrode 26 will be explained. For example, the material of both the through electrode 54 and the wiring electrode 26 is copper. In this case, by bringing the through electrode 54 and the wiring electrode 26 into contact, the copper on both electrodes diffuses into each other, forming a diffusion bond. Through this diffusion bond, the through electrode 54 and the wiring electrode 26 can be bonded.

[0108] In this way, during the bonding of the capacitor part bonding surface 51 and the chip part bonding surface 11, the materials of the contacting portions of the capacitor part bonding surface 51 and the chip part bonding surface 11 are the same, thereby enabling hybrid bonding to occur.

[0109] Furthermore, the description of the above-described connection is merely illustrative. The materials of each part can be appropriately changed. For example, the materials of the through electrode 54 and the wiring electrode 26 are not limited to copper.

[0110] (Dummy pads)

[0111] This section explains the function of the dummy pad 20 in hybrid bonding. The dummy pad 20 enhances the bonding strength between the capacitor bonding surface 51 and the chip bonding surface 11.

[0112] As described above, in the hybrid bonding of the capacitor portion bonding surface 51 and the chip portion bonding surface 11, it is preferable that the materials of the contact portions of the capacitor portion bonding surface 51 and the chip portion bonding surface 11 are the same. Here, as Figure 6 As shown, a capacitor electrode 62 is formed on the capacitor bonding surface 51. The capacitor electrode 62 is typically formed of a metal such as copper. When the dummy pad 20 is not formed on the chip bonding surface 11, the chip bonding surface 11 where the capacitor electrode 62 contacts becomes the chip insulating portion 18. The chip insulating portion 18 is formed of an insulating material. Therefore, no hybrid bonding-based bond is formed between the capacitor electrode 62 and the chip insulating portion 18. This is because one is a metallic material and the other is an insulating material.

[0113] When there is a portion between the capacitor part bonding surface 51 and the chip part bonding surface 11 where bonding will not occur, the bonding strength between the silicon chip part 10 and the capacitor part 50 may sometimes become weak.

[0114] In the silicon chip section 10 of this embodiment, a dummy pad 20 is formed on the chip section bonding surface 11. The dummy pad 20 is positioned at a location overlapping the capacitor electrode 62 when the capacitor section bonding surface 51 and the chip section bonding surface 11 are bonded. Furthermore, the dummy pad 20 is formed of the same material as the capacitor electrode 62. Therefore, when the capacitor section bonding surface 51 and the chip section bonding surface 11 are bonded, bonding can occur between the dummy pad 20 and the capacitor electrode 62. This enhances the bonding strength between the capacitor section bonding surface 51 and the chip section bonding surface 11.

[0115] (Manufacturing method)

[0116] This section describes a method for manufacturing the logic semiconductor device 1 according to this embodiment. The logic semiconductor device 1 is manufactured by bonding the silicon chip portion 10 and the capacitor portion 50. Specifically, as... Figure 3 The chip wafer 310 and the capacitor wafer 350 are brought into contact, thereby bonding the respective silicon chip portions 10 formed on the chip wafer 310 and the respective capacitor portions 50 formed on the capacitor wafer 350. The silicon chip portions 10 and the capacitor portions 50 can also be manufactured using conventional techniques. Therefore, the bonding of the silicon chip portions 10 and the capacitor portions 50 will be explained.

[0117] The silicon chip portion 10 and the capacitor portion 50 can be bonded using hybrid bonding. First, a chip wafer 310 with the silicon chip portion 10 and a capacitor wafer 350 with the capacitor portion 50 are prepared. Next, the chip wafer bonding surface 311 of the chip wafer 310 and the capacitor wafer bonding surface 351 of the capacitor wafer 350 are planarized using CMP (chemical mechanical planarization) or the like. Then, the silicon chip portion 10 of the chip wafer 310 and the capacitor portion 50 of the capacitor wafer 350 are aligned. Furthermore, by bringing the chip wafer bonding surface 311 and the capacitor wafer bonding surface 351 closer together, and more specifically, bringing the chip portion bonding surface 11 and the capacitor portion bonding surface 51 closer together, the chip portion bonding surface 11 and the capacitor portion bonding surface 51 are bonded. At this time, heat or pressure can also be applied to the interface between the chip portion bonding surface 11 and the capacitor portion bonding surface 51. Alternatively, an annealing process can be performed after bonding. After bonding, the components are monolithically processed by cutting to obtain individual logic semiconductor devices 1.

[0118] Furthermore, the manufacturing method of the logic semiconductor device 1 is not limited to the method described above. In the above description, the silicon chip portion 10 and the capacitor portion 50 are bonded together while they are respectively formed on the chip wafer 310 or the capacitor wafer 350, and then monolithically assembled to obtain each logic semiconductor device 1. In contrast, the silicon chip portion 10 and the capacitor portion 50 may be cut from the chip wafer 310 or the capacitor wafer 350 respectively, and the monolithically assembled silicon chip portion 10 and the capacitor portion 50 may be bonded to obtain the logic semiconductor device 1. Alternatively, one may be in the state of a wafer and the other in the state of a chip, and they may be bonded by hybrid bonding or the like. For example, the silicon chip portion 10, which is monolithically assembled by cutting, may be bonded to the capacitor wafer 350 by hybrid bonding or the like.

[0119] The embodiments of the present invention have been described above. The present invention is not limited to the above embodiments, and various modifications, variations, and combinations are possible.

[0120] (1) In a logic semiconductor device, a silicon substrate portion, a transistor layer, a wiring layer and a capacitor portion having through holes and capacitors are formed sequentially.

[0121] (2) In the logic semiconductor device, the wiring layer and the capacitor section are directly connected.

[0122] (3) In the logic semiconductor device, the capacitor is a trench capacitor.

[0123] (4) In the logic semiconductor device, When the surface of the capacitor section that is in contact with the wiring layer is designated as the capacitor section bonding surface, capacitor electrodes, which serve as electrodes of the capacitor, are exposed at the capacitor section bonding surface. When the surface of the wiring layer that is in contact with the capacitor portion is designated as the wiring layer bonding surface, a pad made of metal is formed on the portion of the wiring layer bonding surface that is in contact with the capacitor electrode.

[0124] (5) The manufacturing method of the logic semiconductor device includes: The steps of fabricating a chip wafer having multiple silicon chip portions sequentially having a silicon substrate portion, a transistor layer, and a wiring layer; The steps of fabricating a capacitor wafer having multiple capacitor portions having through holes and capacitors; The steps of contacting the chip wafer and the capacitor wafer to bond the wiring layer and the capacitor portion; and The step of cutting out a logic semiconductor device by bonding a silicon chip portion and a capacitor portion from the chip wafer and the capacitor wafer.

[0125] Explanation of symbols

[0126] 1: Logic semiconductor device; 10: Silicon chip portion; 11: Chip portion bonding surface; 11R: Back side of chip portion bonding surface; 12: Silicon substrate portion; 14: Transistor layer; 16: Wiring layer; 18: Chip portion insulating portion; 20: Dummy pad; 21: First dummy pad; 22: Second dummy pad; 26: Wiring electrode; 50: Capacitor portion; 51: Capacitor portion bonding surface (wiring layer bonding surface); 52: Capacitor portion insulating portion; 53: Through-hole; 54: Through electrode; 55: First through electrode; 56: Second through electrode; 58: Back side of capacitor portion; 59: Device solder portion; 60: Trench capacitor (capacitor); 62: Capacitor electrode; 64: First capacitor electrode 65: Second capacitor electrode; 66: Dielectric layer; 68: First electrode layer; 69: Second electrode layer; 77: Connection wiring; 78: First connection wiring; 79: Second connection wiring; 100: Semiconductor package; 110: Package substrate; 112: Package wiring; 114: Package insulation portion; 116: Package solder portion; 200: Semiconductor package; 210: Silicon chip; 212: Silicon chip solder portion; 220: Intermediate layer; 222: Through-hole; 224: Trench capacitor; 226: Intermediate layer solder portion; 310: Chip wafer; 311: Chip wafer bonding surface; 312: Chip wafer back side; 350: Capacitor wafer; 351: Capacitor wafer bonding surface.

Claims

1. A logic semiconductor device, wherein, A silicon substrate portion, a transistor layer, a wiring layer, and a capacitor portion having through-holes and capacitors are formed sequentially.

2. The logic semiconductor device according to claim 1, wherein, The wiring layer and the capacitor section are directly connected.

3. The logic semiconductor device according to claim 1 or 2, wherein, The capacitor is a trench capacitor.

4. The logic semiconductor device according to claim 1 or 2, wherein, When the surface of the capacitor section that is in contact with the wiring layer is designated as the capacitor section bonding surface, capacitor electrodes, which serve as electrodes of the capacitor, are exposed at the capacitor section bonding surface. When the surface of the wiring layer that is in contact with the capacitor portion is designated as the wiring layer bonding surface, a pad made of metal is formed on the portion of the wiring layer bonding surface that is in contact with the capacitor electrode.

5. The logic semiconductor device according to claim 4, wherein, A through electrode is disposed on the joint surface of the capacitor portion. The capacitor electrode is connected to the through electrode corresponding to the power line and the through electrode corresponding to the ground line.

6. A method for manufacturing a logic semiconductor device, comprising: The steps of fabricating a chip wafer having multiple silicon chip portions sequentially having a silicon substrate portion, a transistor layer, and a wiring layer; The steps of fabricating a capacitor wafer having multiple capacitor portions having through holes and capacitors; The step of bringing the chip wafer and the capacitor wafer into contact to bond the wiring layer and the capacitor portion; as well as The step of cutting out a logic semiconductor device by bonding a silicon chip portion and a capacitor portion from the chip wafer and the capacitor wafer.

7. The method for manufacturing a logic semiconductor device according to claim 6, wherein, The bonding is a direct bonding based on hybrid bonding.

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