Nonvolatile memory cell having an ono compound insulating layer between a floating gate and a control gate and method of manufacturing the same

Abstract

A method includes forming a first insulating layer on an upper surface of a semiconductor substrate, forming a first conductive layer on the first insulating layer, and forming a compound insulating layer on the first conductive layer, where the compound insulating layer includes a nitride sub-layer between a lower oxide sub-layer and an upper oxide sub-layer. A second layer insulating layer is formed on the compound insulating layer. A trench is formed extending through the second insulating layer, the compound insulating layer, the first conductive layer, the first insulating layer, and into the semiconductor substrate. The trench is filled with a fill insulating material. An upper portion of the second insulating layer and the fill insulating material is removed. A second conductive layer is formed on the compound insulating layer and on the fill insulating material in the trench.

Description

Related applications

[0001] This application claims the benefits of U.S. Provisional Application No. 63 / 622,000, filed January 17, 2024, and U.S. Patent Application No. 18 / 655,196, filed May 3, 2024. Technical Field

[0002] The present invention relates to non-volatile memory devices, and more particularly, to improving data retention in non-volatile memory cells by preventing electron trapping in the dielectric between floating gates. Background Technology

[0003] Non-volatile memory devices are well known in the art. See, for example, U.S. Patent 7,868,375, which discloses a four-gate memory cell configuration and is incorporated herein by reference for all purposes. Specifically, this application… Figure 1 An example is illustrated of a pair of split-gate memory cells 10, each having spaced-apart source and drain regions 14 / 16 formed in a semiconductor substrate 12. The source region 14 may be referred to as a source line SL (because it is typically connected to other source regions of other memory cells in the same row or column), and the drain region 16 is typically connected to a bit line. A channel region 18 of the semiconductor substrate 12 extends between the source region 14 and the drain region 16. A floating gate 20 is vertically disposed above and insulated from (and directly controls the conductivity of) a first portion of the channel region 18 (and is partially vertically disposed above and insulated from) the source region 14. A control gate 22 is vertically disposed above and insulated from the floating gate 20. A select gate 24 (also referred to as a word line gate) is vertically disposed above and insulated from (and directly controls the conductivity of) a second portion of the channel region 18, and is partially disposed above the drain region 16. An erase gate 26 is vertically disposed above and insulated from the source region 14 and is laterally adjacent to the floating gate 20. The erase gate 26 may include a notch facing the edge of the floating gate 20.

[0004] Multiple such memory cells 10 can be arranged in rows and columns to form a memory cell array, such as Figures 2 to 3 As shown. Although Figure 1 Only one pair of memory cells 10 is shown (sharing a common source region 14 and an erase gate 26), but the memory cell pairs can be arranged end-to-end to form a row of memory cells (where the memory cell pairs can share a common drain region). Although in Figures 2 to 3Only two such columns are shown, but many such columns may exist. Each column may include a bit line 16a that electrically connects all drain regions 16 in that column together. Each row of memory cells 10 may include a control gate line 22a that electrically connects all control gates 22 in that row of memory cells 10 together. For example, all control gates 22 in each row of memory cells may be formed as a continuous line of conductive material, wherein a portion of the continuous line passing through any given memory cell 10 serves as its control gate 22. Each row of memory cells may include a select gate line 24a that electrically connects all select gates 24 in that row of memory cells 10 together. For example, all select gates 24 in each row of memory cells 10 may be formed as a continuous line of conductive material, wherein a portion of the continuous line passing through any given memory cell 10 serves as its select gate 24. Each row of memory cells may include an erase gate line 26a that electrically connects all erase gates 26 in that row of memory cells together. For example, all erase gates 26 in each row of memory cells may be formed as a continuous line of conductive material, wherein a portion of the continuous line passing through any given memory cell pair serves as its erase gate 26. Finally, each row of memory cell pairs may include a source line 14a that electrically connects all source regions 14 together in that row of memory cell pairs. For example, all source regions 14 in each row of memory cell pairs may be formed as a continuous line of conductive diffusion in the semiconductor substrate 12, wherein a portion of the continuous line passing through any given memory cell pair serves as its source region 14.

[0005] The semiconductor substrate 12 may include staggered columns of active regions 12a (forming columns of memory cells 10) and columns of isolation regions 12b (each isolation region 12b is disposed between two adjacent columns of memory cells 10), such as Figure 3 As best shown. Shallow trench isolation (STI) can be used in isolation region 12b to insulate adjacent columns of memory cells 10 from each other. STI may include trenches 28 formed in isolation region 12b of semiconductor substrate 12, the trenches extending in the column direction. Trenches 28 may be filled with insulating material 30, such as oxides (e.g., silicon oxide, silicon dioxide, or a combination of both).

[0006] Various combinations of voltages are applied to the control gate 22, the select gate 24, the erase gate 26, and / or the source region 14 / drain region 16 to program the split-gate memory cell 10 (i.e., inject electrons into the floating gate 20), erase the split-gate memory cell 10 (i.e., remove electrons from the floating gate 20), and read the split-gate memory cell 10 (i.e., measure or detect the conductivity of the channel region 18 by, for example, measuring or detecting the read current through the channel region 18 to determine the programming state of the floating gate 20).

[0007] The split-gate memory cell 10 can be operated digitally, wherein the split-gate memory cell 10 is set to only one of two possible states: a programmed state and an erased state. Alternatively, the split-gate memory cell 10 can be operated analogically, wherein the memory state of the split-gate memory cell 10 (i.e., the amount of charge on the floating gate 20, such as the number of electrons) can change continuously anywhere from a fully erased state (the minimum number of electrons on the floating gate 20) to a fully programmed state (the maximum number of electrons on the floating gate 20), or only a portion of that range. This means that the storage of the split-gate memory cell 10 is analog, which allows for very precise individual tuning of the amount of current supplied by each split-gate memory cell 10 in the array of split-gate memory cells 10. Alternatively, the split-gate memory cell 10 can be operated as an MLC (multilevel cell), wherein the MLC is programmed to one of many discrete values ​​(such as three or more different values).

[0008] To reduce the lateral size and manufacturing cost of memory cells, Figures 1 to 3 In the fabrication of memory cells and arrays of the type shown, it may be desirable to fabricate floating gates 20 such that they are self-aligned with STI trenches 28 and STI insulating material 30. This can be achieved by forming an insulating layer 32 (e.g., oxide) on the upper surface 12c of the semiconductor substrate 12, forming a first conductive layer 34 (e.g., polysilicon or metal) on the insulating layer 32, and forming an insulating layer 36 (e.g., a nitride such as silicon nitride) on the first conductive layer 34, as shown. Figure 4A As shown. The structure can then be patterned using photolithography processes (e.g., photoresist deposition, selective exposure, and partial removal) to expose portions of the underlying insulating layer 36. One or more etching operations are used to remove the exposed portions of the insulating layer 36, the first conductive layer 34, the insulating layer 32, and the semiconductor substrate 12, leaving trenches 28 extending into the semiconductor substrate 12. Trenches 28 can be filled with STI insulating material 30 by depositing an insulating material followed by chemical mechanical polishing, leaving... Figure 4B The structure shown is as follows. Figure 4C As shown, the insulating layer 36 can be removed together with the upper portion of the STI insulating material 30, thereby aligning the edges of the first conductive layer 34 (which will form the floating gate) with the edges of the STI trench 28 and the STI insulating material 30. Further processing may then include forming an insulating layer 38 on the first conductive layer 34, and forming a second conductive layer 40 on the insulating layer 38, as shown. Figure 4D As shown. The second conductive layer 40 can be patterned into strips of conductive layer 40 to form the control gate line 22a described above.

[0009] In memory cell arrays, it is desirable to minimize electron trapping in the dielectric material surrounding the floating gate that occurs during programming operations. Trapped electrons can detach or drift within the dielectric material, causing undesirable changes to the programmed state of the memory cell. Summary of the Invention

[0010] The aforementioned problems and needs are addressed by a method comprising: forming a first insulating layer on an upper surface of a semiconductor substrate; forming a first conductive layer on the first insulating layer; forming a compound insulating layer on the first conductive layer, wherein the compound insulating layer includes a nitride sublayer located between a lower oxide sublayer and an upper oxide sublayer; forming a second insulating layer on the compound insulating layer; forming a trench extending through the second insulating layer, the compound insulating layer, the first conductive layer, the first insulating layer and into the semiconductor substrate; filling the trench with a filling insulating material; removing the upper portion of the second insulating layer and the filling insulating material; and forming a second conductive layer on the compound insulating layer and on the filling insulating material in the trench.

[0011] A method includes: forming a first insulating layer on an upper surface of a semiconductor substrate; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a trench extending through the second insulating layer, the first conductive layer, the first insulating layer, and into the semiconductor substrate; filling the trench with a filling insulating material; removing the upper portion of the second insulating layer and the filling insulating material; forming a compound insulating layer on the first conductive layer and on the filling insulating material in the trench, wherein the compound insulating layer includes a nitride sublayer located between a lower oxide sublayer and an upper oxide sublayer; removing the portions of the upper oxide sublayer and the nitride sublayer disposed on the filling insulating material in the trench; and forming a second conductive layer on the compound insulating layer and on the lower oxide sublayer in the trench.

[0012] A semiconductor device includes a semiconductor substrate, a first conductive material strip, a plurality of floating gates, a second conductive material strip, and a third conductive material strip. The semiconductor substrate includes an upper surface, alternating active regions and isolation regions having a length extending in a parallel manner in a first direction, and a respective isolation region including a trench formed into the upper surface, the trench having a length extending in the first direction and comprising a filling insulating material filling the trench. The first conductive material strip has a length extending in a second direction orthogonal to the first direction and is located above the active and isolation regions. The plurality of floating gates are disposed above and insulated from the upper surface, wherein a respective floating gate is disposed in an active region of the active region, between adjacent isolation regions in the isolation regions, below the first conductive material strip, and insulated from the first conductive material strip by a compound insulating layer, wherein the compound insulating layer includes a nitride sublayer located between a lower oxide sublayer and an upper oxide sublayer, and wherein the nitride sublayer does not extend completely across the isolation regions. The second conductive material strip has a length extending in the second direction and is located above the active and isolation regions. The third conductive material strip has a length extending in the second direction and located above the active region and the isolation region. The first conductive material strip is disposed between the second and third conductive material strips and is insulated from them.

[0013] Other objects and features of this disclosure will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0014] Figure 1 It is a side sectional view of a typical pair of memory cells.

[0015] Figure 2 yes Figure 1 A schematic layout diagram of a conventional memory cell array.

[0016] Figure 3 yes Figure 1 A partial perspective view of a conventional memory cell array.

[0017] Figures 4A to 4D This is a side cross-sectional view illustrating the conventional formation of the floating gate and control gate conductive layers, as well as the intermediate shallow trench isolation (STI) region.

[0018] Figures 5A to 5D This is a side sectional view illustrating a first example of the formation of a floating gate and a control gate conductive layer, as well as an intermediate shallow trench isolation (STI) region.

[0019] Figure 6 This is a partial perspective view of the resulting memory cell array.

[0020] Figures 7A to 7F This is a side sectional view illustrating a second example of the formation of a floating gate conductive layer, a control gate conductive layer, and an intermediate shallow trench isolation (STI) region. Detailed Implementation

[0021] In the process of forming the floating gate of a non-volatile memory cell, as mentioned above... Figures 4A to 4D As described, it may be desirable to use a compound insulating layer (i.e., an insulating layer with sublayers of different insulating materials) as the insulating layer 38 between the first conductive layer 34 and the second conductive layer 40. One such compound insulating layer is ONO, which is a compound insulating layer comprising a nitride sublayer disposed between two oxide sublayers. ONO insulating layers are known in the art and have been used as the insulating layer 38 between the first conductive layer 34 and the second conductive layer 40 (i.e., ONO insulating layers have been used as intermediate insulators between the floating gate and the control gate of a non-volatile memory cell).

[0022] In such Figures 4A to 4D In the memory cell array described above, the ONO insulating layer continuously passes beneath the STI insulating material between the coupled gate line above the floating gate and the floating gate. The inventors have discovered that in non-volatile memory cells such as those described above, unwanted electron trapping can occur in the nitride sublayer of the ONO insulating layer above the STI insulating region during programming operations. Specifically, a significantly larger number of electrons can accumulate in the nitride sublayer of the ONO insulating layer due to the application of multiple programming operations during erase / program cycles. After the cycle, the accumulated electrons can be trapped from the nitride sublayer of the ONO insulating layer under no-bias or biased conditions. Electron trapping can be accelerated by higher temperatures and control gate read voltage bias. The presence of electrons in the nitride sublayer of the ONO insulating layer reduces the electrostatic potential of the floating gate, which in turn leads to a decrease in read current. Due to electron trapping, a significant increase in cell current can occur, which can degrade the memory cell data retention characteristics. Cell current drift can be particularly detrimental to memory cells used in MLC and / or analog data storage applications, which are especially sensitive to cell current drift.

[0023] The inventors have also discovered that by omitting the nitride sublayer of the ONO insulating layer above the STI isolation region, while keeping the nitride sublayer in the region between the floating gate and the control gate, unwanted electron trapping can be reduced or eliminated. Figures 5A to 5D An example of a method for forming a semiconductor device is illustrated, wherein a nitride sublayer can be selectively removed from an isolation region above the STI to reduce or avoid unwanted electron trapping. Active region 50a is shown as adjacent to isolation region 50b, and it should be understood, as above, regarding... Figure 3As described, staggered columns of active regions 50a (where columns of memory cells 10 are formed) and columns of isolation regions 50b are provided. The method begins by forming a first insulating layer 52 (e.g., oxide) on the upper surface 50c of the semiconductor substrate 50, forming a first conductive layer 54 (e.g., polysilicon or metal) on the first insulating layer 52, forming an ONO insulating layer 56 (also referred to herein as a compound insulating layer 56) on the first conductive layer 54, and forming a second insulating layer 58 on the ONO insulating layer 56, as... Figure 5A As shown. The ONO insulating layer includes an upper oxide sublayer 56c on a nitride sublayer 56b, which is on a lower oxide sublayer 56a (i.e., the nitride sublayer 56b is between the upper oxide sublayer 56c and the lower oxide sublayer 56a, wherein the lower oxide sublayer 56a is closer to the substrate 12 than the upper oxide sublayer 56c). This structure can then be patterned using photolithography processes (e.g., photoresist deposition, selective exposure, and partial removal) to expose portions of the underlying second insulating layer 58. One or more etching processes are used to remove the exposed portions of the second insulating layer 58, the ONO insulating layer 56, the first conductive layer 54, the first insulating layer 52, and the semiconductor substrate 50, leaving trenches 60 extending into the semiconductor substrate 50. Trenches 60 can be filled with a filling insulating material 62, also known as STI insulating material 62, by insulating material deposition and subsequent chemical mechanical polishing, leaving Figure 5B The structure shown.

[0024] Then, as Figure 5C As shown, the second insulating layer 58 can be removed together with the upper portion of the filling insulating material 62. Removal of the second insulating layer 58 may include removing the upper oxide sublayer 56c according to the etching type used, thereby allowing oxide formation to be performed to reform the upper oxide sublayer 56c. The second conductive layer 64 can be formed on the ONO insulating layer 56 in the active region 50a and extends across the isolation region 50b, i.e., across the upper oxide sublayer 56c, as shown. Figure 5DAs shown. At this stage, the edge of the first conductive layer 54 in the active region 50a (which will form a floating gate) is aligned with the edge of the STI trench 60, and an insulating material 62 is filled in the isolation region 50b. Furthermore, the first conductive layer 54 and the second conductive layer 64 are insulated from each other by an ONO insulating layer 56 in the active region 50a, wherein a nitride sublayer 56b is removed from the isolation region 50b. The completion of memory cell formation can be performed by patterning the second conductive layer 64 into strips to form control gate lines 64a constituting the control gate 64b in the active region 50a, and by patterning the first conductive layer 54 to form floating gates 54a (i.e., each floating gate 54a is disposed in an active region of the active region 50a below one of the control gates in the control gate 64b). One or more implantations can be performed to form source regions 66 and drain regions 68 in the semiconductor substrate, wherein a channel region 70 extends between these source regions and these drain regions. Additional conductive material deposition and patterning can be performed to form the select gate line 72a constituting the select gate 72 in the active region 50a, and the erase gate line 74a constituting the erase gate 74 in the active region 50a, such as... Figure 6 As shown.

[0025] This method produces a semiconductor device in which memory cells 76 are disposed in an active region 50a, wherein each memory cell 76 has correspondingly spaced source and drain regions 66 / 68 in a semiconductor substrate 50, and wherein a channel region 70 of the semiconductor substrate 50 extends between the source / drain regions 66 / 68. A floating gate 54a is vertically disposed above and insulated from (and directly controls the conductivity of) a first portion of the channel region 70 (and is partially vertically disposed above and insulated from the source region 66). A control gate 64b is vertically disposed above the floating gate 54a and insulated from it by an ONO insulating layer 56 (i.e., the floating gate 54a is located below the control gate 64b). A select gate 72 (also referred to as a word line gate) is vertically disposed above and insulated from (and directly controls the conductivity of) a second portion of the channel region 70, and is partially vertically disposed above and insulated from the drain region 68. The erase gate 74 is vertically disposed above and insulated from the source region 66, and is laterally adjacent to the floating gate 54a. The erase gate 74 may include a notch 74b facing the edge 54b of the floating gate 54a to enhance erase efficiency.

[0026] like Figure 6As shown, there are alternating active regions 50a and isolation regions 50b, which have lengths extending in a parallel manner along a first direction D1. A corresponding isolation region in isolation region 50b includes a trench 60 formed into the upper surface 50c of the semiconductor substrate 50, having a length extending in the first direction, and containing a filling insulating material 62 filling the trench 60. A first conductive material strip 64a (i.e., a control gate line) has a length extending in a second direction D2 orthogonal to the first direction D1 and is disposed above the active regions 50a and 50b. A floating gate 54a is disposed above and insulated from the upper surface 50c. A corresponding floating gate in floating gate 54a is disposed in an active region of active region 50a, between adjacent isolation regions in isolation region 50b, below the first conductive material strip 64a, and insulated from the first conductive material strip 64a by a compound insulating layer 56, wherein at least a nitride sublayer 56b of the compound insulating layer 56 does not extend completely across isolation region 50b. A second conductive material strip 72a (i.e., select gate line) having a length extending in the second direction D2 is disposed above active region 50a and isolation region 50b. A third conductive material strip 74a (i.e., erase gate line) having a length extending in the second direction D2 is disposed above and insulated from source region 66, wherein the first conductive material strip 64a is disposed between and insulated from the second and third conductive material strips 72a and 74a.

[0027] Figures 7A to 7F Another example illustrates the formation of a floating gate that is insulated from the control gate using an ONO insulating layer, whereby the nitride sublayer of the ONO insulating layer does not extend completely across the isolation region 50b. This process uses... Figure 5A The same structure is shown, except that the ONO insulating layer 56 is omitted (i.e., the second insulating layer 58 is formed directly on the first conductive layer 54, as shown). Figure 7A (As shown). The structure can then be patterned using photolithography processes (e.g., photoresist deposition, selective exposure, and partial removal) to expose portions of the underlying second insulating layer 58. One or more etching operations are used to remove the exposed portions of the second insulating layer 58, the first conductive layer 54, the first insulating layer 52, and the semiconductor substrate 50, leaving trenches 60 extending into the semiconductor substrate 50. Trenches 60 can be filled with an insulating material 62 by insulating material deposition and subsequent chemical mechanical polishing, leaving... Figure 7B The structure shown. (As illustrated) Figure 7C As shown, the second insulating layer 58 can be removed together with the upper portion of the filling insulating material 62. At this stage, the upper surface of the filling insulating material 62 can optionally be recessed relative to the upper surface of the second insulating layer 58. Then, an ONO insulating layer 56 is formed over the structure, as shown. Figure 7D As shown.

[0028] A third insulating layer 78 is formed above the structure, and this third insulating layer is patterned to create an opening 78a in the third insulating layer 78 within the isolation region 50b above the filled insulating material 62. Oxide deposition and etching are used to form an oxide spacer 80 in the opening 78a, which removes the upper oxide sublayer 56c from the isolation region 50b and exposes the nitride sublayer 56b in the isolation region 50b. Nitride etching is then used to remove the nitride sublayer 56b in the isolation region 50b, as... Figure 7E As shown. The oxide spacer 80 and the third insulating layer 78 are removed using one or more etching operations. Then, the upper oxide sublayer of the ONO insulating layer is reformed on the nitride layer. A second conductive layer 64 can then be formed on this structure, as shown. Figure 7F As shown. At this stage, the first conductive layer 54 and the second conductive layer 64 are insulated from each other by the ONO insulating layer 56 in the active region 50a, while the nitride sublayer 56b is mostly omitted from the isolation region 50b. The formation of the memory cell can be completed by patterning the second conductive layer 64 into strips to form the control gate line 64a constituting the control gate 64b, forming the source region 66 and the drain region 68, and then performing additional conductive material deposition and patterning to form the select gate line 72a constituting the select gate 72 and the erase gate line 74a constituting the erase gate 74, as described above relative to... Figure 6 As described.

[0029] The above example has the following advantages: combining the omission of the ONO insulating layer between the floating gate 54a and the control gate 64b in the active region with the omission of the nitride sublayer 56b of the ONO insulating layer 56 in the isolation region 50b prevents electron trapping in the ONO insulating layer 56 in the isolation region 50b. Figures 5A to 5D One advantage of this example is that the ONO insulating layer 56 is self-aligned with the floating gate 54a, and the manufacturing method does not require additional photolithography steps. Figures 7A to 7F One advantage of this example is that, due to the formation of the spacer 80, the nitride sublayer 56b extends partially into the isolation region 50b (i.e., beyond the edge of the floating gate 54a), which has the additional benefit of protecting the quality of the lower oxide sublayer of the ONO insulating layer, thereby preventing charge leakage between the edge of the floating gate 54a and the control gate 64b.

[0030] It should be understood that the foregoing is not limited to the examples described above and illustrated herein, but covers any and all variations falling within the scope of any claim. Any references to examples and inventions herein are not intended to limit the scope of any claim or claim terminology, but only to one or more features that may be covered by one or more of these claims. Furthermore, it will be apparent from the claims and specification that not all method operations need to be performed in the precise order illustrated or protected by the claims, but in any order that allows for the proper formation of the semiconductor device described herein (unless there is an explicit limitation on any order). The examples of materials, processes, and values ​​described above are merely illustrative and should not be construed as limiting the scope of the claims.

Claims

1. A method, the method comprising: A first insulating layer is formed on the upper surface of the semiconductor substrate; A first conductive layer is formed on the first insulating layer; A compound insulating layer is formed on the first conductive layer, wherein the compound insulating layer includes a nitride sublayer located between the lower oxide sublayer and the upper oxide sublayer; A second insulating layer is formed on the compound insulating layer; Forming trenches that extend through the second insulating layer, the compound insulating layer, the first conductive layer, the first insulating layer and into the semiconductor substrate; The trench is filled with insulating material; Remove the second insulating layer and the upper portion of the filling insulating material; as well as A second conductive layer is formed on the compound insulating layer and on the filling insulating material in the trench.

2. The method according to claim 1, wherein the method comprises: The second conductive layer is patterned to form a control gate; The first conductive layer is patterned to form a floating gate beneath the control gate; Form a select gate; A source region and a drain region are formed on the semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source region and the drain region, and wherein the floating gate is disposed above and insulated from a first portion of the channel region, and the selection gate is disposed above and insulated from a second portion of the channel region. as well as An erase gate is formed above and insulated from the source region.

3. The method of claim 1, wherein removing the second insulating layer includes removing the upper oxide sublayer, the method comprising: Before forming the second conductive layer, the upper oxide sublayer is reformed on the nitride sublayer.

4. A method, the method comprising: A first insulating layer is formed on the upper surface of the semiconductor substrate; A first conductive layer is formed on the first insulating layer; A second insulating layer is formed on the first conductive layer; Forming trenches that extend through the second insulating layer, the first conductive layer, the first insulating layer and into the semiconductor substrate; The trench is filled with insulating material; Remove the second insulating layer and the upper portion of the filling insulating material; A compound insulating layer is formed on the first conductive layer and on the filling insulating material in the trench, wherein the compound insulating layer includes a nitride sublayer located between the lower oxide sublayer and the upper oxide sublayer; Remove portions of the upper oxide sublayer and the nitride sublayer disposed on the filling insulating material in the trench; as well as A second conductive layer is formed on the compound insulating layer and on the lower oxide sublayer in the trench.

5. The method according to claim 4, wherein the method comprises: The second conductive layer is patterned to form a control gate; The first conductive layer is patterned to form a floating gate beneath the control gate; Form a select gate; A source region and a drain region are formed on the semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source region and the drain region, and wherein the floating gate is disposed above and insulated from a first portion of the channel region, and the selection gate is disposed above and insulated from a second portion of the channel region. as well as An erase gate is formed above and insulated from the source region.

6. The method of claim 4, wherein removing the portion of the upper oxide sublayer and the nitride sublayer comprises: A third insulating layer is formed on the compound insulating layer; An opening is formed in the third insulating layer above the filling insulating material in the trench; A spacer is formed in the opening; Remove the portion of the upper oxide sublayer and the nitride sublayer located between the spacer; as well as Remove the third insulating layer and the spacer.

7. A semiconductor device, the semiconductor device comprising: Semiconductor substrate, the semiconductor substrate comprising: upper surface, Alternating active and isolation regions, the alternating active and isolation regions having a length extending in a parallel manner in a first direction, and The corresponding isolation zone in the isolation zone includes a trench formed in the upper surface, having a length extending in the first direction, and containing a filling insulating material filling the trench; A first conductive material strip, the first conductive material strip having a length extending in a second direction orthogonal to the first direction, and located above the active region and the isolation region; A plurality of floating gates are disposed above and insulated from the upper surface, wherein a corresponding floating gate of the floating gates is: It is located in one of the active regions, between adjacent isolation regions in the isolation region. Located below the first conductive material strip, and Insulated from the first conductive material strip by a compound insulating layer, wherein the compound insulating layer includes a nitride sublayer located between a lower oxide sublayer and an upper oxide sublayer, and wherein the nitride sublayer does not extend completely across the isolation region; A second conductive material strip, the second conductive material strip having a length extending in the second direction above the active region and the isolation region; and A third conductive material strip has a length extending in the second direction above the active region and the isolation region, wherein the first conductive material strip is disposed between and insulated from the second and third conductive material strips.

8. The semiconductor device of claim 7, wherein the corresponding active region in the active region comprises: Source region; Drain region, wherein the channel region of the semiconductor substrate extends between the source region and the drain region; One of the floating gates is disposed above and insulated from the first portion of the channel region; The second conductive material strip is disposed above and insulated from the second portion of the channel region; and The third conductive material strip is disposed above the source region and is insulated from it.

9. The semiconductor device of claim 7, wherein the nitride sublayer does not extend into the isolation region.

10. The semiconductor device of claim 7, wherein the nitride sublayer extends partially into the isolation region.

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