Magnetic storage element, storage device, and writing method

Abstract

A magnetic storage element has a magnetization fixed layer in which a magnetization direction is fixed and a storage layer in which a magnetization direction is reversible, and the storage layer includes a first region including a ferromagnetic material and a second region including an antiferromagnetic material or a ferrimagnetic material.

Description

Technical Field

[0001] This disclosure relates to magnetic storage elements, storage devices, and writing methods. Background Technology

[0002] Magnetic storage elements, such as those disclosed in Patent Documents 1 and 2, are known. Data is written by reversing the magnetization of the storage layer contained in the magnetic storage element.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-155445

[0006] Patent Document 2: International Publication No. 2018 / 179961

[0007] Non-patent literature

[0008] Non-patent literature 1: Mark Fedorov et al., “Phase stability and magnetic properties in fcc Fe-Cr-Mn-Ni alloys from first-principles modeling”, PHYSICALREVIEW B 101, 174416 (2020)

[0009] Non-patent literature 2: Matsui et al., “Magnetic Properties of fcc γ-Phase in the Ternary Co-Mn-Fe System”, JOURNAL OF THE PHYSICAL SOCIETY OF JAPAN, Vol.35, No.2, AUGUST, 1973.

[0010] Non-patent literature 3: Y. Sokolovskaya et al., “A Ternary Map of Ni-Mn-Ga Heusler Alloys from Ab Initio Calculations”, Materials 11, 973 (2021)

[0011] Non-Patent Literature 4: D. Bandyopadhyay et al., “Magnetic phase transitions in Fe80-xNixCr20 (14≤x≤30) alloy studied by using 57Fe Mössbauer spectroscopy”, Hyperfine Interactions, 122, 239 (1999) 239-252 (using Mössbauer spectroscopy). 57 Fe Mössbauer Spectroscopic Studies Fe 80 - x Ni x Cr 20 "Magnetic Phase Transitions in Alloys with 14 ≤ x ≤ 30", in Hyperfine Interactions, Vol. 122, pp. 239-252 (1999)

[0012] Non-Patent Literature 5: Young K. Yoo and Frank Tsui, “Continuous Phase Diagramming of Epitaxial Films”, MRS Bulletin, p316, (2002)

[0013] Non-patent literature 6: T. Newhouse-Illige et al., “Voltage-controlled interlayer coupling in perpendicularly magnetized magnetic tunnel junctions”, NATURECOMMUNICATIONS 2017. Summary of the Invention

[0014] The technical problem that the invention aims to solve

[0015] Suppressing the power consumption of magnetic storage devices is an important issue. Reducing the power consumption required for magnetization reversal in the storage layer may be an effective countermeasure.

[0016] According to one aspect of this disclosure, power consumption is suppressed.

[0017] Technical solutions to solve technical problems

[0018] One aspect of this disclosure of a magnetic storage element includes: a magnetization fixing layer with a fixed magnetization direction and a storage layer with a reversible magnetization direction, wherein the storage layer includes a first region containing ferromagnetic material and a second region containing antiferromagnetic material or ferrimagnetic material.

[0019] One aspect of the storage device disclosed herein includes: a magnetic storage element; and a control circuit for controlling the writing of data to the magnetic storage element, wherein the magnetic storage element includes a magnetization fixing layer whose magnetization direction is fixed and a storage layer whose magnetization direction is reversible, and the storage layer includes a first region containing ferromagnetic material and a second region containing antiferromagnetic material or ferrimagnetic material.

[0020] One aspect of the present disclosure is a data writing method for a magnetic storage element, the magnetic storage element comprising: a magnetization fixing layer with a fixed magnetization direction and a storage layer with a reversible magnetization direction, the storage layer comprising a first region containing ferromagnetic material and a second region containing antiferromagnetic material or ferrimagnetic material, the magnetic storage element having a resistance value corresponding to the magnetization direction of the storage layer, the writing method comprising: applying a voltage, either a positive voltage or a negative voltage, to the magnetic storage element to give the magnetic storage element a resistance value, either a low resistance value or a high resistance value; and applying another voltage, either a positive voltage or a negative voltage, to the magnetic storage element to give the magnetic storage element another resistance value, either a low resistance value or a high resistance value. Attached Figure Description

[0021] Figure 1 This is a diagram illustrating a schematic structural example of the magnetic storage element 1 according to an embodiment.

[0022] Figure 2 This is a diagram showing a schematic structural example of magnetic storage element 1.

[0023] Figure 3 This is a diagram showing an example of the material composition range in region 32 of the second region.

[0024] Figure 4 This is a diagram showing an example of the material composition range in region 32 of the second region.

[0025] Figure 5 This is a diagram showing an example of the material composition range in region 32 of the second region.

[0026] Figure 6This is a diagram showing an example of the material composition range in region 32 of the second region.

[0027] Figure 7 This is a diagram showing an example of the material composition range in region 32 of the second region.

[0028] Figure 8 This is a diagram showing an example of the material composition range in region 32 of the second region.

[0029] Figure 9 This is a diagram showing an example of the material composition range in region 32 of the second region.

[0030] Figure 10 This is a diagram illustrating an example of the electromagnetic characteristics of magnetic storage element 1.

[0031] Figure 11 This is a diagram illustrating an example of the electromagnetic characteristics of magnetic storage element 1.

[0032] Figure 12 This is a diagram illustrating an example of the electromagnetic characteristics of magnetic storage element 1.

[0033] Figure 13 This is a diagram representing a comparative example.

[0034] Figure 14 This is a diagram representing a comparative example.

[0035] Figure 15 This is a graph showing a comparison of the voltage dependence of hysteresis offset in RH loop characteristics.

[0036] Figure 16 This diagram illustrates the effect of the second region 32 on the magnetization reversal of the first region 31.

[0037] Figure 17 This diagram illustrates the effect of the second region 32 on the magnetization reversal of the first region 31.

[0038] Figure 18 This diagram illustrates the effect of the second region 32 on the magnetization reversal of the first region 31.

[0039] Figure 19 This is a diagram showing a schematic structural example of magnetic storage element 1.

[0040] Figure 20 This is a diagram showing a schematic structural example of magnetic storage element 1.

[0041] Figure 21 This is a diagram showing a schematic structural example of magnetic storage element 1.

[0042] Figure 22 This is a diagram illustrating Embodiment 1.

[0043] Figure 23This is a diagram illustrating Embodiment 2.

[0044] Figure 24 This is a diagram illustrating a comparative embodiment.

[0045] Figure 25 The figures show modified embodiments 11 and 12.

[0046] Figure 26 The figures show Embodiment 3, Modified Embodiment 21, and Modified Embodiment 22.

[0047] Figure 27 The figures show modified embodiments 23 and 24.

[0048] Figure 28 The figures show modified embodiments 13, 14 and 25.

[0049] Figure 29 This is a diagram showing modified embodiment 15.

[0050] Figure 30 This is a diagram showing an experimental example of the material in region 32.

[0051] Figure 31 This is a diagram showing an experimental example of the material in region 32.

[0052] Figure 32 The figures show modified embodiments 41 to 45.

[0053] Figure 33 The figures show modified embodiments 46 and 47.

[0054] Figure 34 The figures show modified embodiments 51 and 52.

[0055] Figure 35 The figures show modified embodiments 61 and 62.

[0056] Figure 36 This is a diagram illustrating the principle of writing data to magnetic storage element 1.

[0057] Figure 37 This is a diagram illustrating a schematic structural example of the storage device 7 according to the first embodiment.

[0058] Figure 38 This is a flowchart illustrating an example of the processing (data writing method) performed during data writing.

[0059] Figure 39 This is a diagram illustrating an example of a timing diagram during data writing.

[0060] Figure 40 This is a flowchart illustrating an example of the processing (data reading method) performed during data reading.

[0061] Figure 41 This is a diagram illustrating an example of a timing diagram during data reading.

[0062] Figure 42 This is a flowchart illustrating an example of the processing (data writing method) performed during data writing.

[0063] Figure 43 This is a diagram illustrating an example of a timing diagram during data writing.

[0064] Figure 44 This is a flowchart illustrating an example of the processing (data writing method) performed when data is written.

[0065] Figure 45 This is a diagram illustrating an example of a timing diagram during data writing.

[0066] Figure 46 This is a schematic structural example of the storage device 7 according to the second embodiment.

[0067] Figure 47 This is a flowchart illustrating a process example executed during initialization.

[0068] Figure 48 This is a diagram showing an example of a timing diagram during initialization.

[0069] Figure 49 This is a flowchart illustrating an example of the processing (data writing method) performed when data is written.

[0070] Figure 50 This is a diagram illustrating a schematic structural example of storage device 7.

[0071] Figure 51 This is a diagram illustrating a schematic structural example of the storage device 7 according to the third embodiment.

[0072] Figure 52 This is a flowchart illustrating a processing example executed in AI chip 10.

[0073] Figure 53 This is a flowchart illustrating a processing example executed in AI chip 10.

[0074] Figure 54 This is a diagram showing a variation.

[0075] Figure 55 This is a flowchart illustrating a processing example executed in AI chip 10.

[0076] Figure 56 This is a flowchart illustrating a processing example executed in AI chip 10.

[0077] Figure 57 This is a flowchart illustrating a processing example executed in AI chip 10.

[0078] Figure 58 This is a diagram illustrating a schematic structural example of the storage device 7 according to the fourth embodiment.

[0079] Figure 59 This is a flowchart illustrating a processing example performed in the solid-state imaging device 14.

[0080] Figure 60 This is a flowchart illustrating a processing example performed in the solid-state imaging device 14.

[0081] Figure 61 This is a flowchart illustrating a processing example performed in the solid-state imaging device 14.

[0082] Figure 62 This is a diagram illustrating a schematic structural example of the storage device 7 according to the fifth embodiment.

[0083] Figure 63 This is a diagram showing a variation.

[0084] Figure 64 This is a diagram illustrating a schematic structural example of the storage device 7 according to the sixth embodiment.

[0085] Figure 65 This is a diagram showing a variation. Detailed Implementation

[0086] Hereinafter, embodiments of the present disclosure will be described in detail based on the accompanying drawings. Furthermore, in the following embodiments, the same reference numerals will be used to label the same elements, and repeated descriptions will be omitted.

[0087] This disclosure will be described in the following order of items.

[0088] 0. Preface

[0089] 1. Implementation methods of magnetic storage elements

[0090] 2. Implementation methods of storage devices

[0091] 2.1 First Implementation Method

[0092] 2.2 Second Implementation Method

[0093] 2.3 Third Implementation Method

[0094] 2.4 Fourth Implementation Method

[0095] 2.5 Fifth Implementation Method

[0096] 2.6 Sixth Implementation Method

[0097] 0. Preface

[0098] Because magnetic storage elements are non-volatile and do not require data refresh, they can help reduce the power consumption of storage devices. By using storage devices for various operations in AI (Artificial Intelligence) computing and solid-state imaging devices, it is possible to suppress power consumption during operations or expand the functionality related to operations.

[0099] Patent document 1 discloses a spin-polarized current-driven (STT: Spin Transfer Torque) type magnetic storage element. It is a bipolar current drive that can operate in both positive and negative directions when the current applied to the magnetic storage element is applied. However, in order to improve the retention characteristics, it is necessary to increase the current during data writing, which leads to increased power consumption.

[0100] Patent document 2 discloses a voltage-controlled (VC) magnetic storage element. It utilizes magnetic anisotropic voltage modulation (VCMA) to eliminate the energy barrier between two states with reversed magnetization directions. Magnetization precession is initiated around an in-plane magnetic field, and the voltage is cut off at opportune moments, thereby restoring the barrier and completing magnetization reversal. Because it is voltage-driven, high-speed and low-power data writing is possible. However, since it is a unipolar voltage-driven toggle write, the initial state must be read at the beginning of the write sequence. Furthermore, timing control on the order of approximately 1 ns (nanoseconds) is required during data writing. Technical challenges such as control difficulties still exist.

[0101] According to the technology of this application, the power consumption (voltage, current) required for magnetization reversal is suppressed. The storage layer of the magnetic storage element includes a first region containing ferromagnetic material and a second region containing antiferromagnetic or ferrimagnetic material, details of which will be described later. Utilizing their magnetic coupling, magnetization reversal in the first region is assisted by the second region, reducing the power consumption required for magnetization reversal, i.e., data writing. Voltage writing can also be performed by applying voltage in the positive and negative layer directions. Furthermore, when the magnetization of the storage layer is reversed, there may be asymmetry between their reversal directions.

[0102] In storage devices using the magnetic storage elements described above, a novel method is employed to write data to the magnetic storage elements. Compared to conventional methods, this method can suppress power consumption and achieve high-speed data writing. It also improves data retention performance.

[0103] In one embodiment, magnetic storage elements of different sizes are mixed and arranged. Two types of storage areas can be implemented within a single device, chip, etc., through the same process: a storage area that does not require long-term data retention (e.g., working memory) and a storage area that requires long-term data retention (e.g., storage memory). For example, both short-term and long-term retention areas required in a chip for AI computation (AI function chip) can be provided within the same chip. The same method can also be applied to solid-state imaging devices such as CMOS image sensors. The functions of various conventional memories such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and flash memory are realized using the disclosed magnetic storage elements.

[0104] 1. Implementation methods of magnetic storage elements

[0105] Figure 1 This is a schematic structural example of the magnetic storage element 1 according to the embodiment. The magnetic storage element 1 is an MTJ (magnetic tunnel junction) element with tunnel magnetoresistance (TMR) effect.

[0106] The magnetic storage element 1 includes a magnetization fixing layer 2 and a storage layer 3. An XYZ coordinate system is also shown. The X-axis and Y-axis directions (XY plane directions) correspond to the layer directions. The Z-axis direction corresponds to the layer thickness direction. The positive and negative Z-axis directions are also called the up-down direction, vertical direction, etc. The magnetic storage element 1 is disposed on a substrate such as a Si substrate; in this sense, the negative Z-axis side can also be called the substrate side. The X-axis and Y-axis directions are also called the horizontal direction, etc. It should be noted that "layer" can be understood to include the meaning of "film," and the terms "layer" and "film" can be interchanged as appropriate without contradiction.

[0107] The magnetic storage element 1 can be either a bottom-pin type structure with the magnetized fixing layer 2 located below the storage layer 3, or a top-pin type structure with the magnetized fixing layer 2 located above the storage layer 3. Figure 1 (A) shows a bottom-pinned magnetic storage element 1. A magnetized fixing layer 2 and a storage layer 3 are stacked sequentially along the positive Z-axis. Figure 1 (B) shows a top-pinned magnetic storage element 1. Storage layer 3 and magnetization fixing layer 2 are stacked sequentially along the positive Z-axis. Unless otherwise specified, it is assumed that the magnetic storage element 1 adopts the following configuration: Figure 1 The bottom studded structure shown in (A).

[0108] Magnetization fixing layer 2 is a layer whose magnetization direction is fixed (pinned layer), also known as magnetization fixing layer, fixing layer, etc. Magnetization fixing layer 2 can contain multiple layers. As a layer contained in magnetization fixing layer 2, Figure 1The middle figure shows the immobilization layer 21 and the reference layer 22. For convenience, the description follows the order of reference layer 22 and immobilization layer 21.

[0109] Reference layer 22 is a layer with a fixed magnetization direction, which corresponds to the magnetization direction of magnetization fixed layer 2. Examples of materials for reference layer 22 include Fe, Co, Ni, Mn, B, etc. At least one or more of these can be used as materials for reference layer 22. Alternatively, it can be said that materials selected from a group thereof are used as materials for reference layer 22.

[0110] The immobilization layer 21 is a pinning layer that fixes the magnetization direction of the reference layer 22. Examples of materials for the immobilization layer 21 include Fe, Co, FeCo, Ru, Ir, Pd, and Os. For example, the immobilization layer 21 can be constructed using a SAF (synthetic antiferromagnetic element) structure, where Fe, Co, FeCo, etc., are disposed on opposite sides of each other via Ru, Ir, Pd, and Os. The immobilization layer 21 can be configured to include a perpendicular magnetization film, and examples of materials for the perpendicular magnetization film include Ir, Pt (platinum), Pd, Ru, Ni, Fe, Co, Mn, and Cr. At least one or more of these materials can be used as the immobilization layer 21.

[0111] Storage layer 3 is a layer with reversible magnetization direction, also known as a free layer, etc. Data corresponding to the magnetization direction of storage layer 3, such as bit data "0" or "1", is stored (written) to storage layer 3. Furthermore, "data" can also be understood as "information," and within the bounds of permissibility, "data" and "information" can be interchanged as appropriate.

[0112] Storage layer 3 includes a first region 31 and a second region 32. The first region 31 contains a ferromagnetic material. The second region 32 contains an antiferromagnetic or ferrimagnetic material. The first region 31 and the second region 32 are configured to be magnetically coupled to each other.

[0113] Region 2, 32, only needs to contain layers, magnetic particles, magnetic regions, etc., of antiferromagnetic particles whose microscopically adjacent magnetic moments are arranged antiparallel rather than in the same direction. It does not necessarily have to be an antiferromagnetic phase with microscopically adjacent magnetic moments of the same magnitude that compensate for each other; adjacent antiferromagnetic phases with different magnitudes of magnetic moments that are antiparallel to each other are also acceptable.

[0114] In storage layer 3, region 31 (first region) and region 32 (second region) can have various configurations. (See reference...) Figure 2 Please provide an explanation.

[0115] Figure 2 This is a diagram illustrating a schematic structural example of a magnetic storage element 1. In this example, in addition to the first region 31 and the second region 32, the storage layer 3 of the magnetic storage element 1 also includes a barrier layer 30 and a spacer region 33.

[0116] exist Figure 2 (A) and Figure 2 In the example shown in (B), region 31 and region 32 are stacked. Specifically, region 31, region 32, and spacer region 33 are implemented as layers containing their respective materials. Region 31 is a layer containing ferromagnetic material (ferromagnetic layer). Region 32 is a layer containing antiferromagnetic or ferrimagnetic material (antiferromagnetic layer or ferrimagnetic layer). Spacer region 33 is a layer containing nonmagnetic material (spacer layer).

[0117] exist Figure 2 In the example shown in (A), the magnetized fixing layer 2, the barrier layer 30, the second region 32, the spacing region 33, and the first region 31 are sequentially stacked along the positive Z-axis. Figure 2 In the example shown in (B), the magnetized fixing layer 2, the barrier layer 30, the first region 31, the spacing region 33 and the second region 32 are stacked sequentially along the positive Z-axis.

[0118] The thickness of region 31 can be, for example, greater than 0.1 nm and less than 1.5 nm. When the thickness is too large, it is difficult to obtain perpendicular magnetic anisotropy. When the thickness is too small, it is difficult to obtain stable magnetization (state).

[0119] The first region 31 can be crystal-oriented with the barrier layer 30 to have a single crystal structure oriented in the (001) plane of the body-centered cubic structure or a polycrystalline structure with preferred orientation in the (001) plane, so as to obtain a good TMR ratio.

[0120] The thickness of the second region 32 can be, for example, greater than 0.1 nm and less than 5 nm. This does not make magnetization reversal too difficult, but makes it easy to obtain the desired magnetization reversal assist effect.

[0121] exist Figure 2 In the example shown in (C), the storage layer 3 includes a plurality of first regions 31 and second regions 32 disposed separately. The first regions 31 and second regions 32 are disposed separately within the storage layer 3, for example, in the form of particles, grains, magnetic domains, etc. In this example, there is a spacer region 33 between the first regions 31 and the second regions 32, but there may be no spacer region 33.

[0122] A barrier layer 30 is disposed between the first region 31 and the second region 32 of the storage layer 3 and the magnetization fixation layer 2 to obtain the TMR effect. The barrier layer 30 is also called a tunnel barrier layer, tunnel barrier layer, etc.

[0123] Examples of materials for the barrier layer 30 are oxides such as MgO. Examples of materials that serve as the basis for oxides include Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C. Oxides containing at least one or more of these can be used as materials for the barrier layer 30.

[0124] For example, Mg oxide, i.e., MgO, can be used as the material for barrier layer 30. To stabilize barrier performance (barrier resistance, etc.), other materials can be added. Examples of other materials include Fe, Co, and Mn. The amount of Fe, Co, or Mn added can be, for example, 20 at% (atomic percentage) or less. The lower limit is only required to be greater than 0 at%. Preferred addition amounts include 1 at%, 5 at%, and 10 at%. From the viewpoint of obtaining a stable TMR ratio (tunneling magnetoresistance ratio), the sheet resistance of barrier layer 30 can be 1 mΩ / μm. 2 above.

[0125] Other examples of materials for the barrier layer 30 include Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. Oxides containing at least one or more of these materials can also be used as materials for the barrier layer 30.

[0126] A spacer region 33 is disposed between the first region 31 and the second region 32 in such a way that the first region 31 and the second region 32 are magnetically coupled to each other. The magnetization of the second region 32 acts on the magnetization of the first region 31 via the spacer region 33. More specifically, the magnetization direction of the first region 31 changes as the magnetization direction of the second region 32 changes, thereby assisting in the reversal of the magnetization of the first region 31.

[0127] Spacer region 33 contains a non-magnetic material. Examples of non-magnetic materials are Ta, Ru, Ir, W, Mo, Rh, Re, Nb, Cu, Cr, V, TiN, TaN, WN, etc. At least one or more of these can be used as the material for spacer region 33. The thickness of spacer region 33 can be, for example, greater than 0.1 nm and less than 1.5 nm. If the thickness of spacer region 33 is less than 0.1 nm, the effect of spacer region 33 becomes smaller, for example, it is easy for the magnetic material components of the first region 31 or the second region 32 to diffuse into each other. If the thickness of spacer region 33 is greater than 1.5 nm, it is difficult to obtain interlayer coupling between the second region 32 and the first region 31.

[0128] More specific descriptions are given of the materials for Region 1 31 and Region 2 32. For example, at least one or more of Co, Fe, Ni, Mn, Al, B, P, C, Zr, Hf, Ta and Nb can be used as the material for Region 1 31.

[0129] An example of a combination of multiple materials is CoFeB. The composition ratio of Co, Fe, and B is designed to achieve perpendicular magnetic anisotropy. For example, the composition ratio of Fe can be greater than that of Co. The composition ratio of B can be below 40 at%. The lower limit only needs to be greater than 0 at%. Examples of lower limit values ​​are 1 at%, 5 at%, 10 at%, etc.

[0130] As the material for region 32, at least one or more of Mn, Cr, Ir, Pt, Pd, Ni, Sn, Fe, Ge, Co, Ga and Si may be used.

[0131] Examples of combinations of materials, more specifically antiferromagnetic or ferrimagnetic alloys, include FeNiMn, CrNiMn, FeCrMn, FeCoMn, CoNiMn, FeNiCr, GaNiMn, CoPtMn, FePMn, FeMn, NiMn, FeNi, PtMn, PdMn, and CoGeMn. Antiferromagnetic or ferrimagnetic phases derived from these alloys can be obtained.

[0132] In one embodiment, the material of region 32 may comprise rare earth materials and metallic materials. Examples of rare earth materials include Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. Examples of metallic materials include Fe, Co, Ni, and Mn. Combinations of at least one rare earth material and at least one metallic material described herein, such as GdFeCo, GdFe, GdCo, TbFeCo, TbFe, TbCo, DyFeCo, DyFe, DyCo, etc., may be used as the material of region 32.

[0133] In one embodiment, the material of the second region 32 may comprise Mn chalcogenides. Examples of Mn chalcogenides are CuMnAs and MnPS3, etc.

[0134] In one embodiment, the material of the second region 32 may comprise an oxide. Examples of oxides include NiO, Cr2O3, CoO, Fe2O3, and Mn2O3.

[0135] Reference Figures 3-9 Describe the composition range of several materials.

[0136] Figures 3 to 9 This is a diagram showing an example of the material composition range of region 32. Each diagram shows a ternary diagram of the composition range.

[0137] Figure 3 The composition range of region 32 is shown when the material is FeNiMn. x Niy Mn z The composition range is shown below. An antiferromagnetic phase or a subferromagnetic phase, as shown in Non-Patent Document 1, can be obtained.

[0138] 0at%<x≤95at%

[0139] 0at%<y≤80at%

[0140] 5at%≤z≤80at%

[0141] The lower limit for x can be greater than 0 at%. Examples of lower limits are 1 at%, 5 at%, 10 at%, etc. The same applies to the lower limit for y.

[0142] Figure 4 The compositional range of region 32 is shown when the material is CrNiMn. Cr x Ni y Mn z The composition range is shown below. An antiferromagnetic phase or a subferromagnetic phase, as shown in Non-Patent Document 1, can be obtained.

[0143] 0at%≤x≤65at%

[0144] 0at%≤y≤75at%

[0145] 0at%≤z≤80at%

[0146] The lower limit for x can be greater than 0 at%. Examples of lower limits are 1 at%, 5 at%, 10 at%, etc. The same applies to the lower limits for y and z.

[0147] Figure 5 The composition range of region 32 is shown when the material is FeCrMn. x Cr y Mn z The composition range is shown below. An antiferromagnetic phase or a subferromagnetic phase, as shown in Non-Patent Document 1, can be obtained.

[0148] 0at%<x≤95at%

[0149] 0at%<y≤70at%

[0150] 5at%≤z≤80at%

[0151] The lower limit for x can be greater than 0 at%. Examples of lower limits are 1 at%, 5 at%, 10 at%, etc. The same applies to the lower limit for y.

[0152] Figure 6 The composition range of region 32 is shown when the material is FeCoMn. Fe x Coy Mn z The composition range is shown below. An antiferromagnetic phase, as shown in Non-Patent Document 2, can be obtained.

[0153] 0at%≤x≤95at%

[0154] 0at%≤y≤50at%

[0155] 5at%≤z≤80at%

[0156] The lower limit for x can be greater than 0 at%. Examples of lower limits are 1 at%, 5 at%, 10 at%, etc. The same applies to the lower limit for y.

[0157] Figure 7 The composition range of region 32 is shown when the material is GaNiMn. x Ni y Mn z The composition range of the alloy is shown below. A ferrimagnetic phase, as shown in Non-Patent Document 3, can be obtained.

[0158] 0at%≤x≤50at%

[0159] 5at%≤y≤80at%

[0160] 5at%≤z≤90at%

[0161] The lower limit of x can be greater than 0 at%. Examples of lower limit values ​​are 1 at%, 5 at%, 10 at%, etc.

[0162] Figure 8 The composition range of region 32 is shown when the material is FeNiCr. x Ni y Cr z The composition range is shown below. A ferrimagnetic phase, as shown in Non-Patent Document 4, can be obtained.

[0163] 60at%≤x≤82at%

[0164] 15at%≤y≤40at%

[0165] 10at%≤z≤35at%

[0166] Figure 9 The composition range of region 32 is shown when the material is CoGeMn. Co x Ge y Mn z The composition range is shown below. An antiferromagnetic phase, as shown in Non-Patent Document 5, can be obtained.

[0167] 0at%≤x≤20at%

[0168] 0at%≤y≤95at%

[0169] 5at%≤z≤100at%

[0170] The upper limit of z can be less than 100at%. Examples of upper limits are 99at%, 95at%, 90at%, etc.

[0171] The aforementioned alloys exhibit antiferromagnetic or ferrimagnetic phases derived from the ordered alloying of their constituent elements. For example, FeNiMn, CrNiMn, FeCrMn, FeCoMn, and GaNiMn exhibit antiferromagnetic or ferrimagnetic phases derived from the ordered alloying of FeMn, NiMn, CoMn, CrFe, and NiFe contained therein. It can be said that the other materials mentioned above are similarly exhibiting this characteristic.

[0172] The characteristics of the magnetic storage element 1 in this embodiment are also reflected in its electromagnetic properties. (Refer to...) Figures 10 to 12 Please provide an explanation.

[0173] Figures 10 to 12 This is a diagram illustrating an example of the electromagnetic characteristics of magnetic storage element 1. Magnetic storage element 1 exhibits an RH hysteresis loop characteristic, where the resistance value varies with the magnitude of the applied magnetic field. The resistance value of magnetic storage element 1 is also referred to as the resistance value R. The applied magnetic field is also referred to as the magnetic field H.

[0174] Figure 10 The RH hysteresis characteristic of magnetic storage element 1 is shown as a graph. The horizontal axis of the graph represents the magnitude of the magnetic field H. The vertical axis of the graph represents the resistance value R. Furthermore, the voltage applied to magnetic storage element 1, more specifically the voltage applied from the upper electrode (corresponding to the capping layer 6) side to the substrate side, is called voltage V. Voltage V can also be called bias voltage, applied voltage, etc.

[0175] Figure 10 The diagram illustrates multiple RH hysteresis loop characteristics corresponding to different voltages V. More specifically, three RH hysteresis loop characteristics are shown as graphs C1, C2, and C3. Graph C1 shows the RH hysteresis loop characteristic when no voltage V is substantially applied to the magnetic storage element 1, i.e., voltage V≈0 (e.g., about 0mV, a few mV, or tens of mV). Graph C2 shows the RH hysteresis loop characteristic when a positive voltage (voltage V>0) is applied to the magnetic storage element 1. Graph C3 shows the RH hysteresis loop characteristic when a negative voltage (voltage V<0) is applied to the magnetic storage element 1.

[0176] When no voltage V is applied to the magnetic storage element 1 (voltage V≈0), the magnetic storage element 1 can have any resistance value between low and high resistance values ​​in the state without a magnetic field (magnetic field H=0), and can store any information in the high-resistance state and the low-resistance state. Furthermore, when a positive magnetic field is applied to the magnetic storage element 1 in the high-resistance state, it switches to the low-resistance state under the positive magnetic field H, and when a negative magnetic field H is applied to the magnetic storage element 1 in the low-resistance state, it switches to the high-resistance state.

[0177] On the other hand, as shown in curves C2 and C3, when a positive voltage or a negative voltage is applied, the magnetic storage element 1 has one of two resistance values: a low resistance value or a high resistance value. When the other voltage is applied, the magnetic storage element 1 has the other resistance value. More specifically, for example, when a sufficiently large positive voltage V is applied, as shown in curve C2, the RH loop characteristic shifts, causing both the magnetic field H switching from the high-resistance state to the low-resistance state of the magnetic storage element 1 and the magnetic field H switching from the low-resistance state to the high-resistance state of the magnetic storage element 1 to become negative. Therefore, even without applying a magnetic field H (external magnetic field), the switching from high resistance to low resistance can be achieved by applying a positive voltage V to the magnetic storage element 1. Similarly, when a sufficiently large negative voltage V is applied, as shown in curve C3, the RH loop characteristic shifts, causing both the magnetic field H switching from the low-resistance state to the high-resistance state of the magnetic storage element 1 and the magnetic field H switching from the high-resistance state to the low-resistance state of the magnetic storage element 1 to become positive. Therefore, even without applying a magnetic field H, the switching from low resistance to high resistance can be achieved by applying a negative voltage V to the magnetic storage element 1. That is, the resistance value of the magnetic storage element 1 can be switched in accordance with the sign of the voltage V applied to it.

[0178] In other words, as shown by line C2, when a positive voltage (voltage V>0) is applied to magnetic storage element 1, magnetic storage element 1 has a low resistance value. As shown by line C3, when a negative voltage (voltage V<0) is applied to magnetic storage element 1, magnetic storage element 1 has a high resistance value.

[0179] Please pay attention to the RH hysteresis characteristics, especially the voltage dependence of its hysteresis. The hysteresis of the RH hysteresis characteristic when a positive voltage is applied to the magnetic storage element 1 and the hysteresis of the RH hysteresis characteristic when a negative voltage is applied to the magnetic storage element 1 are offset from the hysteresis of the RH hysteresis characteristic when no voltage V is actually applied to the magnetic storage element 1 (voltage V≈0). Here, the offset refers to the offset along the horizontal axis of the curve, in other words, the offset along the direction of the magnitude of the magnetic field H.

[0180] Furthermore, as shown in line C1, the hysteresis of the RH hysteresis loop characteristic of the magnetic storage element 1 when no voltage V is substantially applied crosses the magnetic field H=0. As mentioned above, the resistance value of the magnetic storage element 1 can be either high or low.

[0181] In contrast, as shown by line C2, the hysteresis of the RH hysteresis loop characteristic when a positive voltage (voltage V>0) is applied to magnetic storage element 1 does not cross the magnetic field H=0. The resistance value of magnetic storage element 1 is uniquely determined to be a low resistance value and can be switched. Furthermore, as shown by line C3, the hysteresis of the RH hysteresis loop characteristic when a negative voltage (voltage V<0) is applied to magnetic storage element 1 does not cross the magnetic field H=0. The resistance value of magnetic storage element 1 is uniquely determined to be a high resistance value and can be switched.

[0182] As described above, in the magnetic storage element 1, the hysteresis of the RH hysteresis loop characteristic shifts with the sign of the voltage V. Furthermore, this shift can be asymmetrical when the voltage V is positive and negative. The hysteresis of the RH characteristic when a positive or negative voltage is applied to the magnetic storage element 1 is greater than the hysteresis of the RH hysteresis loop characteristic when no voltage V is substantially applied to the magnetic storage element 1. Conversely, the hysteresis of the RH characteristic when another positive or negative voltage is applied to the magnetic storage element 1 is less than the hysteresis of the RH hysteresis loop characteristic when no voltage V is substantially applied. That is, compared to the hysteresis of the RH characteristic when a negative voltage V is applied to the magnetic storage element 1, the difference in the magnitude of the magnetic field H, i.e., the coercivity Hc, during the transition from a high-resistivity state to a low-resistivity state or from a low-resistivity state to a high-resistivity state, is smaller.

[0183] Specifically, in Figure 10 In the examples shown, as indicated by line C2, the hysteresis of the RH characteristic when a positive voltage (V>0) is applied to the magnetic storage element 1 is compared to the hysteresis of the RH loop characteristic when no voltage V is applied to the magnetic storage element 1 (V≈0), as shown by line C1. The switching magnetic field H shifts negatively, and the difference between the magnetic field H (coercivity Hc) between the high-resistivity state and the low-resistivity state becomes larger. Conversely, as indicated by line C3, the hysteresis of the RH characteristic line when a negative voltage (V<0) is applied to the magnetic storage element 1 is compared to the hysteresis of the RH loop characteristic when no voltage V is applied to the magnetic storage element 1 (V≈0), as shown by line C1. The switching magnetic field H shifts positively, and the difference between the magnetic field H (coercivity Hc) between the high-resistivity state and the low-resistivity state becomes smaller.

[0184] As described above, in the magnetic storage element 1 of the embodiment, by applying a positive or negative voltage V, the hysteresis of the RH loop characteristic is shifted to the positive or negative side, thereby enabling the resistance value to be low or high.

[0185] Figure 11Numerous RH loop characteristics corresponding to different voltages V are shown. From the top to the bottom line, the voltage V gradually changes from positive to negative. It can be seen that the offset of the RH loop characteristics varies depending on the applied voltage V. This offset can be altered by specifically designing the material composition and film thickness of the storage layer of the magnetic storage element 1.

[0186] Figure 12 The RV and IV characteristics (IV loop characteristics) of magnetic storage element 1 are shown. The horizontal axis of the graph represents voltage V, and the vertical axis represents current I. The magnetic field H is 0 (zero).

[0187] As shown by arrow AR1, when a positive voltage V is applied, the resistance value changes from high to low, and the current value I increases sharply. Conversely, as shown by arrow AR2, when a negative voltage V is applied, the resistance value changes from low to high, and the current value I decreases sharply. This change in resistance signifies a reversal of the magnetization of the first region 31 of the storage layer 3 of the magnetic storage element 1. The current required for this reversal is, for example, only a few μA to tens of μA, which is significantly lower than the tens of μA required when fabricating the same element using conventional spin-transfer MRAM, enabling lower power consumption.

[0188] The above effects are further illustrated using comparative examples.

[0189] Figure 13 and Figure 14 This is a diagram showing a comparative example. Figure 13 The magnetic storage element 1E of the comparative example and the magnetic storage element 1 of the embodiment are shown. Figure 1 Compared to (etc.), the difference is that storage layer 3 does not include the second region 32. Figure 14 Several RH hysteresis loop characteristics corresponding to different voltages V are shown. Specifically, line C11 represents the RH hysteresis loop characteristics when no voltage V is substantially applied to the magnetic storage element 1, i.e., when voltage V≈0. Line C12 represents the RH hysteresis loop characteristics when a positive voltage (voltage V>0) is applied to the magnetic storage element 1. Line C13 represents the RH hysteresis loop characteristics when a negative voltage (voltage V<0) is applied to the magnetic storage element 1.

[0190] As understood, the above will not occur. Figure 10 The offset of the magnetic storage element 1 in the embodiment makes it difficult to perform magnetization reversal using the offset in the magnetic storage element 1E.

[0191] Figure 15 This is a graph comparing the voltage dependence of the hysteresis offset of the RH loop characteristics. The variation of the RH loop characteristics corresponding to voltage V is schematically shown. In the magnetic storage element 1 of the embodiment, as... Figure 15As shown in (A) and (B), the hysteresis of the RH loop characteristic shifts in response to the application of voltage V, such that the hysteresis of the RH loop characteristic does not cross the magnetic field H=0. Therefore, magnetization reversal can be achieved based on the application of voltage V.

[0192] On the other hand, according to the magnetic storage element 1E of the comparative example, such as Figure 15 As shown in (C) and (D), although the increase or decrease of coercivity due to the VCMA effect (voltage magnetic anisotropy modulation effect) can be observed in the RH loop characteristics in response to the application of voltage V, this hysteresis shift is insufficient for voltage-based switching. Therefore, magnetization reversal is difficult to achieve by simply applying voltage V. For example, it is necessary to precess magnetization around an in-plane magnetic field as an axis, as described in Patent Document 2 above, and to stop applying voltage V at appropriate times.

[0193] As described above, in the magnetic storage element 1 of the embodiment, the second region 32 assists in reversing the magnetization of the first region 31 of the storage layer 3. This mechanism will be explained for example below.

[0194] When a voltage V is applied to the magnetic storage element 1, the polarization direction of the second region 32 changes due to the accumulation or spin injection of spin-polarized carriers. Subsequently, due to the exchange bias between the second region 32 and the first region 31, the magnetization of the first region 31 is reversed (the reversal is assisted). See also... Figures 16 to 18 Please provide an explanation.

[0195] Figures 16 to 18 This diagram illustrates the effect of the second region 32 on the magnetization reversal of the first region 31. The magnetization directions of the first region 31 and the second region 32 of the magnetization fixing layer 2 and the storage layer 3 are also schematically shown with white arrows. Furthermore, it is assumed that the magnetization direction of the magnetization fixing layer 2 is fixed in the positive Z-axis direction. As mentioned earlier, the voltage applied to the magnetic storage element 1 is called voltage V. Assuming that voltage V is a voltage other than 0 (zero), it is a sufficiently large applied voltage in the positive or negative direction, a voltage that can cause magnetization reversal in the first region 31.

[0196] Figure 16 The magnetic storage element 1 shown includes the aforementioned Figure 2 (A) Similar structure. Figure 16 (A) shows the state where no voltage V is applied to the magnetic storage element 1. In this example, the magnetization direction of the first region 31 is negative Z-axis.

[0197] To reverse the magnetization direction of the first region 31, a voltage V is applied to the magnetic storage element 1. In response, firstly as follows... Figure 16 As shown in (B), the magnetization in region 32 is reversed. The exchange coupling between region 32 (magnetization reversed) and region 31 (magnetization reversed) assists (facilitates) the magnetization reversal of region 31. Then as... Figure 16As shown in (C), the magnetization of region 31 in the first region is reversed.

[0198] Figure 17 The magnetic storage element 1 shown includes the same as described above. Figure 2 (B) Similar structure. Figure 17 (A) shows the state where no voltage V is applied to the magnetic storage element 1. In this example, the magnetization direction of the first region 31 is negative Z-axis.

[0199] To reverse the magnetization direction of the first region 31, a voltage V is applied to the magnetic storage element 1. In response, firstly as follows... Figure 17 As shown in (B), the magnetization in region 32 is reversed. The magnetization reversal of region 31 is aided by the exchange coupling between region 32 (magnetization reversal) and region 31. Then, as... Figure 17 As shown in (C), the magnetization of region 31 in the first region is reversed.

[0200] Figure 18 The magnetic storage element 1 shown includes the same as described above. Figure 2 (C) similar structure. Figure 18 (A) shows the state where no voltage V is applied to the magnetic storage element 1. In this example, the magnetization direction of the first region 31 is negative Z-axis.

[0201] To reverse the magnetization direction of the first region 31, a voltage V is applied to the magnetic storage element 1. In response, firstly as follows... Figure 18 As shown in (B), the magnetization in region 32 is reversed. The magnetization reversal of region 31 is aided by the exchange coupling between region 32 (magnetization reversal) and region 31. Then, as... Figure 18 As shown in (C), the magnetization of region 31 in the first region is reversed.

[0202] In the aforementioned magnetic storage element 1, the storage layer 3 includes not only a first region 31 but also a second region 32. Through magnetic coupling (interphase coupling, exchange coupling, etc.) between the first region 31 and the second region 32, an effect assisting in the magnetization reversal of the first region 31 can be achieved. This suppresses the power consumption (voltage, current) required for magnetization reversal and also enables high-speed reversal. Data writing, i.e., voltage writing, can be performed by applying layer-wise positive and negative voltages to the magnetic storage element 1.

[0203] Furthermore, in the magnetic storage element 1 of the embodiment, the magnetization of the first region 31 can be reversed using an unprecedented novel method, wherein for the RH circuit characteristics, a shift occurs including its hysteresis, rather than changing the coercivity by applying a voltage as in VCMA. Low-power drive for magnetization reversal by bidirectional voltage bias can be achieved. For example, problems such as the need for large currents for magnetization reversal as in conventional SST, or the requirement for 1ns short pulse control in a single direction as in VCMA, can be addressed.

[0204] <Variation Example>

[0205] The more specific structure of the magnetic storage element 1 will be described as several variations.

[0206] In one embodiment, the storage layer 3 of the magnetic storage element 1 may include other barrier layers separate from the barrier layer 30. This can improve heat resistance, magnetization reversal efficiency, etc. (See reference...) Figures 19 to 21 Please provide an explanation.

[0207] Figure 19 This is a diagram illustrating a schematic structural example of the magnetic storage element 1. (Similar to the above...) Figure 2 Compared to the structure of the magnetic storage element 1, the storage layer 3 also includes a barrier layer 34.

[0208] The barrier layer 34 is a second barrier region (barrier layer) disposed on the side opposite to the magnetization fixing layer 2, separated from the first region 31 and the second region 32. The material of the barrier layer 34 can be the same as that of the barrier layer 30. An example is an oxide such as MgO. Examples of base materials for the oxide include Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, C, etc. Oxides containing at least one or more of these can be used. Furthermore, as an example, to stabilize barrier performance (barrier resistance, etc.), Fe, Co, Mn, etc., can be added to MgO. The amount of Fe, Co, or Mn added can be, for example, 20 at% (atomic percentage) or less. The lower limit only needs to be greater than 0 at%. Preferred examples of added amounts are 1 at%, 5 at%, 10 at%, etc. From the viewpoint of obtaining a stable TMR ratio (tunneling magnetoresistance ratio), it is preferable that the sheet resistivity of the barrier layer 34 is lower than that of the barrier layer 30. Furthermore, as an example, oxides of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc., including at least one or more of these oxides, can also be used as materials for the barrier layer 34. For example, as shown in Non-Patent Document 6, it is expected that the storage layer 3 can obtain an inversion assist effect due to voltage application via the barrier layer 34. Additionally, antiferromagnetic oxides such as NiO, Cr2O3, CoO, Fe2O3, and Mn2O3 can also be used as materials for the barrier layer 34.

[0209] Other ferromagnetic layers can be disposed on the barrier layer 34, outside of the magnetization fixation layer 2. (See reference...) Figure 20 Please provide an explanation.

[0210] Figure 20 This is a diagram illustrating a schematic structural example of the magnetic storage element 1. (Similar to the above...) Figure 19 In contrast, the magnetic storage element 1 also includes a ferromagnetic layer 4. The ferromagnetic layer 4 is disposed on the side of the barrier layer 34 opposite to the first region 31 and the second region 32, separated by the barrier layer 34. The material of the ferromagnetic layer 4 can be the same as that of the magnetization fixing layer 2. The magnetization fixing layer 2 sandwiching the barrier layer 30 and the first region 31, and the first region 31 sandwiching the second region 32 and the ferromagnetic layer 4, provide the functionality of two MTJ elements (dual MTJ).

[0211] In one embodiment, the magnetic storage element 1 may include other spacer regions in addition to the spacer region 33, more specifically, spacer layers. (See also...) Figure 21 Please provide an explanation.

[0212] Figure 21 This is a diagram illustrating a schematic structural example of the magnetic storage element 1. (Similar to the above...) Figure 20In contrast, the magnetic storage element 1 differs in that it does not include a barrier layer 34 but includes a spacer layer 35. The spacer layer 35 is disposed on the side opposite to the magnetization fixing layer 2, separating the first region 31 and the second region 32. The ferromagnetic layer 4 is disposed on the spacer layer 35, on the side opposite to the first region 31 and the second region 32, separated by the spacer layer 35. The material of the spacer layer 35 can be the same as the material of the spacer region 33. A stacked subferromagnetic structure (SAF) in which the storage layer 3 is antiferromagnetically coupled via the spacer layer 35 can be obtained.

[0213] <Example>

[0214] Several embodiments and variations based on the magnetic storage element 1 described above will be described.

[0215] <Example 1>

[0216] Figure 22 This is a diagram illustrating Embodiment 1. (As shown...) Figure 22 As shown in (A), the magnetic storage element 1 includes a lower electrode layer 5 (base layer), a magnetization fixing layer 2, a storage layer 3 and a capping layer 6 (upper electrode layer) stacked sequentially along the positive Z-axis.

[0217] The materials and thicknesses of each layer (except for the thickness of immobilization layer 21) are also shown. Here, Å (angstrom) is used as the unit of thickness, but it can be converted to nm (nanometer) as appropriate. Furthermore, for layers containing a certain material, the name of that material is appended to the layer name. For example, a layer containing Ta is called the Ta layer.

[0218] The lower electrode layer 5 has a stacked structure comprising a Ta layer and a Ru layer. The thickness of the Ta layer is 50 Å. The thickness of the Ru layer is 100 Å.

[0219] The magnetization immobilization layer 2 comprises an immobilization layer 21 and a reference layer 22 stacked sequentially along the positive Z-axis. The immobilization layer 21 has a stacked structure comprising a Co layer, an Ir layer, a Co layer, and a PtCo layer. The thickness of each layer is, for example, 6 Å for Co, 5 Å for Ir, and 6 Å for Co. The reference layer 22 is a CoFeB layer with a thickness of 10 Å.

[0220] Storage layer 3 comprises a barrier layer 30, a first region 31, a spacer region 33, a second region 32, and a barrier layer 34, stacked sequentially along the positive Z-axis. The barrier layer 30 of storage layer 3 is a 20 Å thick MgFeO layer. The first region 31 is a 6 Å thick CoFeB layer (or any thickness between 6 Å and 8 Å). The spacer region 33 is a 2.5 Å thick Mo layer. The second region 32 is a 10 Å thick FeNiMn layer (or any thickness between 7 Å and 10 Å). The barrier layer 34 is a 6 Å thick MgO layer.

[0221] Cap layer 6 has a layered structure consisting of Ta and Ru layers. The thickness of the Ta layer is 30 Å. The thickness of the Ru layer is 100 Å.

[0222] The magnetic storage element 1 is manufactured by forming films of the aforementioned materials on a Si substrate with circuitry, and performing device fabrication processes such as patterning using photolithography, hard mask formation, ion polishing, and electrode PAD formation. The magnetic storage element 1 has a circular shape with a diameter of approximately 80 nm when viewed from above (along the Z-axis).

[0223] As an evaluation result of the magnetic field tester, Figure 22 Figure (B) shows the RH hysteresis characteristics. Curve C1 represents the RH hysteresis characteristics at voltage V = +10mV. Curve C2 represents the RH hysteresis characteristics at voltage V = +1000mV. Curve C3 represents the RH hysteresis characteristics at voltage V = -1000mV.

[0224] The hysteresis offset of the RH loop characteristic corresponding to the applied voltage, as described above, was confirmed. With magnetic field H=0, magnetic storage element 1 exhibits low resistance when a positive voltage (voltage V>0) is applied. When a negative voltage (voltage V<0) is applied, magnetic storage element 1 exhibits high resistance.

[0225] Figure 22 (C) illustrates the IV characteristic. As shown by arrow AR1, when a positive voltage V, for example, approximately +300mV, is applied, the resistance changes from high to low, and the current I increases sharply. The current required for magnetization reversal (reversal current) is approximately 5.5μA. Conversely, as shown by arrow AR2, when a negative voltage V, for example, approximately -300mV, is applied, the resistance changes from low to high, and the current I decreases sharply. The reversal current is approximately 14μA.

[0226] <Example 2>

[0227] Figure 23 This is a diagram illustrating Example 2. Only the main differences from Example 1 will be described. Figure 23 As shown in (A), the storage layer 3 of the magnetic storage element 1 includes a barrier layer 30, a second region 32, a spacer region 33, and a barrier layer 34 stacked sequentially along the positive Z-axis. The second region 32 is an FeCoMn layer with a thickness of 10 Å (or any thickness between 7 Å and 10 Å).

[0228] Figure 23 (B) shows the RH hysteresis characteristic. Graph C1 shows the RH hysteresis characteristic at voltage V = +10mV. Graph C2 shows the RH hysteresis characteristic at voltage V = +1200mV. Graph C3 shows the RH hysteresis characteristic at voltage V = -1200mV.

[0229] The hysteresis offset of the RH loop characteristic corresponding to the applied voltage, as described above, was confirmed. With magnetic field H=0, magnetic storage element 1 exhibits low resistance when a positive voltage (voltage V>0) is applied. When a negative voltage (voltage V<0) is applied, magnetic storage element 1 exhibits high resistance.

[0230] Figure 23 (C) illustrates the IV characteristic. As shown by arrow AR1, when a positive voltage V, for example, approximately +1200mV, is applied, the resistance changes from high to low, and the current I increases sharply. The current required for magnetization reversal (reversal current) is approximately 30μA. Conversely, as shown by arrow AR2, when a negative voltage V, for example, approximately -800mV, is applied, the resistance changes from low to high, and the current I decreases sharply. The reversal current is approximately 48μA.

[0231] <Comparative Examples>

[0232] Figure 24 This is a diagram illustrating a comparative embodiment. (See diagram for example.) Figure 24 As shown in (A), compared with Example 1 ( Figure 22 In contrast, the magnetic storage element 1E of the comparative embodiment differs in that the storage layer 3 does not include the second region 32, and the spacing region 33 is a Mo layer with a thickness of 3 Å.

[0233] Figure 24 Figure (B) shows the RH hysteresis characteristics. Curve C1 represents the RH hysteresis characteristics at a voltage V = +10mV. Curve C2 represents the RH hysteresis characteristics at a voltage V = +1200mV. Curve C3 represents the RH hysteresis characteristics at a voltage V = -1200mV. As shown in curve C2, the coercivity increases when a positive voltage (V > 0) is applied. As shown in curve C3, the coercivity decreases when a negative voltage (V < 0) is applied. However, almost no hysteresis shift occurs as seen in Example 1, and therefore almost no magnetization reversal occurs due to voltage application.

[0234] The various layered structures and materials described in the previous embodiments can be applied to Embodiments 1 and 2 above. Figure 22 and Figure 23 Several embodiments will be described as variations.

[0235] <Modified Examples 11, 12>

[0236] Figure 25 This diagram illustrates modified embodiments 11 and 12. For simplicity, only the layers of the storage layer 3 of the magnetic storage element 1 and the immobilization layer 21 in the magnetization immobilization layer 2 are shown. Compared with embodiment 2 described above (… Figure 23Compared to the structure of Example 2, the magnetic storage element 1 of Modified Example 11 differs in that the barrier layer 30 of the storage layer 3 is a MnMgO layer. Figure 23 Compared to the structure of the original, the magnetic storage element 1 of Modified Example 12 differs in that the barrier layer 30 of the storage layer 3 is a MnMgO layer, and the second region 32 is an FeCo layer. The second region 32 can be formed by excess Mn diffusing from the barrier layer 30 to the second region 32.

[0237] <Example 3, Modified Example 21, Modified Example 22>

[0238] Figure 26 The figures illustrate Embodiment 3, Modified Embodiment 21, and Modified Embodiment 22. Compared with Embodiment 2 ( Figure 23 Compared to the structure of Embodiment 3, the magnetic storage element 1 of Embodiment 3 differs in that the positions of the first region 31 and the second region 32 are reversed. Compared to Embodiment 3, the magnetic storage element 1 of Modified Embodiment 21 differs in that the barrier layer 30 is an MgO layer and the barrier layer 34 is an FeMgO layer. In the magnetic storage element 1 of Modified Embodiment 22, both the barrier layer 30 and the barrier layer 34 are FeMgO layers.

[0239] The materials of the barrier layer 30 and the blocking layer 34 are as described in the previous embodiments. As mentioned above, additive elements such as Fe, Co, and Mn can be added to MgO. Additive elements other than Fe, Co, and Mn can also be added. Examples of other additive elements are Hf and Zr. See also Figure 27 Please provide an explanation.

[0240] <Modified Embodiment 23, Modified Embodiment 24>

[0241] Figure 27 The figures show modified embodiments 23 and 24. Compared with embodiment 2 ( Figure 23 Compared to the structure of Example 2), the magnetic storage element 1 of Modified Example 23 differs in that the barrier layer 34 is an Hf-MgO layer, and in this example, the barrier layer 30 is an MgO layer. Compared to Example 2 ( Figure 23 Compared to the structure of the original, the difference between the magnetic storage element 1 in modified example 24 and the original is that the barrier layer 34 is an HfZrO layer.

[0242] As described above, the barrier layer 30 can be, for example, an oxide of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc. (Refer to...) Figure 28 Describe several specific examples.

[0243] <Modified Embodiment 13, Modified Embodiment 14, Modified Embodiment 25>

[0244] Figure 28 The figures show modified embodiments 13, 14, and 25. Compared with embodiment 2 ( Figure 23 Compared to the structure of Example 2, the difference in magnetic storage element 1 of Modified Example 13 is that the barrier layer 34 is a Gd2O3 layer. Figure 23 Compared to Embodiment 3, the magnetic storage element 1 of Modified Embodiment 14 differs in that the barrier layer 34 is a Y2O3 layer, and in this example, the second region 32 is a CoFe layer. Compared to Embodiment 3 (… Figure 26 Compared to the structure of the original embodiment, the difference in the magnetic storage element 1 of modified embodiment 25 is that the barrier layer 34 is a La2O3 layer. As shown in Non-Patent Document 6, it is expected that the magnetization reversal of the storage layer 3 can be assisted by applying a voltage through the barrier layer 34.

[0245] As described above, antiferromagnetic oxides such as NiO, Cr2O3, CoO, Fe2O3, and Mn2O3 can be used as the material for the barrier layer 34. (Refer to...) Figure 29 Provide an example.

[0246] <Modified Example 15>

[0247] Figure 29 This is a diagram illustrating modified embodiment 15. Compared to embodiment 2 ( Figure 23 Compared to the structure of the original embodiment, the magnetic storage element 1 of the modified embodiment 15 differs in that the barrier layer 34 is a Cr2O3 layer, and in this example, the barrier layer 30 is a MnMgO layer.

[0248] <Experimental Examples of Materials>

[0249] As a further research finding, referring to Figure 30 and Figure 31 An experimental example of the material in region 32 is described.

[0250] <Experimental Examples 101~116>

[0251] Figure 30 Experimental examples are shown when the material in region 32 is FeNiMn. As Experimental Examples 101 to 116, these are compared with Example 2 (…). Figure 23 In the same stacked structure, the measured values ​​of the reversal voltage (the magnitude of the voltage V required for magnetization reversal) and TMR ratio are shown when the composition ratio of the material in the second region 32 of the storage layer 3 is changed.

[0252] Figure 30(A) presents the measurement results of Experimental Examples 101 to 116 in tabular form. Experimental examples that confirmed the expected results are designated as Examples, and other experimental examples are designated as Comparative Examples. The experimental results of the Examples can define the composition range of the material in the second region 32 of the storage layer 3 of the magnetic storage element 1 of the Embodiment. Figure 30 (B) shows a ternary plot of the composition range. The plot shows the corresponding plots for each experimental example.

[0253] Based on Experimental Examples 101 to 105, the composition dependence of FE (0 at%) and Ni in NiMn (20 at%) was confirmed. A TMR ratio of over 100% is desirable when Ni is less than 80 at%, but when the Ni composition is too high (e.g., 85 at%), the TMR ratio decreases to 62%. Therefore, the Ni composition is preferably less than 80 at%.

[0254] Based on Experimental Examples 107 to 112, the composition dependence of Ni composition (0 at%) and Mn composition (3 at%) in FeMn composition (85 at%) was confirmed. In Experimental Example 107, where the Mn composition was as low as 3 at%, the reversal voltage increased to 1.8 V. In Experimental Example 112, where the Mn composition was as high as 85 at%, the reversal voltage was sufficiently low, but since the TMR ratio decreased to 65%, a Mn composition of 5 at% to 80 at% was more preferable.

[0255] Based on Experimental Examples 108, 105, and 106, the composition dependence when the Mn composition ratio is 5 at% and the Fe to Ni composition ratio is changed can be confirmed. In Experimental Example 106, where the Ni composition ratio is 40 at%, the reversal voltage tends to increase to 1.8 V. Therefore, the Ni composition ratio when Mn is 5 at% is preferably 30 at% or less.

[0256] Based on the above trend, the preferred composition range of FeNiMn is... Figure 30 The shaded region in the ternary diagram of (B). This region is related to the aforementioned... Figure 3 The same can be obtained from the compositional region of the antiferromagnetic or subferromagnetic phase shown in Non-Patent Document 1.

[0257] <Experimental Examples 201~216>

[0258] Figure 31 An experimental example is shown when the material in region 32 is FeCoMn. Figure 31 The measurement results of Experimental Examples 201 to 216 are shown in tabular form in (A). Figure 31 (B) shows a ternary diagram of the composition range.

[0259] Based on Experimental Examples 201 to 204, the composition dependence of Fe (0 at%) and Co in the CoMn composition (20 at%) to 70 at%) was confirmed. Within the range of Co > 50 at%, the reversal voltage increased to over 1.8 V. This can be considered to correspond to the situation where, in the CoMn system, a lower Mn content makes it difficult for CoMn to obtain an antiferromagnetic phase; ideally, the Co content should be less than 50 at%.

[0260] Based on Experimental Examples 205 to 210, the composition dependence of Ni composition (0 at%) and Mn composition (3 at%) in FeMn composition (85 at%) was confirmed. In Experimental Example 107, where the Mn composition was as low as 3 at%, the reversal voltage increased to 1.8 V. In Experimental Example 112, where the Mn composition was as high as 85 at%, although the reversal voltage was sufficiently low, the TMR ratio decreased to 65%. Therefore, a Mn composition of 5 at% to 80 at% is more preferable.

[0261] Based on Experimental Examples 209 and 210, the composition dependence when the Mn composition ratio is 5 at% and the Fe and Ni composition ratios are changed can be confirmed. Even when the Co composition ratio is 50 at%, the reversal voltage is relatively good at 1.55 V.

[0262] Based on Experimental Examples 201, 208, and 212-215, the composition dependence of Mn composition ratio being 25 at% and the Co-Fe composition ratio being changed can be confirmed. The higher the Co composition ratio, the greater the reversal voltage tends to be; in Experimental Example 201 with Co at 75 at% and Experimental Example 212 with Co at 60 at% respectively, the reversal voltages reached as high as 1.8V and 1.83V. The threshold voltage reduction effect is significant when the Co composition ratio is below 50 at%, which is preferred.

[0263] Based on the above trend, the preferred composition range of FeNiMn is... Figure 31 The shaded area in the ternary diagram of (B). This area is related to the previously described... Figure 6 The same can be obtained from the compositional region of the antiferromagnetic or subferromagnetic phase shown in Non-Patent Document 1.

[0264] <Other Modified Embodiments>

[0265] The compositional range in which an antiferromagnetic or subferromagnetic phase can be obtained is approximately the same as the compositional range in which the material of the second region 32 can achieve a reduction in magnetization reversal voltage. Therefore, it can be considered, for example, according to the previously explained... Figure 4 , Figure 5 and Figures 7 to 9 The same effect can be achieved with the range of components shown.

[0266] <Regarding the modified embodiment of the interval region 33>

[0267] Several modified embodiments regarding the interval region 33 will be described. In the previous embodiment 2 ( Figure 23 In this paper, the case where the spacer region 33 contains Mo is used as an example. Several examples of using materials other than Mo are described as modified embodiments 41 to 45.

[0268] <Modified Examples 41 to 45>

[0269] Figure 32 The figures show modified embodiments 41 to 45. For simplicity, only the first region 31, the second region 32, and the spacing region 33 of the storage layer 3 of the magnetic storage element 1 are shown.

[0270] In the magnetic storage element 1 of modified embodiments 41 to 43, the storage layer 3 includes a second region 32, a spacer region 33, and a first region 31 stacked sequentially along the positive Z-axis. In the magnetic storage element 1 of modified embodiment 41, the spacer region 33 of the storage layer 3 is a W layer with a thickness of 2.5 Å. In the magnetic storage element 1 of modified embodiment 42, the spacer region 33 of the storage layer 3 is a Ru layer with a thickness of 2.5 Å. In the magnetic storage element 1 of modified embodiment 43, the spacer region 33 of the storage layer 3 is a Ta layer with a thickness of 2.5 Å.

[0271] In the magnetic storage element 1 of modified embodiments 44 and 45, the storage layer 3 includes a first region 31, a spacer region 33, and a second region 32 stacked sequentially along the positive Z-axis. In the magnetic storage element 1 of modified embodiment 44, the spacer region 33 of the storage layer 3 is an Ir layer with a thickness of 2.5 Å. In the magnetic storage element 1 of modified embodiment 45, the spacer region 33 of the storage layer 3 is a W layer with a thickness of 2.5 Å.

[0272] It can also be a structure without the interval region 33. (See reference...) Figure 33 Please provide an explanation.

[0273] <Modified Embodiments 46 and 47>

[0274] Figure 33 Figures illustrate modified embodiments 46 and 47. In the magnetic storage element 1 of modified embodiment 46, the storage layer 3 includes a second region 32 and a first region 31 stacked sequentially along the positive Z-axis. There is no gap between the second region 32 and the first region 31. In the magnetic storage element 1 of modified embodiment 47, the storage layer 3 includes a first region 31 and a second region 32 stacked sequentially along the positive Z-axis. There is no gap between the first region 31 and the second region 32.

[0275] <Modified Example of Top-Pinned Type>

[0276] As referenced above Figure 1 The magnetic storage element 1 may have a top-pinned structure. (Refer to...) Figure 34 Please provide an explanation.

[0277] <Modified Embodiments 51 and 52>

[0278] Figure 34 The figures show modified embodiments 51 and 52. In the magnetic storage element 1 of modified embodiment 51, embodiment 2 ( Figure 23 The structure of the magnetic storage element 1 in modified embodiment 52 is changed to a top-pinned type. In embodiment 3 ( Figure 26 The structure was changed to a top-pinned type. In all structures, the lower electrode layer 5, storage layer 3, magnetization fixation layer 2, and capping layer 6 are stacked sequentially along the positive Z-axis.

[0279] In the magnetic storage element 1 of Variation 51, the storage layer 3 includes a barrier layer 34, a second region 32, a spacer region 33, a first region 31, and a barrier layer 30, stacked sequentially along the positive Z-axis. The barrier layer 34 is an MgO layer. The second region 32 is a FeCoMn layer with a thickness of 10 Å (or any thickness between 7 Å and 10 Å). The spacer region 33 is a Mo layer with a thickness of 2.5 Å. The first region 31 is a CoFeB layer with a thickness of 6 Å. The barrier layer 30 is a MgFeO layer.

[0280] In the magnetic storage element 1 of modified embodiment 52, the storage layer 3 includes a barrier layer 34, a first region 31, a spacer region 33, a second region 32, and a barrier layer 30, which are sequentially stacked along the positive Z-axis. The barrier layer 34 is an MgO layer. The first region 31 is a CoFeB layer of arbitrary thickness between 6 Å and 8 Å. The spacer region 33 is a Mo layer with a thickness of 2.5 Å. The second region 32 is a FeCoMn layer of arbitrary thickness between 7 Å and 10 Å.

[0281] <Double MTJ, SAF>

[0282] As in the previous implementation method, refer to Figure 20 and Figure 21 The magnetic storage element 1 can have a dual MTJ structure or a SAF structure. (Refer to...) Figure 35 Please provide an explanation.

[0283] <Modified Embodiments 61 and 62>

[0284] Figure 35 The figures show modified embodiments 61 and 62.

[0285] The magnetic storage element 1 in modified embodiment 61 is as described above. Figure 20 An example of the structure shown in (A) is as follows. A magnetized fixing layer 2, a storage layer 3, a ferromagnetic layer 4, and a capping layer 6 are stacked sequentially along the positive Z-axis. The magnetized fixing layer 2 and the ferromagnetic layer 4 are CoFeB layers. The storage layer 3 includes a barrier layer 30, a second region 32, a spacer region 33, a first region 31, and a barrier layer 34, stacked sequentially along the positive Z-axis. The barrier layer 30 is an FeMgO layer. The second region 32 is an FeCoMn layer. The spacer region 33 is a Mo layer. The first region 31 is a CoFeB layer. The barrier layer 34 is an MgO layer. With both barrier layers 30 and 34 formed, the barrier layer 34 is disposed between the first region 31 and the ferromagnetic layer 4. A dual-MTJ structure, where both barrier layers 30 and 34 are used as MTJs, can be obtained.

[0286] The magnetic storage element 1 in modified embodiment 62 is as described above. Figure 21 An example of the structure shown in (A) is presented. A magnetized anchor layer 2, a storage layer 3, a ferromagnetic layer 4, and a capping layer 6 are stacked sequentially along the positive Z-axis. The magnetized anchor layer 2 and the ferromagnetic layer 4 are CoFeB layers. The storage layer 3 comprises a barrier layer 30, a second region 32, a spacer region 33, a first region 31, and a spacer layer 35, stacked sequentially along the positive Z-axis. The barrier layer 30 is an FeMgO layer. The second region 32 is an FeCoMn layer. The spacer region 33 is a Mo layer. The first region 31 is a CoFeB layer. A stacked subferromagnetic structure (SAF) in which the storage layer 3 is antiferromagnetically coupled via the spacer layer 35 is obtained.

[0287] <Summary>

[0288] The magnetic storage element 1 in the above embodiment is determined, for example, in the following manner. (Refer to...) Figures 1 to 9 , Figures 19 to 23 , Figures 25 to 35 As described above, the magnetic storage element 1 includes a magnetization fixing layer 2 with a fixed magnetization direction and a storage layer 3 with a reversible magnetization direction. The storage layer 3 includes a first region 31 containing ferromagnetic material and a second region 32 containing antiferromagnetic or ferrimagnetic material.

[0289] According to the magnetic storage element 1 described above, in the storage layer 3, the magnetization reversal of the first region 31 is assisted by the second region 32, and correspondingly, the power consumption required for magnetization reversal is reduced. Therefore, the power consumption of the magnetic storage element 1 can be suppressed.

[0290] For reference Figure 1 and Figure 2As described above, the first region 31 and the second region 32 can be stacked. Alternatively, the storage layer 3 may also include a plurality of first regions 31 and a plurality of second regions 32 disposed separately. The storage layer 3 may include a spacer region 33 disposed between the first regions 31 and the second regions 32 and comprising a non-magnetic material. The first regions 31 and the second regions 32 may be magnetically coupled to each other. The first regions 31 and the second regions 32 can be configured within the storage layer 3 in various ways, for example.

[0291] For reference Figure 1 and Figure 2 As described above, the first region 31 may contain at least one of Co, Fe, Ni, Mn, Al, B, P, C, Zr, Hf, Ta, and Nb. The first region 31 may contain CoFeB. In this case, the Fe composition ratio in CoFeB may be greater than the Co composition ratio. The B composition ratio in CoFeB may be 40 at% or less. The thickness of the first region 31 may be 0.1 nm or more and 1.5 nm or less. For example, a region constructed in this way can be used as the first region 31.

[0292] For reference Figure 1 and Figure 2 As described above, the second region 32 may contain at least one of Mn, Cr, Ir, Pt, Pd, Ni, Sn, Fe, Ge, Co, Ga, and Si. The second region 32 may contain chalcogenides, such as CuMnAs or MnPS3. The second region 32 may contain oxides, such as NiO, Cr2O3, CoO, Fe2O3, or Mn2O3. The second region 32 may contain antiferromagnetic or ferrimagnetic alloys. These alloys may contain FeNiMn, CrNiMn, FeCrMn, FeCoMn, CoNiMn, FeNiCr, GaNiMn, CoPtMn, FePtMn, FeMn, NiMn, FeNi, PtMn, PdMn, or CoGe. The thickness of the second region 32 may be 0.1 nm or more and 5 nm or less. For example, a region constructed in this way can be used as the second region 32.

[0293] For reference Figure 3 As described above, the alloy of region 32 in the second region can be Fe with the composition ratio of Fe, Ni, and Mn set as x, y, z. x Ni y Mn z The alloy has a composition range of 0at% < x ≤ 95at%, 0at% < y ≤ 80at%, and 5at% ≤ z ≤ 80at%. An antiferromagnetic or ferrimagnetic phase can be obtained. The antiferromagnetic or ferrimagnetic phase shown in Non-Patent Document 1 can also be obtained.

[0294] For reference Figure 4As described above, the alloy of region 32 in the second region can be a Cr alloy with the composition ratio of Cr, Ni, and Mn set as x, y, z. x Ni y Mn z The alloy has a composition range of 0at% < x ≤ 65at%, 0at% < y ≤ 75at%, and 0at% < z ≤ 80at%. An antiferromagnetic or subferromagnetic phase as shown in Non-Patent Document 1 can be obtained.

[0295] For reference Figure 5 As described above, the alloy of region 32 in the second region can be Fe with the composition ratio of Fe, Cr, and Mn set as x, y, z. x Cr y Mn z The alloy has a composition range of 0at% < x ≤ 95at%, 0at% < y ≤ 70at%, and 5at% ≤ z ≤ 80at%. An antiferromagnetic or subferromagnetic phase as shown in Non-Patent Document 1 can be obtained.

[0296] For reference Figure 6 As described above, the alloy of region 32 in the second region can be Fe with the composition ratio of Fe, Co, and Mn set as x, y, z. x Co y Mn z The alloy has a composition range of 0at% < x ≤ 95at%, 0at% < y ≤ 50at%, and 5at% ≤ z ≤ 80at%. An antiferromagnetic phase, as shown in Non-Patent Document 2, can be obtained.

[0297] For reference Figure 7 As described above, the second region 32 can be Ga with the composition ratio of Ga, Ni, and Mn set as x, y, z. x Ni y Mn z The alloy has a composition range of 0at% < x ≤ 50at%, 5at% ≤ y ≤ 80at%, and 5at% ≤ z ≤ 90at%. A ferrimagnetic phase, as shown in Non-Patent Document 3, can be obtained.

[0298] For reference Figure 8 As described above, the second region 32 can be Fe with the composition ratio of Fe, Ni, and Cr set as x, y, z. x Ni y Cr z The alloy has a composition range of 60at%≤x≤82at%, 15at%≤y≤40at%, and 10at%≤z≤35at%. A ferrimagnetic phase, as shown in Non-Patent Document 4, can be obtained.

[0299] For reference Figure 9 As described above, the second region 32 can be a Co compound with the composition ratio of Co, Ge, and Mn set as x, y, z.x 、Ge y Mn z The alloy has a composition range of 0at% < x ≤ 20at%, 0at% < y ≤ 95at%, and 5at% ≤ z < 100at%. An antiferromagnetic phase, as shown in Non-Patent Document 5, can be obtained.

[0300] For reference Figure 2 As described above, the spacer region 33 may contain at least one of Ta, Ru, Ir, W, Mo, Rh, Re, Nb, Cu, Cr, V, TiN, TaN, and WN. The spacer region 33 is disposed between the first region 31 and the second region 32 in such a way that the first region 31 and the second region 32 are magnetically coupled to each other, and the magnetization of the second region 32 can act on the magnetization of the first region 31 via the spacer region 33. The thickness of the spacer region 33 may be 0.1 nm or more and 1.5 nm or less. For example, by providing such a spacer region 33, the first region 31 and the second region 32 can be magnetically coupled, assisting in the magnetization reversal 32 of the first region 31.

[0301] For reference Figure 2 As described above, the storage layer 3 includes a barrier layer 30 disposed between the first region 31 and the second region 32 and the magnetization fixation layer 2. The barrier layer may contain oxides of at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C. The barrier layer 30 may contain oxides of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The barrier layer 30 may contain MgO, and may also contain Fe, Co, or Mn in addition to MgO. In this case, the amount of Fe, Co, or Mn added may be less than 20 at%. For example, by disposing such a barrier layer 30 between the first region 31 and the second region 32 and the magnetization fixation layer 2, the TMR effect can be obtained.

[0302] For reference Figure 19 and Figure 20As described above, the storage layer 3 may include a barrier layer 34 disposed on the side opposite to the magnetization fixing layer 2, separated by the first region 31 and the second region 32. The material of the barrier layer 34 may be the same as that of the barrier layer 30. That is, the barrier layer 34 may contain at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C. The barrier layer 34 may contain oxides of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The barrier layer 34 may contain MgO, and in addition to MgO, may further contain Fe, Co, or Mn. In this case, the amount of Fe, Co, or Mn added may be less than 20 at%. Furthermore, the barrier layer 34 may contain antiferromagnetic oxides, such as NiO, Cr2O3, CoO, Fe2O3, or Mn2O3. By separating such a barrier layer 34 from the barrier layer 30, heat resistance and magnetization reversal efficiency can be improved. Additionally, the storage layer 3 may include a ferromagnetic layer 4 disposed on the side opposite to the first region 31 and the second region 32, separated from the barrier layer 34. This yields a magnetic storage element 1 with a dual-MTJ structure.

[0303] For reference Figure 1 As described above, the ferromagnetic layer of the magnetization fixing layer 2 includes a reference layer 22 whose magnetization direction is fixed, and the reference layer 22 may contain at least one of Fe, Co, Ni, Mn, and B. The magnetization fixing layer 2 may include a fixing layer 21 that fixes the magnetization direction of the reference layer 22. For example, multiple layers such as these can be used as the magnetization fixing layer 2.

[0304] For reference Figure 21 As described above, the storage layer 3 includes a spacer layer 35 disposed on the side opposite to the magnetization fixing layer 2, separating the first region 31 and the second region 32, and a ferromagnetic layer 4 disposed on the side opposite to the first region 31 and the second region 32, separating the spacer layer 35. Thus, a magnetic storage element 1 with a stacked subferromagnetic structure (SAF) can be obtained.

[0305] For reference Figures 10 to 12 As described above, the magnetization direction of the storage layer 3 can be reversed in accordance with the sign of the voltage V applied to the magnetic storage element 1. Thus, for example, not only can the coercivity be changed by applying a voltage as in VCMA, but magnetization reversal can also be achieved.

[0306] 2. Implementation methods of storage devices

[0307] The magnetic storage element 1 can be used as a component of a storage device. Specifically, the magnetic storage element 1 has a resistance value corresponding to the magnetization direction of the storage layer 3. When the magnetization direction of the storage layer 3 is parallel to the magnetization direction of the magnetization fixing layer 2, the magnetic storage element 1 has a low resistance value. When it is antiparallel, with its magnetization direction opposite, the magnetic storage element 1 has a high resistance value. These two resistance values ​​correspond to bit data "0" and "1". Data can be written to the magnetic storage element 1 by executing control to make it have a low or high resistance value. Furthermore, data can be read from the magnetic storage element 1 by detecting its resistance value.

[0308] One of the features of magnetic storage element 1 lies in the principle of writing data to magnetic storage element 1. Although there are some repetitions from before, please refer to [the relevant documentation] again. Figure 36 Please provide an explanation.

[0309] Figure 36 This is a diagram illustrating the principle of writing data to magnetic storage element 1. (As shown...) Figure 36 As shown in (A), when a positive voltage (voltage V>0) of a certain magnitude and pulse length (pulse width) is applied to the magnetic storage element 1, the magnetization direction of the storage layer 3 of the magnetic storage element 1 is reversed, causing its resistance value to change from a low resistance value to a high resistance value. Conversely, as Figure 36 As shown in (B), when a positive voltage (voltage V>0) with a certain magnitude and pulse length is applied to the magnetic storage element 1, the magnetization direction of the storage layer 3 of the magnetic storage element 1 is reversed, causing its resistance value to change from a high resistance value to a low resistance value.

[0310] By including components (e.g., control circuitry) for writing data to or reading data from the magnetic storage element 1 based on the above principles, a storage device comprising the magnetic storage element 1 is provided. Several embodiments will be described.

[0311] 2.1 First Implementation Method

[0312] Figure 37 This is a schematic structural example of the storage device 7 according to the first embodiment. The storage device 7 includes a storage array 70. The storage array 70 includes a plurality of memory cells 71 arranged in a two-dimensional configuration. The memory cells 71 include the aforementioned magnetic storage element 1, and in this example, also include a selection transistor 72. Bit lines BL, source lines SL, and word lines WL are indicated by symbols as signal lines / control lines used for accessing the memory cells 71 for data reading, writing, etc. The word line WL extends in a manner that intersects (e.g., orthogonally) with the bit lines BL and source lines SL.

[0313] Memory cell 71 is the unit for reading and writing data, and in this sense, it can be considered equivalent to magnetic storage element 1. Memory cell 71 and magnetic storage element 1 can be interchanged as appropriate, without contradiction.

[0314] Storage device 7 includes various peripheral circuits / elements disposed around memory unit 71. As peripheral circuits / elements, Figure 37 The diagram illustrates I / O 730, control circuit 731, voltage generation circuit 732, write circuit 733, read circuit 734, bit / source line address decoder 735, bit / source line control circuit 736, word line address decoder 737, word line control circuit 738, and sense amplifier 739. Bit / source line control circuit 736 is connected to bit line BL and source line SL. Word line control circuit 738 is connected to word line WL. Sense amplifier 739 is connected to bit line BL and source line SL.

[0315] The basic operation of a storage device with the above structure is readily understood by anyone skilled in the art, and therefore will be briefly described below. Furthermore, it is not limited to... Figure 37 The structure shown is not the only one that can be used; various well-known structures can be employed instead.

[0316] Through I / O 730, communication is conducted between the external elements of the storage device 7 and the control circuitry 731 of the storage device 7 regarding data writing and reading instructions, the address of the memory cell 71 to be accessed, writing data, reading data, etc. Examples of external elements of the storage device 7 are mainframe computers such as CPUs.

[0317] The control circuit 731 controls other peripheral circuits / components according to instructions. It can be said that the entire storage device 7, except for I / O 730, is essentially controlled by the control circuit 731. The control circuit 731's control includes controlling the writing of data to the magnetic storage element 1 and controlling the reading of data from the magnetic storage element 1. The control circuit 731 may be configured, for example, to include a state machine.

[0318] The voltage generation circuit 732 generates either a pulse voltage for data writing (data write voltage) or a voltage for data reading (data read voltage). The data read voltage is lower than the data write voltage. The voltage required for circuit operation can be provided separately.

[0319] The write circuit 733 uses the voltage generated by the voltage generation circuit 732 to control the pulse of the write voltage.

[0320] The read circuit 734 uses the voltage generated by the voltage generation circuit 732 to control the pulse of the read voltage.

[0321] The bit / source line address decoder 735 obtains the addresses of the bit line BL and source line SL corresponding to the addresses received by the I / O 730 described above.

[0322] The bit / source line control circuit 736 selects and controls the bit line BL and source line SL corresponding to the address of the word line address decoder 737. Data is written to the memory cell 71 using a data write voltage generated by the voltage generation circuit 732 and pulse-controlled by the read circuit 734 via the bit / source line control circuit 736, and data is read from the memory cell 71 using a data read voltage generated by the voltage generation circuit 732 and pulse-controlled by the read circuit 734.

[0323] The word line address decoder 737 obtains the address of the word line WL corresponding to the address received by I / O 730.

[0324] The word line control circuit 738 selects and controls the word line WL corresponding to the address of the word line address decoder 737.

[0325] The readout amplifier 739 detects the data read from the memory cell 71, specifically the resistance value of the magnetic storage element 1.

[0326] The control circuit 731 and the readout amplifier 739 described above control the writing of data to and reading of data from the magnetic storage element 1. Unless otherwise specified, the control unit can be understood as the control circuit 731.

[0327] The memory cell 71 will be described again. The magnetic storage element 1 of the memory cell 71 is electrically connected between the bit line BL and the source line SL. In this example, one end of the magnetic storage element 1 is connected to the bit line BL, and the other end is connected to the source line SL via the select transistor 72.

[0328] The selection transistor 72 is an example of a selection element used to select a memory cell 71 from a plurality of memory cells 71 as the object of data read / write, and more specifically, a FET switch. The function of the selection transistor 72 can also be referred to as a selector function. The FET constituting the selection transistor 72 can be a MOSFET, which can be either an N-type MOSFET or a P-type MOSFET. Here, it is assumed that the FET is an N-type MOSFET.

[0329] The selection transistor 72 switches between a state that allows data access (data read / write) to the corresponding magnetic storage element 1 and a state that prevents data access. Specifically, in Figure 37In the example shown, one of the source and drain of the selection transistor 72 is connected to the magnetic storage element 1, and the other is connected to the source line SL. The gate of the selection transistor 72 is connected to the word line WL. When the selection transistor 72 is on (conducting state), data access to the magnetic storage element 1 connected to the selection transistor 72 is allowed. When the selection transistor 72 is off (non-conducting state), data access to the magnetic storage element 1 connected to the selection transistor 72 is prevented.

[0330] A voltage corresponding to the potential difference between the bit line BL and the source line SL is applied to the magnetic storage element 1 in the memory cell 71, and this voltage corresponds to the aforementioned voltage V. One of a positive voltage (voltage V>0) and a negative voltage (voltage V<0) is applied to the magnetic storage element 1 to give it a resistance value of either low or high. Furthermore, another of a positive and negative voltage is applied to the magnetic storage element 1 to give it the other resistance value of either low or high. Figure 37 In the example shown, when the source line SL is used as the reference potential, the potential of the bit line BL represents the voltage V applied to the magnetic storage element 1.

[0331] When the potential of bit line BL is higher than the potential of source line SL, a positive voltage (V>0) is applied to magnetic storage element 1. (Refer to previous text) Figure 36 As described in (A), the magnetic storage element 1 has a low resistance value.

[0332] When the potential of the source line SL is higher than the potential of the bit line BL, in other words, when the potential of the bit line BL is lower than the potential of the source line SL, a negative voltage (V<0) is applied to the magnetic storage element 1. (Refer to previous text) Figure 37 As described in (B), the magnetic storage element 1 has a high resistance value.

[0333] Furthermore, the absolute values ​​(|V|) of the aforementioned positive and negative voltages can be the same or different. By making the absolute value of one voltage smaller than the absolute value of the other voltage, the possibility of suppressing power consumption is further increased.

[0334] In addition, applied to Figure 37 The direction of the voltage V of the magnetic storage element 1 shown can be reversed; in this case, the potentials of the bit line BL and the source line SL have the opposite relationship to those described above. However, unless otherwise stated below, it is assumed that an voltage V is applied to the magnetic storage element 1. Figure 37 The voltage V in the indicated direction.

[0335] The names of the bit line BL and source line SL, and the circuit design of storage device 7, are not limited to the examples described herein. Various other well-known names and circuit designs may be used.

[0336] Reference Figure 38The following describes the operations related to data writing and data reading in storage device 7. The operations are controlled, for example, by a state machine included in control circuit 731, and more specifically by write circuit 733 and read circuit 734, as well as bit / source line control circuit 736 and word line control circuit 738, which operate under the control of control circuit 731.

[0337] Figure 38 This is a flowchart illustrating an example of the processing (data writing method) performed during data writing. The process begins in response to the input of a write command and the input of write data. Assume that a memory cell 71, including the magnetic storage element 1 to be written, has been selected, and the corresponding selection transistor 72 is turned on.

[0338] To achieve a high resistance value for the magnetic storage element 1 (step S1: Yes), the source line SL of the bit line BL and source line SL is set to a high potential (step S2), and a voltage is set to make the resistance value of the magnetic storage element 1 high (step S3). That is, the applied voltage to the magnetic storage element 1 is set to a positive voltage (voltage V>0).

[0339] Conversely, if it is desired that the magnetic storage element 1 has a resistance value (step S1: No), the bit line BL in the bit line BL and the source line SL is set to a high potential (step S4), and a voltage is set to make the resistance value of the magnetic storage element 1 a low resistance value (step S5). That is, the applied voltage to the magnetic storage element 1 is set to a negative voltage (voltage V<0).

[0340] After setting in step S3 or S5, a pulse voltage with the set voltage is applied (step S6). The magnetic storage element 1 then becomes either low or high resistance. Alternatively, the resistance value of the magnetic storage element 1 may switch between low and high resistance.

[0341] Figure 39 This is a diagram illustrating an example of a timing diagram during data writing. The write start signal is, for example, generated by control circuit 731 (…). Figure 37 The write direction control signal indicates the switching direction of the resistance value of magnetic storage element 1, i.e., low resistance value → high resistance value or high resistance value → low resistance value. Word line voltage, bit line voltage, and source line voltage represent the voltages applied to word line WL, bit line BL, and source line SL. Bit line BL, source line SL, and word line WL are selected by bit / source line address decoder 735 and word line address decoder 737, and word line voltage, bit line voltage, and source line voltage are generated by bit / source line control circuit 736 and word line control circuit 738. Bit line voltage and source line voltage are detected by sense amplifier 739.

[0342] Figure 39(A) shows a timing diagram when the resistance value of magnetic storage element 1 is switched from a high resistance value to a low resistance value. Figure 39 (B) shows a timing diagram when the resistance value of magnetic storage element 1 is switched from a low resistance value to a high resistance value.

[0343] In response to the write start signal, a word line voltage is applied. Simultaneously, when switching the resistance value of magnetic storage element 1 from a high resistance value to a low resistance value, as... Figure 39 As shown in (A), the bit line voltage is controlled to be higher than the source line voltage. When switching the resistance value of magnetic storage element 1 from a low resistance value to a high resistance value, as... Figure 39 As shown in (B), the source line voltage is controlled to be higher than the bit line voltage. This causes the resistance value of the magnetic storage element 1 to switch from a high resistance value to a low resistance value, or vice versa.

[0344] In addition, Figure 39 In this context, word line voltage, bit line voltage, and source line voltage are described as having the same pulse width, but these voltages can also have different pulse widths. For example, control can be implemented as follows: first, the word line voltage rises, then the bit line voltage or source line voltage rises, and then, after the bit line voltage or source line voltage falls, the word line voltage falls.

[0345] Figure 40 This is a flowchart illustrating an example of the processing (data reading method) performed during data reading. The process begins in response to an input read command. Assume that memory cell 71, which includes magnetic storage element 1 as the object of data reading, has been selected, and the corresponding selection transistor 72 is turned on.

[0346] Set one of the bit line BL and the source line SL to a high potential (step S11), and set the read voltage (step S12). For example, set the bit line BL to a high potential. The read voltage is a voltage that allows the resistance value of the magnetic storage element 1 to be read without switching the resistance value of the magnetic storage element 1. The magnitude of the read voltage can be less than the voltage applied during writing (write voltage).

[0347] A pulse voltage with a set voltage is applied (step S13), and the readout amplifier 739 detects the voltage at this time. Since the detection voltage varies with the resistance value of the magnetic storage element 1, the resistance value of the magnetic storage element 1 is determined to be low or high based on the detection result (step S14).

[0348] Furthermore, in step S11 above, either the bit line BL or the source line SL can be arbitrarily selected to be set to a high potential. For example, the one with a lower probability of accidental writes caused by the applied read voltage can be selected.

[0349] Figure 41This is a diagram illustrating an example of a timing diagram during data reading. The start-read signal is, for example, given by control circuit 731 (…). Figure 37 The sense amplifier enable signal is generated by the sense amplifier 739 to enable voltage detection of the source line SL, for example, by the control circuit 731. Figure 37 )generate.

[0350] In response to the read start signal, a word line voltage is applied. Simultaneously, in this example, the bit line voltage is controlled to be higher than the source line voltage. The read amplifier 739 then effectively operates, thereby determining whether the resistance value of the magnetic storage element 1 is low or high.

[0351] In addition, such as Figure 41 As illustrated, the bit line voltage during reading, i.e., the read voltage, may be lower than the bit line voltage during writing. Figure 39 (A) refers to the write voltage. Furthermore, although the word line voltage, bit line voltage, and sense amplifier enable signal are described as having the same pulse width, their voltage or signal pulse widths can be different. For example, control can be implemented such that the word line voltage rises first, then the bit line voltage rises, and then the word line voltage falls after the bit line voltage falls. The sense amplifier 739 can be enabled after the bit line voltage is applied.

[0352] For example, data writing to and data reading from the magnetic storage element 1 can be performed as described above. A storage device 7 utilizing the magnetic storage element 1 is provided. The storage device 7 can also obtain the power consumption suppression and other effects of the magnetic storage element 1 described above.

[0353] <Modifications of the first embodiment>

[0354] Several variations based on the technology of the first embodiment described above will be described. Descriptions that are repeated previously will be omitted as appropriate.

[0355] <Modification 1 of the first embodiment>

[0356] In one implementation, a verification read can be performed during the write operation. The read value (resistance value, bit value, etc.) is compared with the value to be written, i.e., the expected value; if they do not match, the write voltage is applied again. See reference... Figure 42 and Figure 43 Please provide an explanation.

[0357] Figure 42 This is a flowchart illustrating an example of the processing (data write method) performed during data writing. (Refer to previous...) Figure 38After the processing of steps S1 to S6 as described above is completed, a verification reading is performed (step S7), and it is determined whether the read value is consistent with the expected value (step S8). If the read value is consistent with the expected value (step S8: Yes), the flowchart processing ends; if they are inconsistent (step S8: No), the processing returns to step S6, and the pulse voltage is applied again.

[0358] The pulse voltage is repeatedly applied until the resistance value of magnetic storage element 1 matches the desired value, thereby reliably performing data writing to magnetic storage element 1. Furthermore, a maximum value can be set for the number of repetitions of steps S6 to S8. The flowchart process ends when the number of repetitions exceeds the maximum value.

[0359] Figure 43 This is a diagram illustrating an example of a timing diagram during data writing. The comparison result signal indicates whether the value read is consistent with the expected value (match or mismatch), generated, for example, by the sense amplifier 739 or a separately configured verification circuit (not shown). Figure 43 In the example shown, the comparison result signal is high when the read value matches the expected value.

[0360] As previously explained Figure 39 Similarly, in response to the write start signal, a word line voltage is applied. Simultaneously, when switching the resistance value of magnetic storage element 1 from a high resistance value to a low resistance value, as... Figure 43 As shown in (A), the bit line voltage is controlled to be higher than the source line voltage. When switching the resistance value of magnetic storage element 1 from a low resistance value to a high resistance value, as... Figure 43 As shown in (B), the source line voltage is controlled to be higher than the bit line voltage. Here, it is assumed that the first data write fails and the resistance value of magnetic storage element 1 does not become the expected value.

[0361] Next, a verification read is performed. In response to the read start signal, a word line voltage is applied. In this example, the bit line voltage is controlled to apply the same voltage as the read voltage. Furthermore, the read amplifier 739 is enabled to determine whether the resistance value of the magnetic storage element 1 is high or low. It is then determined whether the resistance value shown in the determination result, i.e., the read value, matches the expected value.

[0362] If the read value does not match the expected value (mismatch), the write operation to magnetic storage element 1 is performed again. In response to the second write start signal, one of the word line voltage, bit line voltage, and source line voltage is controlled to be higher than the other. Here, it is assumed that the second data write is successful, and the resistance value of magnetic storage element 1 becomes the expected value. Afterwards, a verification read is performed, and it is determined that the read value matches the expected value (match). The data write operation to magnetic storage element 1 is then complete.

[0363] Additionally, if the read value also differs from the expected value during the second verification read, further data writing and verification reads will be performed. As mentioned above, a maximum number of repetitions can be set.

[0364] Based on the above variation 1, by verifying the read to determine the write error and then rewriting, the write error rate can be reduced accordingly.

[0365] <Modification 2 of the first embodiment>

[0366] In one implementation, the voltage setting can be changed when the write voltage is applied again based on the result of the verification read. For example, the write voltage can be gradually increased, or the pulse width (pulse length) can be gradually increased. The write error rate varies depending on the magnitude of the write voltage and the pulse width. The magnitude of the write voltage and the pulse width corresponding to the predetermined write error rate can be distributed among the magnetic storage elements 1 of the individual memory cells 71 in the memory array 70.

[0367] When the write voltage is set according to the magnetic storage element 1 located at the edge of the distribution, in other words, the magnetic storage element 1 that requires the maximum write voltage or the longest pulse width, the power consumption required to write data to most of the magnetic storage elements 1 unnecessarily increases. Power consumption can be suppressed by gradually changing the write voltage in accordance with the result of the verification read. (Refer to...) Figure 44 and Figure 45 Please provide an explanation.

[0368] Figure 44 This is a flowchart illustrating an example of the processing (data write method) performed during data writing. (Refer to previous...) Figure 42 If the read value in step S8 is inconsistent with the expected value (step S8: No), the voltage is reset (step S9). For example, the magnitude or pulse width of the read voltage is set to be greater than the magnitude or pulse width of the voltage set in the previous step S3, step S5, or the last time in step S9. After that, the process returns to step S6, and the pulse voltage is applied again.

[0369] Figure 45 This is a diagram illustrating an example of a timing diagram during data writing. (Similar to the above...) Figure 43 The similarities are: the first write operation failed, but the second write operation succeeded after a verification read. However, in this example, the voltage of the second write operation was higher than that of the first. Figure 45 In the example shown in (A), as indicated by the dashed line, the bit line voltage during the second write is greater than the bit line voltage during the first write. Figure 45In the example shown in (B), as indicated by the dashed line, the source line voltage during the second write is greater than the source line voltage during the first write. Alternatively, the voltage can be reset so that the pulse width of the second write voltage is greater than that of the first write voltage, either without changing the write voltage magnitude or while changing the write voltage magnitude.

[0370] According to the above-described variation 2, the write error rate can be reduced, and the possibility of reducing power consumption is increased.

[0371] 2.2 Second Implementation Method

[0372] As previously referred to Figure 10 As described above, the magnetic storage element 1 has characteristics that differ depending on the write direction, i.e., switching from a low resistance value to a high resistance value and switching from a high resistance value to a low resistance value. To reduce the write error rate on one side, it is conceivable that a longer voltage (e.g., a voltage with a larger pulse width) needs to be applied. Since the write latency is determined by the length of the applied voltage, the worst-case latency is visible from the outside of the storage device 7. It is generally believed that by pre-initializing unwanted data, the write time can appear short.

[0373] In the first embodiment described above, upon receiving a write command, data is written to the magnetic storage element 1. In this second embodiment, the magnetic storage element 1 is pre-initialized to have a resistance value that is either low or high. After initialization, only for magnetic storage elements 1 whose resistance value needs to be changed from the initial value, their resistance value is switched to the other resistance value that is either low or high.

[0374] In one embodiment, the time for applying voltage to the magnetic storage element 1 to give it a resistance value (initial value) can be shorter than the time for applying voltage to the magnetic storage element 1 to give it another resistance value. This reduces the time required for data writing.

[0375] Furthermore, unless otherwise stated, it is assumed in the following text that the resistance value of the magnetic storage element 1 after initialization is a high resistance value (i.e., initial value = high resistance value).

[0376] Figure 46 This is a schematic structural example of the storage device 7 according to the second embodiment. The storage device 7 includes a plurality of storage blocks 8 and an access control unit 9.

[0377] As multiple storage blocks 8, in Figure 46 In the diagram, the three storage blocks 8 are labeled as storage block 8-1, storage block 8-2, and storage block 8-3. Unless otherwise specified, they are simply referred to as storage block 8.

[0378] Storage block 8 includes the storage array 70, control circuitry 731, and sense amplifier 739 described in the previous first embodiment. Although Figure 46 Not shown in the diagram, but bit line BL, source line SL, and word line WL ( Figure 37 It is also included in storage block 8.

[0379] One of the features of the second embodiment is that the storage device 7 includes multiple storage arrays 70, etc., corresponding to multiple storage blocks 8. The multiple storage blocks 8 can operate in parallel. For example, for an input number of bits N (N is an integer greater than 2), N storage blocks 8 operate in parallel.

[0380] The access control unit 9 is configured to simultaneously control multiple memory blocks 8. The functions of the access control unit 9 can be implemented through hardware design, and some functions can also be implemented through software design. Figure 46 In the example shown, the access control unit 9 includes a microcontroller 91 and an initialization table 92, in addition to the I / O 730 described in the first embodiment. The microcontroller 91 performs various controls / processes according to the software design. Examples of control include management control of initialized regions (memory areas within the memory array 70), in which the initialization table 92 is also used. Unless otherwise stated, the unit for initializing the target region is set to each memory block 8.

[0381] The I / O 730 facilitates the exchange of instructions, addresses, write data, and read data between the storage device 7 and external devices. The initialization table 92 manages initialized regions and addresses, recording this information. The initialization table 92 can be stored in non-volatile memory. As the non-volatile memory, any storage array 70 within the storage block 8 can be used, or other non-volatile memory not shown can be used. When the storage block 8 is powered on, the information in the initialization table 92 can be loaded from the non-volatile memory into the SRAM for use; when the storage block 8 is powered off, the information in the initialization table 92 can be stored in the non-volatile memory.

[0382] The microcontroller 91 controls the commands input from I / O 730, manages the updates of the initialization table 92, and controls the forward storage of information in the non-volatile memory before shutdown.

[0383] Figure 47 This is a flowchart illustrating a process example executed during initialization. The process begins in response to the input of an initialization command.

[0384] The microcontroller 91 of the access control unit 9 determines whether initialization is complete (step S21). If initialization is complete (step S21: Yes), the flowchart processing ends. Otherwise (step S21: No), for each memory block 8, for example, under the control of the control circuit 731, the resistance value of the magnetic storage element 1 in the initialization target area is initialized.

[0385] Specifically, in this example, the source line SL of the bit line BL and the source line SL is set to a high potential (step S22), and a voltage is set to make the resistance of the magnetic storage element 1 a high resistance value (step S23). This initialization voltage can be the same as that in step S3 of the previous embodiment 1 (step S23). Figure 38 The voltage can be the same as the write voltage set in (etc.), or it can be a voltage set separately for initialization.

[0386] Furthermore, as mentioned above, the resistance value of the magnetic storage element 1 after initialization can also be a low resistance value (in other words, the initial value = low resistance value). In this case, the bit line BL can be set to a high potential in step S22 above.

[0387] Figure 48 This is a diagram illustrating an example of a timing diagram during initialization. The initialization start signal is, for example, given by control circuit 731 (…). Figure 46 )generate.

[0388] In response to the initialization start signal, a word line voltage is applied. Simultaneously, in this example, the source line voltage is controlled to be higher than the bit line voltage. The resistance value of magnetic storage element 1 is initialized to a high resistance value.

[0389] Furthermore, the pulse widths of the word line voltage and the source line voltage can be different. For example, control can be implemented as follows: the word line voltage rises first, then the source line voltage rises, and then the word line voltage falls after the source line voltage falls. Moreover, their pulse widths can be the same as described above. Figure 39 The pulse widths during writing can be the same or different.

[0390] Figure 49 This is a flowchart illustrating an example of the processing (data writing method) performed when data is written. The process begins in response to the input of a write command and the input of data to be written.

[0391] The microcontroller 91 of the access control unit 9 determines whether to make the magnetic storage element 1 of the corresponding memory block 8 have a low resistance value (step S31). If it is necessary to make the magnetic storage element 1 have a low resistance value (step S31: Yes), the reference to the previous process is executed on the corresponding memory block 8. Figure 38 The processing of steps S4 to S6 is explained. Otherwise, that is, when it is desired to make the magnetic storage element 1 have a high resistance value (step S31: no), for the corresponding storage block 8, the process is transferred to the above. Figure 47The processing of steps S21 to S23 is performed. If initialization is not completed (step S21: No), a pulse voltage is applied after the processing of steps S22 and S23 (step S6). Furthermore, when initialization is completed in step S21 (step S21: Yes), the flowchart processing ends.

[0392] Since the timing diagram is based on the aforementioned Figure 39 and Figure 43 Since a similar explanation can be provided, detailed explanations are omitted.

[0393] The storage device 7 according to the second embodiment can suppress write latency.

[0394] <Modifications of the second embodiment>

[0395] By changing the storage layer 3 of the magnetic storage element 1 in storage block 8 ( Figure 1 The size of the magnetic storage element 1 (e.g., [size of the storage layer 1]) can alter the retention characteristics of the magnetic storage element 1. The size of the storage layer 3 is defined by its thickness (length along the Z-axis) when viewed from the side of the magnetic storage element 1, and its area when viewed from above (along the Z-axis). The size of the storage layer 3 can be understood as thickness, area, volume, etc. Unless otherwise stated, it is assumed that the size of the storage layer 3 refers to its volume. The larger the size of the magnetic storage element 1, the higher its retention characteristics (performance), and the longer it can retain data.

[0396] In one embodiment, the plurality of storage blocks 8 included in the storage device 7 may include magnetic storage elements 1 having different sizes from each other. (See also...) Figure 50 Please provide an explanation.

[0397] Figure 50 This is a schematic structural example of the storage device 7. Two storage blocks 8 are illustrated as storage blocks 8 included in the storage device 7. The first and second storage blocks are illustrated as storage block 8-1 and storage block 8-2, respectively. Unless otherwise specified, they are simply referred to as storage block 8. Furthermore, Figure 50 The memory array 70 and the magnetic storage element 1 included in the memory block 8 are shown only schematically.

[0398] The magnetic storage element 1 included in storage block 8-1 and the magnetic storage element 1 included in storage block 8-2 have different sizes. In this example, the size of the magnetic storage element 1 in storage block 8-1 is larger than the size of the magnetic storage element 1 in storage block 8-2.

[0399] Compared to magnetic storage element 1 in storage block 8-2, magnetic storage element 1 in storage block 8-1 has higher retention characteristics. Storage block 8-1 is suitable for long-term data storage. Although the retention characteristics of magnetic storage element 1 in storage block 8-2 are lower than those in storage block 8-1, it can shorten the time required to write data or reduce power (voltage, current). Storage block 8-2 is suitable for short-term data storage.

[0400] As described above, it is effective to use multiple memory blocks 8, each comprising a magnetic storage element 1 with different dimensions (retention characteristics) from the others. Including this, the memory device 7 described above can be assembled and used in various chips and devices, etc. The third to fifth embodiments will be described.

[0401] 2.3 Third Implementation Method

[0402] Figure 51 This is a schematic structural example of the storage device 7 according to the third embodiment. The storage device 7 is assembled and used in the AI ​​chip 10. The AI ​​chip 10 is, for example, configured as a semiconductor chip including Si semiconductors, and includes an AI processing circuit 11 and a storage area 12.

[0403] AI processing circuit 11 performs various AI (Artificial Intelligence) processes. Examples of AI processing include recognition and reasoning. Examples of processing objects include, but are not limited to, articles, images, videos, sounds, and music.

[0404] Storage area 12 stores the data used in AI chip 10. The storage device 7 is used in this storage area 12. Specifically, storage area 12 includes a long-term storage area 121 and a short-term storage area 122.

[0405] In this example, learning data is stored in the long-term retention area 121. Since the learning data is updated infrequently, long-term data retention is required for the long-term retention area 121. Calculated values ​​are stored in the short-term retention area 122. Because the calculated values ​​are updated frequently (rewritten, etc.), the short-term retention area 122 only needs to retain data for short periods, but low latency is required.

[0406] The long-term storage area 121 of storage area 12 includes storage block 8-1. (See previous reference...) Figure 50 The storage block 8-1 described here includes a magnetic storage element 1 with a large size, suitable for long-term data retention.

[0407] The short-term holding area 122 of storage area 12 includes storage block 8-2. (See previous reference...) Figure 50The storage block 8-2 here includes a magnetic storage element 1 with a small size. The writing time is short, and correspondingly, low latency can be achieved.

[0408] Figure 52 and Figure 53 This is a flowchart illustrating a processing example executed in AI chip 10.

[0409] Figure 52 The process for updating learning data is illustrated. When learning data is input (step S31), the data is stored in the long-term retention area 121 (step S32). Specifically, bit data is written into the magnetic storage element 1 of the storage block 8-1 included in the long-term retention area 121. The learning data can be generated and updated by the AI ​​processing circuit 11.

[0410] Figure 53 The process flow during AI processing is illustrated. When AI processing target data is input (step S41), learning data is read from the long-term storage area 121 (step S42), and AI processing is performed (step S43). For example, the AI ​​processing circuit 11 performs a product sum operation on the input data and the learning data. The operation value used at this time is stored in the short-term storage area 122 (step S44). It can also be described as temporarily storing the intermediate results of the operation. The operation using the learning data and the intermediate results of the operation is repeated a predetermined number of times, corresponding to the components of the AI ​​processing circuit 11, such as the number of networks and the number of layers (step S45: No, steps S42 to S44). When the predetermined number of times is reached (step S45: Yes), the AI ​​processing circuit 11 ends the operation and outputs the result (step S46).

[0411] When writing data to the long-term storage region 121 and the short-term storage region 122, the same method as described above can be used. For example, when writing data to the long-term storage region 121, i.e., updating the learning data, since high-speed processing like AI processing is not required, a verification read can be performed to significantly reduce the write error rate. The flowchart and timing diagram are the same as described above. Figures 42 to 45 The same applies. When writing data to the short-term holding area 122, i.e., updating the calculated value, from the perspective of low-latency access, verification reading can be omitted. The flowchart and timing diagram are the same as above. Figure 38 and Figure 39 The same is fine.

[0412] For example, as described above, the storage device 7 can be assembled and used in the AI ​​chip 10. Furthermore, the same application can be performed on chips and devices configured to perform various known processes, not limited to AI processing. In this sense, the AI ​​chip 10 can be replaced, as appropriate, with chips and devices not limited to AI processing.

[0413] <Modifications of the Third Embodiment>

[0414] Several variations of the third embodiment described above will be explained.

[0415] <Modification 1 of the third embodiment>

[0416] In the long-term retention region 121, because learning data is retained across a long period, the error rate may increase over time. To address this, error correction techniques can be applied to the long-term retention region 121. By storing error correction encoded data, fault tolerance is improved. In one implementation, error correction can be performed only on the long-term retention region 121, which is part of the short-term retention region 122. See also... Figure 54 Please provide an explanation.

[0417] Figure 54 This is a diagram illustrating a modified example. The AI ​​chip 10 only has error correction functionality for the long-term storage region 121, which is one of the long-term storage region 121 and the short-term storage region 122. Specifically, the AI ​​chip 10 includes an error correction circuit 13. The error correction circuit 13 performs error correction encoding on the learning data stored in the long-term storage region 121, or performs error correction decoding on the learning data read from the long-term storage region 121.

[0418] Figure 55 and Figure 56 This is a flowchart illustrating a processing example executed in AI chip 10.

[0419] Figure 55 This illustrates the process for updating learning data. This process is similar to the one described above. Figure 52 The difference between the previous process and the previous one is that step S33 is included between step S31 and step S32. When learning data is input (step S31), the data is coded for error correction (step S33) and stored in the long-term storage area 121 (step S32).

[0420] Figure 56 This illustrates the process of AI processing. This process is similar to the one described above. Figure 53 The difference between this process and the previous one is that step S47 is included between steps S42 and S43. When the input data is used as the object of AI processing (step S41), the learning data is read from the long-term storage area 121 (step S42) and error correction decoding is performed (step S47). The subsequent processing steps S44 to S46 are as described above.

[0421] The aforementioned error correction function can also be used to refresh the data in the long-term maintenance zone 121. (Refer to...) Figure 57 Please provide an explanation.

[0422] Figure 57This is a flowchart illustrating a processing example executed in the AI ​​chip 10. The process begins in response to receiving a refresh command. When a refresh command is received, learning data is read from the long-term storage area 121 (step S51), and error detection is performed (step S52). If no error is found (step S53: No), the flowchart processing ends. If an error is found (step S53: Yes), it is determined whether it can be corrected (step S54). If it can be corrected (step S54: Yes), the error is corrected (step S55), and the corrected learning data is saved in the long-term storage area 121 (step S56), ending the flowchart processing. If it cannot be corrected (step S54: No), the system is notified (step S57), ending the flowchart processing. The system may be, for example, a system running on a device equipped with the AI ​​chip 10.

[0423] By using error correction functions as described above, the fault tolerance of data, especially learning data, can be improved for long-term preservation.

[0424] <Modification 2 of the third embodiment>

[0425] Error correction techniques can also be applied to the short-term hold region 122. The error correction capabilities of the error-correcting codes can be designed differently between the long-term hold region 121 and the short-term hold region 122. In the short-term hold region 122, from the perspective of low-latency readout, for example, Hamming codes or 2-bit corrected BCH codes can be used. In the long-term hold region 121, because the tolerance for low latency is higher compared to the short-term hold region 122, correspondingly higher-performance error-correcting codes can be used. Both the long-term hold region 121 and the short-term hold region 122 can improve fault tolerance.

[0426] 2.4 Fourth Implementation Method

[0427] Figure 58 This is a schematic structural example of the storage device 7 according to the fourth embodiment. The storage device 7 is assembled and used in the solid-state imaging device 14 (image sensor). Figure 58 In the diagram, the constituent elements of the solid-state imaging device 14, namely ADC 141, frame memory control unit 142, logic unit 143, memory control unit 144, I / F 145, and storage area 146, are shown by labeling.

[0428] First, storage area 146 will be described. Storage area 146 stores data used in the solid-state imaging device 14. Representative memory functions related to data processing in the solid-state imaging device 14 include frame memory storing one frame of image data, image processing memory storing data related to image processing, and non-volatile memory for storing setting values ​​for image processing and data transmission. Some or all of these utilize the technology of storage device 7. Specifically, storage area 146 includes a short-term retention area 147 and a long-term retention area 148.

[0429] Image data is stored in the short-term retention area 147. The short-term retention area 147 includes a storage block 8-2. As described above, the storage block 8-2 here includes a small-sized magnetic storage element 1, which requires short writing time and can achieve low latency.

[0430] In this example, there are two short-term holding regions 147. One short-term holding region 147 is illustrated as short-term holding region 147-1. The other short-term holding region 147 is illustrated as short-term holding region 147-2. Short-term holding regions 147-1 and 147-2 are each configured to include storage block 8-2. The storage block 8-2 included in short-term holding region 147-1 is illustrated as storage block 8-2-1. The storage block 8-2 included in short-term holding region 147-2 is illustrated as storage block 8-2-2. Furthermore, without specifically distinguishing between short-term holding regions 147-1 and 147-2, and storage blocks 8-2-1 and 8-2-2, they are simply referred to as short-term holding regions 147 and storage block 8-2.

[0431] The long-term storage area 148 stores program data and operating settings. Program data includes, for example, control programs used to control the solid-state imaging device 14 as a whole. Operating settings include, for example, parameters specifying the operation of image processing and I / F 145 within the solid-state imaging device 14. The long-term storage area 148 includes a storage block 8-1. As described above, the storage block 8-1 here includes a large-size magnetic storage element 1, suitable for long-term data retention.

[0432] The ADC 141 converts the analog pixel signal obtained from the pixel array section (not shown) into a digital signal. The frame memory control unit 142 stores one frame of image data in the short-term holding area 147-1 of the memory area 146. The logic unit 143 performs image processing based on the one frame of image data. One example of image processing is image correction processing, but it is not limited to this, and various known image processing methods can be performed. The memory control unit 144 stores the logically processed image data in the short-term holding area 147-2 of the memory area 146. The I / F 145 outputs the image data to the outside.

[0433] Furthermore, as described above, the short-term holding area 147-1, which stores one frame of image data after AD conversion, is used as a frame memory. The short-term holding area 147-2, which stores image data after image processing and before output by I / F 145, can also be referred to as a buffer, subsequent memory, main memory, etc.

[0434] Figures 59 to 61 This is a flowchart illustrating a processing example performed in the solid-state imaging device 14.

[0435] Figure 59 The startup process is shown. Operating settings are read from the long-term retention area 148 (step S61). Since internal non-volatile memory is used, there is no need to load data from external flash memory, thus speeding up the startup process.

[0436] Figure 60 The process of updating program data is shown. When program data is entered (step S71), the data is stored in the long-term storage area 148 (step S72).

[0437] Figure 61 The flowchart illustrates the image data processing procedure. An AD conversion is performed on the pixel signal (step S81), and the resulting image data is stored in the short-term holding region 147-1 (step S82). Image data is read from the short-term holding region 147-1 (step S83), image processing is performed, and the image data is stored in the short-term holding region 147-2 (step S84). Image data is read from the short-term holding region 147-2 and output from I / F 145 (step S85).

[0438] When writing data to the long-term storage area 148 and the short-term storage area 147, the same method as described above can be used. For example, when writing data to the long-term storage area 148, i.e., updating program data, since high-speed processing like image processing is not required, a verification read can be performed to significantly reduce the write error rate. The flowchart and timing diagram are the same as described above. Figures 42 to 45 The same applies. When writing data to the short-term holding region 147, i.e., updating image data, from the perspective of low-latency access, verification reading can be omitted. The flowchart and timing diagram are the same as those described above. Figure 38 and Figure 39 The same is fine.

[0439] <Modifications of the Fourth Embodiment>

[0440] Several variations of the fourth embodiment described above will be explained.

[0441] <Modification 1 of the 4th Embodiment>

[0442] In the fourth embodiment, error correction code technology can also be applied in the same way as in the third embodiment. The solid-state imaging device 14 at this time includes, for example, the same as previously referenced... Figure 54 The same circuit as the error correction circuit 13 described herein can be used. Error correction circuit 13 can be set only for the long-term retention area 148 of the short-term retention area 147 and the long-term retention area 148 of the storage area 146. This can improve the fault tolerance of the data involved in long-term data retention.

[0443] <Modification 2 of the 4th Embodiment>

[0444] Error correction techniques can also be applied to short-term retention region 147. The error correction capabilities of the error correction code can be designed differently between long-term retention region 148 and short-term retention region 147. Due to the details being similar to those of long-term retention region 121 and short-term retention region 122 mentioned above... Figure 51 Similarly, it will not be repeated here. Both the long-term hold zone 148 and the short-term hold zone 147 can improve fault tolerance.

[0445] In one embodiment, the solid-state imaging device 14 may have a stacked structure with multiple chips stacked on top of each other. This will be described as a fifth embodiment.

[0446] 2.5 Fifth Implementation Method

[0447] Figure 62 This is a schematic structural example of the storage device 7 according to the fifth embodiment. The solid-state imaging device 14 includes multiple chips and has a stacked structure formed by stacking these chips. Chips CH1 and CH2 are shown as examples of the multiple chips. Chips CH1 and CH2 function as the solid-state imaging device 14 in their stacked state. Figure 62 In the diagram, chip CH1 and chip CH2 are shown in a decomposed manner along the stacking direction.

[0448] Chip CH1 is a pixel chip. Chip CH1 contains, for example, multiple pixels (pixel array section) arranged in a two-dimensional array, and pixel circuits including transistors for pixel driving.

[0449] Chip CH2 is an image processing chip used to process pixel signals. In this example, chip CH2 includes a logic area R1 and a memory area R2. The logic area R1 contains the aforementioned... Figure 58 The ADC 141, frame memory control unit 142, logic unit 143, memory control unit 144, I / F 145, etc. are shown. The aforementioned memory area 146 is provided in memory area R2, which also includes memory device 7.

[0450] For example, the storage device 7 can be applied to a solid-state imaging device 14 having the above-described stacked chip structure.

[0451] <Modifications of the 5th Embodiment>

[0452] Figure 63 The diagram shows a modified example. In chip CH2, SRAM 15 is provided in the area outside the logic region R1 and the memory region R2. The memory device 7 can also be applied to such a solid-state imaging device 14.

[0453] 2.6 Implementation Method 6

[0454] Figure 64 This is a schematic structural example of the storage device 7 according to the sixth embodiment. The storage device 7 is assembled and used in the CPU 16. The CPU 16 includes a CPU core 160, a level 1 cache 161, and a level 2 cache 162.

[0455] CPU core 160 uses L1 cache 161 and L2 cache 162 to perform various computational operations.

[0456] The Level 1 cache 161 includes a storage device 7 and an error correction circuit 13. The error correction circuit 13 is as previously described. Although in Figure 65 The error correction circuit 13 is represented as an element other than the storage device 7, but the error correction circuit 13 may also be included in the storage device 7 as a constituent element of the storage device 7.

[0457] The L2 cache 162, like the L1 cache 161, includes a storage device 7 and an error correction circuit 13.

[0458] The aforementioned CPU 16 is suitable for systems requiring large-scale caches and high-speed processing, such as processors mounted on servers in communication networks. In SRAM, due to its large area, leakage is also significant; therefore, as the size of the cache increases, memory power consumption becomes a problem. Compared to SRAM, the magnetic storage element 1 included in the storage device 7 has a smaller area, reducing leakage.

[0459] Alternatively, the structure can be without error correction circuit 13. When error correction circuit 13 is present, the possibility of reducing the write error rate is correspondingly increased.

[0460] <Modifications of the 6th Embodiment>

[0461] Figure 65 The diagram illustrates a modified example. The L1 cache 161 of the CPU 16 includes SRAM 15. This allows for a structure where storage device 7 and SRAM 15 coexist. Various designs corresponding to required specifications are possible.

[0462] <Summary>

[0463] The storage device 7 described above is determined, for example, in the following manner. (Refer to...) Figures 1 to 9 , Figures 19 to 23 , Figures 25 to 45 As described above, the storage device 7 includes a magnetic storage element 1 and a control circuit 731 for controlling the writing of data to the magnetic storage element 1. The magnetic storage element 1 includes a magnetization fixing layer 2 whose magnetization direction is fixed and a storage layer 3 whose magnetization direction can be reversed. The storage layer 3 includes a first region 31 containing a ferromagnetic material and a second region containing an antiferromagnetic material or a ferrimagnetic material.

[0464] According to the above-described storage device 7, the storage device 7 can also obtain the power consumption suppression and other effects of the above-described magnetic storage element 1.

[0465] For reference Figure 10 , Figures 36 to 39 As described above, the magnetic storage element 1 has a resistance value corresponding to the magnetization direction of the storage layer 3. The control performed by the control circuit 731 may include: applying a voltage of either a positive voltage (voltage V>0) or a negative voltage (voltage V<0) to the magnetic storage element 1 to give it a resistance value of either a low resistance value or a high resistance value (steps S2, S3, and S6, or steps S4, S5, and S6); and applying another voltage of either a positive voltage or a negative voltage to the magnetic storage element to give it another resistance value of either a low resistance value or a high resistance value (steps S2, S3, and S6, or steps S4, S5, and S6). For example, data can be written to the magnetic storage element 1 in this manner.

[0466] For reference Figure 10As described above, when a magnetic field H is not applied to the magnetic storage element 1, and a positive or negative voltage is applied to the magnetic storage element 1, the magnetic storage element 1 becomes a resistance value that is either low or high. Similarly, when a positive or negative voltage is applied to the magnetic storage element 1, the magnetic storage element 1 becomes a resistance value that is either low or high. The magnetic storage element 1 has an RH hysteresis loop characteristic, where the resistance value changes with the magnitude of the applied magnetic field (magnetic field H). Furthermore, the hysteresis of the RH hysteresis loop characteristic when a positive voltage (voltage V>0) is applied to the magnetic storage element 1 and the hysteresis of the RH hysteresis loop characteristic when a negative voltage (voltage V<0) is applied to the magnetic storage element 1 can be shifted to opposite sides from the hysteresis of the RH hysteresis loop characteristic when no voltage is applied to the magnetic storage element 1 (voltage V≈0). The hysteresis of the RH hysteresis characteristic when no voltage is applied to the magnetic storage element 1 (V≈0) can cross the applied magnetic field magnitude = 0 (magnetic field H=0), while the hysteresis of the RH hysteresis characteristic when a positive voltage is applied to the magnetic storage element 1 (voltage V>0) and the hysteresis of the RH hysteresis characteristic when a negative voltage is applied to the magnetic storage element 1 (voltage V<0) do not cross the applied magnetic field magnitude = 0 (magnetic field H=0). The hysteresis of the RH hysteresis characteristic when one of the positive and negative voltages (e.g., voltage V>0) is applied to the magnetic storage element 1 can be greater than the hysteresis of the RH hysteresis characteristic when no voltage is applied to the magnetic storage element 1 (voltage V≈0), and the hysteresis of the RH hysteresis characteristic when the other of the positive and negative voltages (e.g., voltage V<0) is applied to the magnetic storage element 1 can be smaller than the hysteresis of the RH hysteresis characteristic when no voltage is applied to the magnetic storage element 1 (voltage V≈0). For example, data can be written to the magnetic storage element 1 using this electromagnetic characteristic.

[0467] For reference Figures 46 to 49 As described above, the control circuit 731 may perform initialization to give the magnetic storage element 1 a resistance value of either low or high (e.g., high resistance) (steps S22, S23, and S6), and then switch the initialized resistance value of the magnetic storage element 1 to another resistance value of either low or high (e.g., low resistance) (steps S4 to S6). The voltage application time for giving the magnetic storage element 1 one resistance value can be shorter than the voltage application time for giving the magnetic storage element 1 another resistance value. This reduces the time required for data writing.

[0468] For reference Figure 46 and Figure 50As described above, the storage device 7 may include storage blocks 8-1 and 8-2 (a first storage block and a second storage block), which include magnetic storage elements 1 of different sizes. Therefore, the two types of storage blocks 8 can be used separately. For example, a storage block 8 including magnetic storage elements 1 of a large size is suitable for long-term data storage. A storage block 8 including magnetic storage elements 1 of a small size can be used to shorten the time required to write data or reduce power (voltage, current).

[0469] Storage device 7 can be assembled and used in various chips and devices, etc. For example, see reference. Figures 51 to 57 As described above, the storage device 7 can be assembled and used in the AI ​​chip 10. (See reference...) Figures 58 to 63 As described above, the storage device 7 can be assembled and used in the solid-state imaging device 14. (See reference...) Figure 64 and Figure 65 As described above, storage device 7 can be assembled and used in CPU 16.

[0470] The various processes performed in storage device 7 can also be identified as techniques of methods. One such method is the data writing method. (See reference...) Figures 1 to 9 , Figures 19 to 23 , Figures 25 to 45 As described above, the writing method is a method of writing data into a magnetic storage element 1. The magnetic storage element 1 includes a magnetization-fixed layer 2 with a fixed magnetization direction and a storage layer 3 with a reversible magnetization direction. The storage layer 3 includes a first region 31 containing a ferromagnetic material and a second region 32 containing an antiferromagnetic material or a ferrimagnetic material. The magnetic storage element 1 has a resistance value corresponding to the magnetization direction of the storage layer 3. The writing method includes applying one of a positive voltage (voltage V>0) and a negative voltage (voltage V<0) to the magnetic storage element 1 to give it a resistance value of either a low resistance value or a high resistance value (steps S2, S3, and S6, or steps S4, S5, and S6), and applying another voltage (positive voltage and negative voltage) to the magnetic storage element to give it another resistance value of either a low resistance value or a high resistance value (steps S2, S3, and S6, or steps S4, S5, and S6). With such a writing method, power consumption can also be suppressed as described above.

[0471] Furthermore, the effects described in this disclosure are merely illustrative and are not limited to the disclosed content. Other effects are also possible.

[0472] The embodiments of this disclosure have been described above, but the technical scope of this disclosure is not limited to the above embodiments themselves, and various modifications can be made without departing from the spirit of this disclosure. In addition, the constituent elements of different embodiments and variations can be combined as appropriate.

[0473] In addition, this technology can also adopt the following structure.

[0474] (1) A magnetic storage element, comprising:

[0475] A magnetization fixation layer whose magnetization direction is fixed; and

[0476] A storage layer with reversible magnetization direction, wherein,

[0477] The storage layer includes:

[0478] The first region contains ferromagnetic material; and

[0479] The second region contains antiferromagnetic or ferrimagnetic materials.

[0480] (2) The magnetic storage element according to (1), wherein

[0481] The first region and the second region are stacked.

[0482] (3) The magnetic storage element according to (1), wherein

[0483] The storage layer comprises a plurality of the first regions and a plurality of the second regions, which are distributed in a distributed manner.

[0484] (4) The magnetic storage element according to any one of (1) to (3), wherein

[0485] The storage layer includes a spacer region disposed between the first region and the second region and containing a non-magnetic material.

[0486] (5) The magnetic storage element according to any one of (1) to (3), wherein

[0487] The first region contains at least one of Co, Fe, Ni, Mn, Al, B, P, C, Zr, Hf, Ta, and Nb.

[0488] (6) The magnetic storage element according to (5), wherein

[0489] The first region contains CoFeB.

[0490] (7) The magnetic storage element according to (6), wherein

[0491] In the first region, the Fe composition ratio in the CoFeB is greater than the Co composition ratio.

[0492] (8) The magnetic storage element according to (6) or (7), wherein

[0493] The proportion of B in the CoFeB of the first region is less than 40 at%.

[0494] (9) The magnetic storage element according to any one of (1) to (8), wherein

[0495] The first region has a thickness of more than 0.1 nm and less than 1.5 nm.

[0496] (10) The magnetic storage element according to any one of (1) to (9), wherein

[0497] The second region contains at least one of Mn, Cr, Ir, Pt, Pd, Ni, Sn, Fe, Ge, Co, Ga, and Si.

[0498] (11) The magnetic storage element according to any one of (1) to (9), wherein

[0499] The second region contains chalcogenides.

[0500] (12) The magnetic storage element according to (11), wherein

[0501] The chalcogenides in the second region include CuMnAs or MnPS3.

[0502] (13) The magnetic storage element according to any one of (1) to (9), wherein

[0503] The second region contains oxides.

[0504] (14) The magnetic storage element according to (13), wherein

[0505] The oxide in the second region comprises NiO, Cr2O3, CoO, Fe2O3, or Mn2O3.

[0506] (15) The magnetic storage element according to (10), wherein

[0507] The second region contains an antiferromagnetic alloy or a subferromagnetic alloy.

[0508] (16) The magnetic storage element according to (15), wherein

[0509] The antiferromagnetic or subferromagnetic alloy in the second region includes FeNiMn, CrNiMn, FeCrMn, FeCoMn, CoNiMn, FeNiCr, GaNiMn, CoPtMn, FePtMn, FeMn, NiMn, FeNi, PtMn, PdMn, or CoGeMn.

[0510] (17) The magnetic storage element according to (16), wherein

[0511] The alloy in the second region is an Fe alloy with Fe, Ni, and Mn composition ratios set as x, y, and z. x Ni y Mn z The alloy has a composition range of 0at% < x ≤ 95at%, 0at% < y ≤ 80at%, and 5at% ≤ z ≤ 80at%.

[0512] (18) The magnetic storage element according to (16), wherein

[0513] The alloy in the second region is a Cr alloy with the composition ratio of Cr, Ni, and Mn set as x, y, z. x Ni y Mn z The alloy has a composition range of 0at% < x ≤ 65at%, 0at% < y ≤ 75at%, and 0at% < z ≤ 80at%.

[0514] (19) The magnetic storage element according to (16), wherein

[0515] The alloy in the second region is an Fe alloy with Fe, Cr, and Mn composition ratios set as x, y, and z. x Cr y Mn z The alloy has a composition range of 0at% < x ≤ 95at%, 0at% < y ≤ 70at%, and 5at% ≤ z ≤ 80at%.

[0516] (20) The magnetic storage element according to (16), wherein

[0517] The alloy in the second region is an Fe alloy with Fe, Co, and Mn composition ratios set as x, y, z. x Co y Mn z The alloy has a composition range of 0at% < x ≤ 95at%, 0at% < y ≤ 50at%, and 5at% ≤ z ≤ 80at%.

[0518] (21) The magnetic storage element according to (16), wherein

[0519] The second region is Ga in which the composition ratio of Ga, Ni, and Mn is set as x, y, z. x Ni y Mn z The alloy has a composition range of 0at% < x ≤ 50at%, 5at% ≤ y ≤ 80at%, and 5at% ≤ z ≤ 90at%.

[0520] (22) The magnetic storage element according to (16), wherein

[0521] The second region is a Fe region where the composition ratio of Fe, Ni, and Cr is set as x, y, z. x Ni y Cr z The alloy has a composition range of 60at%≤x≤82at%, 15at%≤y≤40at%, and 10at%≤z≤35at%.

[0522] (23) The magnetic storage element according to (16), wherein

[0523] The second region is a Co region with the composition ratio of Co, Ge, and Mn set as x, y, z. x 、Ge y Mn z The alloy has a composition range of 0at% < x ≤ 20at%, 0at% < y ≤ 95at%, and 5at% ≤ z < 100at%.

[0524] (24) The magnetic storage element according to any one of (1) to (23), wherein

[0525] The first region and the second region are configured to be magnetically coupled to each other.

[0526] (25) The magnetic storage element according to any one of (1) to (24), wherein

[0527] The second region has a thickness of more than 0.1 nm and less than 5 nm.

[0528] (26) The magnetic storage element according to (4), wherein

[0529] The spacer region contains at least one of Ta, Ru, Ir, W, Mo, Rh, Re, Nb, Cu, Cr, V, TiN, TaN, and WN.

[0530] (27) The magnetic storage element according to (4) or (26), wherein

[0531] The interval region is disposed between the first region and the second region in such a way that the first region and the second region are magnetically coupled to each other.

[0532] The magnetization of the second region acts on the magnetization of the first region via the interval region.

[0533] (28) The magnetic storage element according to (4), (26) or (27), wherein

[0534] The spacing region has a thickness of more than 0.1 nm and less than 1.5 nm.

[0535] (29) The magnetic storage element according to any one of (1) to (28), wherein

[0536] The storage layer includes a barrier layer disposed between the first region and the second region and the magnetization fixation layer.

[0537] The barrier layer comprises an oxide of at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C.

[0538] (30) The magnetic storage element according to any one of (1) to (28), wherein

[0539] The storage layer includes a barrier layer disposed between the first region and the second region and the magnetization fixation layer.

[0540] The barrier layer comprises an oxide of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

[0541] (31) The magnetic storage element according to (29), wherein

[0542] The barrier layer contains MgO.

[0543] (32) The magnetic storage element according to (31), wherein

[0544] In addition to MgO, the barrier layer also contains Fe, Co or Mn.

[0545] (33) The magnetic storage element according to (32), wherein

[0546] The amount of Fe, Co, or Mn added to the MgO in the barrier layer is less than 20 at%.

[0547] (34) The magnetic storage element according to any one of (1) to (33), wherein

[0548] The storage layer includes a barrier layer disposed on the side opposite to the magnetization fixation layer, separated by the first region and the second region.

[0549] The barrier layer comprises at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C.

[0550] (35) The magnetic storage element according to any one of (1) to (33), wherein

[0551] The storage layer includes a barrier layer disposed on the side opposite to the magnetization fixation layer, separated by the first region and the second region.

[0552] The barrier layer comprises an oxide of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

[0553] (36) The magnetic storage element according to (34), wherein

[0554] The barrier layer contains MgO.

[0555] (37) The magnetic storage element according to (36), wherein

[0556] In addition to MgO, the barrier layer also contains Fe, Co or Mn.

[0557] (38) The magnetic storage element according to (37), wherein

[0558] The amount of Fe, Co, or Mn added to the MgO in the barrier layer is less than 20 at%.

[0559] (39) The magnetic storage element according to (34), (36), (37) or (38), wherein

[0560] The barrier layer contains antiferromagnetic oxide.

[0561] (40) The magnetic storage element according to (39), wherein

[0562] The antiferromagnetic oxide of the barrier layer comprises NiO, Cr2O3, CoO, Fe2O3, or Mn2O3.

[0563] (41) The magnetic storage element according to any one of (1) to (40), wherein

[0564] The magnetization fixing layer includes a reference layer whose magnetization direction is fixed.

[0565] The reference layer comprises at least one of Fe, Co, Ni, Mn and B.

[0566] (42) The magnetic storage element according to (41), wherein

[0567] The magnetization fixing layer includes a fixing layer that fixes the magnetization direction of the reference layer.

[0568] (43) The magnetic storage element according to any one of (1) to (42), wherein

[0569] The storage layer includes:

[0570] A barrier layer is set between the first region and the second region and the magnetization fixation layer;

[0571] A barrier layer is disposed on the side opposite to the magnetization fixing layer, separated by the first region and the second region;

[0572] A ferromagnetic layer is disposed on the side opposite to the first region and the second region, separated from the barrier layer.

[0573] (44) The magnetic storage element according to any one of (1) to (42), wherein

[0574] The storage layer includes:

[0575] A spacer layer is disposed on the opposite side of the magnetization fixing layer, separating the first region and the second region;

[0576] A ferromagnetic layer is disposed on the side opposite to the first region and the second region, separated by the spacer layer.

[0577] (45) The magnetic storage element according to any one of (1) to (44), wherein

[0578] The magnetization direction of the storage layer is reversed accordingly with the positive and negative values ​​of the voltage applied to the magnetic storage element.

[0579] (46) A storage device comprising:

[0580] Magnetic storage elements; and

[0581] The control circuit controls the writing of data to the magnetic storage element.

[0582] The magnetic storage element includes:

[0583] A magnetization fixation layer whose magnetization direction is fixed; and

[0584] A storage layer with reversible magnetization direction.

[0585] The storage layer includes:

[0586] The first region contains ferromagnetic material; and

[0587] The second region contains antiferromagnetic or ferrimagnetic materials.

[0588] (47) The storage device according to (46), wherein

[0589] The magnetic storage element has a resistance value corresponding to the magnetization direction of the storage layer.

[0590] The control performed by the control circuit includes:

[0591] A voltage, either positive or negative, is applied to the magnetic storage element to give it a resistance value, either low or high; and

[0592] Apply a voltage, either a positive voltage or a negative voltage, to the magnetic storage element to give it a resistance value, either a low resistance value or a high resistance value.

[0593] (48) The storage device according to (47), wherein

[0594] When no magnetic field is applied to the magnetic storage element,

[0595] When a positive voltage or a negative voltage is applied to the magnetic storage element, the magnetic storage element becomes either a low resistance value or a high resistance value.

[0596] When a voltage, either positive or negative, is applied to the magnetic storage element, the magnetic storage element becomes either a low resistance value or a high resistance value.

[0597] (49) The storage device according to any one of (46) to (48), wherein

[0598] The magnetic storage element has an RH hysteresis characteristic, where the resistance value changes hysteretly with the magnitude of the applied magnetic field, and

[0599] The hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic storage element and the hysteresis of the RH loop characteristic when a negative voltage is applied to the magnetic storage element are offset from the hysteresis of the RH loop characteristic when no voltage is applied to the magnetic storage element to the opposite side.

[0600] (50) The storage device according to (49), wherein

[0601] When the hysteresis loop characteristic of the magnetic storage element is substantially without voltage, a magnetic field of magnitude 0 is applied across it.

[0602] The hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic storage element and the hysteresis of the RH loop characteristic when a negative voltage is applied to the magnetic storage element do not cross the applied magnetic field magnitude = 0.

[0603] (51) The storage device according to (49) or (50), wherein

[0604] The hysteresis of the RH hysteresis characteristic when a positive or negative voltage is applied to the magnetic storage element is greater than the hysteresis of the RH hysteresis characteristic when no voltage is substantially applied to the magnetic storage element.

[0605] The hysteresis of the RH loop characteristic when a positive voltage or a negative voltage is applied to the magnetic storage element is less than the hysteresis of the RH loop characteristic when no voltage is substantially applied to the magnetic storage element.

[0606] (52) The storage device according to any one of (46) to (51), wherein

[0607] The control performed by the control circuit includes:

[0608] Perform initialization to give the magnetic storage element a resistance value that is either low or high; and

[0609] Switch the resistance value of the initialized magnetic storage element to either a low resistance value or a high resistance value.

[0610] (53) The storage device according to (52), wherein

[0611] The voltage applied to the magnetic storage element for giving it one resistance value is applied for a shorter time than the voltage applied to the magnetic storage element for giving it another resistance value.

[0612] (54) The storage device according to any one of (46) to (53) comprises:

[0613] The first storage block and the second storage block include magnetic storage elements having different sizes from each other.

[0614] (55) The storage device according to any one of (46) to (53), wherein

[0615] The storage device was assembled and used in an AI chip.

[0616] (56) The storage device according to any one of (46) to (53), wherein

[0617] The storage device was assembled and used in a solid-state imaging device.

[0618] (57) The storage device according to any one of (46) to (53), wherein

[0619] The storage device was assembled and used in the CPU.

[0620] (58) A method for writing data to a magnetic storage element, wherein

[0621] The magnetic storage element includes:

[0622] A magnetization fixation layer whose magnetization direction is fixed; and

[0623] A storage layer with reversible magnetization direction.

[0624] The storage layer includes:

[0625] The first region contains ferromagnetic material; and

[0626] The second region contains antiferromagnetic or ferrimagnetic materials.

[0627] The magnetic storage element has a resistance value corresponding to the magnetization direction of the storage layer.

[0628] The writing method includes:

[0629] A voltage, either a positive voltage or a negative voltage, is applied to the magnetic storage element to give the magnetic storage element a resistance value, either a low resistance value or a high resistance value.

[0630] Apply a voltage, either a positive voltage or a negative voltage, to the magnetic storage element to give it a resistance value, either a low resistance value or a high resistance value.

[0631] (59) The writing method according to (58), wherein

[0632] When no magnetic field is applied to the magnetic storage element,

[0633] When a positive voltage or a negative voltage is applied to the magnetic storage element, the magnetic storage element becomes either a low resistance value or a high resistance value.

[0634] When a voltage, either positive or negative, is applied to the magnetic storage element, the magnetic storage element becomes either a low resistance value or a high resistance value.

[0635] (60) The writing method according to (58) or (59), wherein

[0636] The magnetic storage element has an RH hysteresis characteristic, where the resistance value changes hysteretly with the magnitude of the applied magnetic field.

[0637] The hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic storage element and the hysteresis of the RH loop characteristic when a negative voltage is applied to the magnetic storage element are offset from the hysteresis of the RH loop characteristic when no voltage is applied to the magnetic storage element to the opposite side.

[0638] (61) The writing method according to (60), wherein

[0639] When the hysteresis loop characteristic of the magnetic storage element is substantially without voltage, a magnetic field of magnitude 0 is applied across it.

[0640] The hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic storage element and the hysteresis of the RH loop characteristic when a negative voltage is applied to the magnetic storage element do not cross the applied magnetic field magnitude = 0.

[0641] (62) The writing method according to (60) or (61), wherein

[0642] The hysteresis of the RH hysteresis characteristic when a positive or negative voltage is applied to the magnetic storage element is greater than the hysteresis of the RH hysteresis characteristic when no voltage is substantially applied to the magnetic storage element.

[0643] The hysteresis of the RH loop characteristic when a positive voltage or a negative voltage is applied to the magnetic storage element is less than the hysteresis of the RH loop characteristic when no voltage is substantially applied to the magnetic storage element.

[0644] (63) The writing method according to any one of (58) to (62) includes:

[0645] Perform initialization to give the magnetic storage element a resistance value that is either low or high; and

[0646] Switch the resistance value of the initialized magnetic storage element to either a low resistance value or a high resistance value.

[0647] (64) The writing method according to (63), wherein

[0648] The voltage applied to the magnetic storage element for giving it one resistance value is applied for a shorter time than the voltage applied to the magnetic storage element for giving it another resistance value.

[0649] Explanation of reference numerals in the attached figures

[0650] 1: Magnetic storage element

[0651] 2: Ferromagnetic layer

[0652] 21: Immobilization layer

[0653] 22: Reference Layer

[0654] 3: Storage layer

[0655] 30: Barrier Layer

[0656] 31: Area 1

[0657] 32: Area 2

[0658] 33: Interval area

[0659] 34: Barrier Layer

[0660] 35: Spare layer

[0661] 4: Ferromagnetic layer

[0662] 5: Lower electrode layer

[0663] 6: Cover layer

[0664] 7: Storage device

[0665] 70: Storage Array

[0666] 71: Memory Unit

[0667] 72: Select Transistor

[0668] 730: I / O

[0669] 731: Control Circuit

[0670] 732: Voltage Generation Circuit

[0671] 733: Write Circuit

[0672] 734: Reading Circuit

[0673] 735: Bit / Source Line Address Decoder

[0674] 736: Bit / Source Line Control Circuit

[0675] 737: Word Line Address Decoder

[0676] 738: Word line control circuit

[0677] 739: Readout Amplifier

[0678] 8: Storage Block

[0679] 8-1: Storage Block (Storage Block 1)

[0680] 8-2: Storage Block (Second Storage Block)

[0681] 8-3: Storage Block

[0682] 9: Access Control Unit

[0683] 91: Microcontroller

[0684] 92: Initialize the table

[0685] 10: AI Chips

[0686] 11: AI Processing Circuit

[0687] 12: Storage area

[0688] 121: Long-term maintenance zone

[0689] 122: Short-term maintenance zone

[0690] 13: Error Correction Circuit

[0691] 14: Solid-state imaging device

[0692] 15: SRAM

[0693] 16: CPU

[0694] BL: Bitline

[0695] SL: Source Line

[0696] WL: Wordline

[0697] CH1: Chip

[0698] CH2: Chip

[0699] R1: Logical area

[0700] R2: Storage area.

Claims

1. A magnetic storage element, comprising: A magnetization fixation layer in which the magnetization direction is fixed; as well as A storage layer with reversible magnetization direction, wherein, The storage layer includes: The first region contains ferromagnetic material; and The second region contains antiferromagnetic or ferrimagnetic materials.

2. The magnetic storage element according to claim 1, wherein... The first region and the second region are stacked.

3. The magnetic storage element according to claim 1, wherein... The storage layer comprises a plurality of the first regions and a plurality of the second regions, which are distributed in a distributed manner.

4. The magnetic storage element according to claim 1, wherein... The storage layer includes a spacer region disposed between the first region and the second region and containing a non-magnetic material.

5. The magnetic storage element according to claim 1, wherein... The first region contains at least one of Co, Fe, Ni, Mn, Al, B, P, C, Zr, Hf, Ta, and Nb.

6. The magnetic storage element according to claim 5, wherein The first region contains CoFeB.

7. The magnetic storage element according to claim 6, wherein... In the first region, the Fe composition ratio in the CoFeB is greater than the Co composition ratio.

8. The magnetic storage element according to claim 6, wherein The proportion of B in the CoFeB of the first region is less than 40 at%.

9. The magnetic storage element according to claim 1, wherein... The first region has a thickness of more than 0.1 nm and less than 1.5 nm.

10. The magnetic storage element according to claim 1, wherein The second region contains at least one of Mn, Cr, Ir, Pt, Pd, Ni, Sn, Fe, Ge, Co, Ga, and Si.

11. The magnetic storage element according to claim 1, wherein The second region contains chalcogenides.

12. The magnetic storage element according to claim 11, wherein... The chalcogenides in the second region include CuMnAs or MnPS3.

13. The magnetic storage element according to claim 1, wherein... The second region contains oxides.

14. The magnetic storage element according to claim 13, wherein... The oxide in the second region comprises NiO, Cr2O3, CoO, Fe2O3, or Mn2O3.

15. The magnetic storage element according to claim 10, wherein... The second region contains an antiferromagnetic alloy or a hypoferromagnetic alloy.

16. The magnetic storage element according to claim 15, wherein... The antiferromagnetic or subferromagnetic alloy in the second region includes FeNiMn, CrNiMn, FeCrMn, FeCoMn, CoNiMn, FeNiCr, GaNiMn, CoPtMn, FePtMn, FeMn, NiMn, FeNi, PtMn, PdMn, or CoGeMn.

17. The magnetic storage element according to claim 16, wherein... The alloy in the second region is an Fe alloy with Fe, Ni, and Mn composition ratios set as x, y, and z. x Ni y Mn z The alloy has a composition range of 0at% < x ≤ 95at%, 0at% < y ≤ 80at%, and 5at% ≤ z ≤ 80at%.

18. The magnetic storage element according to claim 16, wherein... The alloy in the second region is a Cr alloy with the composition ratio of Cr, Ni, and Mn set as x, y, z. x Ni y Mn z The alloy has a composition range of 0at% < x ≤ 65at%, 0at% < y ≤ 75at%, and 0at% < z ≤ 80at%.

19. The magnetic storage element according to claim 16, wherein The alloy in the second region is an Fe alloy with Fe, Cr, and Mn composition ratios set as x, y, and z. x Cr y Mn z The alloy has a composition range of 0at% < x ≤ 95at%, 0at% < y ≤ 70at%, and 5at% ≤ z ≤ 80at%.

20. The magnetic storage element according to claim 16, wherein... The alloy in the second region is an Fe alloy with Fe, Co, and Mn composition ratios set as x, y, z. x Co y Mn z The alloy has a composition range of 0at% < x ≤ 95at%, 0at% < y ≤ 50at%, and 5at% ≤ z ≤ 80at%.

21. The magnetic storage element according to claim 16, wherein The second region is Ga in which the composition ratio of Ga, Ni, and Mn is set as x, y, z. x Ni y Mn z The alloy has a composition range of 0at% < x ≤ 50at%, 5at% ≤ y ≤ 80at%, and 5at% ≤ z ≤ 90at%.

22. The magnetic storage element according to claim 16, wherein... The second region is a Fe region where the composition ratio of Fe, Ni, and Cr is set as x, y, z. x Ni y Cr z The alloy has a composition range of 60at%≤x≤82at%, 15at%≤y≤40at%, and 10at%≤z≤35at%.

23. The magnetic storage element according to claim 16, wherein... The second region is a Co region with the composition ratio of Co, Ge, and Mn set as x, y, z. x 、Ge y Mn z The alloy has a composition range of 0at% < x ≤ 20at%, 0at% < y ≤ 95at%, and 5at% ≤ z < 100at%.

24. The magnetic storage element according to claim 1, wherein The first region and the second region are configured to be magnetically coupled to each other.

25. The magnetic storage element according to claim 1, wherein The second region has a thickness of more than 0.1 nm and less than 5 nm.

26. The magnetic storage element according to claim 4, wherein... The spacer region contains at least one of Ta, Ru, Ir, W, Mo, Rh, Re, Nb, Cu, Cr, V, TiN, TaN, and WN.

27. The magnetic storage element according to claim 4, wherein The interval region is disposed between the first region and the second region in such a way that the first region and the second region are magnetically coupled to each other. The magnetization of the second region acts on the magnetization of the first region via the interval region.

28. The magnetic storage element according to claim 4, wherein The spacing region has a thickness of more than 0.1 nm and less than 1.5 nm.

29. The magnetic storage element according to claim 1, wherein The storage layer includes a barrier layer disposed between the first region and the second region and the magnetization fixation layer. The barrier layer comprises an oxide of at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C.

30. The magnetic storage element according to claim 1, wherein The storage layer includes a barrier layer disposed between the first region and the second region and the magnetization fixation layer. The barrier layer comprises an oxide of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

31. The magnetic storage element according to claim 29, wherein... The barrier layer contains MgO.

32. The magnetic storage element according to claim 31, wherein... In addition to MgO, the barrier layer also contains Fe, Co or Mn.

33. The magnetic storage element according to claim 32, wherein... The amount of Fe, Co, or Mn added to the MgO in the barrier layer is less than 20 at%.

34. The magnetic storage element according to claim 1, wherein The storage layer includes a barrier layer disposed on the side opposite to the magnetization fixation layer, separated by the first region and the second region. The barrier layer comprises at least one of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Mo, Cu, Ba, Ta, W, V, Ni, Co, Mn, Cr, Fe, B, and C.

35. The magnetic storage element according to claim 1, wherein... The storage layer includes a barrier layer disposed on the side opposite to the magnetization fixation layer, separated by the first region and the second region. The barrier layer comprises an oxide of at least one of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

36. The magnetic storage element according to claim 34, wherein... The barrier layer contains MgO.

37. The magnetic storage element according to claim 36, wherein... In addition to MgO, the barrier layer also contains Fe, Co or Mn.

38. The magnetic storage element according to claim 37, wherein... The amount of Fe, Co, or Mn added to the MgO in the barrier layer is less than 20 at%.

39. The magnetic storage element according to claim 34, wherein... The barrier layer contains antiferromagnetic oxide.

40. The magnetic storage element according to claim 39, wherein The antiferromagnetic oxide of the barrier layer comprises NiO, Cr2O3, CoO, Fe2O3, or Mn2O3.

41. The magnetic storage element according to claim 1, wherein The magnetization fixing layer includes a reference layer whose magnetization direction is fixed. The reference layer comprises at least one of Fe, Co, Ni, Mn and B.

42. The magnetic storage element according to claim 41, wherein... The magnetization fixing layer includes a fixing layer that fixes the magnetization direction of the reference layer.

43. The magnetic storage element according to claim 1, wherein The storage layer includes: A barrier layer is set between the first region and the second region and the magnetization fixation layer; A barrier layer is disposed on the side opposite to the magnetization fixing layer, separated by the first region and the second region; A ferromagnetic layer is disposed on the side opposite to the first region and the second region, separated from the barrier layer.

44. The magnetic storage element according to claim 1, wherein The storage layer includes: A spacer layer is disposed on the opposite side of the magnetization fixing layer, separating the first region and the second region; A ferromagnetic layer is disposed on the side opposite to the first region and the second region, separated by the spacer layer.

45. The magnetic storage element according to claim 1, wherein The magnetization direction of the storage layer is reversed accordingly with the positive and negative values ​​of the voltage applied to the magnetic storage element.

46. ​​A storage device comprising: Magnetic storage elements; as well as The control circuit controls the writing of data to the magnetic storage element. in, The magnetic storage element includes: A magnetization fixation layer whose magnetization direction is fixed; and A storage layer with reversible magnetization direction. The storage layer includes: The first region contains ferromagnetic material; as well as The second region contains antiferromagnetic or ferrimagnetic materials.

47. The storage device according to claim 46, wherein The magnetic storage element has a resistance value corresponding to the magnetization direction of the storage layer. The control performed by the control circuit includes: A voltage, either positive or negative, is applied to the magnetic storage element to give it a resistance value, either low or high. as well as Apply a voltage, either a positive voltage or a negative voltage, to the magnetic storage element to give it a resistance value, either a low resistance value or a high resistance value.

48. The storage device according to claim 47, wherein When no magnetic field is applied to the magnetic storage element, When a positive voltage or a negative voltage is applied to the magnetic storage element, the magnetic storage element becomes either a low resistance value or a high resistance value. When a voltage, either positive or negative, is applied to the magnetic storage element, the magnetic storage element becomes either a low resistance value or a high resistance value.

49. The storage device according to claim 46, wherein The magnetic storage element has an RH hysteresis characteristic, where the resistance value changes hysteretly with the magnitude of the applied magnetic field. in, The hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic storage element and the hysteresis of the RH loop characteristic when a negative voltage is applied to the magnetic storage element are offset from the hysteresis of the RH loop characteristic when no voltage is applied to the magnetic storage element to the opposite side.

50. The storage device according to claim 49, wherein When the hysteresis loop characteristic of the magnetic storage element is substantially without voltage, a magnetic field of magnitude 0 is applied across it. The hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic storage element and the hysteresis of the RH loop characteristic when a negative voltage is applied to the magnetic storage element do not cross the applied magnetic field magnitude = 0.

51. The storage device according to claim 49, wherein The hysteresis of the RH hysteresis characteristic when a positive or negative voltage is applied to the magnetic storage element is greater than the hysteresis of the RH hysteresis characteristic when no voltage is substantially applied to the magnetic storage element. in, The hysteresis of the RH loop characteristic when a positive voltage or a negative voltage is applied to the magnetic storage element is less than the hysteresis of the RH loop characteristic when no voltage is substantially applied to the magnetic storage element.

52. The storage device according to claim 46, wherein The control performed by the control circuit includes: Perform initialization to give the magnetic storage element a resistance value that is either low or high; as well as Switch the resistance value of the initialized magnetic storage element to either a low resistance value or a high resistance value.

53. The storage device according to claim 52, wherein The voltage applied to the magnetic storage element for giving it one resistance value is applied for a shorter time than the voltage applied to the magnetic storage element for giving it another resistance value.

54. The storage device according to claim 46, comprising: The first storage block and the second storage block include magnetic storage elements having different sizes from each other.

55. The storage device according to claim 46, wherein The storage device was assembled and used in an AI chip.

56. The storage device according to claim 46, wherein The storage device was assembled and used in a solid-state imaging device.

57. The storage device according to claim 46, wherein The storage device was assembled and used in the CPU.

58. A method for writing data to a magnetic storage element, wherein... The magnetic storage element includes: A magnetization fixation layer in which the magnetization direction is fixed; as well as A storage layer with reversible magnetization direction. The storage layer includes: The first region contains ferromagnetic material; and The second region contains antiferromagnetic or ferrimagnetic materials. The magnetic storage element has a resistance value corresponding to the magnetization direction of the storage layer. The writing method includes: A voltage, either positive or negative, is applied to the magnetic storage element to give it a resistance value, either low or high. Apply a voltage, either a positive voltage or a negative voltage, to the magnetic storage element to give it a resistance value, either a low resistance value or a high resistance value.

59. The writing method according to claim 58, wherein When no magnetic field is applied to the magnetic storage element, When a positive voltage or a negative voltage is applied to the magnetic storage element, the magnetic storage element becomes either a low resistance value or a high resistance value. When a voltage, either positive or negative, is applied to the magnetic storage element, the magnetic storage element becomes either a low resistance value or a high resistance value.

60. The writing method according to claim 58, wherein The magnetic storage element has an RH hysteresis characteristic, where the resistance value changes hysteretly with the magnitude of the applied magnetic field. in, The hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic storage element and the hysteresis of the RH loop characteristic when a negative voltage is applied to the magnetic storage element are offset from the hysteresis of the RH loop characteristic when no voltage is applied to the magnetic storage element to the opposite side.

61. The writing method according to claim 60, wherein When the hysteresis loop characteristic of the magnetic storage element is substantially without voltage, a magnetic field of magnitude 0 is applied across it. The hysteresis of the RH loop characteristic when a positive voltage is applied to the magnetic storage element and the hysteresis of the RH loop characteristic when a negative voltage is applied to the magnetic storage element do not cross the applied magnetic field magnitude = 0.

62. The writing method according to claim 60, wherein The hysteresis of the RH hysteresis characteristic when a positive or negative voltage is applied to the magnetic storage element is greater than the hysteresis of the RH hysteresis characteristic when no voltage is substantially applied to the magnetic storage element. The hysteresis of the RH loop characteristic when a positive voltage or a negative voltage is applied to the magnetic storage element is less than the hysteresis of the RH loop characteristic when no voltage is substantially applied to the magnetic storage element.

63. The writing method according to claim 58, comprising: Initialization is performed to give the magnetic storage element a resistance value that is either low or high; as well as Switch the resistance value of the initialized magnetic storage element to either a low resistance value or a high resistance value.

64. The writing method according to claim 63, wherein The voltage applied to the magnetic storage element for giving it one resistance value is applied for a shorter time than the voltage applied to the magnetic storage element for giving it another resistance value.

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