Semiconductor device

Abstract

A semiconductor device (1) is provided with: a semiconductor layer (40) including a first region (A1) and a second region (A2) and having an area bisected by the first region (A1) and the second region (A2); a transistor (10) and a transistor (20) formed with a first gate wire (114) surrounding a first source electrode (11) and a second gate wire (124) surrounding a second source electrode (21), the first gate wire (114) and the second gate wire (124) being formed across a boundary (90C) between the first region (A1) and the second region (A2), a drain wire (140) surrounding the first gate wire (114) and the second gate wire (124), and the drain wire (140) not being formed between the first gate wire (114) and the second gate wire (124).

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] A semiconductor device is known to include a vertical MOS transistor and an equipotential ring (EQR) (see, for example, Patent Document 1).

[0003] (Existing technical documents) (Patent Documents) Patent Document 1: International Publication No. WO 2024 / 018715 Summary of the Invention

[0004] The problem that the invention aims to solve While semiconductor devices can suppress leakage current by using an EQR (Electronic Quenching Resistor), it is difficult to use the area directly below the EQR as the active region of a vertical MOS transistor. This prevents the semiconductor device from sufficiently expanding its active region, making it difficult to reduce on-resistance.

[0005] Therefore, the purpose of this disclosure is to provide a semiconductor device that can reduce on-resistance while suppressing leakage current.

[0006] Methods for solving problems One aspect of this disclosure relates to a semiconductor device comprising: a semiconductor layer including a semiconductor substrate on a back side and a first region and a second region on a front side, wherein the second region is adjacent to the first region in a plan view of the semiconductor substrate, and the area of ​​the semiconductor layer is bisected by the first region and the second region in the plan view; a first vertical MOS transistor formed in the first region of the semiconductor layer; a second vertical MOS transistor formed in the second region of the semiconductor layer; and a metal layer formed in contact with the back side of the semiconductor layer, wherein the semiconductor substrate is a shared drain region of the first vertical MOS transistor and the second vertical MOS transistor, and a metal layer is formed in the first region in the plan view. The first vertical MOS transistor has a first source electrode and a first gate wiring connected to and surrounding the first source electrode. In the second region, a second source electrode of the second vertical MOS transistor and a second gate wiring connected to and surrounding the second source electrode are formed. The first gate wiring and the second gate wiring are formed across the boundary between the first region and the second region. A drain wiring connected to the shared drain region is formed on the outer periphery of the semiconductor layer. The drain wiring surrounds the first gate wiring and the second gate wiring. No drain wiring is formed between the first gate wiring and the second gate wiring.

[0007] Invention Effects This disclosure provides a semiconductor device that can reduce on-resistance while suppressing leakage current. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment.

[0009] Figure 2 This is a plan view showing an example of the arrangement of the pads of the semiconductor device according to the embodiment.

[0010] Figure 3 This is a cross-sectional view showing the main current flowing through the semiconductor device according to the embodiment.

[0011] Figure 4 This is a plan view showing an example of the electrode configuration of the semiconductor device according to the embodiment.

[0012] Figure 5 This is a circuit diagram illustrating an example of a semiconductor device according to an embodiment.

[0013] Figure 6This is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment.

[0014] Figure 7 This is a plan view showing an example of the pad configuration of the semiconductor device involved in Comparative Example 2.

[0015] Figure 8 This is a plan view showing an example of the electrode configuration of the semiconductor device in Comparative Example 2.

[0016] Figure 9 This is a cross-sectional view showing an example of the structure of the semiconductor device involved in Comparative Example 1 before BT testing.

[0017] Figure 10 This is a cross-sectional view showing an example of the structure of the semiconductor device involved in Comparative Example 1 of the BT test.

[0018] Figure 11 This is a cross-sectional view showing an example of the structure of the semiconductor device involved in Comparative Example 2 before BT testing.

[0019] Figure 12 This is a cross-sectional view showing an example of the structure of the semiconductor device involved in Comparative Example 2 of the BT test.

[0020] Figure 13 The graph shows the electrical characteristics of the semiconductor device involved in Comparative Example 1 and the semiconductor device involved in Comparative Example 2 after BT testing.

[0021] Figure 14 This is a cross-sectional view showing an example of the structure of a semiconductor device involved in an embodiment of a BT test of a first vertical MOS transistor.

[0022] Figure 15 This is a cross-sectional view showing an example of the structure of a semiconductor device involved in an embodiment of a BT test of a second vertical MOS transistor.

[0023] Figure 16 This is a cross-sectional view showing an example of the structure of the semiconductor device involved in Comparative Example 2.

[0024] Figure 17 This is a plan view showing an example of the electrode configuration of the semiconductor device according to the embodiment.

[0025] Figure 18 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a variation of embodiment 1.

[0026] Figure 19 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a variation of embodiment 1.

[0027] Figure 20 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a modified example 2 of the embodiment.

[0028] Figure 21 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a variation of embodiment 3.

[0029] Figure 22 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a variation of embodiment 4.

[0030] Figure 23 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a variation of embodiment 5. Detailed Implementation

[0031] The embodiments described below are all examples of this disclosure. The values, shapes, materials, constituent elements, arrangement positions of constituent elements, and connection methods shown in the following embodiments are only examples and are not intended to limit this disclosure.

[0032] In the following implementation, the terms "above" and "below" do not refer to the absolute spatial concepts of upward (vertically above) and downward (vertically below). Furthermore, the terms "above" and "below" apply not only to the case where two constituent elements are arranged apart from each other and other constituent elements exist between them, but also to the case where two constituent elements are arranged closely together and in contact.

[0033] Furthermore, all accompanying figures are schematic diagrams and not rigorous illustrations. Therefore, for example, the scales in the figures may not be consistent. In all figures, substantially identical structures are given the same reference numerals, and repeated descriptions are omitted or simplified.

[0034] Furthermore, in this specification, terms indicating the relationship between elements such as parallel or orthogonal elements, terms indicating the shape of elements such as circles or rectangles, and numerical ranges are not merely expressions with a strict meaning, but also include substantially equivalent ranges, such as expressions containing a difference of about a few percent.

[0035] Furthermore, in this specification and accompanying drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system. In embodiments, the two axes parallel to the semiconductor substrate are designated as the x-axis and y-axis, and the direction orthogonal to the x-axis and y-axis is designated as the z-axis direction. In the embodiments described below, sometimes the positive z-axis direction is referred to as upward, and the negative z-axis direction as downward.

[0036] Furthermore, in this specification, "plan view" refers to the view of the semiconductor substrate from the positive z-axis direction, and the resulting image is called a plan view.

[0037] (Implementation Method) [Structure of a semiconductor device] The structure of the semiconductor device according to this embodiment will be described below. The semiconductor device according to this embodiment is a flip-chip size package (CSP) type semiconductor device in which two vertical metal-oxide-semiconductor (MOS) transistors are formed on a semiconductor substrate. The two vertical MOS transistors are power transistors, specifically trench MOS field-effect transistors (FETs).

[0038] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to this embodiment. Figure 2 This is a plan view showing an example of the arrangement of the pads of the semiconductor device 1 according to this embodiment. Figure 3 This is a cross-sectional view showing the main current flowing in the semiconductor device 1 according to this embodiment. The main current refers to the primary component of the current flowing in the circuit; it is the current flowing in the designed direction along the designed current path, excluding leakage current and surge current. Inside the semiconductor device 1, the main current refers to the current flowing along... Figure 3 The current flowing along the path indicated by the double-headed arrows, in the plan view of semiconductor device 1, refers to the main current flowing horizontally inside semiconductor device 1 (i.e., in...). Figure 3 The current flowing in the horizontal direction is inside the metal layer 30 or the semiconductor substrate 32. Figure 1 and Figure 3 Show Figure 2 The cross section of line II in the middle.

[0039] like Figure 1 and Figure 2 As shown, the semiconductor device 1 includes: a semiconductor layer 40, a metal layer 30, a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed in a first region A1 of the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed in a second region A2 of the semiconductor layer 40. In addition, the semiconductor device 1 also includes an interlayer insulating layer 34 and a passivation layer 35.

[0040] Semiconductor layer 40 includes a semiconductor substrate 32 located on its back side (i.e., the negative z-axis side) and a first region A1 and a second region A2 located on its front side (i.e., the positive z-axis side). Here, as... Figure 2As shown, in a plan view of the semiconductor substrate 32, the first region A1 and the second region A2 are adjacent to each other. In the plan view of the semiconductor substrate 32, the area of ​​the semiconductor layer 40 is bisected by the first region A1 and the second region A2. That is, the first region A1 and the second region A2 are one and the other sides that bisecte the area of ​​the semiconductor layer 40. The semiconductor layer 40 also includes a low-concentration impurity layer 33 located further along the positive z-axis than the semiconductor substrate 32, and is formed by stacking the semiconductor substrate 32 and the low-concentration impurity layer 33.

[0041] The semiconductor substrate 32 is made of silicon containing impurities of the first conductivity type.

[0042] A low-concentration impurity layer 33 is disposed on the front side of the semiconductor layer 40, in contact with the semiconductor substrate 32, and is composed of silicon containing impurities of a first conductivity type. The impurity concentration of the low-concentration impurity layer 33 is lower than the impurity concentration of the first conductivity type in the semiconductor substrate 32. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32, for example, by epitaxial growth.

[0043] The metal layer 30 is formed in contact with the back side of the semiconductor layer 40, that is, in contact with the main surface of the semiconductor substrate 32 on the negative z-axis of the semiconductor layer 40. The metal layer 30 can be a multilayer structure containing layers with silver or copper as the main component. In addition, the metal layer 30 may contain trace amounts of elements other than metals that are mixed in as impurities during the metal manufacturing process. Furthermore, the metal layer 30 may also be formed on the entire back side of the semiconductor layer 40.

[0044] In addition, such as Figure 1 and Figure 2 As shown, transistor 10 has a first source electrode 11, a first source region 14, a first gate conductor 15, a first gate oxide film 16, a first body region 18, and a first gate wiring 114. Furthermore, transistor 10 has a plurality (here, seven) of first source pads 111 and first gate pads 119 on the surface of semiconductor layer 40 (i.e., the surface of low-concentration impurity layer 33), which are bonded to the mounting substrate by bonding material during flip-chip mounting. And, as described later... Figure 4 As shown, transistor 10 has a first gate electrode 19.

[0045] Transistor 20 has a second source electrode 21, a second source region 24, a second gate conductor 25, a second gate oxide film 26, a second body region 28, and a second gate wiring 124. Furthermore, transistor 20 has a plurality (here, seven) of second source pads 121 and second gate pads 129 on the surface of semiconductor layer 40 (i.e., the surface of low-concentration impurity layer 33), which are bonded to the mounting substrate by bonding material during flip-chip mounting. And, as described later... Figure 4As shown, transistor 20 has a second gate electrode 29. In addition, the first source pad 111, the first gate pad 119, the second source pad 121 and the second gate pad 129 are sometimes collectively referred to as "pads".

[0046] like Figure 2 As shown, in the plan view, the semiconductor layer 40 is rectangular, and transistors 10 and 20 are arranged along the first direction (x-axis direction), with the main current flowing along the first direction. Here, it is assumed that the semiconductor layer 40 is rectangular in the plan view, having one long side 91 and another long side 92 parallel to the first direction, and one short side 93 and another short side 94 in a direction orthogonal to the first direction (y-axis direction). That is, it is assumed here that the semiconductor layer 40 is a rectangle with the first direction as its long side.

[0047] exist Figure 2 In the plan view, centerline 90 is the line that bisects the rectangular semiconductor layer 40 along the first direction. Therefore, centerline 90 is a straight line in the plan view that is orthogonal to the first direction.

[0048] Boundary 90C is the boundary between region A1 and region A2. In the plan view of semiconductor substrate 32, the area of ​​semiconductor layer 40 is bisected by region A1 and region A2. That is, boundary 90C bisects the area of ​​semiconductor layer 40 in the plan view, but it does not necessarily have to be a straight line. In the plan view, the center line 90 and boundary 90C may coincide or not.

[0049] like Figure 2 As shown, the first gate pad 119 is configured such that, in a plan view, no portion of the plurality of first source pads 111 is sandwiched between it and a long side 91 and between it and the boundary 90C in the first direction.

[0050] The plurality of first source pads 111 in a plan view comprise a plurality of generally rectangular pads (here, all the first source pads 111), the length direction of each of these generally rectangular first source pads 111 being parallel to one short side 93 and another short side 94 and being arranged in a striped pattern.

[0051] The second gate pad 129 is configured such that, in a plan view, it does not sandwich any portion of the plurality of second source pads 121 between itself and another long side 92 and between itself and the boundary 90C in the first direction.

[0052] The plurality of second source pads 121 comprise a plurality of generally rectangular pads (here, all the second source pads 121) in a plan view, the length direction of each of these generally rectangular second source pads 121 being parallel to one short side 93 and another short side 94 and being arranged in a striped pattern.

[0053] Furthermore, the number of the first gate pad 119 and the number of the second gate pad 129 are not necessarily limited to [specific numbers to be filled in]. Figure 2 The example shown can be one, but there can also be two or more. Furthermore, the first gate pad 119 and the second gate pad 129 can each be... Figure 2 The shape shown may be roughly circular, but it may not be roughly circular.

[0054] Furthermore, the number of multiple first source pads 111 and the number of multiple second source pads 121 are not necessarily limited to [specific values]. Figure 2 The example shown has 7 pads, but there could be more than 7. Furthermore, the multiple generally rectangular first source pads 111 are not limited to... Figure 2 The configuration shown can also be parallel to one long side 91 and another long side 92, and arranged in a striped pattern, and the plurality of generally rectangular second source pads 121 are not limited to Figure 2 The configuration shown can be parallel to one long side 91 and the other long side 92, and in a striped pattern.

[0055] like Figure 1 and Figure 2 As shown, in the first region A1 of the low-concentration impurity layer 33, a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed. In the first body region 18, a first source region 14 containing impurities of the first conductivity type, a first gate conductor 15, and a first gate oxide film 16 are formed.

[0056] In the first region A1, a first source electrode 11 of a transistor 10 is formed. The first source electrode 11 is connected to the first source region 14 and the first body region 18. A first gate oxide film 16 is formed inside a plurality of first gate trenches 17, which extend from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a depth of a portion of the low-concentration impurity layer 33.

[0057] The first gate conductor 15 is formed inside the first gate trench 17 and on the first gate oxide film 16. The first gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40 and electrically connected to the first gate pad 119. As a non-limiting example, the first gate conductor 15 may be polysilicon containing impurities.

[0058] As a non-limiting example, the first gate oxide film 16 may be made of silicon oxide (SiO2).２ )constitute.

[0059] As a non-limiting example, the first source electrode 11 may be made of one or more metals including aluminum, copper, gold, and silver.

[0060] In the second region A2 of the low-concentration impurity layer 33, a second body region 28 containing impurities of a second conductivity type is formed. In the second body region 28, a second source region 24 containing impurities of a first conductivity type, a second gate conductor 25, and a second gate oxide film 26 are formed.

[0061] In region A2, a second source electrode 21 of transistor 20 is formed. The second source electrode 21 is connected to the second source region 24 and the second body region 28. A second gate oxide film 26 is formed inside a plurality of second gate trenches 27, which extend from the upper surface of semiconductor layer 40 through the second source region 24 and the second body region 28 to a depth of a portion of the low-concentration impurity layer 33.

[0062] The second gate conductor 25 is formed inside the second gate trench 27 and on the second gate oxide film 26. The second gate conductor 25 is a buried gate electrode buried inside the semiconductor layer 40 and electrically connected to the second gate pad 129. As a non-limiting example, the second gate conductor 25 may be polysilicon containing impurities.

[0063] As a non-limiting example, the second gate oxide film 26 can be made of silicon oxide (SiO2). ２ )constitute.

[0064] As a non-limiting example, the second source electrode 21 may be made of one or more metals including aluminum, copper, gold, and silver.

[0065] With the above-described structure of transistors 10 and 20, semiconductor substrate 32 serves as a shared drain region in which the first drain region of transistor 10 and the second drain region of transistor 20 are shared.

[0066] In addition, such as Figure 3 As shown, the semiconductor device 1 uses a bidirectional path from the first source electrode 11 through the first drain region, the metal layer 30 and the second drain region to the second source electrode 21 as the main current path.

[0067] The interlayer insulating layer 34 is an insulating layer formed above the semiconductor layer 40 and has multiple openings. The passivation layer 35 is a layer formed above the semiconductor layer 40. A portion of the passivation layer 35 is also formed above the interlayer insulating layer 34 and the first source electrode 11, and above the interlayer insulating layer 34 and the second source electrode 21.

[0068] like Figure 1As shown, the first source region 14 and the first body region 18 are covered by an interlayer insulating layer 34 with an opening, and are connected to the first source electrode 11 through the opening of the interlayer insulating layer 34. The first source electrode 11 is disposed in the opening and connected to the first source region 14 and the first body region 18. The interlayer insulating layer 34 and the first source electrode 11 are covered by a passivation layer 35 with an opening.

[0069] The second source region 24 and the second body region 28 are covered by an interlayer insulating layer 34 with an opening, and are connected to the second source electrode 21 through the opening of the interlayer insulating layer 34. The second source electrode 21 is disposed in the opening and connected to the second source region 24 and the second body region 28. The interlayer insulating layer 34 and the second source electrode 21 are covered by a passivation layer 35 with an opening.

[0070] As a non-limiting example, the interlayer insulating layer 34 can be made of silicon oxide (SiO2). ２ )constitute.

[0071] As a non-limiting example, the passivation layer 35 may be composed of polyimide.

[0072] Therefore, the plurality of first source pads 111 and the plurality of second source pads 121 refer to the regions through which the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1 through the openings in the passivation layer 35, i.e., terminal portions. Similarly, the first gate pads 119 and the second gate pads 129 refer to the regions through which the first gate electrode 19 and the second gate electrode 29 are partially exposed on the surface of the semiconductor device 1 through the openings in the passivation layer 35, i.e., terminal portions.

[0073] In semiconductor device 1, for example, the first conductivity type can be set as N-type and the second conductivity type can be set as P-type. In this case, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low concentration impurity layer 33 are N-type semiconductors, and the first body region 18 and the second body region 28 can be P-type semiconductors.

[0074] Furthermore, in the semiconductor device 1, for example, the first conductivity type can be set to P-type and the second conductivity type can be set to N-type. In this case, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 are P-type semiconductors, and the first body region 18 and the second body region 28 can be N-type semiconductors.

[0075] In addition, semiconductor device 1 also includes drain wiring 140. (Refer to below) Figure 4 The description includes the configuration of the electrodes of the drain wiring 140.

[0076] Figure 4 This is a plan view showing an example of the electrode arrangement of the semiconductor device 1 according to this embodiment. More specifically, Figure 4This is a plan view showing a typical example of the shapes of the first source electrode 11, the first gate electrode 19, the first gate wiring 114, the second source electrode 21, the second gate electrode 29, the second gate wiring 124, and the drain wiring 140 in a plan view of the constituent elements of the semiconductor device 1. Furthermore, in Figure 4 In this illustration, the interlayer insulating layer 34 and passivation layer 35 included in the semiconductor device 1 are omitted and are considered transparent. Furthermore, in Figure 4 In the diagram, the first source pad 111, the first gate pad 119, the second source pad 121, and the second gate pad 129 are shown with dashed lines at their respective positions. Furthermore, in... Figure 4 In the middle, the drain wiring 140 is marked with dot-shaped marks.

[0077] As a non-limiting example, the first gate electrode 19 may be made of one or more metals including aluminum, copper, gold, and silver.

[0078] In the first region A1, a first gate wiring 114 of transistor 10 is formed. The first gate wiring 114 is connected to the first gate electrode 19. In plan view, the first gate wiring 114 is formed to surround the first source electrode 11. That is, the first gate wiring 114 is located in the first region A1 further outward than the first source electrode 11, that is, close to one side of the long side 91, long side 92, short side 93, and short side 94 that form the edge of the semiconductor layer 40, and has a frame shape. Furthermore, in plan view, the first gate electrode 19 is also located inside the frame-shaped first gate wiring 114.

[0079] The first gate wiring 114 is composed of two layers: a first gate wiring metal 1141 and a first gate wiring conductor 1142 formed on the semiconductor layer 40 (more specifically, the low-concentration impurity layer 33). The first gate wiring metal 1141 and the first gate wiring conductor 1142 each have a layered shape. The first gate wiring metal 1141 has a film-like portion on the positive z-axis side and a protrusion that protrudes from the film-like portion toward the negative z-axis side and contacts the first gate wiring conductor 1142.

[0080] like Figure 1 As shown, the first gate wiring 114 does not contact the low-concentration impurity layer 33, but is disposed above the low-concentration impurity layer 33. The protrusions of the first gate wiring conductor 1142 and the first gate wiring metal 1141 of the first gate wiring 114 are buried inside the interlayer insulating layer 34, and the film-like portion of the first gate wiring metal 1141 of the first gate wiring 114 is disposed above the interlayer insulating layer 34 and is covered by the passivation layer 35.

[0081] The width of the first gate wiring 114 is its length in a direction orthogonal to the direction in which the first gate wiring 114 extends, for example, in... Figure 1 The cross-sectional view shown, parallel to the zx plane, represents the length of the first gate wiring 114 in the x-axis direction.

[0082] In the first gate wiring 114, the width of the first gate wiring conductor 1142 is greater than the width of the first gate wiring metal 1141. More specifically, the width of the first gate wiring conductor 1142 is greater than the width of the film portion of the first gate wiring metal 1141.

[0083] The first gate wiring metal 1141 is made of metal, and as a non-limiting example, it may also be made of one or more metals including aluminum, copper, gold, and silver. In this embodiment, the first gate wiring metal 1141 is made of a metal including copper and with aluminum as the main component.

[0084] As a non-limiting example, the first gate wiring conductor 1142 is made of a non-metallic conductor, and more specifically, of polysilicon.

[0085] As a non-limiting example, the second gate electrode 29 may be made of one or more metals including aluminum, copper, gold, and silver.

[0086] In the second region A2, a second gate wiring 124 of the transistor 20 is formed. The second gate wiring 124 is connected to the second gate electrode 29. In plan view, the second gate wiring 124 is formed to surround the second source electrode 21. That is, the second gate wiring 124 is located in the second region A2 further outward than the second source electrode 21, that is, close to one side of the long side 91, long side 92, short side 93, and short side 94 that form the edge of the semiconductor layer 40, and has a frame shape. Furthermore, in plan view, the second gate electrode 29 is also located inside the frame-shaped second gate wiring 124.

[0087] The second gate wiring 124 is composed of two layers: a second gate wiring metal 1241 and a second gate wiring conductor 1242 formed on the semiconductor layer 40 (more specifically, the low-concentration impurity layer 33). The second gate wiring metal 1241 and the second gate wiring conductor 1242 each have a layered shape. The second gate wiring metal 1241 has a film-like portion on the positive z-axis side and a protrusion that protrudes from the film-like portion toward the negative z-axis side and contacts the second gate wiring conductor 1242.

[0088] like Figure 1As shown, the second gate wiring 124 does not contact the low-concentration impurity layer 33, but is disposed above the low-concentration impurity layer 33. The protrusions of the second gate wiring conductor 1242 and the second gate wiring metal 1241 of the second gate wiring 124 are buried inside the interlayer insulating layer 34, and the film-like portion of the second gate wiring metal 1241 of the second gate wiring 124 is disposed above the interlayer insulating layer 34 and is covered by the passivation layer 35.

[0089] The width of the second gate wiring 124 is its length in a direction orthogonal to the extension direction of the second gate wiring 124, for example, in... Figure 1 The cross-sectional view shown, parallel to the zx plane, represents the length of the second gate wiring 124 in the x-axis direction.

[0090] In the second gate wiring 124, the width of the second gate wiring conductor 1242 is greater than the width of the second gate wiring metal 1241. More specifically, the width of the second gate wiring conductor 1242 is greater than the width of the film portion of the second gate wiring metal 1241.

[0091] The second gate wiring metal 1241 is made of metal, and as a non-limiting example, it may also be made of one or more metals including aluminum, copper, gold, and silver. In this embodiment, the second gate wiring metal 1241 is made of a metal including copper and with aluminum as the main component.

[0092] As a non-limiting example, the second gate wiring conductor 1242 is made of a non-metallic conductor, and more specifically, of polysilicon.

[0093] The first active region 100 refers to the smallest region encompassing all areas where conduction channels are formed when a voltage exceeding a threshold is applied to the first gate electrode 19 (first gate conductor 15) of the transistor 10. The portion forming the conduction channel refers to the portion of each of the plurality of first gate trenches 17 adjacent to the first source region 14. The first active region 100 is contained within the first body region 18.

[0094] The second active region 200 refers to the smallest region encompassing all areas where conduction channels are formed when a voltage exceeding a threshold is applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20. The portion forming the conduction channel refers to the portion of each of the plurality of second gate trenches 27 adjacent to the second source region 24. The second active region 200 is contained within the second body region 28.

[0095] A PN junction exists at the contact surface between the first body region 18 and the low-concentration impurity layer 33, functioning as a body diode. A PN junction also exists at the contact surface between the second body region 28 and the low-concentration impurity layer 33, functioning as a body diode. These body diodes... Figure 1 It is shown schematically in the diagram.

[0096] Figure 5 This is a circuit diagram illustrating an example of the semiconductor device 1 according to this embodiment. Figure 5 The diagram shows the first gate pad G1, the first source pad S1, the second gate pad G2, and the second source pad S2. The first gate pad G1 and the first source pad S1 are equivalent to... Figure 2 The first gate pad 119 and the first source pad 111 are shown in the figure. The second gate pad G2 and the second source pad S2 are equivalent to... Figure 2 The second gate pad 129 and the second source pad 121 in the example.

[0097] Furthermore, the first gate wiring 114 and the second gate wiring 124 are formed across the boundary 90C between the first region A1 and the second region A2. That is, there is a boundary 90C between the first gate wiring 114 and the second gate wiring 124. Alternatively, it can be said that the first gate wiring 114 and the second gate wiring 124 are formed opposite each other across the boundary 90C. Furthermore, the statement that the first gate wiring 114 and the second gate wiring 124 are opposite each other means that in the portion of the first gate wiring 114 and the second gate wiring 124 formed across the boundary 90C, at least a portion of the first gate wiring 114 and the second gate wiring 124 will overlap when the semiconductor device 1 is folded along the centerline 90.

[0098] Drain wiring 140 is a component connected to the shared drain region. Drain wiring 140 is not connected to the first gate electrode 19 and the second gate electrode 29, nor to the first source electrode 11 and the second source electrode 21, and is formed such that it is at the same potential as the shared drain region.

[0099] Drain wiring 140 is formed on the outer periphery of semiconductor layer 40, that is, disposed near the long side 91, long side 92, short side 93, and short side 94, which are the edges of semiconductor layer 40. In this embodiment, drain wiring 140 is disposed on a side closer to the edge of semiconductor layer 40 than the first gate wiring 114 and the second gate wiring 124. In other words, drain wiring 140 is disposed on the outermost periphery of semiconductor layer 40, surrounding the first gate wiring 114 and the second gate wiring 124 together. Drain wiring 140 is formed across first region A1 and second region A2.

[0100] In this embodiment, the semiconductor layer 40 is rectangular in shape. Therefore, the drain wiring 140 is also a rectangular frame shape, and no branches or the like are provided on this frame shape. That is, the drain wiring 140 is not formed between the first gate wiring 114 and the second gate wiring 124.

[0101] Figure 6This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to this embodiment. Figure 6 Show Figure 2 A cross-section of the VI-VI line. Drain wiring 140 is formed above semiconductor layer 40. Drain wiring 140 consists of two layers: drain wiring metal 141 and drain wiring conductor 142. Drain wiring metal 141 and drain wiring conductor 142 each have a layered shape. Drain wiring metal 141 has a film-like portion on the positive z-axis side and a protrusion extending from this film-like portion towards the negative z-axis side and contacting drain wiring conductor 142.

[0102] like Figure 6 As shown, the drain wiring 140 does not contact the low-concentration impurity layer 33, but is disposed above the low-concentration impurity layer 33. The protrusions of the drain wiring conductor 142 and the drain wiring metal 141 of the drain wiring 140 are embedded inside the interlayer insulating layer 34, and the film-like portion of the drain wiring metal 141 of the drain wiring 140 is disposed above the interlayer insulating layer 34 and is covered by the passivation layer 35.

[0103] The width of the drain wiring 140 is its length in a direction orthogonal to the direction in which the drain wiring 140 extends, for example, in... Figure 6 The cross-sectional view shown, parallel to the zx plane, represents the length of the drain wiring 140 along the x-axis.

[0104] In the drain wiring 140, the width of the drain wiring metal 141 (more specifically, the width of the film portion of the drain wiring metal 141) is the same as, but not limited to, the width of the drain wiring conductor 142.

[0105] The drain wiring metal 141 is made of metal, and as a non-limiting example, it may also be made of one or more metals including aluminum, copper, gold, and silver. In this embodiment, the drain wiring metal 141 is made of a metal including copper and with aluminum as the main component.

[0106] As a non-limiting example, the drain wiring conductor 142 is made of a non-metallic conductor, and more specifically, of polysilicon.

[0107] Drain wiring 140 acts as an EQR (Equipotential Ring). As an EQR, drain wiring 140 is designed to suppress leakage current in transistors 10 and 20.

[0108] The function will now be described using Comparative Example 1 and Comparative Example 2. First, the semiconductor device 1y involved in Comparative Example 1 and the semiconductor device 1z involved in Comparative Example 2 will be described.

[0109] The semiconductor device 1y involved in Comparative Example 1 has the same structure as the semiconductor device 1 involved in this embodiment, except that it does not include the drain wiring 140.

[0110] The semiconductor device 1z involved in Comparative Example 2 has the same structure as the semiconductor device 1 involved in this embodiment, except that the drain wiring 140 is replaced by the first drain wiring 113 and the second drain wiring 123.

[0111] Figure 7 This is a plan view showing an example of the pad configuration of the semiconductor device 1z involved in Comparative Example 2. Figure 8 This is a plan view showing an example of the electrode arrangement of the semiconductor device 1z involved in Comparative Example 2. Additionally, Figure 8 and Figure 4 Similarly, this is a plan view showing a typical example of the shapes of the first source electrode 11, the first gate electrode 19, the first gate wiring 114, the second source electrode 21, the second gate electrode 29, the second gate wiring 124, the first drain wiring 113, and the second drain wiring 123 in a plan view of the constituent elements of the semiconductor device 1z. Furthermore, in Figure 8 In this illustration, the interlayer insulating layer 34 and passivation layer 35 included in the semiconductor device 1z are omitted and are considered transparent. Furthermore, in Figure 8 In the diagram, the first source pad 111, the first gate pad 119, the second source pad 121, and the second gate pad 129 are shown with dashed lines at their respective positions. Furthermore, in... Figure 8 In the middle, the first drain wiring 113 and the second drain wiring 123 are marked with dot-shaped marks.

[0112] The first drain wiring 113 is an electrode disposed in the first region A1. The first drain wiring 113 is disposed in the first region A1 on a side further from the outer periphery of the semiconductor layer 40 than the first gate wiring 114, that is, near the side close to the long side 91, long side 92, short side 93, and short side 94, which are the edges of the semiconductor layer 40. In other words, the first drain wiring 113 is disposed on the outermost periphery of the first region A1.

[0113] The second drain wiring 123 is an electrode disposed in the second region A2. The second drain wiring 123 is disposed in the second region A2 on the side of the semiconductor layer 40 further away than the second gate wiring 124, that is, near the side close to the long side 91, long side 92, short side 93, and short side 94 that are the edges of the semiconductor layer 40. That is, the second drain wiring 123 is disposed on the outermost periphery of the second region A2.

[0114] The first drain wiring 113 is not connected to the first gate electrode 19 and the second gate electrode 29, nor is it connected to the first source electrode 11 and the second source electrode 21. The second drain wiring 123 is not connected to the first gate electrode 19 and the second gate electrode 29, nor is it connected to the first source electrode 11 and the second source electrode 21. The first drain wiring 113 and the second drain wiring 123 are formed in such a way that they are at the same potential as the shared drain region.

[0115] At the boundary 90C between region A1 and region A2, the first drain wiring 113 and the second drain wiring 123 are shared. At this boundary 90C, the shared first drain wiring 113 and second drain wiring 123 are sometimes referred to as common drain wiring 130. Common drain wiring 130 is formed between the first gate wiring 114 and the second gate wiring 124.

[0116] Next, the functions of the first drain wiring 113, the second drain wiring 123, and the common drain wiring 130 will be explained.

[0117] In typical vertical MOS transistors, a bias-temperature test (BT test) is performed as a reliability test. The BT test involves applying a reverse voltage, which is guaranteed to have an upper limit, to the body diode for an extended period of time at a high temperature to confirm whether applying this reverse voltage will cause abnormal electrical characteristics.

[0118] Figure 9 This is a cross-sectional view showing an example of the structure of the semiconductor device 1y involved in Comparative Example 1 before BT testing. Figure 10 This is a cross-sectional view showing an example of the structure of the semiconductor device 1y involved in Comparative Example 1 of the BT test. Figure 11 This is a cross-sectional view showing an example of the structure of the semiconductor device 1z involved in Comparative Example 2 before BT testing. Figure 12 This is a cross-sectional view showing an example of the structure of the semiconductor device 1z involved in Comparative Example 2 of the BT test. Figure 11 and Figure 12 Show Figure 7 A cross-section of the XI-XI line. Furthermore... Figure 9 and Figure 10 Shown in equivalent Figure 11 and Figure 12 A cross-sectional view of the semiconductor device 1y at the location shown in the cross-sectional view.

[0119] exist Figure 10 and Figure 12The diagram schematically shows a first gate pad G1, a first source pad S1, a drain pad D connected to the semiconductor substrate 32 which serves as a shared drain region, and a body diode. However, the semiconductor device 1 according to this embodiment does not have a drain pad D. Figure 10 and Figure 12 The drain pad D shown corresponds to the second source pad S2 of transistor 20. However, since illustrating transistor 20 in this diagram would be cumbersome, it is explained as drain pad D for simplicity. Furthermore, in BT testing, as an example, 0V is applied to the first gate pad G1, 0V to the first source pad S1, and 23V to the drain pad D. The voltage applied to the drain pad D only needs to be within the upper limit, for example, 23V as described above.

[0120] First, the changes that occurred in the semiconductor device 1y involved in Comparative Example 1 due to BT testing will be explained.

[0121] like Figure 10 As shown, during the BT test, mobile ions within the interlayer insulating layer 34 migrate to the vicinity of the interface between the interlayer insulating layer 34 and the low-concentration impurity layer 33. These mobile ions, such as negative ions, are influenced by the electric field generated during the BT test and migrate to the vicinity of the interface between the interlayer insulating layer 34 and the low-concentration impurity layer 33. As a result, an inversion layer 331y is formed near the interface between the low-concentration impurity layer 33 and the interlayer insulating layer 34. This inversion layer 331y is formed because ions with the same charge as the mobile ions within the interlayer insulating layer 34 move away from the vicinity of the interface between the interlayer insulating layer 34 and the low-concentration impurity layer 33, resulting in this portion being relatively positively charged. This inversion layer 331y connects to the first body region 18, becoming a leakage path.

[0122] Next, the changes that occurred in the semiconductor device 1z involved in Comparative Example 2 due to BT testing will be explained.

[0123] Similar to Comparative Example 1, such as Figure 12 As shown, in Comparative Example 2, inversion layers 331z and 332z are also formed. However, in Comparative Example 2, a first drain wiring 113 is formed. Since a voltage of 23V is applied to the first drain wiring 113, it is difficult for inversion layers 331z and 332z to form directly below the first drain wiring 113 (on the negative z-axis side). In other words, inversion layers 331z and 332z are not connected but disconnected, thus making it difficult to become a leakage path.

[0124] Figure 13 This is a graph showing the electrical characteristics of semiconductor device 1y according to Comparative Example 1 and semiconductor device 1z according to Comparative Example 2 after BT testing. Figure 13In the diagram, the horizontal axis VDSS represents the drain-source voltage, and the vertical axis IDSS represents the drain-source current.

[0125] After the BT test, compared to semiconductor device 1z, the IDSS waveform of semiconductor device 1y showed a significant increase deviating from the normal range as VDSS increased. As described above, this is because a leakage path was generated in semiconductor device 1y, resulting in abnormal electrical characteristics due to the BT test. On the other hand, in semiconductor device 1z, the increase in IDSS was within the normal range accompanying the increase in VDSS, and no waveform that could be identified as leakage appeared. This is because semiconductor device 1z in Comparative Example 2, by including the first drain wiring 113, the second drain wiring 123, and the common drain wiring 130, suppressed the generation of leakage paths. That is, in semiconductor device 1z, the abnormal electrical characteristics caused by the BT test were suppressed.

[0126] The semiconductor device 1 according to this embodiment, having a drain wiring 140, is similar to the semiconductor device 1z in Comparative Example 2 in that it can suppress the generation of leakage paths and suppress the increase of IDSS leakage. Here, we will use Figure 14 This describes the behavior of semiconductor device 1 near boundary 90C during BT testing.

[0127] Figure 14 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 involved in this embodiment during a BT test of transistor 10. Figure 15 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 involved in this embodiment during a BT test of transistor 20. Additionally, Figure 14 and Figure 15 and Figure 1 Same, shown Figure 2 Cross section of Line II.

[0128] exist Figure 14 and Figure 15 The diagram schematically shows the first gate pad G1, the first source pad S1, the second gate pad G2, the second source pad S2, and the body diode.

[0129] Furthermore, in the BT test of transistor 10, as an example, 0V is applied to the first gate pad G1 and the first source pad S1, and 23V is applied to the second gate pad G2 and the second source pad S2. In the BT test of transistor 20, as an example, 23V is applied to the first gate pad G1 and the first source pad S1, and 0V is applied to the second gate pad G2 and the second source pad S2.

[0130] Here, we focus on the region between the first body region 18 and the second body region 28, that is, near the boundary 90C. In the semiconductor device 1, mobile ions within the interlayer insulating layer 34 also move to the vicinity of the interface between the interlayer insulating layer 34 and the low-concentration impurity layer 33, and an inversion layer 331 is formed near the interface between the low-concentration impurity layer 33 and the interlayer insulating layer 34.

[0131] However, in the BT test of transistor 10, due to the voltage applied to the second gate wiring 124, the inversion layer 331 is difficult to form directly below the second gate wiring 124 (on the negative z-axis side). That is, in this BT test, the second gate wiring 124 acts as a counterweight to the transistor 10. Figure 12 The first drain wiring 113 described in Comparative Example 2 has the same function. Therefore, it is difficult to form a leakage path between the first body region 18 and the second body region 28.

[0132] Similarly, in the BT test of transistor 20, due to the voltage applied to the first gate wiring 114, the inversion layer 331 is difficult to form directly below the first gate wiring 114 (negative z-axis side). That is, in this BT test, the first gate wiring 114 acts as a counterweight to the transistor 20. Figure 12 The second drain wiring 123 described in Comparative Example 2 has the same function. Therefore, it is difficult to form a leakage path between the first body region 18 and the second body region 28.

[0133] Thus, even when the semiconductor device 1 according to this embodiment undergoes BT testing, it is difficult to form a leakage path. That is, in the semiconductor device 1, abnormal electrical characteristics caused by BT testing are suppressed.

[0134] Here, a comparison is made between the semiconductor device 1 according to this embodiment and the semiconductor device 1z according to Comparative Example 2. Figure 16 This is a cross-sectional view showing an example of the structure of the semiconductor device 1z involved in Comparative Example 2. Figure 16 Show Figure 7 Cross section of line XVI-XVI.

[0135] As described above, in this embodiment, no drain wiring 140 is formed between the first gate wiring 114 and the second gate wiring 124. On the other hand, in Comparative Example 2, a common drain wiring 130 is formed between the first gate wiring 114 and the second gate wiring 124.

[0136] In the semiconductor device 1 according to this embodiment, the second gate wiring 124 functions as an EQR in the BT test of transistor 10 and the first gate wiring 114 functions as an EQR in the BT test of transistor 20. Therefore, even if a drain wiring 140 is not formed between the first gate wiring 114 and the second gate wiring 124, a semiconductor device 1 capable of suppressing leakage current can be realized.

[0137] Furthermore, in semiconductor device 1, compared to semiconductor device 1z according to Comparative Example 2, since the common-drain wiring 130 is not provided, the first active region 100 and the second active region 200 can be made larger. Accordingly, in semiconductor device 1 with larger first active region 100 and second active region 200, the on-resistance can be reduced.

[0138] In summary, the semiconductor device 1 described in this embodiment can reduce on-resistance while suppressing leakage current.

[0139] And, it will be used again below. Figure 1 and Figure 6 The semiconductor device 1 according to this embodiment will be described.

[0140] First of all, let me explain Figure 6 The minimum value of the width Wd of the drain wiring 140 shown is... Figure 1 The relationship between the minimum value of the width W1 of the first gate wiring 114 and the minimum value of the width W2 of the second gate wiring 124.

[0141] As described above, in the drain wiring 140, the width of the drain wiring metal 141 (more specifically, the width of the film portion of the drain wiring metal 141) is the same as the width of the drain wiring conductor 142. Therefore, the minimum value of the width Wd of the drain wiring 140 is the minimum value of the width of the drain wiring metal 141 (the width of the film portion of the drain wiring metal 141), and also the minimum value of the width of the drain wiring conductor 142.

[0142] Furthermore, in the drain wiring 140, when the width of the drain wiring metal 141 (the width of the film portion of the drain wiring metal 141) is inconsistent with the width of the drain wiring conductor 142, the minimum value of the width Wd of the drain wiring 140 is equivalent to the smaller of the minimum value of the width of the drain wiring metal 141 (the width of the film portion of the drain wiring metal 141) and the minimum value of the width of the drain wiring conductor 142.

[0143] In the first gate wiring 114, the width of the first gate wiring conductor 1142 is greater than the width of the first gate wiring metal 1141. Here, the minimum value of the width W1 of the first gate wiring 114 corresponds to the minimum value of the width of the first gate wiring metal 1141 (more specifically, the width of the film portion of the first gate wiring metal 1141).

[0144] In the second gate wiring 124, the width of the second gate wiring conductor 1242 is greater than the width of the second gate wiring metal 1241. Here, the minimum value of the width W2 of the second gate wiring 124 corresponds to the minimum value of the width of the second gate wiring metal 1241 (more specifically, the width of the film portion of the second gate wiring metal 1241).

[0145] Furthermore, in this embodiment, the minimum value of the width Wd of the drain wiring 140 is less than the minimum value of the width W1 of the first gate wiring 114 or the minimum value of the width W2 of the second gate wiring 124. More specifically, the minimum value of the width Wd of the drain wiring 140 is less than the smaller of the minimum value of the width W1 of the first gate wiring 114 and the minimum value of the width W2 of the second gate wiring 124.

[0146] In addition, such as Figure 1 As shown, the closest distance between the first gate wiring 114 and the second gate wiring 124, which are positioned across the boundary 90C between the first region A1 and the second region A2, is defined as the closest distance D1. The closest distance D1 can also be described as the closest distance between the first gate wiring 114 and the second gate wiring 124 facing each other across the boundary 90C. Furthermore, the closest distance D1 is as follows... Figure 1 The distance shown is from the end of the first gate wiring 114 (the end on the positive x-axis) to the end of the second gate wiring 124 (the end on the negative x-axis).

[0147] The closest distance D1 is less than the minimum value of the width Wd of the drain wiring 140 and the closest distance D2 between the drain wiring 140 and the first gate wiring 114 or between the drain wiring 140 and the second gate wiring 124 (see...). Figure 6 The sum of the two distances. Furthermore, the closest distance D2 refers to the shorter of the closest distances between the drain wiring 140 and the first gate wiring 114, and between the drain wiring 140 and the second gate wiring 124. Here, it is assumed that the closest distance D2 is the closest distance between the drain wiring 140 and the first gate wiring 114. Furthermore, the closest distance D2 is as follows: Figure 6 The distance shown is from the end of the drain wiring 140 (the end on the positive x-axis) to the end of the first gate wiring 114 (the end on the negative x-axis).

[0148] Widths Wd, W1, and W2, as well as the closest distances D1 and D2, are in the aforementioned relationship. Thus, for example, the first gate wiring 114 and the second gate wiring 124 are so close to each other that there is not enough space between them near the boundary 90C to accommodate the drain wiring 140. Due to this proximity, an extra region is created within the semiconductor device 1, which can then be used as the first active region 100 and the second active region 200. In other words, because the first active region 100 and the second active region 200 can be increased, the semiconductor device 1 can significantly reduce its on-resistance.

[0149] In addition, such as Figure 1 As shown in the plan view, the closest distance between the first body region 18 and the second body region 28, which are separated by the boundary 90C of the first region A1 and the second region A2, is defined as the closest distance D3. The closest distance D3 can also be described as the closest distance between the first body region 18 and the second body region 28, which are separated by the boundary 90C. Furthermore, the closest distance D3 is as follows... Figure 1 The distance shown is from the end of the first body region 18 (the end on the positive side of the x-axis) to the end of the second body region 28 (the end on the negative side of the x-axis).

[0150] The closest distance D3 is greater than the closest distance D4 between the first gate wiring conductor 1142 and the second gate wiring conductor 1242, which are positioned across the boundary 90C between the first region A1 and the second region A2. The closest distance D4 can also be described as the closest distance between the first gate wiring conductor 1142 and the second gate wiring conductor 1242, which are positioned opposite each other across the boundary 90C. Furthermore, the closest distance D4 is as follows... Figure 1 The distance shown is from the end of the first gate wiring conductor 1142 (the end on the positive x-axis) to the end of the second gate wiring conductor 1242 (the end on the negative x-axis).

[0151] In this embodiment, in a plan view, the positive x-axis end of the first gate wiring 114 coincides with the positive x-axis end of the first gate wiring conductor 1142, and the negative x-axis end of the second gate wiring 124 coincides with the negative x-axis end of the second gate wiring conductor 1242. Therefore, the closest distance D1 coincides with the closest distance D4.

[0152] As described above, the closest distance D3 is greater than the closest distance D4. That is, the first body region 18 and the second body region 28 are sufficiently separated, and the first gate wiring 114 and the second gate wiring 124 are disposed above each other, so it is difficult to form a leakage path between the first body region 18 and the second body region 28.

[0153] Furthermore, in a plan view, the first gate wiring 114 overlaps with the terminal portion of the first body region 18 of the transistor 10, and the second gate wiring 124 overlaps with the terminal portion of the second body region 28 of the transistor 20.

[0154] exist Figure 1 In the first gate wiring 114, the first gate wiring conductor 1142 overlaps with the terminal portion of the first body region 18, and the second gate wiring conductor 1242 of the second gate wiring 124 overlaps with the terminal portion of the second body region 28. Figure 1 Region A3 is the region where the first gate wiring conductor 1142 overlaps with the terminal portion (the end on the positive x-axis side) of the first body region 18. Figure 1 Region A4 is the region where the second gate wiring conductor 1242 overlaps with the terminal portion (the end on the negative side of the x-axis) of the second body region 28.

[0155] also, Figure 6 As shown, the first gate wiring conductor 1142 of the first gate wiring 114 formed near the edge (short side 93) of the semiconductor layer 40 also overlaps with the termination portion of the first body region 18. That is, Figure 6 Region A5 is the area where the first gate wiring conductor 1142 overlaps with the terminal portion (the end on the negative x-axis side) of the first body region 18. Additionally, although not shown, at other edges of the semiconductor layer 40 beyond the short side 93, there is also overlap... Figure 6 The first gate wiring conductor 1142 described herein is the same. That is, the second gate wiring conductor 1242 of the second gate wiring 124 formed near the edge (short side 94) of the semiconductor layer 40 also overlaps with the terminal portion (the end on the positive x-axis side) of the second body region 28. The first gate wiring conductor 1142 formed near the edge (long side 91) of the semiconductor layer 40 also overlaps with the terminal portion (the end on the positive y-axis side) of the first body region 18. The second gate wiring conductor 1242 formed near the edge (long side 91) of the semiconductor layer 40 also overlaps with the terminal portion (the end on the positive y-axis side) of the second body region 28. The first gate wiring conductor 1142 formed near the edge (long side 92) of the semiconductor layer 40 also overlaps with the terminal portion (the end on the negative y-axis side) of the first body region 18. The second gate wiring conductor 1242 formed near the edge (long side 92) of the semiconductor layer 40 also overlaps with the terminal portion (the end on the negative y-axis side) of the second body region 28.

[0156] Therefore, the inversion layer 331 connected to the first body region 18 and the second body region 28 due to the BT test can be further suppressed, thereby realizing a semiconductor device 1 that can further suppress leakage current.

[0157] In addition, will use Figure 17 The drain wiring 140 is described.

[0158] Figure 17 This is a plan view showing an example of the electrode arrangement of the semiconductor device 1 according to this embodiment. Additionally, Figure 17 and Figure 4 Similarly, the illustrations of the interlayer insulating layer 34 and passivation layer 35 are omitted, and they are considered transparent. Furthermore, in Figure 17 In, with Figure 4 Similarly, the first source pad 111, the first gate pad 119, the second source pad 121, and the second gate pad 129 are shown with dashed lines at their respective positions.

[0159] In addition, Figure 17 An enlarged view of a portion of the drain wiring 140 is also shown within the area enclosed by a dashed rectangle. Furthermore, for simplicity, the second gate wiring 124, etc., are omitted in this enlarged view.

[0160] The drain wiring 140 of this embodiment has a rectangular frame portion 150, four corner portions 160 and four contact portions 170 in a plan view.

[0161] Frame part 150 Figure 17 The portion indicated by dark dots is shown in the center. The frame line portion 150 corresponds to the film-like portion of the drain wiring metal 141 described above. The width of the frame line portion 150 corresponds to the width of the film-like portion of the drain wiring metal 141, which is width Wd. Furthermore, Figure 17 The image shows the four corners C1, C2, C3, and C4 of the frame portion 150 of the rectangle.

[0162] The four corner portions 160 are located on the inner sides of the four corners C1, C2, C3, and C4 of the frame portion 150, respectively. Figure 17 The enlarged view shows the parts represented by light-colored dots. Each of the four corners 160 is connected to each of the four corners C1, C2, C3, and C4, meaning there is a one-to-one correspondence between each corner 160 and each corner. Figure 17 In the enlarged view, a corner 160 is connected to corner C4, and the corner 160 and corner C4 have a one-to-one relationship.

[0163] The shape of each of the four corners 160 can be, for example, a rectangle, but is not limited to this. Figure 17 The enlarged view shows a corner 160 that is a quarter circle with corner C4 of the frame portion 150 as its vertex. Furthermore, corner C4 corresponds to the corner of the inner edge of the frame portion 150. Figure 17 The enlarged view is schematically shown using circles. Figure 17 In the enlarged view, the corner C4a corresponding to the outer edge of the frame portion 150 is also schematically shown as a circle, and a corner portion 160 can also be a quarter circle with corner C4a as the vertex.

[0164] Each of the four contact portions 170 is connected to a shared drain region. Each of the four contact portions 170 extends in the negative z-axis direction and connects to the low-concentration impurity layer 33. Each of the four contact portions 170 is positioned to overlap with one of the four corner portions 160 in a plan view. That is, one contact portion 170 is paired with one corner portion 160, thus overlapping in a plan view. In this embodiment, one contact portion 170 overlaps with the frame portion 150 and one corner portion 160, and more specifically, is contained within the frame portion 150 and one corner portion 160.

[0165] Each of the four contact portions 170 is rectangular in shape, but is not limited thereto. Furthermore, the dimensions of each of the four contact portions 170 are preferably greater than the width Wd. Figure 17 The enlarged view shows the length L of one side of a rectangular contact portion 170, which is preferably greater than the width Wd. Additionally, in Figure 17 The other three contacts 170, not shown in the enlarged view, are the same.

[0166] Therefore, the four corners of the semiconductor device 1, which are redundant areas, can be used to form a contact portion 170 that is larger than the width Wd of the frame portion 150.

[0167] In addition, Figure 17 In the overall diagram of the semiconductor device 1 shown in the figure, for the sake of simplicity, the description of the four corner portions 160 and the four contact portions 170 in the drain wiring 140 is omitted, and only a frame portion 150 is shown.

[0168] Hereinafter, variations 1 to 5 of the embodiments will be described. The description will focus on the differences from the embodiments, and the description of the commonalities will be omitted or simplified.

[0169] [Variation Example 1] Figure 18 This is a cross-sectional view showing an example of the structure of the semiconductor device 1a according to a modified example 1 of this embodiment. Figure 19 This is a cross-sectional view showing an example of the structure of the semiconductor device 1a according to Modification 1 of this embodiment. Additionally, Figure 18 The following is illustrated in the equivalent embodiment. Figure 1 A cross-sectional view of semiconductor device 1a at the location shown in the cross-sectional view. Figure 19 The following is illustrated in the equivalent embodiment. Figure 6 A cross-sectional view of semiconductor device 1a at the location shown in the cross-sectional view.

[0170] The semiconductor device 1a of this modified example has the same structure as the semiconductor device 1 according to the embodiment, except that it has a first gate wiring 114a and a second gate wiring 124a in place of the first gate wiring 114 and the second gate wiring 124.

[0171] The first gate wiring 114a has the same structure as the first gate wiring 114 in the embodiment, except that the first gate wiring metal 1141a is used instead of the first gate wiring metal 1141.

[0172] Compared to the first gate wiring metal 1141, the first gate wiring metal 1141a is wider. Here, the width of the first gate wiring metal 1141a (more specifically, the width of the film portion of the first gate wiring metal 1141a) is the same as the width of the first gate wiring conductor 1142.

[0173] The second gate wiring 124a has the same structure as the second gate wiring 124 in the embodiment, except that the second gate wiring metal 1241a is used instead of the second gate wiring metal 1241.

[0174] Compared to the second gate wiring metal 1241, the second gate wiring metal 1241a is wider. Here, the width of the second gate wiring metal 1241a (more specifically, the width of the film portion of the second gate wiring metal 1241a) is the same as the width of the second gate wiring conductor 1242.

[0175] In another embodiment, the first gate wiring conductor 1142 overlaps with the terminal portion of the first body region 18, and the second gate wiring conductor 1242 overlaps with the terminal portion of the second body region 28. In this modified example, the first gate wiring metal 1141a overlaps with the terminal portion of the first body region 18, and the second gate wiring metal 1241a overlaps with the terminal portion of the second body region 28.

[0176] Figure 18 Region A3a is the region where the first gate wiring metal 1141a overlaps with the terminal portion (the end on the positive x-axis side) of the first body region 18. Figure 18 Region A4a is the region where the second gate wiring metal 1241a overlaps with the terminal portion (the end on the negative side of the x-axis) of the second body region 28.

[0177] also, Figure 19 As shown, the first gate wiring metal 1141a formed near the edge (short side 93) of the semiconductor layer 40 also overlaps with the terminal portion of the first body region 18. That is, Figure 19Region A5a is the region where the first gate wiring metal 1141a overlaps with the terminal portion (the end on the negative x-axis side) of the first body region 18. Additionally, although not shown, at other edges of the semiconductor layer 40 beyond the short side 93, it also overlaps with... Figure 19 The first gate wiring metal 1141a described herein is the same. That is, the second gate wiring metal 1241a formed near the edge (short side 94) of the semiconductor layer 40 also overlaps with the terminal portion (the end on the positive x-axis side) of the second body region 28. The first gate wiring metal 1141a formed near the edge (long side 91) of the semiconductor layer 40 also overlaps with the terminal portion (the end on the positive y-axis side) of the first body region 18. The second gate wiring metal 1241a formed near the edge (long side 91) of the semiconductor layer 40 also overlaps with the terminal portion (the end on the positive y-axis side) of the second body region 28. The first gate wiring metal 1141a formed near the edge (long side 92) of the semiconductor layer 40 also overlaps with the terminal portion (the end on the negative y-axis side) of the first body region 18. The second gate wiring metal 1241a formed near the edge (long side 92) of the semiconductor layer 40 also overlaps with the terminal portion (the end on the negative y-axis side) of the second body region 28.

[0178] Therefore, especially between the first gate wiring 114a and the second gate wiring 124a (separated by boundary 90C), the inversion layer 331 connected to the first body region 18 and the second body region 28 due to BT testing can be further suppressed, thereby realizing a semiconductor device 1a that can suppress leakage current.

[0179] [Modification Example 2] Figure 20 This is a cross-sectional view showing an example of the structure of the semiconductor device 1b according to Modification 2 of this embodiment. Additionally, Figure 20 The following is illustrated in the equivalent embodiment. Figure 6 A cross-sectional view of semiconductor device 1b at the location shown in the cross-sectional view.

[0180] The semiconductor device 1b of this modified example has the same structure as the semiconductor device 1 according to the embodiment, except that it has a drain wiring 140b instead of a drain wiring 140.

[0181] Drain wiring 140b is formed above semiconductor layer 40, and more specifically, in contact with the upper surface of interlayer insulating layer 34. Drain wiring 140b is made of metal, and more specifically, of a metal containing copper and primarily composed of aluminum.

[0182] Furthermore, in this embodiment, the drain wiring 140 is composed of two layers: drain wiring metal 141 and drain wiring conductor 142, but it is not limited to this. In this modified example, the drain wiring 140b is composed of one layer. More specifically, the drain wiring 140b is composed of a film portion of the drain wiring metal 141.

[0183] Furthermore, in this modified example, the drain wiring 140b is preferably characterized by having Figure 17 The frame portion 150, four corner portions 160 and four contact portions 170 are described in the text, and the size of the contact portion 170 is preferably larger than the width of the frame portion 150.

[0184] [Modification Example 3] Figure 21 This is a cross-sectional view showing an example of the structure of the semiconductor device 1c according to Modification 3 of this embodiment. Additionally, Figure 21 The following is illustrated in the equivalent embodiment. Figure 6 A cross-sectional view of the semiconductor device 1c at the location shown in the cross-sectional view.

[0185] The semiconductor device 1c of this modified example has the same structure as the semiconductor device 1 according to the embodiment, except that it has a drain wiring 140c instead of a drain wiring 140.

[0186] Drain wiring 140c is formed above semiconductor layer 40, and more specifically, is embedded inside interlayer insulating layer 34. Drain wiring 140c is made of non-metallic conductor, and more specifically, of polysilicon.

[0187] In this variation, the drain wiring 140c is composed of a single layer. More specifically, the drain wiring 140c is composed of the drain wiring conductor 142 described in the embodiment.

[0188] Furthermore, in this modified example, the drain wiring 140c is preferably characterized by having Figure 17 The diagram describes a frame portion 150, four corner portions 160, and four contact portions 170, with the contact portion 170 preferably having a larger size than the frame portion 150. Furthermore, in this case, the frame portion 150 corresponds to the drain wiring conductor 142.

[0189] [Variation Example 4] Figure 22 This is a cross-sectional view showing an example of the structure of the semiconductor device 1d according to Modification 4 of this embodiment. Additionally, Figure 22 The following is illustrated in the equivalent embodiment. Figure 6 A cross-sectional view of semiconductor device 1d at the location shown in the cross-sectional view.

[0190] The semiconductor device 1d of this modified example has the same structure as the semiconductor device 1 according to the embodiment, except that it has a drain wiring 140d instead of a drain wiring 140.

[0191] In this modified example, the drain wiring 140d is a conductor buried in a trench disposed in the semiconductor layer 40. The trench extends from the upper surface of the semiconductor layer 40 to a depth extending to a portion of the semiconductor layer 40. More specifically, the trench extends from the upper surface of the low-concentration impurity layer 33 of the semiconductor layer 40 to a depth extending to a portion of the low-concentration impurity layer 33, and is formed to a depth that does not reach the semiconductor substrate 32. The drain wiring 140d is disposed inside the trench and is covered by an interlayer insulating layer 34.

[0192] As a non-limiting example, the drain wiring 140d is preferably polysilicon containing impurities.

[0193] [Variation Example 5] Figure 23 This is a cross-sectional view showing an example of the structure of the semiconductor device 1e according to Modification 5 of this embodiment. Additionally, Figure 23 The following is illustrated in the equivalent embodiment. Figure 6 The cross-sectional view shown is a cross-sectional view of the semiconductor device 1e at the location of the cross-sectional view shown.

[0194] The semiconductor device 1e in this modified example has the same structure as the semiconductor device 1 in the embodiment, except for the following two points. First, the semiconductor device 1e includes a drain wiring 140e, an interlayer insulating layer 34e, and a passivation layer 35e in place of the drain wiring 140, the interlayer insulating layer 34, and the passivation layer 35. Second, the positional relationship between the drain wiring 140e and the first gate wiring 114 or the second gate wiring 124 differs from that in the embodiment.

[0195] Drain wiring 140e is formed above semiconductor layer 40, and more specifically, in contact with the upper surface of interlayer insulating layer 34e. Drain wiring 140e is made of metal, and more specifically, of a metal containing copper and primarily composed of aluminum.

[0196] The drain wiring 140e is the same as the drain wiring 140b in Modified Example 2, consisting of a single layer and a film portion of the drain wiring metal 141.

[0197] Since the drain wiring 140e has the structure described above, the thickness of the interlayer insulating layer 34e directly below the drain wiring 140e can be thinner than the thickness of the interlayer insulating layer 34e directly below the first gate wiring 114, which consists of two layers. The interlayer insulating layer 34e has the same structure as the interlayer insulating layer 34, except that its thickness differs between the areas directly below the drain wiring 140e and the areas directly below the first gate wiring 114.

[0198] Since the drain wiring 140e is formed in contact with the upper surface of the interlayer insulating layer 34e, the upper surface 140eT of the drain wiring 140e is located at a lower position than the upper surface 114T of the first gate wiring 114 or the upper surface of the second gate wiring 124. The upper surface 114T of the first gate wiring 114 is the main surface on the positive z-axis side of the first gate wiring metal 1141. The upper surface of the second gate wiring 124 is the main surface on the positive z-axis side of the second gate wiring metal 1241.

[0199] The upper surface 140eT only needs to be located at a position lower than at least one of the upper surface 114T of the first gate wiring 114 and the upper surface of the second gate wiring 124. That is, the z-axis position of the upper surface 140eT only needs to be closer to the negative z-axis than at least one of the upper surface 114T of the first gate wiring 114 and the upper surface of the second gate wiring 124.

[0200] exist Figure 23 In this configuration, the upper surface 140eT is located at a lower position than the upper surface 114T. Alternatively, the upper surface 140eT can also be located at a higher position than the upper surface of the second gate wiring 124.

[0201] For example, when the upper surface 33T of the low-concentration impurity layer 33 is used as a reference, the height H1 from the upper surface 33T to the upper surface 140eT is lower than the height H2 from the upper surface 33T to the upper surface 114T.

[0202] Passivation layer 35e covers the drain wiring 140e and the first gate wiring 114 (more specifically, the first gate wiring metal 1141) in this positional relationship. Since the upper surface 140eT is located lower than the upper surface 114T, the passivation layer 35e extends from the center of the semiconductor device 1e towards the ends (in... Figure 23 The height decreases towards the negative x-axis. That is, the position of the upper surface of the passivation layer 35e above the drain wiring 140e is closer to the negative z-axis than the position of the upper surface of the passivation layer 35e above the first gate wiring 114. Alternatively, for example, the passivation layer 35e can decrease in height gradually from the center to the end of the semiconductor device 1e, or it can be as follows: Figure 23 As shown, the height decreases in a stepped manner.

[0203] Thus, since the height of the passivation layer 35e decreases from the center to the end of the semiconductor device 1e, it is easier for the passivation layer 35e to cover the layer located below it. In other words, the coverage of the passivation layer 35e is improved, and the peeling of the passivation layer 35e is suppressed. That is, a semiconductor device 1e with high long-term reliability is achieved.

[0204] [Effects, etc.] The semiconductor device 1 according to this embodiment includes: a semiconductor layer 40, comprising a first region A1 and a second region A2 located on the back side, including a semiconductor substrate 32, and located on the front side. In a plan view of the semiconductor substrate 32, the second region A2 is adjacent to the first region A1, and in the plan view, the area of ​​the semiconductor layer is bisected by the first region A1 and the second region A2; a first vertical MOS transistor 10 formed in the first region A1 of the semiconductor layer 40; a second vertical MOS transistor 20 formed in the second region A2 of the semiconductor layer 40; and a metal layer 30 formed in contact with the back side of the semiconductor layer 40. The semiconductor substrate 32 is a shared drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20. In the plan view, in the first region A1, a first source electrode 11 of a first vertical MOS transistor 10 and a first gate wiring 114 connected to and surrounding the first source electrode 19 of the first vertical MOS transistor 10 are formed. In the second region A2, a second source electrode 21 of a second vertical MOS transistor 20 and a second gate wiring 124 connected to and surrounding the second source electrode 21 of the second vertical MOS transistor 20 are formed. The first gate wiring 114 and the second gate wiring 124 are formed across the boundary 90C between the first region A1 and the second region A2. On the outer periphery of the semiconductor layer 40, a drain wiring 140 connected to the shared drain region is formed. The drain wiring 140 surrounds the first gate wiring 114 and the second gate wiring 124. No drain wiring 140 is formed between the first gate wiring 114 and the second gate wiring 124.

[0205] Therefore, if in Figure 14 and Figure 15 As explained, since the first gate wiring 114 and the second gate wiring 124 function as an EQR (Electrical EQ Reduction) circuit, a semiconductor device 1 capable of suppressing leakage current is realized. Furthermore, in the semiconductor device 1, a drain wiring 140 is not formed between the first gate wiring 114 and the second gate wiring 124. Therefore, for example, compared to the semiconductor device 1z according to Comparative Example 2, in the semiconductor device 1, since the common drain wiring 130 is not provided, the first active region 100 and the second active region 200 can be made larger. Thus, the semiconductor device 1 with larger first active region 100 and second active region 200 can achieve a reduction in on-resistance. In summary, the semiconductor device 1 according to this embodiment can suppress leakage current while reducing on-resistance.

[0206] In the implementation, in a plan view, the minimum value of the width Wd of the drain wiring 140 is less than the minimum value of the width W1 of the first gate wiring 114 or less than the minimum value of the width W2 of the second gate wiring 124. The closest distance D1 between the first gate wiring 114 and the second gate wiring 124, which are configured across the boundary 90C of the first region A1 and the second region A2, is less than the sum of the minimum value of the width Wd of the drain wiring 140 and the closest distance D2 between the drain wiring 140 and the first gate wiring 114 or between the drain wiring 140 and the second gate wiring 124.

[0207] Thus, for example, near boundary 90C, the first gate wiring 114 and the second gate wiring 124 are adjacent to each other. Due to this proximity, an extra region is generated within the semiconductor device 1, which can be used as the first active region 100 and the second active region 200. That is, since the first active region 100 and the second active region 200 can be made larger, the semiconductor device 1 can reduce the on-resistance more significantly.

[0208] In an embodiment, in a plan view, the first gate wiring 114 overlaps with the terminal portion of the first body region 18 of the first vertical MOS transistor 10, and the second gate wiring 124 overlaps with the terminal portion of the second body region 28 of the second vertical MOS transistor 20.

[0209] Accordingly, particularly between the first gate wiring 114 and the second gate wiring 124 (separated by boundary 90C), the first body region 18 and the second body region 28 are connected to further suppress the inversion layer 331 generated by the BT test, thereby realizing a semiconductor device 1 that can further suppress leakage current.

[0210] In this embodiment, the first gate wiring 114 is composed of two layers: a first gate wiring metal 1141 and a first gate wiring conductor 1142 formed above the semiconductor layer 40. The second gate wiring 124 is composed of two layers: a second gate wiring metal 1241 and a second gate wiring conductor 1242 formed above the semiconductor layer 40. In a plan view, the first gate wiring conductor 1142 overlaps with the terminal portion of the first body region 18 of the first vertical MOS transistor 10, and the second gate wiring conductor 1242 overlaps with the terminal portion of the second body region 28 of the second vertical MOS transistor 20.

[0211] Accordingly, the first body region 18 and the second body region 28 are connected to further suppress the inversion layer 331 generated by the BT test, thereby realizing a semiconductor device 1 that can further suppress leakage current.

[0212] In Modification 1, the first gate wiring 114a is composed of two layers: a first gate wiring metal 1141a and a first gate wiring conductor 1142 formed above the semiconductor layer 40. The second gate wiring 124a is composed of two layers: a second gate wiring metal 1241a and a second gate wiring conductor 1242 formed above the semiconductor layer 40. In plan view, the first gate wiring metal 1141a overlaps with the terminal portion of the first body region 18 of the first vertical MOS transistor 10, and the second gate wiring metal 1241a overlaps with the terminal portion of the second body region 28 of the second vertical MOS transistor 20.

[0213] Accordingly, the first body region 18 and the second body region 28 are connected to further suppress the inversion layer 331 generated by the BT test, thereby realizing a semiconductor device 1a that can further suppress leakage current.

[0214] In the implementation, in a plan view, the closest distance D3 between the first body region 18 and the second body region 28, which are arranged across the boundary 90C between the first region A1 and the second region A2, is greater than the closest distance D4 between the first gate wiring conductor 1142 and the second gate wiring conductor 1242, which are arranged across the boundary 90C between the first region A1 and the second region A2.

[0215] Accordingly, the first body region 18 and the second body region 28 are sufficiently separated, and the first gate wiring 114 and the second gate wiring 124 are disposed above each other, making it difficult to form a leakage path between the first body region 18 and the second body region 28. That is, the semiconductor device 1 according to this embodiment can further suppress leakage current.

[0216] In Modification 2, drain wiring 140b is formed above semiconductor layer 40 and is made of metal.

[0217] Accordingly, a drain wiring 140b made of metal can be realized.

[0218] In Modification 3, drain wiring 140c is formed above semiconductor layer 40 and is composed of non-metallic conductors.

[0219] Accordingly, it is possible to realize drain wiring 140c made of non-metallic conductors.

[0220] In Variation 4, the drain wiring 140d is a conductor buried inside a trench formed from the upper surface of the semiconductor layer 40 to a depth of a portion of the semiconductor layer 40.

[0221] Therefore, it is possible to achieve 140d drain wiring embedded inside the trench.

[0222] In this embodiment, the drain wiring 140 has, in a plan view: a rectangular frame portion 150; corner portions 160 located on the inner sides of the four corners C1, C2, C3, and C4 of the frame portion 150; and contact portions 170 that overlap with each of the four corner portions 160 and are connected to a shared drain region. The dimensions of each of the four contact portions 170 are larger than the width Wd of the frame portion 150.

[0223] Therefore, the four corners of the semiconductor device 1, which are redundant areas, can be used to form a contact portion 170 that is larger than the width Wd of the frame portion 150.

[0224] In this embodiment, each of the four corner portions 160 is a quarter circle with a vertex at one of the corners of the frame portion 150 (e.g., each of corners C1, C2, C3, and C4). In a plan view, each of the four contact portions 170 is rectangular. In each of the four contact portions 170, the length of one side of the rectangle is greater than the width Wd of the frame portion 150.

[0225] Accordingly, the four corners of the semiconductor device 1, which are redundant areas, are utilized more effectively, and the contact portion 170 can be more reliably connected to the shared drain region.

[0226] In variation 2, the drain wiring 140b is composed of one layer.

[0227] Accordingly, a drain wiring 140b consisting of a single layer can be realized.

[0228] In Modification 5, the upper surface 140eT of the drain wiring 140e is located at a lower position than the upper surface 114T of the first gate wiring 114 or the upper surface of the second gate wiring 124.

[0229] Accordingly, the passivation layer 35e more easily covers the layer underneath it. In other words, the coverage of the passivation layer 35e is improved, and the peeling of the passivation layer 35e is suppressed. Thus, a semiconductor device 1e with high long-term reliability is achieved.

[0230] (Other implementation methods) The semiconductor device of one embodiment of the present disclosure has been described above based on the embodiments and various modifications, but the present disclosure is not limited to these embodiments and modifications. Various modifications to the embodiments that can be conceived by those skilled in the art without departing from the spirit of the present disclosure may also be included within the scope of one or more embodiments of the present disclosure.

[0231] Furthermore, in the embodiments described, the drain wiring 140 surrounding the first gate wiring 114 and the second gate wiring 124 refers to both the case where the drain wiring 140 completely surrounds the first gate wiring 114 and the second gate wiring 124 without any breaks, forming a complete frame, and the case where the drain wiring 140 is broken by a predetermined distance. The drain wiring 140 only needs to be provided in the portion adjacent to the first gate wiring 114 and the second gate wiring 124 in a plan view without including other constituent elements. When the drain wiring 140 is broken, the number of breaks is not particularly limited; for example, it can be one or multiple breaks. The location of the break in the drain wiring 140 is not particularly limited; for example, it can be at the intersection of the boundary 90C and the drain wiring 140 in a plan view (two locations).

[0232] Industrial availability This disclosure can be widely used in semiconductor devices and the like mounted on a mounting substrate.

[0233] Explanation of reference numerals in the attached figures 1, 1a, 1b, 1c, 1d, 1e, 1y, 1z: Semiconductor devices 10: Transistor (First Vertical MOS Transistor) 11: First source electrode 14: First source region 15: First gate conductor 16: First gate oxide film 17: Gate Trench No. 1 18: 1st body area 19: Gate electrode 1 20: Transistor (Second Vertical MOS Transistor) 21: Second source electrode 24: Second source region 25: Second gate conductor 26: Second gate oxide film 27: Second gate trench 28: 2nd body area 29: Second gate electrode 30: Metal layer 32: Semiconductor substrate 33: Low-concentration impurity layer 33T, 114T, 140eT: Upper surface 34, 34e: Interlayer insulation layer 35, 35e: Passivation layer 40: Semiconductor layer 90: Center line 90C: Boundary 91, 92: Long side 93, 94: Short side 100: First active region 111, S1: First source pad 113: First drain wiring 114, 114a: First gate wiring 119, G1: Gate pad #1 121, S2: Second source pad 123: Second drain wiring 124, 124a: Second gate wiring 129, G2: Second gate pad 130; Common-drain wiring 140, 140b, 140c, 140d, 140e; Drain wiring 141; Drain wiring metal 142; Drain wiring conductor 150: Frame section 160: Corner 170; Contact Department 200: Second active region 331, 331y, 331z, 332z; Inverted layer 1141, 1141a: First gate wiring metal 1142: First gate wiring conductor 1241, 1241a: Second gate wiring metal 1242: Second gate wiring conductor A1: Area 1 A2: Area 2 A3, A3a, A4, A4a, A5, A5a: Area C1, C2, C3, C4, C4a: Angles D: Drain pad D1, D2, D3, D4: Closest Distance W1, W2, Wd: Width.

Claims

1. A semiconductor device, The semiconductor device includes: A semiconductor layer includes a semiconductor substrate on the back side and a first region and a second region on the front side, wherein the second region is adjacent to the first region in a plan view of the semiconductor substrate, and the area of ​​the semiconductor layer is bisected by the first region and the second region in the plan view. A first vertical MOS transistor is formed in the first region of the semiconductor layer; A second vertical MOS transistor is formed in the second region of the semiconductor layer; and A metal layer is formed in contact with the back side of the semiconductor layer. The semiconductor substrate is the shared drain region of the first vertical MOS transistor and the second vertical MOS transistor. In the plan view, In the first region, the following are formed: The first source electrode of the first vertical MOS transistor: and The first gate wiring is connected to the first gate electrode of the first vertical MOS transistor and surrounds the first source electrode. In the second region, the following are formed: The second source electrode of the second vertical MOS transistor: and The second gate wiring is connected to the second gate electrode of the second vertical MOS transistor and surrounds the second source electrode. The first gate wiring and the second gate wiring are formed across the boundary between the first region and the second region. A drain wiring connected to the shared drain region is formed on the outer periphery of the semiconductor layer. The drain wiring surrounds the first gate wiring and the second gate wiring. The drain wiring is not formed between the first gate wiring and the second gate wiring.

2. The semiconductor device as claimed in claim 1, In the plan view, The minimum width of the drain wiring is less than the minimum width of the first gate wiring or less than the minimum width of the second gate wiring. The closest distance between the first gate wiring and the second gate wiring, which are configured across the boundary between the first region and the second region, is less than the sum of the minimum width of the drain wiring and the closest distance between the drain wiring and the first gate wiring or between the drain wiring and the second gate wiring.

3. The semiconductor device as claimed in claim 2, In the plan view, The first gate wiring overlaps with the terminal portion of the first body region of the first vertical MOS transistor. The second gate wiring overlaps with the terminal portion of the second body region of the second vertical MOS transistor.

4. The semiconductor device as claimed in claim 3, The first gate wiring is composed of two layers: a first gate wiring metal and a first gate wiring conductor formed above the semiconductor layer. The second gate wiring is composed of two layers: a second gate wiring metal and a second gate wiring conductor formed above the semiconductor layer. In the plan view, The first gate wiring conductor overlaps with the terminal portion of the first body region of the first vertical MOS transistor. The second gate wiring conductor overlaps with the terminal portion of the second body region of the second vertical MOS transistor.

5. The semiconductor device as claimed in claim 3, The first gate wiring is composed of two layers: a first gate wiring metal and a first gate wiring conductor formed above the semiconductor layer. The second gate wiring is composed of two layers: a second gate wiring metal and a second gate wiring conductor formed above the semiconductor layer. In the plan view, The first gate wiring metal overlaps with the terminal portion of the first body region of the first vertical MOS transistor. The second gate wiring metal overlaps with the terminal portion of the second body region of the second vertical MOS transistor.

6. The semiconductor device as claimed in claim 4 or 5, In the plan view, the closest distance between the first body region and the second body region, which are separated by the boundary between the first region and the second region, is greater than the closest distance between the first gate wiring conductor and the second gate wiring conductor, which are separated by the boundary between the first region and the second region.

7. The semiconductor device as claimed in claim 2, The drain wiring is formed above the semiconductor layer and is made of metal.

8. The semiconductor device as claimed in claim 2, The drain wiring is formed above the semiconductor layer and is composed of a non-metallic conductor.

9. The semiconductor device as claimed in claim 2, The drain wiring is a conductor buried inside a trench that extends from the upper surface of the semiconductor layer to a depth of a portion of the semiconductor layer.

10. The semiconductor device as claimed in claim 1, 7, or 8, The drain wiring has the following characteristics in the plan view: The rectangular frame-like border section; The corners located on the inner sides of the four corners of the frame; and The contact portion that overlaps with each of the four corner portions and is connected to the shared drain region. The dimensions of each of the four contact portions are greater than the width of the frame portion.

11. The semiconductor device as claimed in claim 10, The shape of each of the four corners is a quarter circle with the corner of the frame portion as its vertex. In the plan view, each of the four contact portions is rectangular in shape. In each of the four contact portions, the length of one side of the rectangle is greater than the width of the frame portion.

12. The semiconductor device as claimed in claim 10, The drain wiring consists of one layer.

13. The semiconductor device as claimed in claim 12, The upper surface of the drain wiring is located at a lower position than the upper surface of the first gate wiring or the upper surface of the second gate wiring.

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