Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having an active region and a termination region surrounding the active region in a plan view perpendicular to the first main surface. The silicon carbide substrate has a first semiconductor region having a first conductivity type, and a plurality of second semiconductor regions having a second conductivity type provided in the first semiconductor region. The plurality of second semiconductor regions are arranged along a first axis parallel to the first main surface in the active region and the termination region, and extend along a second axis parallel to the first main surface and perpendicular to the first axis. The second semiconductor regions have a first region in the active region, and a second region in the termination region. A first width of the first region along the first axis is narrower than a second width of the second region along the first axis.

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device.

[0002] This application claims priority based on Japanese Patent Application No. 2024-030928, filed on March 1, 2024, and the entire contents set forth in the aforementioned Japanese application are incorporated herein by reference. Background Technology

[0003] Traditionally, silicon carbide semiconductor devices with superjunction structures have been disclosed.

[0004] Existing technical documents Patent documents Patent Document 1: International Publication No. 2022 / 118976 [Non-patent literature] [Non-Patent Literature 1] T. Masuda et al., “Edge Termination Design of 1.2 kV 4H-SiC Superjunction V-groove MOSFET with Strong Process Stability”, Proceedings of the 32nd International Symposium on Power Semiconductor Devices and Integrated Circuits (ISPSD), pp. 166-169, September 2020. Summary of the Invention

[0005] The silicon carbide semiconductor device of the present invention includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. Viewed from above perpendicular to the first main surface, it has an active region and a terminal region surrounding the active region. The silicon carbide substrate has: a first semiconductor region having a first conductivity type, and a plurality of second semiconductor regions having a second conductivity type disposed within the first semiconductor region; the plurality of second semiconductor regions are arranged along a first axis parallel to the first main surface within the active region and the terminal region, and extend along a second axis parallel to the first main surface and perpendicular to the first axis; each second semiconductor region has a first region located in the active region and a second region located in the terminal region; the first width of the first region along the first axis is narrower than the second width of the second region along the first axis. Attached Figure Description

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[0014] [The problem this invention aims to solve] A silicon carbide semiconductor device with a superjunction structure has an active region and a termination region surrounding the active region. In the active region and the termination region, a parallel structure of alternating p-pillars and n-pillars is provided. In this silicon carbide semiconductor device with a superjunction structure, the parallel structure is uniformly formed in the active region and the termination region surrounding the active region. Therefore, it is difficult to establish a breakdown voltage difference between the active region and the termination region.

[0015] The purpose of this invention is to provide a silicon carbide semiconductor device that enables the active region to have a lower withstand voltage than the terminal region.

[0016] [Effects of the Invention] According to the present invention, the withstand voltage of the active region can be lower than that of the terminal region.

[0017] The specific implementation method will be described below.

[0018] [Description of Embodiments of the Invention] First, embodiments of the present invention are listed and described. In the following description, the same or corresponding elements will be given the same reference numerals, and the same descriptions will not be repeated. In the following description, the XYZ rectangular coordinate system is used, but this coordinate system is set for illustrative purposes only and does not limit the orientation of the silicon carbide semiconductor device. The XY top view is called the planar top view. When viewed from any point, the +Z direction is sometimes referred to as above, upper side, or up, and the -Z direction is referred to as below, lower side, or down.

[0019] [1] According to one aspect of the present invention, a silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, having an active region and a terminal region surrounding the active region in a top view perpendicular to the first main surface; the silicon carbide substrate has: a first semiconductor region having a first conductivity type, and a plurality of second semiconductor regions having a second conductivity type disposed within the first semiconductor region; the plurality of second semiconductor regions are arranged along a first axis parallel to the first main surface in the active region and the terminal region, and extend along a second axis parallel to the first main surface and perpendicular to the first axis; the second semiconductor regions have a first region located in the active region and a second region located in the terminal region; the first width of the first region along the first axis is narrower than the second width of the second region along the first axis. In this case, the withstand voltage of the active region can be lower than the withstand voltage of the terminal region. Therefore, in the event of avalanche breakdown, the leakage current can be uniformly distributed in the active region. As a result, avalanche tolerance can be improved.

[0020] [2] In [1], the second semiconductor region may have a third region located between the first region and the second region, the third region having a third width along the first axis that can widen from the first region to the second region. In this case, it is easier to reduce the electric field concentration at the boundary between the first and second regions.

[0021] [3] In [2], the length of the third region along the second axis can be greater than twice the difference between the second width and the first width. In this case, it is easier to reduce the electric field concentration at the boundary between the first and second regions.

[0022] [4] In [1] to [3], a plurality of second semiconductor regions may be arranged at a fixed interval along the first axis. In this case, leakage current is easily distributed uniformly within the active region in the event of avalanche breakdown.

[0023] [5] In [1] to [4], the silicon carbide substrate has a third semiconductor region having the second conductivity type. The third semiconductor region is disposed in the active region and the terminal region and forms the first main surface. A plurality of second semiconductor regions can be electrically connected to the third semiconductor region. In this case, since the p-type region is at the source potential, the feedback capacitance between the gate electrode and the drain electrode can be reduced.

[0024] [Detailed Description of Embodiments of the Invention] [Structure of a silicon carbide semiconductor device] Embodiments of the present invention relate to so-called vertical MOS (Metal Oxide Semiconductor) field-effect transistors (FETs) using silicon carbide. A MOS-type FET is an example of a silicon carbide semiconductor device.

[0025] Figure 1 This is a schematic diagram showing the outline of the silicon carbide substrate in the silicon carbide semiconductor device according to the embodiment. Figure 2 This is a diagram showing the interlayer insulating film and the first main surface structure in the active region of a silicon carbide semiconductor device according to an embodiment. Figure 3 This is a diagram showing the structure of the p-type region near the boundary between the active region and the terminal region of the silicon carbide semiconductor device in an embodiment. Figure 4 This is a cross-sectional view showing the active region structure of a silicon carbide semiconductor device according to an embodiment. Figure 5 This is a cross-sectional view showing the terminal region structure of the silicon carbide semiconductor device according to the embodiment. Figure 2 Corresponding to Figure 1 Region II in the middle. Figure 3 Corresponding to Figure 1 Region III in the middle. Figure 4 Equivalent to along Figure 1 Cross-sectional view of line IV-IV. Figure 5 Equivalent to along Figure 1 Cross-sectional view of the VV line.

[0026] like Figures 1 to 5 As shown, the silicon carbide semiconductor device 100 of the embodiment includes: a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a barrier metal film 84, a source electrode 60, and a drain electrode 70.

[0027] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is located in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40. The silicon carbide epitaxial layer 40 includes the first main surface 1. The silicon carbide single crystal substrate 50 includes the second main surface 2. The silicon carbide epitaxial layer 40 is located on the silicon carbide single crystal substrate 50. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 contain, for example, hexagonal silicon carbide with polytype 4H. The silicon carbide single crystal substrate 50 contains, for example, n-type impurities such as nitrogen (N), and has an n-type conductivity type (first conductivity type).

[0028] The silicon carbide substrate 10 has an active region 110 and a termination region 120. The active region 110 is, for example, a rounded rectangle in a top view perpendicular to the first main surface 1. The active region 110 may also be a rounded square in a top view. The termination region 120 surrounds the active region 110 in a top view. The termination region 120 is disposed around the active region 110 in a top view.

[0029] The silicon carbide epitaxial layer 40 has: a drift region 11, a bulk region 12, a source region 13, a current diffusion region 14, a p-type region 16 for superjunction, a contact region 18, and a p-type connection region 19.

[0030] The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. The drift region 11 is disposed on the silicon carbide single crystal substrate 50. The drift region 11 is an example of a first semiconductor region.

[0031] The current diffusion region 14 contains n-type impurities such as phosphorus and has n-type conductivity. The current diffusion region 14 is disposed on the drift region 11. The lower end face of the current diffusion region 14 is in contact with the upper end face of the drift region 11.

[0032] Body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity (second conductivity type). Body region 12 is located within active region 110. Body region 12 is disposed on current diffusion region 14. The lower end face of body region 12 is in contact with the upper end face of current diffusion region 14.

[0033] Source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. Source region 13 is located within active region 110. Source region 13 is disposed on body region 12. The lower end face of source region 13 is in contact with the upper end face of body region 12. Source region 13 includes a first main surface 1.

[0034] A plurality of gate trenches 5, defined by side surface 3 and bottom surface 4, are provided on the first main surface 1. The gate trenches 5 are disposed within the active region 110. The gate trenches 5 extend, for example, along the X-axis. The plurality of gate trenches 5 are disposed along the Y-axis at a fixed spacing (first spacing P1). The side surface 3 penetrates the source region 13, the body region 12, the current diffusion region 14, and a portion of the drift region 11, and reaches the drift region 11. The bottom surface 4 is connected to the side surface 3. The bottom surface 4 is located in the drift region 11. The bottom surface 4 is, for example, parallel to the first main surface 1 and the second main surface 2. The side surface 3 is, for example, inclined relative to the plane containing the bottom surface 4.

[0035] Contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. Contact region 18 is located within active region 110. Contact region 18 extends through source region 13 and contacts body region 12. Contact region 18 includes a first main surface 1. In a top view perpendicular to the first main surface 1, contact region 18 is located between adjacent gate trenches 5 along the Y-axis. Between two adjacent gate trenches 5 along the Y-axis, contact region 18 and source region 13 may also be alternately arranged along the X-axis. Contact region 18 may also be located in terminal region 120. Contact region 18 is an example of a third semiconductor region.

[0036] The p-type region 16 contains p-type impurities such as aluminum and has p-type conductivity. The p-type region 16 is located within the active region 110 and the terminal region 120. The p-type region 16 is disposed within the drift region 11. Multiple p-type regions 16 extend along the X-axis and are arranged along the Y-axis. Multiple p-type regions 16 extend parallel to the gate trench 5. Multiple p-type regions 16 may also be arranged at a fixed interval along the Y-axis. In this case, leakage current is easily uniformly distributed in the active region 110 during avalanche breakdown. Multiple p-type regions 16 may also be arranged in a stripe pattern. Multiple p-type regions 16 may also extend along the Y-axis and be arranged along the X-axis. Multiple p-type regions 16 may also extend perpendicular to the gate trench 5. The effective concentration of p-type impurities in the p-type region 16 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 5×10 17 cm -3 Below, p-type region 16 is an example of a second semiconductor region. The Y-axis is an example of a first axis, and the X-axis is an example of a second axis.

[0037] The p-type region 16 has a first region 16a, a second region 16b, and a third region 16c. The first region 16a is located within the active region 110. The second region 16b and the third region 16c are located within the terminal region 120. The third region 16c is located between the first region 16a and the second region 16b.

[0038] The first width W1 of the first region 16a along the Y-axis can be narrower than the second width W2 of the second region 16b along the Y-axis. In this case, the withstand voltage of the active region 110 can be lower than that of the terminal region 120. Therefore, in the event of avalanche breakdown, the leakage current can be uniformly distributed within the active region 110. As a result, avalanche resistance can be improved.

[0039] The third width W3 of the third region 16c along the Y-axis can widen from the first region 16a to the second region 16b. In this case, it is easier to reduce the electric field concentration at the boundary between the first region 16a and the second region 16b. The third width W3 can also widen continuously from the first region 16a to the second region 16b.

[0040] The length L3 of the third region 16c along the X-axis can be greater than twice the difference between the second width W2 and the first width W1. That is, the relation L3 > 2 × (W2 - W1) can be satisfied. In this case, it is easy to reduce the electric field concentration at the boundary between the first region 16a and the second region 16b.

[0041] Viewed from above perpendicular to the first main surface 1, the p-type region 16 is located between adjacent gate trenches 5 along the Y-axis. The p-type region 16 is located away from the gate trenches 5. Along the Y-axis, the p-type region 16 is further away from the gate trenches 5 than the body region 12. Viewed from above perpendicular to the first main surface 1, the p-type region 16 overlaps with the contact region 18.

[0042] The p-type connection region 19 contains p-type impurities such as aluminum and has p-type conductivity. The p-type connection region 19 is located within the active region 110 and the terminal region 120. The p-type connection region 19 is located between the p-type region 16 and the contact region 18. The lower end face of the p-type connection region 19 contacts the upper end face of the p-type region 16. The upper end face of the p-type connection region 19 contacts the source region 13 and the contact region 18. The p-type connection region 19 electrically connects the p-type region 16 and the contact region 18. In this case, since the p-type region 16 is at the source potential, the feedback capacitance between the gate electrode 82 and the drain electrode 70 can be reduced. The effective concentration of the p-type impurities in the p-type connection region 19 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 5×10 17 cm -3 the following.

[0043] Viewed from above perpendicular to the first main surface 1, the p-type connection region 19 is located between adjacent gate trenches 5 along the Y-axis. The p-type connection region 19 is located away from the gate trenches 5. Along the Y-axis, the p-type connection region 19 is further away from the gate trenches 5 than the body region 12. Viewed from above perpendicular to the first main surface 1, the p-type connection region 19 overlaps with the p-type region 16 and the contact region 18. The side of the p-type connection region 19 contacts the drift region 11, the current diffusion region 14, and the body region 12. The width of the p-type connection region 19 along the Y-axis can be wider than the width of the p-type region 16 along the Y-axis.

[0044] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 comprises, for example, silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the drift region 11 at the bottom surface 4. The gate insulating film 81 is in contact with the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may also be in contact with the source region 13 at the first main surface 1.

[0045] A gate electrode 82 is disposed on a gate insulating film 81. The gate electrode 82 is formed, for example, from polysilicon (Poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside a gate trench 5. The gate electrode 82 is opposite to the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may be opposite to a first main surface 1. The gate electrode 82 extends along the X-axis. In a top view perpendicular to the first main surface 1, the gate electrode 82 may overlap with multiple gate trenches 5.

[0046] An interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with both the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is, for example, formed from a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A portion of the interlayer insulating film 83 may be disposed inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface with continuously varying curvature. Alternatively, the upper surface of the interlayer insulating film 83 may be a curved surface convex in the +Z direction above the gate trench 5.

[0047] Contact holes 90 are provided at fixed intervals along the Y-axis in the interlayer insulating film 83 and the gate insulating film 81. The contact holes 90 are provided such that the gate trench 5 is located between adjacent contact holes 90 along the Y-axis. The contact holes 90 extend along the X-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0048] A barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is formed, for example, from a material containing titanium nitride (TiN).

[0049] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 is disposed within a contact hole 90. The contact electrode 61 contacts the source region 13 and the contact region 18 at the first main surface 1. The contact electrode 61 is formed, for example, of a material containing nickel silicide (NiSi). The contact electrode 61 may also be formed of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic contact with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 contacts the barrier metal film 84 and the contact electrode 61. The source wiring 62 is formed, for example, of an aluminum-containing material.

[0050] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single-crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is formed, for example, of a material containing nickel silicide. The drain electrode 70 may also be formed of a material containing titanium, aluminum, and silicon. The drain electrode 70 forms an ohmic contact with the silicon carbide single-crystal substrate 50.

[0051] In this invention, the effective concentration of the first conductivity type impurity is the concentration obtained by subtracting the concentration of the second conductivity type impurity from the concentration of the first conductivity type impurity. Similarly, the effective concentration of the second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentration can be measured, for example, using a scanning capacitance microscope (SCM).

[0052] In this invention, the first width W1, the second width W2, the third width W3, and the length L3 can be measured, for example, using a scanning electron microscope (SEM).

[0053] [Manufacturing Method of Silicon Carbide Semiconductor Device] Next, the manufacturing method of the silicon carbide semiconductor device 100 will be described. Figures 6 to 8 This is a cross-sectional view showing the manufacturing method of the silicon carbide semiconductor device 100 according to the embodiment. Figure 7 This is a cross-sectional view showing the structure of the active region 110. Figure 8 This is a cross-sectional view showing the structure of terminal region 120.

[0054] First, such as Figure 6 As shown, a silicon carbide single-crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single-crystal substrate 50. For example, the silicon carbide single-crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0055] Next, as Figure 7 and Figure 8 As shown, a p-type region 16 is formed by implanting ions into the silicon carbide epitaxial layer 40. During ion implantation to form the p-type region 16, channel implantation of p-type impurities such as aluminum is performed. The upper surface of the p-type region 16 is separated from the upper surface of the silicon carbide epitaxial layer 40.

[0056] Next, by implanting ions into the silicon carbide epitaxial layer 40, a body region 12, a source region 13, a current diffusion region 14, a contact region 18, and a p-type connection region 19 are formed. The remaining portion of the silicon carbide epitaxial layer 40 becomes the drift region 11. Then, a plurality of gate trenches 5 are formed. Next, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a barrier metal film 84, a source electrode 60, and a drain electrode 70 are formed (see...). Figure 4 and Figure 5 ).

[0057] In this way, a silicon carbide semiconductor device 100 can be manufactured.

[0058] The embodiments have been described in detail above, but the present invention is not limited to the specific embodiments. Various modifications and alterations can be made within the scope of the claims.

[0059] Explanation of reference numerals in the attached figures 1 First Main Face 2 Second Main Face 3. Side view 4 bottom 5 Gate trench 10 Silicon carbide substrate 11 Drift Area 12 body regions 13 Source Regions 14 Current diffusion region 16 p-type region 16a First Region 16b Second Region 16c Third Region 18 Contact Area 19 p-type connection area 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 source electrodes 61 Contact Electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 gate electrode 83 interlayer insulating film 84 Barrier Metal Film 90 contact hole 100 Silicon Carbide Semiconductor Device 110 Active Area 120 Terminal Area L3 length P1 First Spacing W1 First Width W2 Second Width W3 Third Width

Claims

1. A silicon carbide semiconductor device comprising a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having an active region and a terminal region surrounding the active region in a top view perpendicular to the first main surface. The silicon carbide substrate has: a first semiconductor region having a first conductivity type, and Within the first semiconductor region, there are a plurality of second semiconductor regions having a second conductivity type. A plurality of second semiconductor regions are arranged along a first axis parallel to the first main surface and extending along a second axis parallel to the first main surface and perpendicular to the first axis within the active region and the terminal region. The second semiconductor region has a first region located in the active region and a second region located in the terminal region. The first width of the first region along the first axis is narrower than the second width of the second region along the first axis.

2. The silicon carbide semiconductor device according to claim 1, wherein the second semiconductor region has a third region located between the first region and the second region. The third width of the third region along the first axis widens from the first region toward the second region.

3. The silicon carbide semiconductor device of claim 2, wherein the length of the third region along the second axis is greater than twice the difference between the second width and the first width.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein a plurality of second semiconductor regions are arranged at a fixed interval along the first axis.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the silicon carbide substrate includes a third semiconductor region having the second conductivity type. The third semiconductor region is located within the active region and the terminal region, and constitutes the first main surface. The second semiconductor regions are electrically connected to the third semiconductor region.

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